./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:29,174 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:29,184 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:29,228 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:29,229 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:29,230 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:29,231 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:29,233 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:29,234 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:29,235 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:29,236 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:29,237 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:29,237 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:29,238 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:29,239 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:29,240 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:29,241 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:29,242 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:29,243 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:29,245 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:29,247 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:29,248 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:29,249 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:29,250 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:29,252 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:29,253 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:29,253 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:29,254 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:29,255 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:29,256 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:29,256 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:29,257 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:29,257 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:29,258 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:29,259 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:29,259 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:29,260 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:29,260 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:29,260 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:29,261 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:29,262 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:29,265 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:29,292 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:29,293 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:29,294 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:29,294 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:29,296 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:29,297 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:29,297 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:29,297 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:29,297 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:29,297 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:29,298 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:29,298 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:29,299 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:29,299 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:29,299 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:29,299 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:29,299 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:29,300 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:29,300 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:29,300 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:29,300 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:29,300 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:29,301 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:29,301 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:29,302 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:29,302 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:29,302 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:29,303 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:29,303 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:29,303 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:29,303 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:29,304 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:29,305 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:29,305 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2021-12-19 19:17:29,547 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:29,580 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:29,583 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:29,584 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:29,584 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:29,586 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.09.cil.c [2021-12-19 19:17:29,640 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b096e6318/d0283d135e794f92b72bcf3f641e0f46/FLAGcea32b0cd [2021-12-19 19:17:30,072 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:30,073 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c [2021-12-19 19:17:30,087 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b096e6318/d0283d135e794f92b72bcf3f641e0f46/FLAGcea32b0cd [2021-12-19 19:17:30,097 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b096e6318/d0283d135e794f92b72bcf3f641e0f46 [2021-12-19 19:17:30,100 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:30,101 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:30,104 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:30,105 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:30,108 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:30,109 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,111 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7bc19b04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30, skipping insertion in model container [2021-12-19 19:17:30,111 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,117 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:30,157 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:30,276 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2021-12-19 19:17:30,366 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:30,374 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:30,384 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2021-12-19 19:17:30,428 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:30,444 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:30,444 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30 WrapperNode [2021-12-19 19:17:30,445 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:30,446 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:30,446 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:30,446 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:30,452 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,463 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,531 INFO L137 Inliner]: procedures = 46, calls = 57, calls flagged for inlining = 52, calls inlined = 170, statements flattened = 2581 [2021-12-19 19:17:30,532 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:30,532 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:30,533 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:30,533 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:30,545 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,545 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,560 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,575 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,611 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,647 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,661 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,672 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:30,673 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:30,673 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:30,673 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:30,676 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (1/1) ... [2021-12-19 19:17:30,685 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:30,708 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:30,721 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:30,760 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:30,785 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:30,786 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:30,786 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:30,786 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:30,873 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:30,874 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:32,133 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:32,155 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:32,156 INFO L301 CfgBuilder]: Removed 13 assume(true) statements. [2021-12-19 19:17:32,160 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:32 BoogieIcfgContainer [2021-12-19 19:17:32,161 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:32,164 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:32,164 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:32,167 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:32,168 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:32,168 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:30" (1/3) ... [2021-12-19 19:17:32,169 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2592c3d5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:32, skipping insertion in model container [2021-12-19 19:17:32,170 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:32,170 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:30" (2/3) ... [2021-12-19 19:17:32,170 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2592c3d5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:32, skipping insertion in model container [2021-12-19 19:17:32,170 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:32,170 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:32" (3/3) ... [2021-12-19 19:17:32,172 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2021-12-19 19:17:32,208 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:32,208 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:32,208 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:32,208 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:32,209 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:32,209 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:32,209 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:32,209 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:32,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2021-12-19 19:17:32,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:32,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:32,322 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,323 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:32,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2021-12-19 19:17:32,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:32,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:32,353 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,354 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:32,367 INFO L791 eck$LassoCheckResult]: Stem: 531#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 999#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 220#L1359true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1059#L634true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 721#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 769#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 695#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 483#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 972#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 327#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 930#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 849#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 673#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 374#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 224#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1090#L922true assume !(0 == ~M_E~0); 1027#L922-2true assume !(0 == ~T1_E~0); 1047#L927-1true assume !(0 == ~T2_E~0); 539#L932-1true assume !(0 == ~T3_E~0); 428#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 482#L942-1true assume !(0 == ~T5_E~0); 725#L947-1true assume !(0 == ~T6_E~0); 543#L952-1true assume !(0 == ~T7_E~0); 620#L957-1true assume !(0 == ~T8_E~0); 969#L962-1true assume !(0 == ~T9_E~0); 409#L967-1true assume !(0 == ~E_1~0); 936#L972-1true assume !(0 == ~E_2~0); 704#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1038#L982-1true assume !(0 == ~E_4~0); 105#L987-1true assume !(0 == ~E_5~0); 109#L992-1true assume !(0 == ~E_6~0); 356#L997-1true assume !(0 == ~E_7~0); 880#L1002-1true assume !(0 == ~E_8~0); 346#L1007-1true assume !(0 == ~E_9~0); 8#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 872#L443true assume !(1 == ~m_pc~0); 557#L443-2true is_master_triggered_~__retres1~0#1 := 0; 548#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 962#L455true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190#L1140true assume !(0 != activate_threads_~tmp~1#1); 63#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 896#L462true assume 1 == ~t1_pc~0; 450#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L474true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 315#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 980#L481true assume !(1 == ~t2_pc~0); 774#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 529#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426#L493true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 237#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1082#L500true assume 1 == ~t3_pc~0; 462#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 738#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688#L512true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 765#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 9#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 750#L519true assume 1 == ~t4_pc~0; 156#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 578#L531true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 210#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 504#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90#L538true assume !(1 == ~t5_pc~0); 827#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 43#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 954#L550true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 602#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1103#L557true assume 1 == ~t6_pc~0; 401#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 809#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146#L569true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 211#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 931#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1052#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 400#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 349#L588true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 657#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258#L595true assume 1 == ~t8_pc~0; 1002#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 689#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 845#L607true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 506#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 934#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153#L614true assume !(1 == ~t9_pc~0); 451#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 101#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195#L626true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 671#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 238#L1212-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415#L1025true assume !(1 == ~M_E~0); 461#L1025-2true assume !(1 == ~T1_E~0); 595#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 745#L1035-1true assume !(1 == ~T3_E~0); 234#L1040-1true assume !(1 == ~T4_E~0); 729#L1045-1true assume !(1 == ~T5_E~0); 184#L1050-1true assume !(1 == ~T6_E~0); 293#L1055-1true assume !(1 == ~T7_E~0); 94#L1060-1true assume !(1 == ~T8_E~0); 125#L1065-1true assume !(1 == ~T9_E~0); 949#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 544#L1075-1true assume !(1 == ~E_2~0); 1086#L1080-1true assume !(1 == ~E_3~0); 536#L1085-1true assume !(1 == ~E_4~0); 839#L1090-1true assume !(1 == ~E_5~0); 967#L1095-1true assume !(1 == ~E_6~0); 576#L1100-1true assume !(1 == ~E_7~0); 583#L1105-1true assume !(1 == ~E_8~0); 82#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 265#L1115-1true assume { :end_inline_reset_delta_events } true; 206#L1396-2true [2021-12-19 19:17:32,376 INFO L793 eck$LassoCheckResult]: Loop: 206#L1396-2true assume !false; 950#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966#L897true assume false; 786#L912true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51#L634-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 971#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 174#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 278#L932-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 534#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 77#L942-3true assume !(0 == ~T5_E~0); 624#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 279#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 811#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 833#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 633#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 855#L972-3true assume 0 == ~E_2~0;~E_2~0 := 1; 538#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1089#L982-3true assume !(0 == ~E_4~0); 1061#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 244#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 360#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 242#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 494#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 95#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272#L443-30true assume 1 == ~m_pc~0; 111#L444-10true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 262#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 884#L455-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 946#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 711#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332#L462-30true assume !(1 == ~t1_pc~0); 801#L462-32true is_transmit1_triggered_~__retres1~1#1 := 0; 701#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L474-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 741#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1067#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323#L481-30true assume 1 == ~t2_pc~0; 157#L482-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 666#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185#L493-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141#L1156-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 552#L500-30true assume !(1 == ~t3_pc~0); 1068#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 362#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194#L512-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1026#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 291#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638#L519-30true assume 1 == ~t4_pc~0; 586#L520-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 404#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30#L531-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 411#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 926#L538-30true assume !(1 == ~t5_pc~0); 865#L538-32true is_transmit5_triggered_~__retres1~5#1 := 0; 281#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257#L550-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 661#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144#L557-30true assume !(1 == ~t6_pc~0); 368#L557-32true is_transmit6_triggered_~__retres1~6#1 := 0; 389#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430#L569-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1045#L1188-30true assume !(0 != activate_threads_~tmp___5~0#1); 152#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 511#L576-30true assume !(1 == ~t7_pc~0); 42#L576-32true is_transmit7_triggered_~__retres1~7#1 := 0; 384#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1074#L588-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 836#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 235#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215#L595-30true assume !(1 == ~t8_pc~0); 756#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 181#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47#L607-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 837#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1093#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 939#L614-30true assume 1 == ~t9_pc~0; 183#L615-10true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 640#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#L626-10true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 618#L1212-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 495#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 317#L1025-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 464#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 856#L1035-3true assume !(1 == ~T3_E~0); 1018#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1040#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 846#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 687#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 46#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 720#L1065-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 713#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 522#L1075-3true assume !(1 == ~E_2~0); 857#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 940#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 698#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1006#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 728#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 915#L1105-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 777#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 753#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 122#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50#L752-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 710#L1415true assume !(0 == start_simulation_~tmp~3#1); 408#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 970#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 413#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 598#L752-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1077#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1062#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 458#L1378true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 161#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 206#L1396-2true [2021-12-19 19:17:32,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2021-12-19 19:17:32,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,394 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403463492] [2021-12-19 19:17:32,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,643 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1403463492] [2021-12-19 19:17:32,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1403463492] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,644 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:32,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216028554] [2021-12-19 19:17:32,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,668 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:32,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:32,669 INFO L85 PathProgramCache]: Analyzing trace with hash -2065415498, now seen corresponding path program 1 times [2021-12-19 19:17:32,669 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:32,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450497479] [2021-12-19 19:17:32,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:32,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:32,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:32,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:32,735 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:32,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450497479] [2021-12-19 19:17:32,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450497479] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:32,736 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:32,736 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:32,742 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2081523585] [2021-12-19 19:17:32,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:32,744 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:32,744 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:32,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:32,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:32,800 INFO L87 Difference]: Start difference. First operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:32,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:32,892 INFO L93 Difference]: Finished difference Result 1100 states and 1636 transitions. [2021-12-19 19:17:32,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:32,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1100 states and 1636 transitions. [2021-12-19 19:17:32,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:32,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1100 states to 1094 states and 1630 transitions. [2021-12-19 19:17:32,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:32,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:32,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1630 transitions. [2021-12-19 19:17:32,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:32,950 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-19 19:17:32,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1630 transitions. [2021-12-19 19:17:33,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:33,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1630 transitions. [2021-12-19 19:17:33,025 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-19 19:17:33,025 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2021-12-19 19:17:33,025 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:33,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1630 transitions. [2021-12-19 19:17:33,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,048 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,048 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,049 INFO L791 eck$LassoCheckResult]: Stem: 3047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2648#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2649#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3178#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2998#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2999#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2815#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2816#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3255#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3162#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2870#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2654#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2655#L922 assume !(0 == ~M_E~0); 3300#L922-2 assume !(0 == ~T1_E~0); 3301#L927-1 assume !(0 == ~T2_E~0); 3055#L932-1 assume !(0 == ~T3_E~0); 2940#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2941#L942-1 assume !(0 == ~T5_E~0); 2997#L947-1 assume !(0 == ~T6_E~0); 3059#L952-1 assume !(0 == ~T7_E~0); 3060#L957-1 assume !(0 == ~T8_E~0); 3120#L962-1 assume !(0 == ~T9_E~0); 2916#L967-1 assume !(0 == ~E_1~0); 2917#L972-1 assume !(0 == ~E_2~0); 3183#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3184#L982-1 assume !(0 == ~E_4~0); 2424#L987-1 assume !(0 == ~E_5~0); 2425#L992-1 assume !(0 == ~E_6~0); 2433#L997-1 assume !(0 == ~E_7~0); 2847#L1002-1 assume !(0 == ~E_8~0); 2834#L1007-1 assume !(0 == ~E_9~0); 2222#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2223#L443 assume !(1 == ~m_pc~0); 3075#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3066#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3067#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2588#L1140 assume !(0 != activate_threads_~tmp~1#1); 2337#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2338#L462 assume 1 == ~t1_pc~0; 2966#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2933#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2308#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2309#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2796#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2797#L481 assume !(1 == ~t2_pc~0); 2583#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2582#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2937#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2676#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2677#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2769#L500 assume 1 == ~t3_pc~0; 2979#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2980#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3170#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3171#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2224#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2225#L519 assume 1 == ~t4_pc~0; 2523#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2524#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2768#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2628#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2629#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2391#L538 assume !(1 == ~t5_pc~0); 2392#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2298#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2299#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2567#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2568#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3105#L557 assume 1 == ~t6_pc~0; 2904#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2605#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2505#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2630#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3283#L576 assume !(1 == ~t7_pc~0); 2592#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2593#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2837#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2838#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3154#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2713#L595 assume 1 == ~t8_pc~0; 2714#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3172#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3173#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3022#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3023#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2516#L614 assume !(1 == ~t9_pc~0); 2517#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2416#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2417#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2596#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2678#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2679#L1025 assume !(1 == ~M_E~0); 2925#L1025-2 assume !(1 == ~T1_E~0); 2978#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3100#L1035-1 assume !(1 == ~T3_E~0); 2672#L1040-1 assume !(1 == ~T4_E~0); 2673#L1045-1 assume !(1 == ~T5_E~0); 2578#L1050-1 assume !(1 == ~T6_E~0); 2579#L1055-1 assume !(1 == ~T7_E~0); 2400#L1060-1 assume !(1 == ~T8_E~0); 2401#L1065-1 assume !(1 == ~T9_E~0); 2464#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3061#L1075-1 assume !(1 == ~E_2~0); 3062#L1080-1 assume !(1 == ~E_3~0); 3050#L1085-1 assume !(1 == ~E_4~0); 3051#L1090-1 assume !(1 == ~E_5~0); 3250#L1095-1 assume !(1 == ~E_6~0); 3084#L1100-1 assume !(1 == ~E_7~0); 3085#L1105-1 assume !(1 == ~E_8~0); 2373#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2374#L1115-1 assume { :end_inline_reset_delta_events } true; 2535#L1396-2 [2021-12-19 19:17:33,051 INFO L793 eck$LassoCheckResult]: Loop: 2535#L1396-2 assume !false; 2618#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2647#L897 assume !false; 3290#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3197#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2245#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2246#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3245#L766 assume !(0 != eval_~tmp~0#1); 3231#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2315#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2316#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2830#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2559#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2560#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2738#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2365#L942-3 assume !(0 == ~T5_E~0); 2366#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2739#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2740#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3241#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3132#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3133#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3053#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3054#L982-3 assume !(0 == ~E_4~0); 3302#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2689#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2690#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2684#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2685#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2402#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2403#L443-30 assume 1 == ~m_pc~0; 2436#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2437#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2720#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3268#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3187#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2820#L462-30 assume 1 == ~t1_pc~0; 2664#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2666#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3168#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3169#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3209#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2807#L481-30 assume !(1 == ~t2_pc~0); 2528#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2527#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2580#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2493#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2494#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2774#L500-30 assume 1 == ~t3_pc~0; 2531#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2532#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2594#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2595#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L519-30 assume 1 == ~t4_pc~0; 3093#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2909#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2271#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2272#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2921#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3034#L538-30 assume 1 == ~t5_pc~0; 2412#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2413#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2711#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2712#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2489#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2490#L557-30 assume 1 == ~t6_pc~0; 2210#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2888#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2948#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2514#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L576-30 assume 1 == ~t7_pc~0; 3027#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2297#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2882#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3248#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2674#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2637#L595-30 assume !(1 == ~t8_pc~0); 2638#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2569#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2306#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2307#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3249#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3285#L614-30 assume !(1 == ~t9_pc~0); 2576#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2575#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2710#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2404#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2405#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3013#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2798#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2799#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2983#L1035-3 assume !(1 == ~T3_E~0); 3258#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3298#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3254#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3167#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2304#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2305#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3189#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3035#L1075-3 assume !(1 == ~E_2~0); 3036#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3259#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3180#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3200#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3201#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2452#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2453#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3212#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2321#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2310#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1415 assume !(0 == start_simulation_~tmp~3#1); 2912#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2913#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2361#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2923#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3102#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3303#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2971#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2534#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2535#L1396-2 [2021-12-19 19:17:33,054 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2021-12-19 19:17:33,054 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,056 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440547096] [2021-12-19 19:17:33,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,151 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,151 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440547096] [2021-12-19 19:17:33,151 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440547096] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,151 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,151 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,151 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049341162] [2021-12-19 19:17:33,152 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,152 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,153 INFO L85 PathProgramCache]: Analyzing trace with hash -1392985774, now seen corresponding path program 1 times [2021-12-19 19:17:33,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349307915] [2021-12-19 19:17:33,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,297 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349307915] [2021-12-19 19:17:33,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349307915] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,298 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533588853] [2021-12-19 19:17:33,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,299 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:33,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:33,300 INFO L87 Difference]: Start difference. First operand 1094 states and 1630 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,325 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2021-12-19 19:17:33,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:33,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1629 transitions. [2021-12-19 19:17:33,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1629 transitions. [2021-12-19 19:17:33,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:33,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:33,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1629 transitions. [2021-12-19 19:17:33,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,346 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-19 19:17:33,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1629 transitions. [2021-12-19 19:17:33,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:33,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1629 transitions. [2021-12-19 19:17:33,381 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-19 19:17:33,381 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2021-12-19 19:17:33,381 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:33,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1629 transitions. [2021-12-19 19:17:33,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,393 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,395 INFO L791 eck$LassoCheckResult]: Stem: 5242#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 5243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4843#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4844#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5390#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5391#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5373#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5193#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5194#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5010#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5011#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5450#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5357#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5065#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4850#L922 assume !(0 == ~M_E~0); 5495#L922-2 assume !(0 == ~T1_E~0); 5496#L927-1 assume !(0 == ~T2_E~0); 5250#L932-1 assume !(0 == ~T3_E~0); 5135#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5136#L942-1 assume !(0 == ~T5_E~0); 5192#L947-1 assume !(0 == ~T6_E~0); 5254#L952-1 assume !(0 == ~T7_E~0); 5255#L957-1 assume !(0 == ~T8_E~0); 5317#L962-1 assume !(0 == ~T9_E~0); 5111#L967-1 assume !(0 == ~E_1~0); 5112#L972-1 assume !(0 == ~E_2~0); 5378#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5379#L982-1 assume !(0 == ~E_4~0); 4619#L987-1 assume !(0 == ~E_5~0); 4620#L992-1 assume !(0 == ~E_6~0); 4628#L997-1 assume !(0 == ~E_7~0); 5042#L1002-1 assume !(0 == ~E_8~0); 5029#L1007-1 assume !(0 == ~E_9~0); 4417#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L443 assume !(1 == ~m_pc~0); 5270#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5261#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5262#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4783#L1140 assume !(0 != activate_threads_~tmp~1#1); 4532#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4533#L462 assume 1 == ~t1_pc~0; 5161#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5128#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4503#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4504#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 4991#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4992#L481 assume !(1 == ~t2_pc~0); 4778#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4777#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5132#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4871#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4872#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4964#L500 assume 1 == ~t3_pc~0; 5174#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5175#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5365#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5366#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4419#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4420#L519 assume 1 == ~t4_pc~0; 4718#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4719#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4963#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4825#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4826#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4586#L538 assume !(1 == ~t5_pc~0); 4587#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4493#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4494#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4762#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4763#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5302#L557 assume 1 == ~t6_pc~0; 5099#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4700#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4701#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4827#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5478#L576 assume !(1 == ~t7_pc~0); 4787#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4788#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5033#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5349#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4908#L595 assume 1 == ~t8_pc~0; 4909#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5367#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5368#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5217#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5218#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4711#L614 assume !(1 == ~t9_pc~0); 4712#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4611#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4612#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4791#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4873#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4874#L1025 assume !(1 == ~M_E~0); 5120#L1025-2 assume !(1 == ~T1_E~0); 5173#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5295#L1035-1 assume !(1 == ~T3_E~0); 4868#L1040-1 assume !(1 == ~T4_E~0); 4869#L1045-1 assume !(1 == ~T5_E~0); 4773#L1050-1 assume !(1 == ~T6_E~0); 4774#L1055-1 assume !(1 == ~T7_E~0); 4595#L1060-1 assume !(1 == ~T8_E~0); 4596#L1065-1 assume !(1 == ~T9_E~0); 4659#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5256#L1075-1 assume !(1 == ~E_2~0); 5257#L1080-1 assume !(1 == ~E_3~0); 5245#L1085-1 assume !(1 == ~E_4~0); 5246#L1090-1 assume !(1 == ~E_5~0); 5445#L1095-1 assume !(1 == ~E_6~0); 5279#L1100-1 assume !(1 == ~E_7~0); 5280#L1105-1 assume !(1 == ~E_8~0); 4568#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4569#L1115-1 assume { :end_inline_reset_delta_events } true; 4730#L1396-2 [2021-12-19 19:17:33,396 INFO L793 eck$LassoCheckResult]: Loop: 4730#L1396-2 assume !false; 4813#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4842#L897 assume !false; 5485#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5392#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4442#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4443#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5440#L766 assume !(0 != eval_~tmp~0#1); 5426#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4510#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4511#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5025#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4754#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4755#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4933#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4560#L942-3 assume !(0 == ~T5_E~0); 4561#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4934#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4935#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5436#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5327#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5328#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5248#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5249#L982-3 assume !(0 == ~E_4~0); 5497#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4884#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4885#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4882#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4883#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4597#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4598#L443-30 assume 1 == ~m_pc~0; 4631#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4632#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4915#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5382#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5015#L462-30 assume 1 == ~t1_pc~0; 4860#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4862#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5363#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5364#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5404#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5002#L481-30 assume 1 == ~t2_pc~0; 4721#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4722#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4775#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4688#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4689#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4969#L500-30 assume 1 == ~t3_pc~0; 4726#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4727#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4789#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4790#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4954#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4955#L519-30 assume 1 == ~t4_pc~0; 5289#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5104#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4467#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5116#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5229#L538-30 assume !(1 == ~t5_pc~0); 4609#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 4608#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4906#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4907#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L557-30 assume 1 == ~t6_pc~0; 4405#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4406#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5083#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5137#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 4709#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4710#L576-30 assume 1 == ~t7_pc~0; 5222#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4487#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5076#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5443#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4867#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4832#L595-30 assume !(1 == ~t8_pc~0); 4833#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4764#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5444#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5480#L614-30 assume 1 == ~t9_pc~0; 4769#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4770#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4905#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4599#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4600#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5208#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4993#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4994#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5178#L1035-3 assume !(1 == ~T3_E~0); 5453#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5493#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5449#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5362#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4499#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4500#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5384#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5230#L1075-3 assume !(1 == ~E_2~0); 5231#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5454#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5375#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5376#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5395#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5396#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4647#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4648#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5408#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4516#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4505#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4506#L1415 assume !(0 == start_simulation_~tmp~3#1); 5108#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5109#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4556#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5118#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 5297#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5498#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5168#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4729#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4730#L1396-2 [2021-12-19 19:17:33,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,399 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2021-12-19 19:17:33,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862808494] [2021-12-19 19:17:33,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,401 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862808494] [2021-12-19 19:17:33,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862808494] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,467 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293675873] [2021-12-19 19:17:33,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,467 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 1 times [2021-12-19 19:17:33,468 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,469 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275942371] [2021-12-19 19:17:33,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,469 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,533 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275942371] [2021-12-19 19:17:33,533 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275942371] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,533 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,533 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694911958] [2021-12-19 19:17:33,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,534 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,534 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:33,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:33,535 INFO L87 Difference]: Start difference. First operand 1094 states and 1629 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,557 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2021-12-19 19:17:33,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:33,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1628 transitions. [2021-12-19 19:17:33,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1628 transitions. [2021-12-19 19:17:33,572 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:33,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:33,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1628 transitions. [2021-12-19 19:17:33,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,576 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-19 19:17:33,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1628 transitions. [2021-12-19 19:17:33,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:33,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1628 transitions. [2021-12-19 19:17:33,594 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-19 19:17:33,594 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2021-12-19 19:17:33,594 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:33,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1628 transitions. [2021-12-19 19:17:33,599 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,601 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,601 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,602 INFO L791 eck$LassoCheckResult]: Stem: 7437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 7438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7038#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7039#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7585#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7586#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7568#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7388#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7389#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7205#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7206#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7646#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7552#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7260#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7044#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7045#L922 assume !(0 == ~M_E~0); 7690#L922-2 assume !(0 == ~T1_E~0); 7691#L927-1 assume !(0 == ~T2_E~0); 7445#L932-1 assume !(0 == ~T3_E~0); 7330#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7331#L942-1 assume !(0 == ~T5_E~0); 7387#L947-1 assume !(0 == ~T6_E~0); 7449#L952-1 assume !(0 == ~T7_E~0); 7450#L957-1 assume !(0 == ~T8_E~0); 7512#L962-1 assume !(0 == ~T9_E~0); 7306#L967-1 assume !(0 == ~E_1~0); 7307#L972-1 assume !(0 == ~E_2~0); 7573#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7574#L982-1 assume !(0 == ~E_4~0); 6814#L987-1 assume !(0 == ~E_5~0); 6815#L992-1 assume !(0 == ~E_6~0); 6823#L997-1 assume !(0 == ~E_7~0); 7239#L1002-1 assume !(0 == ~E_8~0); 7224#L1007-1 assume !(0 == ~E_9~0); 6612#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6613#L443 assume !(1 == ~m_pc~0); 7465#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7456#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7457#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6978#L1140 assume !(0 != activate_threads_~tmp~1#1); 6727#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6728#L462 assume 1 == ~t1_pc~0; 7356#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7324#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6698#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6699#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7186#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7187#L481 assume !(1 == ~t2_pc~0); 6973#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6972#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7066#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7067#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7161#L500 assume 1 == ~t3_pc~0; 7369#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7370#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7560#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7561#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6614#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6615#L519 assume 1 == ~t4_pc~0; 6913#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6914#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7158#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7020#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7021#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6781#L538 assume !(1 == ~t5_pc~0); 6782#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6688#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6689#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6957#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6958#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7497#L557 assume 1 == ~t6_pc~0; 7294#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6995#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6897#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6898#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7022#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7673#L576 assume !(1 == ~t7_pc~0); 6982#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6983#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7227#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7228#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7544#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7103#L595 assume 1 == ~t8_pc~0; 7104#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7562#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7563#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7412#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7413#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6906#L614 assume !(1 == ~t9_pc~0); 6907#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6806#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6807#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6986#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7068#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7069#L1025 assume !(1 == ~M_E~0); 7315#L1025-2 assume !(1 == ~T1_E~0); 7368#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7490#L1035-1 assume !(1 == ~T3_E~0); 7063#L1040-1 assume !(1 == ~T4_E~0); 7064#L1045-1 assume !(1 == ~T5_E~0); 6968#L1050-1 assume !(1 == ~T6_E~0); 6969#L1055-1 assume !(1 == ~T7_E~0); 6790#L1060-1 assume !(1 == ~T8_E~0); 6791#L1065-1 assume !(1 == ~T9_E~0); 6854#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7451#L1075-1 assume !(1 == ~E_2~0); 7452#L1080-1 assume !(1 == ~E_3~0); 7440#L1085-1 assume !(1 == ~E_4~0); 7441#L1090-1 assume !(1 == ~E_5~0); 7640#L1095-1 assume !(1 == ~E_6~0); 7474#L1100-1 assume !(1 == ~E_7~0); 7475#L1105-1 assume !(1 == ~E_8~0); 6763#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6764#L1115-1 assume { :end_inline_reset_delta_events } true; 6925#L1396-2 [2021-12-19 19:17:33,602 INFO L793 eck$LassoCheckResult]: Loop: 6925#L1396-2 assume !false; 7008#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7037#L897 assume !false; 7680#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7587#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6637#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6638#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7635#L766 assume !(0 != eval_~tmp~0#1); 7621#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6705#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6706#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7222#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6949#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6950#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7128#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6755#L942-3 assume !(0 == ~T5_E~0); 6756#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7129#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7130#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7631#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7522#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7523#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7443#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7444#L982-3 assume !(0 == ~E_4~0); 7692#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7079#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7080#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7077#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7078#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6792#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6793#L443-30 assume 1 == ~m_pc~0; 6826#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6827#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7110#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7658#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7577#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7210#L462-30 assume !(1 == ~t1_pc~0); 7056#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 7057#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7558#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7559#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7599#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7197#L481-30 assume 1 == ~t2_pc~0; 6916#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6917#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6970#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6886#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6887#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7164#L500-30 assume 1 == ~t3_pc~0; 6921#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6922#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6984#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6985#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7147#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7148#L519-30 assume !(1 == ~t4_pc~0); 7322#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 7299#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6661#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6662#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7311#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7424#L538-30 assume 1 == ~t5_pc~0; 6802#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6803#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7101#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7102#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6879#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6880#L557-30 assume 1 == ~t6_pc~0; 6600#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6601#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7278#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7332#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 6904#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6905#L576-30 assume 1 == ~t7_pc~0; 7417#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6685#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7271#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7638#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7062#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7027#L595-30 assume !(1 == ~t8_pc~0); 7028#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 6961#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6696#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6697#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7639#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7675#L614-30 assume 1 == ~t9_pc~0; 6964#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6965#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7100#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6794#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6795#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7403#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7188#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7189#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7373#L1035-3 assume !(1 == ~T3_E~0); 7648#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7688#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7644#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7557#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6694#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6695#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7579#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7425#L1075-3 assume !(1 == ~E_2~0); 7426#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7649#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7570#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7571#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7590#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7591#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6842#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6843#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7603#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6711#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6700#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6701#L1415 assume !(0 == start_simulation_~tmp~3#1); 7303#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7304#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6751#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7313#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 7492#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7693#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7363#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6924#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6925#L1396-2 [2021-12-19 19:17:33,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2021-12-19 19:17:33,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,603 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983124428] [2021-12-19 19:17:33,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,604 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983124428] [2021-12-19 19:17:33,632 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983124428] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,632 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914184513] [2021-12-19 19:17:33,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,633 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,634 INFO L85 PathProgramCache]: Analyzing trace with hash -173500974, now seen corresponding path program 1 times [2021-12-19 19:17:33,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629385402] [2021-12-19 19:17:33,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,684 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,685 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629385402] [2021-12-19 19:17:33,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629385402] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,686 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,686 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,686 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155289245] [2021-12-19 19:17:33,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,687 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,687 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:33,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:33,688 INFO L87 Difference]: Start difference. First operand 1094 states and 1628 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,709 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2021-12-19 19:17:33,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:33,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1627 transitions. [2021-12-19 19:17:33,716 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1627 transitions. [2021-12-19 19:17:33,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:33,722 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:33,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1627 transitions. [2021-12-19 19:17:33,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,724 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-19 19:17:33,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1627 transitions. [2021-12-19 19:17:33,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:33,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1627 transitions. [2021-12-19 19:17:33,743 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-19 19:17:33,743 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2021-12-19 19:17:33,743 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:33,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1627 transitions. [2021-12-19 19:17:33,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,751 INFO L791 eck$LassoCheckResult]: Stem: 9632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9233#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9234#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9780#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9781#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9763#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9583#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9584#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9400#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9401#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9841#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9747#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9455#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9239#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9240#L922 assume !(0 == ~M_E~0); 9885#L922-2 assume !(0 == ~T1_E~0); 9886#L927-1 assume !(0 == ~T2_E~0); 9640#L932-1 assume !(0 == ~T3_E~0); 9525#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9526#L942-1 assume !(0 == ~T5_E~0); 9582#L947-1 assume !(0 == ~T6_E~0); 9644#L952-1 assume !(0 == ~T7_E~0); 9645#L957-1 assume !(0 == ~T8_E~0); 9707#L962-1 assume !(0 == ~T9_E~0); 9501#L967-1 assume !(0 == ~E_1~0); 9502#L972-1 assume !(0 == ~E_2~0); 9768#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9769#L982-1 assume !(0 == ~E_4~0); 9009#L987-1 assume !(0 == ~E_5~0); 9010#L992-1 assume !(0 == ~E_6~0); 9018#L997-1 assume !(0 == ~E_7~0); 9434#L1002-1 assume !(0 == ~E_8~0); 9420#L1007-1 assume !(0 == ~E_9~0); 8807#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8808#L443 assume !(1 == ~m_pc~0); 9660#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9651#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9652#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9173#L1140 assume !(0 != activate_threads_~tmp~1#1); 8922#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8923#L462 assume 1 == ~t1_pc~0; 9551#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9519#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8893#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8894#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9381#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9382#L481 assume !(1 == ~t2_pc~0); 9168#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9167#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9522#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9261#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9262#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9356#L500 assume 1 == ~t3_pc~0; 9564#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9755#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9756#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8812#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8813#L519 assume 1 == ~t4_pc~0; 9111#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9112#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9353#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9215#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9216#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8976#L538 assume !(1 == ~t5_pc~0); 8977#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8883#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8884#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9152#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9153#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9692#L557 assume 1 == ~t6_pc~0; 9489#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9190#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9092#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9093#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9217#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9868#L576 assume !(1 == ~t7_pc~0); 9177#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9178#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9422#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9423#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9739#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9298#L595 assume 1 == ~t8_pc~0; 9299#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9757#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9758#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9607#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9608#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9101#L614 assume !(1 == ~t9_pc~0); 9102#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9001#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9002#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9181#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9263#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9264#L1025 assume !(1 == ~M_E~0); 9510#L1025-2 assume !(1 == ~T1_E~0); 9563#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9685#L1035-1 assume !(1 == ~T3_E~0); 9258#L1040-1 assume !(1 == ~T4_E~0); 9259#L1045-1 assume !(1 == ~T5_E~0); 9163#L1050-1 assume !(1 == ~T6_E~0); 9164#L1055-1 assume !(1 == ~T7_E~0); 8985#L1060-1 assume !(1 == ~T8_E~0); 8986#L1065-1 assume !(1 == ~T9_E~0); 9049#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9646#L1075-1 assume !(1 == ~E_2~0); 9647#L1080-1 assume !(1 == ~E_3~0); 9635#L1085-1 assume !(1 == ~E_4~0); 9636#L1090-1 assume !(1 == ~E_5~0); 9835#L1095-1 assume !(1 == ~E_6~0); 9669#L1100-1 assume !(1 == ~E_7~0); 9670#L1105-1 assume !(1 == ~E_8~0); 8958#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 8959#L1115-1 assume { :end_inline_reset_delta_events } true; 9120#L1396-2 [2021-12-19 19:17:33,751 INFO L793 eck$LassoCheckResult]: Loop: 9120#L1396-2 assume !false; 9206#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9232#L897 assume !false; 9875#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9782#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8832#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8833#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9830#L766 assume !(0 != eval_~tmp~0#1); 9816#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8900#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8901#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9417#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9144#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9145#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9323#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8950#L942-3 assume !(0 == ~T5_E~0); 8951#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9324#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9325#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9826#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9717#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9718#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9638#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9639#L982-3 assume !(0 == ~E_4~0); 9887#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9274#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9275#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9272#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9273#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8987#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8988#L443-30 assume 1 == ~m_pc~0; 9021#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9022#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9305#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9853#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9773#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9405#L462-30 assume 1 == ~t1_pc~0; 9250#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9252#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9752#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9753#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9794#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9392#L481-30 assume 1 == ~t2_pc~0; 9108#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9109#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9165#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9078#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9079#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9359#L500-30 assume 1 == ~t3_pc~0; 9116#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9117#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9179#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9180#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9342#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9343#L519-30 assume !(1 == ~t4_pc~0); 9517#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9494#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8856#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8857#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9506#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9619#L538-30 assume 1 == ~t5_pc~0; 8997#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8998#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9296#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9297#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9074#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9075#L557-30 assume 1 == ~t6_pc~0; 8795#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8796#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9473#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9527#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 9099#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9100#L576-30 assume 1 == ~t7_pc~0; 9612#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8880#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9467#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9833#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9257#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9222#L595-30 assume !(1 == ~t8_pc~0); 9223#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9158#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8891#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8892#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9834#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9870#L614-30 assume 1 == ~t9_pc~0; 9160#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9161#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9295#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8989#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8990#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9598#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9383#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9384#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9568#L1035-3 assume !(1 == ~T3_E~0); 9843#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9883#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9839#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9754#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8889#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8890#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9774#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9620#L1075-3 assume !(1 == ~E_2~0); 9621#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9844#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9765#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9766#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9785#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9786#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9037#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9798#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8906#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8895#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 8896#L1415 assume !(0 == start_simulation_~tmp~3#1); 9499#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9500#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8946#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9508#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 9687#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9888#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9119#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9120#L1396-2 [2021-12-19 19:17:33,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,752 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2021-12-19 19:17:33,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686366851] [2021-12-19 19:17:33,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,782 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686366851] [2021-12-19 19:17:33,783 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686366851] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,783 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,783 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326990491] [2021-12-19 19:17:33,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,784 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,785 INFO L85 PathProgramCache]: Analyzing trace with hash -1095421325, now seen corresponding path program 1 times [2021-12-19 19:17:33,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717810053] [2021-12-19 19:17:33,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,832 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717810053] [2021-12-19 19:17:33,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717810053] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,833 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,833 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,833 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407061015] [2021-12-19 19:17:33,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,834 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,834 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:33,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:33,835 INFO L87 Difference]: Start difference. First operand 1094 states and 1627 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:33,862 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2021-12-19 19:17:33,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:33,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1626 transitions. [2021-12-19 19:17:33,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1626 transitions. [2021-12-19 19:17:33,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:33,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:33,877 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1626 transitions. [2021-12-19 19:17:33,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:33,879 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-19 19:17:33,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1626 transitions. [2021-12-19 19:17:33,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:33,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:33,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1626 transitions. [2021-12-19 19:17:33,897 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-19 19:17:33,897 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2021-12-19 19:17:33,897 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:33,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1626 transitions. [2021-12-19 19:17:33,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:33,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:33,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:33,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:33,904 INFO L791 eck$LassoCheckResult]: Stem: 11827#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 11428#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11429#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11975#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 11976#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11958#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11778#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11779#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11595#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11596#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12036#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11942#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11650#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11434#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11435#L922 assume !(0 == ~M_E~0); 12080#L922-2 assume !(0 == ~T1_E~0); 12081#L927-1 assume !(0 == ~T2_E~0); 11835#L932-1 assume !(0 == ~T3_E~0); 11720#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11721#L942-1 assume !(0 == ~T5_E~0); 11777#L947-1 assume !(0 == ~T6_E~0); 11839#L952-1 assume !(0 == ~T7_E~0); 11840#L957-1 assume !(0 == ~T8_E~0); 11902#L962-1 assume !(0 == ~T9_E~0); 11696#L967-1 assume !(0 == ~E_1~0); 11697#L972-1 assume !(0 == ~E_2~0); 11963#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 11964#L982-1 assume !(0 == ~E_4~0); 11204#L987-1 assume !(0 == ~E_5~0); 11205#L992-1 assume !(0 == ~E_6~0); 11213#L997-1 assume !(0 == ~E_7~0); 11629#L1002-1 assume !(0 == ~E_8~0); 11615#L1007-1 assume !(0 == ~E_9~0); 11002#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11003#L443 assume !(1 == ~m_pc~0); 11855#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11846#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11847#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11368#L1140 assume !(0 != activate_threads_~tmp~1#1); 11117#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11118#L462 assume 1 == ~t1_pc~0; 11746#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11716#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11088#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11089#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11576#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11577#L481 assume !(1 == ~t2_pc~0); 11363#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11362#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11717#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11456#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11457#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11551#L500 assume 1 == ~t3_pc~0; 11759#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11760#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11950#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11951#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11007#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11008#L519 assume 1 == ~t4_pc~0; 11306#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11307#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11548#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11410#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11411#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11171#L538 assume !(1 == ~t5_pc~0); 11172#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11078#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11079#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11347#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11348#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11887#L557 assume 1 == ~t6_pc~0; 11684#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11385#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11287#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11288#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11412#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12063#L576 assume !(1 == ~t7_pc~0); 11372#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11373#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11617#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 11934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11495#L595 assume 1 == ~t8_pc~0; 11496#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11952#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11953#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11802#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11803#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11296#L614 assume !(1 == ~t9_pc~0); 11297#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11196#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11197#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11376#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11458#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11459#L1025 assume !(1 == ~M_E~0); 11705#L1025-2 assume !(1 == ~T1_E~0); 11758#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11881#L1035-1 assume !(1 == ~T3_E~0); 11453#L1040-1 assume !(1 == ~T4_E~0); 11454#L1045-1 assume !(1 == ~T5_E~0); 11358#L1050-1 assume !(1 == ~T6_E~0); 11359#L1055-1 assume !(1 == ~T7_E~0); 11180#L1060-1 assume !(1 == ~T8_E~0); 11181#L1065-1 assume !(1 == ~T9_E~0); 11244#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11841#L1075-1 assume !(1 == ~E_2~0); 11842#L1080-1 assume !(1 == ~E_3~0); 11830#L1085-1 assume !(1 == ~E_4~0); 11831#L1090-1 assume !(1 == ~E_5~0); 12030#L1095-1 assume !(1 == ~E_6~0); 11864#L1100-1 assume !(1 == ~E_7~0); 11865#L1105-1 assume !(1 == ~E_8~0); 11153#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11154#L1115-1 assume { :end_inline_reset_delta_events } true; 11315#L1396-2 [2021-12-19 19:17:33,904 INFO L793 eck$LassoCheckResult]: Loop: 11315#L1396-2 assume !false; 11401#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11427#L897 assume !false; 12070#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11977#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11027#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11028#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12025#L766 assume !(0 != eval_~tmp~0#1); 12011#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11095#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11096#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11612#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11339#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11340#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11518#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11145#L942-3 assume !(0 == ~T5_E~0); 11146#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11519#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11520#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12021#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11912#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11913#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11833#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11834#L982-3 assume !(0 == ~E_4~0); 12082#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11469#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11470#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11464#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11465#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11182#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11183#L443-30 assume 1 == ~m_pc~0; 11216#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11217#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11500#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12048#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11967#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11600#L462-30 assume 1 == ~t1_pc~0; 11444#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11446#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11947#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11948#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11989#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11587#L481-30 assume 1 == ~t2_pc~0; 11303#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11304#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11360#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11273#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11274#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11554#L500-30 assume !(1 == ~t3_pc~0); 11313#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 11312#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11375#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11537#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11538#L519-30 assume 1 == ~t4_pc~0; 11873#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11689#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11051#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11052#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11701#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11814#L538-30 assume 1 == ~t5_pc~0; 11192#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11193#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11491#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11492#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11269#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11270#L557-30 assume !(1 == ~t6_pc~0); 10992#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 10991#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11668#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11722#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 11294#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11295#L576-30 assume !(1 == ~t7_pc~0); 11076#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 11077#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11662#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12028#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11452#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11417#L595-30 assume !(1 == ~t8_pc~0); 11418#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11353#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11086#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11087#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12029#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12065#L614-30 assume 1 == ~t9_pc~0; 11355#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11356#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11490#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11184#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11793#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11578#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11579#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11763#L1035-3 assume !(1 == ~T3_E~0); 12038#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12078#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12034#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11949#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11084#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11085#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11815#L1075-3 assume !(1 == ~E_2~0); 11816#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12039#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11960#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11961#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11981#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11232#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11233#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11993#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11101#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11090#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11091#L1415 assume !(0 == start_simulation_~tmp~3#1); 11694#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11695#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11141#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11703#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11882#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12083#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11753#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11314#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11315#L1396-2 [2021-12-19 19:17:33,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,905 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2021-12-19 19:17:33,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,906 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897321243] [2021-12-19 19:17:33,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,932 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897321243] [2021-12-19 19:17:33,933 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897321243] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,933 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,933 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,933 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397553246] [2021-12-19 19:17:33,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,934 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:33,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:33,936 INFO L85 PathProgramCache]: Analyzing trace with hash 1306266033, now seen corresponding path program 1 times [2021-12-19 19:17:33,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:33,940 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515498727] [2021-12-19 19:17:33,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:33,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:33,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:33,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:33,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:33,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515498727] [2021-12-19 19:17:33,993 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515498727] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:33,994 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:33,994 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:33,995 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619348485] [2021-12-19 19:17:33,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:33,996 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:33,996 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:33,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:33,997 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:33,997 INFO L87 Difference]: Start difference. First operand 1094 states and 1626 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,017 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2021-12-19 19:17:34,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:34,020 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1625 transitions. [2021-12-19 19:17:34,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1625 transitions. [2021-12-19 19:17:34,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:34,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:34,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1625 transitions. [2021-12-19 19:17:34,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,033 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-19 19:17:34,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1625 transitions. [2021-12-19 19:17:34,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:34,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1625 transitions. [2021-12-19 19:17:34,052 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-19 19:17:34,052 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2021-12-19 19:17:34,052 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:34,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1625 transitions. [2021-12-19 19:17:34,057 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,059 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,060 INFO L791 eck$LassoCheckResult]: Stem: 14022#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 14023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 13623#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13624#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14170#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14171#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14153#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13973#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13974#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13790#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13791#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14231#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14137#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13845#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13629#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13630#L922 assume !(0 == ~M_E~0); 14275#L922-2 assume !(0 == ~T1_E~0); 14276#L927-1 assume !(0 == ~T2_E~0); 14030#L932-1 assume !(0 == ~T3_E~0); 13915#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13916#L942-1 assume !(0 == ~T5_E~0); 13972#L947-1 assume !(0 == ~T6_E~0); 14034#L952-1 assume !(0 == ~T7_E~0); 14035#L957-1 assume !(0 == ~T8_E~0); 14098#L962-1 assume !(0 == ~T9_E~0); 13891#L967-1 assume !(0 == ~E_1~0); 13892#L972-1 assume !(0 == ~E_2~0); 14158#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14159#L982-1 assume !(0 == ~E_4~0); 13401#L987-1 assume !(0 == ~E_5~0); 13402#L992-1 assume !(0 == ~E_6~0); 13408#L997-1 assume !(0 == ~E_7~0); 13824#L1002-1 assume !(0 == ~E_8~0); 13810#L1007-1 assume !(0 == ~E_9~0); 13197#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13198#L443 assume !(1 == ~m_pc~0); 14050#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14041#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14042#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13563#L1140 assume !(0 != activate_threads_~tmp~1#1); 13312#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13313#L462 assume 1 == ~t1_pc~0; 13941#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13911#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13283#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13771#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13772#L481 assume !(1 == ~t2_pc~0); 13558#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13557#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13912#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13651#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13652#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13746#L500 assume 1 == ~t3_pc~0; 13954#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13955#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14145#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14146#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13202#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13203#L519 assume 1 == ~t4_pc~0; 13501#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13502#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13743#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13605#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13606#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13366#L538 assume !(1 == ~t5_pc~0); 13367#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13273#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13274#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13542#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13543#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14082#L557 assume 1 == ~t6_pc~0; 13879#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13580#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13484#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13485#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13607#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14258#L576 assume !(1 == ~t7_pc~0); 13567#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13568#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13812#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13813#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14129#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13690#L595 assume 1 == ~t8_pc~0; 13691#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14147#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14148#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13997#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 13998#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13491#L614 assume !(1 == ~t9_pc~0); 13492#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13391#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13392#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13571#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13653#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13654#L1025 assume !(1 == ~M_E~0); 13900#L1025-2 assume !(1 == ~T1_E~0); 13953#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14076#L1035-1 assume !(1 == ~T3_E~0); 13648#L1040-1 assume !(1 == ~T4_E~0); 13649#L1045-1 assume !(1 == ~T5_E~0); 13553#L1050-1 assume !(1 == ~T6_E~0); 13554#L1055-1 assume !(1 == ~T7_E~0); 13375#L1060-1 assume !(1 == ~T8_E~0); 13376#L1065-1 assume !(1 == ~T9_E~0); 13439#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14036#L1075-1 assume !(1 == ~E_2~0); 14037#L1080-1 assume !(1 == ~E_3~0); 14025#L1085-1 assume !(1 == ~E_4~0); 14026#L1090-1 assume !(1 == ~E_5~0); 14225#L1095-1 assume !(1 == ~E_6~0); 14059#L1100-1 assume !(1 == ~E_7~0); 14060#L1105-1 assume !(1 == ~E_8~0); 13348#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13349#L1115-1 assume { :end_inline_reset_delta_events } true; 13510#L1396-2 [2021-12-19 19:17:34,060 INFO L793 eck$LassoCheckResult]: Loop: 13510#L1396-2 assume !false; 13596#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13620#L897 assume !false; 14265#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14172#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13222#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13223#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14220#L766 assume !(0 != eval_~tmp~0#1); 14206#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13290#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13291#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13807#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13534#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13535#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13713#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13340#L942-3 assume !(0 == ~T5_E~0); 13341#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13714#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13715#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14216#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14107#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14108#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14028#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14029#L982-3 assume !(0 == ~E_4~0); 14277#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13664#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13665#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13659#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13660#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13377#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13378#L443-30 assume 1 == ~m_pc~0; 13411#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13412#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13695#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14243#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14162#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13795#L462-30 assume 1 == ~t1_pc~0; 13639#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13641#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14142#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14143#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14184#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13782#L481-30 assume 1 == ~t2_pc~0; 13498#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13499#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13555#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13468#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13469#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13749#L500-30 assume 1 == ~t3_pc~0; 13506#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13507#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13569#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13570#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13732#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13733#L519-30 assume 1 == ~t4_pc~0; 14068#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13884#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13246#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13247#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13896#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14009#L538-30 assume 1 == ~t5_pc~0; 13387#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13388#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13686#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13687#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13464#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13465#L557-30 assume 1 == ~t6_pc~0; 13185#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13186#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13863#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13920#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 13489#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13490#L576-30 assume 1 == ~t7_pc~0; 14002#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13272#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13857#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14223#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13647#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13612#L595-30 assume !(1 == ~t8_pc~0); 13613#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13548#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13281#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13282#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14224#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14260#L614-30 assume !(1 == ~t9_pc~0); 13552#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 13551#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13685#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13379#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13380#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13988#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13773#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13958#L1035-3 assume !(1 == ~T3_E~0); 14233#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14273#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14229#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14144#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13279#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13280#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14164#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14010#L1075-3 assume !(1 == ~E_2~0); 14011#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14234#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14155#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14156#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14175#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14176#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13427#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13428#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14189#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13296#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13285#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13286#L1415 assume !(0 == start_simulation_~tmp~3#1); 13889#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13890#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13336#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13898#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 14077#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14278#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13948#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13509#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13510#L1396-2 [2021-12-19 19:17:34,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,061 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2021-12-19 19:17:34,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906628205] [2021-12-19 19:17:34,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,087 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906628205] [2021-12-19 19:17:34,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906628205] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,088 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066180075] [2021-12-19 19:17:34,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,088 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1885053619, now seen corresponding path program 1 times [2021-12-19 19:17:34,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [551749519] [2021-12-19 19:17:34,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,124 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [551749519] [2021-12-19 19:17:34,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [551749519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,124 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094843712] [2021-12-19 19:17:34,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,125 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,126 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:34,126 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:34,126 INFO L87 Difference]: Start difference. First operand 1094 states and 1625 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,155 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2021-12-19 19:17:34,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:34,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1624 transitions. [2021-12-19 19:17:34,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1624 transitions. [2021-12-19 19:17:34,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:34,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:34,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1624 transitions. [2021-12-19 19:17:34,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,172 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-19 19:17:34,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1624 transitions. [2021-12-19 19:17:34,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:34,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1624 transitions. [2021-12-19 19:17:34,195 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-19 19:17:34,195 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2021-12-19 19:17:34,195 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:34,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1624 transitions. [2021-12-19 19:17:34,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,203 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,203 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,203 INFO L791 eck$LassoCheckResult]: Stem: 16217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 16218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15818#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15819#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16365#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16366#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16349#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15985#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15986#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16426#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16332#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16040#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15824#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15825#L922 assume !(0 == ~M_E~0); 16470#L922-2 assume !(0 == ~T1_E~0); 16471#L927-1 assume !(0 == ~T2_E~0); 16225#L932-1 assume !(0 == ~T3_E~0); 16110#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16111#L942-1 assume !(0 == ~T5_E~0); 16167#L947-1 assume !(0 == ~T6_E~0); 16229#L952-1 assume !(0 == ~T7_E~0); 16230#L957-1 assume !(0 == ~T8_E~0); 16293#L962-1 assume !(0 == ~T9_E~0); 16089#L967-1 assume !(0 == ~E_1~0); 16090#L972-1 assume !(0 == ~E_2~0); 16353#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16354#L982-1 assume !(0 == ~E_4~0); 15596#L987-1 assume !(0 == ~E_5~0); 15597#L992-1 assume !(0 == ~E_6~0); 15603#L997-1 assume !(0 == ~E_7~0); 16019#L1002-1 assume !(0 == ~E_8~0); 16005#L1007-1 assume !(0 == ~E_9~0); 15392#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15393#L443 assume !(1 == ~m_pc~0); 16245#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16236#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16237#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15758#L1140 assume !(0 != activate_threads_~tmp~1#1); 15507#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15508#L462 assume 1 == ~t1_pc~0; 16136#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16106#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15478#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15479#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 15966#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15967#L481 assume !(1 == ~t2_pc~0); 15753#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15752#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16107#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15846#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15847#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15939#L500 assume 1 == ~t3_pc~0; 16149#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16150#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16340#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16341#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15394#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15395#L519 assume 1 == ~t4_pc~0; 15693#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15694#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15938#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15798#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15799#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15561#L538 assume !(1 == ~t5_pc~0); 15562#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15468#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15469#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15737#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15738#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16275#L557 assume 1 == ~t6_pc~0; 16074#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15775#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15672#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15673#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15800#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16453#L576 assume !(1 == ~t7_pc~0); 15762#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15763#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16007#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16008#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16324#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15883#L595 assume 1 == ~t8_pc~0; 15884#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16342#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16343#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16192#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15686#L614 assume !(1 == ~t9_pc~0); 15687#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15585#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15586#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15766#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15848#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15849#L1025 assume !(1 == ~M_E~0); 16095#L1025-2 assume !(1 == ~T1_E~0); 16148#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16270#L1035-1 assume !(1 == ~T3_E~0); 15842#L1040-1 assume !(1 == ~T4_E~0); 15843#L1045-1 assume !(1 == ~T5_E~0); 15748#L1050-1 assume !(1 == ~T6_E~0); 15749#L1055-1 assume !(1 == ~T7_E~0); 15570#L1060-1 assume !(1 == ~T8_E~0); 15571#L1065-1 assume !(1 == ~T9_E~0); 15634#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16231#L1075-1 assume !(1 == ~E_2~0); 16232#L1080-1 assume !(1 == ~E_3~0); 16220#L1085-1 assume !(1 == ~E_4~0); 16221#L1090-1 assume !(1 == ~E_5~0); 16420#L1095-1 assume !(1 == ~E_6~0); 16254#L1100-1 assume !(1 == ~E_7~0); 16255#L1105-1 assume !(1 == ~E_8~0); 15543#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15544#L1115-1 assume { :end_inline_reset_delta_events } true; 15707#L1396-2 [2021-12-19 19:17:34,204 INFO L793 eck$LassoCheckResult]: Loop: 15707#L1396-2 assume !false; 15788#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15817#L897 assume !false; 16460#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16367#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15415#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15416#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16415#L766 assume !(0 != eval_~tmp~0#1); 16401#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15485#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15486#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15999#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15729#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15730#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15908#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15535#L942-3 assume !(0 == ~T5_E~0); 15536#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15909#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15910#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16411#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16302#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16303#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16223#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16224#L982-3 assume !(0 == ~E_4~0); 16472#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15859#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15860#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15854#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15855#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15572#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15573#L443-30 assume 1 == ~m_pc~0; 15606#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15607#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15890#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16438#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16357#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15990#L462-30 assume 1 == ~t1_pc~0; 15834#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15836#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16337#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16338#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16379#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15977#L481-30 assume 1 == ~t2_pc~0; 15696#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15697#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15750#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15663#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15664#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15944#L500-30 assume 1 == ~t3_pc~0; 15701#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15702#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15764#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15765#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15927#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15928#L519-30 assume 1 == ~t4_pc~0; 16263#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16079#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15441#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15442#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16091#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16204#L538-30 assume !(1 == ~t5_pc~0); 15584#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 15583#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15881#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15882#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15659#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15660#L557-30 assume 1 == ~t6_pc~0; 15380#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15381#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16058#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16115#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 15684#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15685#L576-30 assume 1 == ~t7_pc~0; 16197#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15467#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16052#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16418#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15844#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15807#L595-30 assume !(1 == ~t8_pc~0); 15808#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15743#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15476#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15477#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16419#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16455#L614-30 assume 1 == ~t9_pc~0; 15745#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15746#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15880#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15574#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15575#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16183#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15968#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15969#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16153#L1035-3 assume !(1 == ~T3_E~0); 16428#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16468#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16424#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16339#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15474#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15475#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16359#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16205#L1075-3 assume !(1 == ~E_2~0); 16206#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16429#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16350#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16351#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16370#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16371#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15622#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15623#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16384#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15491#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15483#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15484#L1415 assume !(0 == start_simulation_~tmp~3#1); 16084#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16085#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15531#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16093#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16272#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16473#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16143#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15706#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15707#L1396-2 [2021-12-19 19:17:34,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2021-12-19 19:17:34,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523241541] [2021-12-19 19:17:34,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,205 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523241541] [2021-12-19 19:17:34,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523241541] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216243111] [2021-12-19 19:17:34,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,238 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,238 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,238 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 2 times [2021-12-19 19:17:34,238 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046522466] [2021-12-19 19:17:34,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,245 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,279 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,280 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046522466] [2021-12-19 19:17:34,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046522466] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,280 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,280 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781462024] [2021-12-19 19:17:34,284 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:34,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:34,286 INFO L87 Difference]: Start difference. First operand 1094 states and 1624 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,305 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2021-12-19 19:17:34,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:34,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1623 transitions. [2021-12-19 19:17:34,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1623 transitions. [2021-12-19 19:17:34,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2021-12-19 19:17:34,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2021-12-19 19:17:34,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1623 transitions. [2021-12-19 19:17:34,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,324 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-19 19:17:34,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1623 transitions. [2021-12-19 19:17:34,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2021-12-19 19:17:34,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1623 transitions. [2021-12-19 19:17:34,344 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-19 19:17:34,344 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2021-12-19 19:17:34,344 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:34,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1623 transitions. [2021-12-19 19:17:34,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2021-12-19 19:17:34,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,352 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,353 INFO L791 eck$LassoCheckResult]: Stem: 18411#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18013#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18014#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18560#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18561#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18543#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18363#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18364#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18179#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18180#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18620#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18526#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18235#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18019#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18020#L922 assume !(0 == ~M_E~0); 18665#L922-2 assume !(0 == ~T1_E~0); 18666#L927-1 assume !(0 == ~T2_E~0); 18420#L932-1 assume !(0 == ~T3_E~0); 18305#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18306#L942-1 assume !(0 == ~T5_E~0); 18362#L947-1 assume !(0 == ~T6_E~0); 18424#L952-1 assume !(0 == ~T7_E~0); 18425#L957-1 assume !(0 == ~T8_E~0); 18485#L962-1 assume !(0 == ~T9_E~0); 18281#L967-1 assume !(0 == ~E_1~0); 18282#L972-1 assume !(0 == ~E_2~0); 18548#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18549#L982-1 assume !(0 == ~E_4~0); 17789#L987-1 assume !(0 == ~E_5~0); 17790#L992-1 assume !(0 == ~E_6~0); 17798#L997-1 assume !(0 == ~E_7~0); 18212#L1002-1 assume !(0 == ~E_8~0); 18199#L1007-1 assume !(0 == ~E_9~0); 17587#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17588#L443 assume !(1 == ~m_pc~0); 18440#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18431#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18432#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17953#L1140 assume !(0 != activate_threads_~tmp~1#1); 17702#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17703#L462 assume 1 == ~t1_pc~0; 18331#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18298#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17673#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17674#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18160#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18161#L481 assume !(1 == ~t2_pc~0); 17948#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17947#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18302#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18041#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18042#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18134#L500 assume 1 == ~t3_pc~0; 18344#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18345#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18535#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18536#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17589#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17590#L519 assume 1 == ~t4_pc~0; 17888#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17889#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18133#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17993#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 17994#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17756#L538 assume !(1 == ~t5_pc~0); 17757#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17663#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17664#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17932#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17933#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18470#L557 assume 1 == ~t6_pc~0; 18269#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17970#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17867#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17868#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 17995#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18648#L576 assume !(1 == ~t7_pc~0); 17957#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17958#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18202#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18203#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18519#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18078#L595 assume 1 == ~t8_pc~0; 18079#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18537#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18538#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18387#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18388#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17881#L614 assume !(1 == ~t9_pc~0); 17882#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17780#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17961#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18043#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18044#L1025 assume !(1 == ~M_E~0); 18290#L1025-2 assume !(1 == ~T1_E~0); 18343#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18465#L1035-1 assume !(1 == ~T3_E~0); 18037#L1040-1 assume !(1 == ~T4_E~0); 18038#L1045-1 assume !(1 == ~T5_E~0); 17943#L1050-1 assume !(1 == ~T6_E~0); 17944#L1055-1 assume !(1 == ~T7_E~0); 17765#L1060-1 assume !(1 == ~T8_E~0); 17766#L1065-1 assume !(1 == ~T9_E~0); 17829#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18426#L1075-1 assume !(1 == ~E_2~0); 18427#L1080-1 assume !(1 == ~E_3~0); 18415#L1085-1 assume !(1 == ~E_4~0); 18416#L1090-1 assume !(1 == ~E_5~0); 18615#L1095-1 assume !(1 == ~E_6~0); 18449#L1100-1 assume !(1 == ~E_7~0); 18450#L1105-1 assume !(1 == ~E_8~0); 17738#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17739#L1115-1 assume { :end_inline_reset_delta_events } true; 17902#L1396-2 [2021-12-19 19:17:34,353 INFO L793 eck$LassoCheckResult]: Loop: 17902#L1396-2 assume !false; 17983#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18012#L897 assume !false; 18655#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18562#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17610#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17611#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18610#L766 assume !(0 != eval_~tmp~0#1); 18596#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17680#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17681#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18194#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17924#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17925#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18103#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17730#L942-3 assume !(0 == ~T5_E~0); 17731#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18104#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18105#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18606#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18497#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18498#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18418#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18419#L982-3 assume !(0 == ~E_4~0); 18667#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18054#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18055#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18049#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18050#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17768#L443-30 assume 1 == ~m_pc~0; 17801#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17802#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18085#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18633#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18552#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18185#L462-30 assume 1 == ~t1_pc~0; 18029#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18031#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18532#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18533#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18574#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18172#L481-30 assume 1 == ~t2_pc~0; 17891#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17892#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17945#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17858#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17859#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18139#L500-30 assume 1 == ~t3_pc~0; 17896#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17897#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17959#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17960#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18122#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18123#L519-30 assume 1 == ~t4_pc~0; 18458#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18274#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17636#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17637#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18286#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18399#L538-30 assume 1 == ~t5_pc~0; 17777#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17778#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18076#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18077#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17854#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17855#L557-30 assume 1 == ~t6_pc~0; 17575#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17576#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18253#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18310#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 17879#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17880#L576-30 assume 1 == ~t7_pc~0; 18392#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17662#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18247#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18613#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18039#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18002#L595-30 assume !(1 == ~t8_pc~0); 18003#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 17938#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17671#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17672#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18614#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18650#L614-30 assume 1 == ~t9_pc~0; 17940#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17941#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18075#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17769#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17770#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18378#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18163#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18164#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18348#L1035-3 assume !(1 == ~T3_E~0); 18623#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18663#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18619#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18534#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17669#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17670#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18554#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18400#L1075-3 assume !(1 == ~E_2~0); 18401#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18624#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18545#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18546#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18565#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18566#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17817#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17818#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18579#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17686#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17678#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 17679#L1415 assume !(0 == start_simulation_~tmp~3#1); 18279#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18280#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17726#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18288#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 18467#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18668#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18338#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17901#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 17902#L1396-2 [2021-12-19 19:17:34,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,354 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2021-12-19 19:17:34,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,354 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355918794] [2021-12-19 19:17:34,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,355 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355918794] [2021-12-19 19:17:34,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355918794] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,394 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558273034] [2021-12-19 19:17:34,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,395 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,395 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 1 times [2021-12-19 19:17:34,396 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,396 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022069409] [2021-12-19 19:17:34,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022069409] [2021-12-19 19:17:34,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022069409] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,436 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,436 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1897667684] [2021-12-19 19:17:34,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,437 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,437 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:34,438 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:34,438 INFO L87 Difference]: Start difference. First operand 1094 states and 1623 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,581 INFO L93 Difference]: Finished difference Result 1991 states and 2943 transitions. [2021-12-19 19:17:34,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:34,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1991 states and 2943 transitions. [2021-12-19 19:17:34,592 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1847 [2021-12-19 19:17:34,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1991 states to 1991 states and 2943 transitions. [2021-12-19 19:17:34,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1991 [2021-12-19 19:17:34,604 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1991 [2021-12-19 19:17:34,605 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1991 states and 2943 transitions. [2021-12-19 19:17:34,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,608 INFO L681 BuchiCegarLoop]: Abstraction has 1991 states and 2943 transitions. [2021-12-19 19:17:34,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1991 states and 2943 transitions. [2021-12-19 19:17:34,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1991 to 1991. [2021-12-19 19:17:34,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1991 states, 1991 states have (on average 1.4781516825715721) internal successors, (2943), 1990 states have internal predecessors, (2943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1991 states to 1991 states and 2943 transitions. [2021-12-19 19:17:34,655 INFO L704 BuchiCegarLoop]: Abstraction has 1991 states and 2943 transitions. [2021-12-19 19:17:34,655 INFO L587 BuchiCegarLoop]: Abstraction has 1991 states and 2943 transitions. [2021-12-19 19:17:34,655 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:34,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1991 states and 2943 transitions. [2021-12-19 19:17:34,662 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1847 [2021-12-19 19:17:34,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:34,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:34,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:34,664 INFO L791 eck$LassoCheckResult]: Stem: 21558#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21559#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 21116#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21117#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21747#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21748#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21723#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21499#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21500#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21292#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21293#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21825#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21705#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21357#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21122#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21123#L922 assume !(0 == ~M_E~0); 21898#L922-2 assume !(0 == ~T1_E~0); 21899#L927-1 assume !(0 == ~T2_E~0); 21568#L932-1 assume !(0 == ~T3_E~0); 21435#L937-1 assume !(0 == ~T4_E~0); 21436#L942-1 assume !(0 == ~T5_E~0); 21498#L947-1 assume !(0 == ~T6_E~0); 21572#L952-1 assume !(0 == ~T7_E~0); 21573#L957-1 assume !(0 == ~T8_E~0); 21648#L962-1 assume !(0 == ~T9_E~0); 21406#L967-1 assume !(0 == ~E_1~0); 21407#L972-1 assume !(0 == ~E_2~0); 21730#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21731#L982-1 assume !(0 == ~E_4~0); 20884#L987-1 assume !(0 == ~E_5~0); 20885#L992-1 assume !(0 == ~E_6~0); 20893#L997-1 assume !(0 == ~E_7~0); 21332#L1002-1 assume !(0 == ~E_8~0); 21317#L1007-1 assume !(0 == ~E_9~0); 20682#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20683#L443 assume !(1 == ~m_pc~0); 21591#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21579#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21580#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21054#L1140 assume !(0 != activate_threads_~tmp~1#1); 20797#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20798#L462 assume 1 == ~t1_pc~0; 21465#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21427#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20768#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20769#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21273#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21274#L481 assume !(1 == ~t2_pc~0); 21049#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21048#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21432#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21145#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21146#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21245#L500 assume 1 == ~t3_pc~0; 21479#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21480#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21713#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21714#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20684#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20685#L519 assume 1 == ~t4_pc~0; 20987#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20988#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21244#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21095#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21096#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20851#L538 assume !(1 == ~t5_pc~0); 20852#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20758#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20759#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21032#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21033#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21629#L557 assume 1 == ~t6_pc~0; 21393#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21071#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20969#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20970#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21097#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21867#L576 assume !(1 == ~t7_pc~0); 21058#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21059#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21320#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21321#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21693#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21184#L595 assume 1 == ~t8_pc~0; 21185#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21715#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21716#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21528#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21529#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20980#L614 assume !(1 == ~t9_pc~0); 20981#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 20876#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20877#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21062#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21147#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21148#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 21416#L1025-2 assume !(1 == ~T1_E~0); 21478#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21622#L1035-1 assume !(1 == ~T3_E~0); 21141#L1040-1 assume !(1 == ~T4_E~0); 21142#L1045-1 assume !(1 == ~T5_E~0); 21044#L1050-1 assume !(1 == ~T6_E~0); 21045#L1055-1 assume !(1 == ~T7_E~0); 20860#L1060-1 assume !(1 == ~T8_E~0); 20861#L1065-1 assume !(1 == ~T9_E~0); 20924#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21574#L1075-1 assume !(1 == ~E_2~0); 21575#L1080-1 assume !(1 == ~E_3~0); 21563#L1085-1 assume !(1 == ~E_4~0); 21564#L1090-1 assume !(1 == ~E_5~0); 21819#L1095-1 assume !(1 == ~E_6~0); 21604#L1100-1 assume !(1 == ~E_7~0); 21605#L1105-1 assume !(1 == ~E_8~0); 20833#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 20834#L1115-1 assume { :end_inline_reset_delta_events } true; 20999#L1396-2 [2021-12-19 19:17:34,664 INFO L793 eck$LassoCheckResult]: Loop: 20999#L1396-2 assume !false; 21939#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21935#L897 assume !false; 21908#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21909#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 20705#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20706#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21809#L766 assume !(0 != eval_~tmp~0#1); 21810#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20775#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20776#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21883#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21024#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21025#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21212#L937-3 assume !(0 == ~T4_E~0); 20825#L942-3 assume !(0 == ~T5_E~0); 20826#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21213#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21214#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21804#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21662#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21663#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21566#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21567#L982-3 assume !(0 == ~E_4~0); 21910#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21158#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21159#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21153#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21154#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20862#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20863#L443-30 assume 1 == ~m_pc~0; 20896#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20897#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21841#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21842#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21735#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21736#L462-30 assume 1 == ~t1_pc~0; 21132#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21134#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21729#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21764#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21765#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21284#L481-30 assume !(1 == ~t2_pc~0); 20992#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 20991#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21046#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20954#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20955#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21584#L500-30 assume !(1 == ~t3_pc~0); 21585#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 21341#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21342#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22021#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22020#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22019#L519-30 assume !(1 == ~t4_pc~0); 21430#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 21431#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20731#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20732#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22017#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22015#L538-30 assume !(1 == ~t5_pc~0); 22013#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 21216#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21217#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21695#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21696#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20961#L557-30 assume !(1 == ~t6_pc~0); 20962#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 21376#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21377#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21902#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 21903#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21533#L576-30 assume 1 == ~t7_pc~0; 21534#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21369#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21370#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21814#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21815#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22007#L595-30 assume 1 == ~t8_pc~0; 22005#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21038#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21039#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21816#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21817#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21869#L614-30 assume 1 == ~t9_pc~0; 21870#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22001#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21999#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21997#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21995#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21994#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21516#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21993#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21992#L1035-3 assume !(1 == ~T3_E~0); 21991#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21894#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21990#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21989#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21988#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21987#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21986#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21985#L1075-3 assume !(1 == ~E_2~0); 21984#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21983#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21982#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21981#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21979#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21978#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21977#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21967#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21966#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21965#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 21734#L1415 assume !(0 == start_simulation_~tmp~3#1); 21486#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21963#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21954#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21953#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21952#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21951#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21949#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20998#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 20999#L1396-2 [2021-12-19 19:17:34,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,665 INFO L85 PathProgramCache]: Analyzing trace with hash 521066337, now seen corresponding path program 1 times [2021-12-19 19:17:34,665 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,665 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707345017] [2021-12-19 19:17:34,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,666 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,706 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707345017] [2021-12-19 19:17:34,706 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707345017] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,706 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,706 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,706 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161864718] [2021-12-19 19:17:34,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,708 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:34,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:34,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1576927346, now seen corresponding path program 1 times [2021-12-19 19:17:34,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:34,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713739315] [2021-12-19 19:17:34,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:34,709 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:34,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:34,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:34,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:34,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713739315] [2021-12-19 19:17:34,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713739315] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:34,748 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:34,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:34,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981113585] [2021-12-19 19:17:34,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:34,748 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:34,749 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:34,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:34,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:34,750 INFO L87 Difference]: Start difference. First operand 1991 states and 2943 transitions. cyclomatic complexity: 954 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:34,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:34,912 INFO L93 Difference]: Finished difference Result 3627 states and 5350 transitions. [2021-12-19 19:17:34,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:34,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3627 states and 5350 transitions. [2021-12-19 19:17:34,931 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3459 [2021-12-19 19:17:34,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3627 states to 3627 states and 5350 transitions. [2021-12-19 19:17:34,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3627 [2021-12-19 19:17:34,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3627 [2021-12-19 19:17:34,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3627 states and 5350 transitions. [2021-12-19 19:17:34,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:34,959 INFO L681 BuchiCegarLoop]: Abstraction has 3627 states and 5350 transitions. [2021-12-19 19:17:34,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3627 states and 5350 transitions. [2021-12-19 19:17:35,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3627 to 3625. [2021-12-19 19:17:35,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3625 states, 3625 states have (on average 1.4753103448275862) internal successors, (5348), 3624 states have internal predecessors, (5348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3625 states to 3625 states and 5348 transitions. [2021-12-19 19:17:35,058 INFO L704 BuchiCegarLoop]: Abstraction has 3625 states and 5348 transitions. [2021-12-19 19:17:35,058 INFO L587 BuchiCegarLoop]: Abstraction has 3625 states and 5348 transitions. [2021-12-19 19:17:35,058 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:35,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3625 states and 5348 transitions. [2021-12-19 19:17:35,074 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3459 [2021-12-19 19:17:35,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:35,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:35,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,076 INFO L791 eck$LassoCheckResult]: Stem: 27166#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27167#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 26745#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26746#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27326#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 27327#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27308#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27109#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27110#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26917#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26918#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27400#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27291#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26974#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26751#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26752#L922 assume !(0 == ~M_E~0); 27462#L922-2 assume !(0 == ~T1_E~0); 27463#L927-1 assume !(0 == ~T2_E~0); 27175#L932-1 assume !(0 == ~T3_E~0); 27046#L937-1 assume !(0 == ~T4_E~0); 27047#L942-1 assume !(0 == ~T5_E~0); 27108#L947-1 assume !(0 == ~T6_E~0); 27179#L952-1 assume !(0 == ~T7_E~0); 27180#L957-1 assume !(0 == ~T8_E~0); 27246#L962-1 assume !(0 == ~T9_E~0); 27020#L967-1 assume !(0 == ~E_1~0); 27021#L972-1 assume !(0 == ~E_2~0); 27313#L977-1 assume !(0 == ~E_3~0); 27314#L982-1 assume !(0 == ~E_4~0); 26513#L987-1 assume !(0 == ~E_5~0); 26514#L992-1 assume !(0 == ~E_6~0); 26522#L997-1 assume !(0 == ~E_7~0); 26952#L1002-1 assume !(0 == ~E_8~0); 26938#L1007-1 assume !(0 == ~E_9~0); 26310#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26311#L443 assume !(1 == ~m_pc~0); 27195#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27186#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27187#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26683#L1140 assume !(0 != activate_threads_~tmp~1#1); 26425#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26426#L462 assume 1 == ~t1_pc~0; 27073#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27040#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26396#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26397#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 26898#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26899#L481 assume !(1 == ~t2_pc~0); 26678#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26677#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27043#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26774#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 26775#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26873#L500 assume 1 == ~t3_pc~0; 27086#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27087#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27300#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27301#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 26315#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26316#L519 assume 1 == ~t4_pc~0; 26618#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26619#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26870#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26726#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 26727#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26480#L538 assume !(1 == ~t5_pc~0); 26481#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26386#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26387#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26662#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26663#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27229#L557 assume 1 == ~t6_pc~0; 27008#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26701#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26602#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26603#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 26728#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27437#L576 assume !(1 == ~t7_pc~0); 26687#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26688#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26940#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26941#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 27281#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26811#L595 assume 1 == ~t8_pc~0; 26812#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27302#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27303#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27137#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27138#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26611#L614 assume !(1 == ~t9_pc~0); 26612#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 26505#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26506#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26691#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 26776#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26777#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 27029#L1025-2 assume !(1 == ~T1_E~0); 27221#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27222#L1035-1 assume !(1 == ~T3_E~0); 27343#L1040-1 assume !(1 == ~T4_E~0); 27695#L1045-1 assume !(1 == ~T5_E~0); 27694#L1050-1 assume !(1 == ~T6_E~0); 27693#L1055-1 assume !(1 == ~T7_E~0); 27691#L1060-1 assume !(1 == ~T8_E~0); 26554#L1065-1 assume !(1 == ~T9_E~0); 26555#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 27181#L1075-1 assume !(1 == ~E_2~0); 27182#L1080-1 assume !(1 == ~E_3~0); 27630#L1085-1 assume !(1 == ~E_4~0); 27628#L1090-1 assume !(1 == ~E_5~0); 27627#L1095-1 assume !(1 == ~E_6~0); 27626#L1100-1 assume !(1 == ~E_7~0); 27533#L1105-1 assume !(1 == ~E_8~0); 27522#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 27513#L1115-1 assume { :end_inline_reset_delta_events } true; 27506#L1396-2 [2021-12-19 19:17:35,077 INFO L793 eck$LassoCheckResult]: Loop: 27506#L1396-2 assume !false; 27500#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27495#L897 assume !false; 27494#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27493#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27483#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27482#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27480#L766 assume !(0 != eval_~tmp~0#1); 27479#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27478#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27476#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27477#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28338#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28334#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28332#L937-3 assume !(0 == ~T4_E~0); 28330#L942-3 assume !(0 == ~T5_E~0); 28325#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28323#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28320#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28318#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28315#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28303#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28296#L977-3 assume !(0 == ~E_3~0); 28291#L982-3 assume !(0 == ~E_4~0); 28256#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28254#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28252#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28249#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28247#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28245#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28243#L443-30 assume 1 == ~m_pc~0; 28240#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28238#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28235#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28233#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28231#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28229#L462-30 assume !(1 == ~t1_pc~0); 28226#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 28224#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28221#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28219#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28217#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28215#L481-30 assume 1 == ~t2_pc~0; 28212#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28210#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28207#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28205#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28203#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28201#L500-30 assume !(1 == ~t3_pc~0); 28198#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 28196#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28193#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28191#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28189#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28187#L519-30 assume 1 == ~t4_pc~0; 28184#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28182#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28180#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27990#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27957#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27954#L538-30 assume 1 == ~t5_pc~0; 27952#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27949#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27947#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27945#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27944#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27943#L557-30 assume 1 == ~t6_pc~0; 26298#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26299#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26992#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27048#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 26609#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26610#L576-30 assume 1 == ~t7_pc~0; 27143#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26383#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26985#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27391#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26769#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26733#L595-30 assume !(1 == ~t8_pc~0); 26734#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 26668#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26394#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26395#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27392#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27439#L614-30 assume !(1 == ~t9_pc~0); 26672#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 26671#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26808#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26493#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26494#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27126#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27127#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27090#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27091#L1035-3 assume !(1 == ~T3_E~0); 27402#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27457#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27610#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27607#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27604#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27601#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27598#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27595#L1075-3 assume !(1 == ~E_2~0); 27591#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27587#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27585#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27583#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27581#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27579#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27576#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27574#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27563#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27561#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27559#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 27557#L1415 assume !(0 == start_simulation_~tmp~3#1); 27094#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27552#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27542#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27540#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 27538#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27534#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27523#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 27514#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 27506#L1396-2 [2021-12-19 19:17:35,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,077 INFO L85 PathProgramCache]: Analyzing trace with hash -473627361, now seen corresponding path program 1 times [2021-12-19 19:17:35,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222458544] [2021-12-19 19:17:35,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:35,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:35,109 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:35,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222458544] [2021-12-19 19:17:35,109 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222458544] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:35,109 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:35,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:35,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352012458] [2021-12-19 19:17:35,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:35,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:35,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,111 INFO L85 PathProgramCache]: Analyzing trace with hash 103457645, now seen corresponding path program 1 times [2021-12-19 19:17:35,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104701262] [2021-12-19 19:17:35,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:35,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:35,145 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:35,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104701262] [2021-12-19 19:17:35,146 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104701262] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:35,146 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:35,146 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:35,146 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697572742] [2021-12-19 19:17:35,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:35,147 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:35,147 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:35,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:35,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:35,148 INFO L87 Difference]: Start difference. First operand 3625 states and 5348 transitions. cyclomatic complexity: 1727 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:35,247 INFO L93 Difference]: Finished difference Result 6752 states and 9893 transitions. [2021-12-19 19:17:35,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:35,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6752 states and 9893 transitions. [2021-12-19 19:17:35,286 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6583 [2021-12-19 19:17:35,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6752 states to 6752 states and 9893 transitions. [2021-12-19 19:17:35,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6752 [2021-12-19 19:17:35,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6752 [2021-12-19 19:17:35,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6752 states and 9893 transitions. [2021-12-19 19:17:35,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:35,346 INFO L681 BuchiCegarLoop]: Abstraction has 6752 states and 9893 transitions. [2021-12-19 19:17:35,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6752 states and 9893 transitions. [2021-12-19 19:17:35,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6752 to 6744. [2021-12-19 19:17:35,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6744 states, 6744 states have (on average 1.4657473309608542) internal successors, (9885), 6743 states have internal predecessors, (9885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6744 states to 6744 states and 9885 transitions. [2021-12-19 19:17:35,558 INFO L704 BuchiCegarLoop]: Abstraction has 6744 states and 9885 transitions. [2021-12-19 19:17:35,558 INFO L587 BuchiCegarLoop]: Abstraction has 6744 states and 9885 transitions. [2021-12-19 19:17:35,558 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:35,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6744 states and 9885 transitions. [2021-12-19 19:17:35,587 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6575 [2021-12-19 19:17:35,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:35,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:35,589 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,589 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:35,590 INFO L791 eck$LassoCheckResult]: Stem: 37593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 37594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 37129#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37130#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37782#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 37783#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37754#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37527#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37528#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37309#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37310#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37881#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37735#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37377#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37135#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37136#L922 assume !(0 == ~M_E~0); 37965#L922-2 assume !(0 == ~T1_E~0); 37966#L927-1 assume !(0 == ~T2_E~0); 37601#L932-1 assume !(0 == ~T3_E~0); 37462#L937-1 assume !(0 == ~T4_E~0); 37463#L942-1 assume !(0 == ~T5_E~0); 37526#L947-1 assume !(0 == ~T6_E~0); 37605#L952-1 assume !(0 == ~T7_E~0); 37606#L957-1 assume !(0 == ~T8_E~0); 37678#L962-1 assume !(0 == ~T9_E~0); 37432#L967-1 assume !(0 == ~E_1~0); 37433#L972-1 assume !(0 == ~E_2~0); 37764#L977-1 assume !(0 == ~E_3~0); 37765#L982-1 assume !(0 == ~E_4~0); 36897#L987-1 assume !(0 == ~E_5~0); 36898#L992-1 assume !(0 == ~E_6~0); 36906#L997-1 assume !(0 == ~E_7~0); 37352#L1002-1 assume !(0 == ~E_8~0); 37337#L1007-1 assume !(0 == ~E_9~0); 36694#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36695#L443 assume !(1 == ~m_pc~0); 37621#L443-2 is_master_triggered_~__retres1~0#1 := 0; 37612#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37613#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37067#L1140 assume !(0 != activate_threads_~tmp~1#1); 36808#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36809#L462 assume !(1 == ~t1_pc~0); 37456#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37457#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36780#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36781#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 37288#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37289#L481 assume !(1 == ~t2_pc~0); 37062#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 37061#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37459#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37159#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 37160#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37260#L500 assume 1 == ~t3_pc~0; 37503#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37504#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37746#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37747#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 36699#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36700#L519 assume 1 == ~t4_pc~0; 37004#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37005#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37257#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37110#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 37111#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36864#L538 assume !(1 == ~t5_pc~0); 36865#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36770#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36771#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37046#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37047#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37658#L557 assume 1 == ~t6_pc~0; 37419#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37085#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36985#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36986#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 37112#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37926#L576 assume !(1 == ~t7_pc~0); 37071#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37072#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37339#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37340#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 37723#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37196#L595 assume 1 == ~t8_pc~0; 37197#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37748#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37749#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37562#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 37563#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36994#L614 assume !(1 == ~t9_pc~0); 36995#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 36889#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36890#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37075#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 37161#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37162#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 37444#L1025-2 assume !(1 == ~T1_E~0); 40602#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40601#L1035-1 assume !(1 == ~T3_E~0); 40599#L1040-1 assume !(1 == ~T4_E~0); 40597#L1045-1 assume !(1 == ~T5_E~0); 40595#L1050-1 assume !(1 == ~T6_E~0); 40593#L1055-1 assume !(1 == ~T7_E~0); 40590#L1060-1 assume !(1 == ~T8_E~0); 40588#L1065-1 assume !(1 == ~T9_E~0); 40586#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40584#L1075-1 assume !(1 == ~E_2~0); 40582#L1080-1 assume !(1 == ~E_3~0); 40579#L1085-1 assume !(1 == ~E_4~0); 40576#L1090-1 assume !(1 == ~E_5~0); 40574#L1095-1 assume !(1 == ~E_6~0); 40572#L1100-1 assume !(1 == ~E_7~0); 40570#L1105-1 assume !(1 == ~E_8~0); 40568#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 40550#L1115-1 assume { :end_inline_reset_delta_events } true; 40539#L1396-2 [2021-12-19 19:17:35,590 INFO L793 eck$LassoCheckResult]: Loop: 40539#L1396-2 assume !false; 40531#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40524#L897 assume !false; 40520#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40515#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40501#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40498#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40493#L766 assume !(0 != eval_~tmp~0#1); 40494#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41864#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41863#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41862#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41861#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41860#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41859#L937-3 assume !(0 == ~T4_E~0); 41858#L942-3 assume !(0 == ~T5_E~0); 41857#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41856#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41855#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41854#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41853#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41852#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41851#L977-3 assume !(0 == ~E_3~0); 41850#L982-3 assume !(0 == ~E_4~0); 41849#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41848#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41847#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41846#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41845#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41844#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41843#L443-30 assume 1 == ~m_pc~0; 41841#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41840#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41839#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41838#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41837#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41836#L462-30 assume !(1 == ~t1_pc~0); 41835#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 41834#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41833#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41832#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41831#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41830#L481-30 assume 1 == ~t2_pc~0; 41828#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41827#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41826#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41825#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41824#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41823#L500-30 assume !(1 == ~t3_pc~0); 41821#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 41820#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41819#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41818#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41817#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41816#L519-30 assume 1 == ~t4_pc~0; 41814#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41813#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41812#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41811#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41810#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41809#L538-30 assume 1 == ~t5_pc~0; 41808#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41806#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41805#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41804#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41803#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41802#L557-30 assume 1 == ~t6_pc~0; 41800#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41799#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41798#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41797#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 41796#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41795#L576-30 assume 1 == ~t7_pc~0; 41793#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41792#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41791#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41790#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41789#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41788#L595-30 assume 1 == ~t8_pc~0; 41786#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41785#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41784#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41783#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41782#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41781#L614-30 assume 1 == ~t9_pc~0; 41779#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41778#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41777#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41776#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41775#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41774#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37549#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41773#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41772#L1035-3 assume !(1 == ~T3_E~0); 41771#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41768#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41767#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41766#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41765#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41764#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41763#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41762#L1075-3 assume !(1 == ~E_2~0); 41761#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41758#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41757#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41756#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41755#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41754#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41753#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41752#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41742#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 41741#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 41740#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 41739#L1415 assume !(0 == start_simulation_~tmp~3#1); 37511#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 41737#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 37440#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 37441#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 37653#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37982#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40603#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 40551#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 40539#L1396-2 [2021-12-19 19:17:35,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1193492222, now seen corresponding path program 1 times [2021-12-19 19:17:35,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,591 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061029839] [2021-12-19 19:17:35,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,591 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:35,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:35,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:35,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061029839] [2021-12-19 19:17:35,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061029839] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:35,622 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:35,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:35,623 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [536405970] [2021-12-19 19:17:35,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:35,624 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:35,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:35,624 INFO L85 PathProgramCache]: Analyzing trace with hash 855239663, now seen corresponding path program 1 times [2021-12-19 19:17:35,624 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:35,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413826386] [2021-12-19 19:17:35,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:35,625 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:35,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:35,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:35,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:35,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413826386] [2021-12-19 19:17:35,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413826386] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:35,714 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:35,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:35,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750296761] [2021-12-19 19:17:35,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:35,715 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:35,715 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:35,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:35,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:35,716 INFO L87 Difference]: Start difference. First operand 6744 states and 9885 transitions. cyclomatic complexity: 3149 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:35,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:35,962 INFO L93 Difference]: Finished difference Result 15869 states and 23068 transitions. [2021-12-19 19:17:35,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:35,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15869 states and 23068 transitions. [2021-12-19 19:17:36,049 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15669 [2021-12-19 19:17:36,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15869 states to 15869 states and 23068 transitions. [2021-12-19 19:17:36,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15869 [2021-12-19 19:17:36,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15869 [2021-12-19 19:17:36,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15869 states and 23068 transitions. [2021-12-19 19:17:36,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:36,154 INFO L681 BuchiCegarLoop]: Abstraction has 15869 states and 23068 transitions. [2021-12-19 19:17:36,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15869 states and 23068 transitions. [2021-12-19 19:17:36,481 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15869 to 12660. [2021-12-19 19:17:36,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12660 states, 12660 states have (on average 1.4585308056872037) internal successors, (18465), 12659 states have internal predecessors, (18465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12660 states to 12660 states and 18465 transitions. [2021-12-19 19:17:36,545 INFO L704 BuchiCegarLoop]: Abstraction has 12660 states and 18465 transitions. [2021-12-19 19:17:36,545 INFO L587 BuchiCegarLoop]: Abstraction has 12660 states and 18465 transitions. [2021-12-19 19:17:36,545 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:36,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12660 states and 18465 transitions. [2021-12-19 19:17:36,600 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12488 [2021-12-19 19:17:36,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,603 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,603 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,603 INFO L791 eck$LassoCheckResult]: Stem: 60173#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 60174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 59748#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59749#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60348#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 60349#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60325#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60119#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60120#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59919#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59920#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60441#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60306#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59982#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59754#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59755#L922 assume !(0 == ~M_E~0); 60516#L922-2 assume !(0 == ~T1_E~0); 60517#L927-1 assume !(0 == ~T2_E~0); 60182#L932-1 assume !(0 == ~T3_E~0); 60058#L937-1 assume !(0 == ~T4_E~0); 60059#L942-1 assume !(0 == ~T5_E~0); 60118#L947-1 assume !(0 == ~T6_E~0); 60186#L952-1 assume !(0 == ~T7_E~0); 60187#L957-1 assume !(0 == ~T8_E~0); 60257#L962-1 assume !(0 == ~T9_E~0); 60031#L967-1 assume !(0 == ~E_1~0); 60032#L972-1 assume !(0 == ~E_2~0); 60330#L977-1 assume !(0 == ~E_3~0); 60331#L982-1 assume !(0 == ~E_4~0); 59518#L987-1 assume !(0 == ~E_5~0); 59519#L992-1 assume !(0 == ~E_6~0); 59527#L997-1 assume !(0 == ~E_7~0); 59957#L1002-1 assume !(0 == ~E_8~0); 59942#L1007-1 assume !(0 == ~E_9~0); 59317#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59318#L443 assume !(1 == ~m_pc~0); 60205#L443-2 is_master_triggered_~__retres1~0#1 := 0; 60193#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60194#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59686#L1140 assume !(0 != activate_threads_~tmp~1#1); 59431#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59432#L462 assume !(1 == ~t1_pc~0); 60049#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60050#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59403#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59404#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 59899#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59900#L481 assume !(1 == ~t2_pc~0); 59681#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59680#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60055#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59777#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 59778#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59873#L500 assume !(1 == ~t3_pc~0); 60400#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60365#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60316#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60317#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 59319#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59320#L519 assume 1 == ~t4_pc~0; 59621#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59622#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59872#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59728#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 59729#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59485#L538 assume !(1 == ~t5_pc~0); 59486#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59393#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59394#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59665#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59666#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60240#L557 assume 1 == ~t6_pc~0; 60019#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59703#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59600#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59601#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 59730#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60484#L576 assume !(1 == ~t7_pc~0); 59690#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59691#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59945#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59946#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 60298#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59815#L595 assume 1 == ~t8_pc~0; 59816#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60318#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60319#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60147#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 60148#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59614#L614 assume !(1 == ~t9_pc~0); 59615#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 59509#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59510#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59694#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 59779#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59780#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 60041#L1025-2 assume !(1 == ~T1_E~0); 60233#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60234#L1035-1 assume !(1 == ~T3_E~0); 59773#L1040-1 assume !(1 == ~T4_E~0); 59774#L1045-1 assume !(1 == ~T5_E~0); 60357#L1050-1 assume !(1 == ~T6_E~0); 59864#L1055-1 assume !(1 == ~T7_E~0); 59865#L1060-1 assume !(1 == ~T8_E~0); 59559#L1065-1 assume !(1 == ~T9_E~0); 59560#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 60188#L1075-1 assume !(1 == ~E_2~0); 60189#L1080-1 assume !(1 == ~E_3~0); 60529#L1085-1 assume !(1 == ~E_4~0); 64652#L1090-1 assume !(1 == ~E_5~0); 64651#L1095-1 assume !(1 == ~E_6~0); 64650#L1100-1 assume !(1 == ~E_7~0); 64649#L1105-1 assume !(1 == ~E_8~0); 64648#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 64646#L1115-1 assume { :end_inline_reset_delta_events } true; 64632#L1396-2 [2021-12-19 19:17:36,604 INFO L793 eck$LassoCheckResult]: Loop: 64632#L1396-2 assume !false; 64621#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64613#L897 assume !false; 64611#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64531#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64514#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64508#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64500#L766 assume !(0 != eval_~tmp~0#1); 64501#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67509#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67507#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67505#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67503#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67501#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67499#L937-3 assume !(0 == ~T4_E~0); 67497#L942-3 assume !(0 == ~T5_E~0); 67495#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67493#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67490#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67488#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67486#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67484#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 67482#L977-3 assume !(0 == ~E_3~0); 67480#L982-3 assume !(0 == ~E_4~0); 67478#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67476#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67474#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67472#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67470#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67468#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67465#L443-30 assume !(1 == ~m_pc~0); 67463#L443-32 is_master_triggered_~__retres1~0#1 := 0; 67460#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67458#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67456#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67454#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67453#L462-30 assume !(1 == ~t1_pc~0); 67451#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 67449#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67447#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67445#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 67443#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67440#L481-30 assume 1 == ~t2_pc~0; 67437#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 67435#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67433#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67431#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67429#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67426#L500-30 assume !(1 == ~t3_pc~0); 62069#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 67423#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67421#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67419#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67417#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67414#L519-30 assume 1 == ~t4_pc~0; 67411#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 67409#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67407#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67405#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67403#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67400#L538-30 assume !(1 == ~t5_pc~0); 67397#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 67395#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67393#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67391#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 67389#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67386#L557-30 assume 1 == ~t6_pc~0; 67383#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 67381#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67379#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 67377#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 67375#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67372#L576-30 assume 1 == ~t7_pc~0; 67369#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67367#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67365#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67363#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 67362#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67361#L595-30 assume !(1 == ~t8_pc~0); 67360#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 67357#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67355#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 67353#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 67351#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67349#L614-30 assume !(1 == ~t9_pc~0); 67207#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 67204#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 67202#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67200#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 67198#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67196#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64342#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67192#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67190#L1035-3 assume !(1 == ~T3_E~0); 67189#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67187#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 67186#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67184#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 67181#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 67179#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67177#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67175#L1075-3 assume !(1 == ~E_2~0); 67173#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65651#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 67170#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67168#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67166#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67164#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67162#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 65696#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 65392#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 65385#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 65379#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 65376#L1415 assume !(0 == start_simulation_~tmp~3#1); 65373#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 64863#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 64844#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 64837#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 64830#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64821#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64815#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 64647#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 64632#L1396-2 [2021-12-19 19:17:36,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1281749155, now seen corresponding path program 1 times [2021-12-19 19:17:36,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794572884] [2021-12-19 19:17:36,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,605 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:36,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:36,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:36,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:36,641 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794572884] [2021-12-19 19:17:36,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794572884] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:36,641 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:36,641 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:36,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210803477] [2021-12-19 19:17:36,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:36,642 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:36,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,643 INFO L85 PathProgramCache]: Analyzing trace with hash 296653803, now seen corresponding path program 1 times [2021-12-19 19:17:36,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426199842] [2021-12-19 19:17:36,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:36,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:36,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:36,674 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:36,674 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426199842] [2021-12-19 19:17:36,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426199842] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:36,674 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:36,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:36,675 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1623865842] [2021-12-19 19:17:36,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:36,675 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:36,675 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:36,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:36,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:36,676 INFO L87 Difference]: Start difference. First operand 12660 states and 18465 transitions. cyclomatic complexity: 5813 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,027 INFO L93 Difference]: Finished difference Result 29834 states and 43207 transitions. [2021-12-19 19:17:37,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:37,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29834 states and 43207 transitions. [2021-12-19 19:17:37,189 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 29599 [2021-12-19 19:17:37,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29834 states to 29834 states and 43207 transitions. [2021-12-19 19:17:37,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29834 [2021-12-19 19:17:37,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29834 [2021-12-19 19:17:37,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29834 states and 43207 transitions. [2021-12-19 19:17:37,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,496 INFO L681 BuchiCegarLoop]: Abstraction has 29834 states and 43207 transitions. [2021-12-19 19:17:37,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29834 states and 43207 transitions. [2021-12-19 19:17:37,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29834 to 23847. [2021-12-19 19:17:37,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23847 states, 23847 states have (on average 1.4526774856376063) internal successors, (34642), 23846 states have internal predecessors, (34642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23847 states to 23847 states and 34642 transitions. [2021-12-19 19:17:38,075 INFO L704 BuchiCegarLoop]: Abstraction has 23847 states and 34642 transitions. [2021-12-19 19:17:38,075 INFO L587 BuchiCegarLoop]: Abstraction has 23847 states and 34642 transitions. [2021-12-19 19:17:38,075 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:38,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23847 states and 34642 transitions. [2021-12-19 19:17:38,246 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 23668 [2021-12-19 19:17:38,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,249 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,249 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,249 INFO L791 eck$LassoCheckResult]: Stem: 102678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 102679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 102246#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 102247#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102875#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 102876#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102853#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102620#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 102621#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 102420#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 102421#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 102963#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 102835#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 102486#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 102252#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 102253#L922 assume !(0 == ~M_E~0); 103053#L922-2 assume !(0 == ~T1_E~0); 103054#L927-1 assume !(0 == ~T2_E~0); 102688#L932-1 assume !(0 == ~T3_E~0); 102560#L937-1 assume !(0 == ~T4_E~0); 102561#L942-1 assume !(0 == ~T5_E~0); 102619#L947-1 assume !(0 == ~T6_E~0); 102694#L952-1 assume !(0 == ~T7_E~0); 102695#L957-1 assume !(0 == ~T8_E~0); 102779#L962-1 assume !(0 == ~T9_E~0); 102534#L967-1 assume !(0 == ~E_1~0); 102535#L972-1 assume !(0 == ~E_2~0); 102860#L977-1 assume !(0 == ~E_3~0); 102861#L982-1 assume !(0 == ~E_4~0); 102023#L987-1 assume !(0 == ~E_5~0); 102024#L992-1 assume !(0 == ~E_6~0); 102032#L997-1 assume !(0 == ~E_7~0); 102461#L1002-1 assume !(0 == ~E_8~0); 102445#L1007-1 assume !(0 == ~E_9~0); 101821#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101822#L443 assume !(1 == ~m_pc~0); 102715#L443-2 is_master_triggered_~__retres1~0#1 := 0; 102702#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102703#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102185#L1140 assume !(0 != activate_threads_~tmp~1#1); 101935#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101936#L462 assume !(1 == ~t1_pc~0); 102552#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102553#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 101907#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 101908#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 102401#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102402#L481 assume !(1 == ~t2_pc~0); 102180#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102179#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102557#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102275#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 102276#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102375#L500 assume !(1 == ~t3_pc~0); 102927#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 102889#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102844#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 102845#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 101823#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101824#L519 assume !(1 == ~t4_pc~0); 102607#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102373#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102374#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 102225#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 102226#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 101990#L538 assume !(1 == ~t5_pc~0); 101991#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 101897#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 101898#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 102163#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 102164#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 102760#L557 assume 1 == ~t6_pc~0; 102522#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 102202#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 102101#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102102#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 102227#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103006#L576 assume !(1 == ~t7_pc~0); 102189#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 102190#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 102448#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 102449#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 102827#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 102313#L595 assume 1 == ~t8_pc~0; 102314#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 102846#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 102847#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 102649#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 102650#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 102115#L614 assume !(1 == ~t9_pc~0); 102116#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 102014#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 102015#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102193#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 102277#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102278#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 102544#L1025-2 assume !(1 == ~T1_E~0); 102751#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 102752#L1035-1 assume !(1 == ~T3_E~0); 102271#L1040-1 assume !(1 == ~T4_E~0); 102272#L1045-1 assume !(1 == ~T5_E~0); 102174#L1050-1 assume !(1 == ~T6_E~0); 102175#L1055-1 assume !(1 == ~T7_E~0); 109751#L1060-1 assume !(1 == ~T8_E~0); 109745#L1065-1 assume !(1 == ~T9_E~0); 109746#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 102696#L1075-1 assume !(1 == ~E_2~0); 102697#L1080-1 assume !(1 == ~E_3~0); 109728#L1085-1 assume !(1 == ~E_4~0); 109727#L1090-1 assume !(1 == ~E_5~0); 109726#L1095-1 assume !(1 == ~E_6~0); 109725#L1100-1 assume !(1 == ~E_7~0); 109724#L1105-1 assume !(1 == ~E_8~0); 109723#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 109721#L1115-1 assume { :end_inline_reset_delta_events } true; 109716#L1396-2 [2021-12-19 19:17:38,250 INFO L793 eck$LassoCheckResult]: Loop: 109716#L1396-2 assume !false; 109694#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 109682#L897 assume !false; 109677#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 109543#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 109528#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 109524#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 109516#L766 assume !(0 != eval_~tmp~0#1); 109517#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 113962#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 113954#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 113949#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 113944#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 113939#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 113935#L937-3 assume !(0 == ~T4_E~0); 113930#L942-3 assume !(0 == ~T5_E~0); 113924#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 113918#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 113912#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 113907#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 113902#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 113898#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 113894#L977-3 assume !(0 == ~E_3~0); 113888#L982-3 assume !(0 == ~E_4~0); 113883#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 113878#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 113875#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 113871#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 113866#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 113862#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 113858#L443-30 assume !(1 == ~m_pc~0); 113853#L443-32 is_master_triggered_~__retres1~0#1 := 0; 113848#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113843#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 113838#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 113833#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 113827#L462-30 assume !(1 == ~t1_pc~0); 113822#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 113816#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 113811#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 113805#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 113801#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113798#L481-30 assume 1 == ~t2_pc~0; 113795#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 113793#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113791#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 113788#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 113786#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110367#L500-30 assume !(1 == ~t3_pc~0); 110362#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 110357#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110351#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110350#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110349#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110348#L519-30 assume !(1 == ~t4_pc~0); 105432#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 110347#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110346#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110345#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110344#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110343#L538-30 assume 1 == ~t5_pc~0; 110321#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 110318#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110316#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 110314#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 110312#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110310#L557-30 assume 1 == ~t6_pc~0; 110307#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 110306#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110304#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110302#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 110300#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110298#L576-30 assume 1 == ~t7_pc~0; 110295#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 110292#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110290#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110288#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 110286#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110284#L595-30 assume 1 == ~t8_pc~0; 110281#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 110278#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110276#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 110274#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110272#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 110270#L614-30 assume 1 == ~t9_pc~0; 110267#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 110264#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 110262#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110260#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 110258#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110256#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 110252#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 110249#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 110247#L1035-3 assume !(1 == ~T3_E~0); 110245#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 110241#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110239#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 110237#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 110234#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 110232#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 110230#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 110228#L1075-3 assume !(1 == ~E_2~0); 110226#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 110222#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 110220#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 110218#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 110216#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 110214#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 110212#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 110210#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 110190#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 110188#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 110186#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 110185#L1415 assume !(0 == start_simulation_~tmp~3#1); 110183#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 110181#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 110172#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 109788#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 109777#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109772#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109735#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 109722#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 109716#L1396-2 [2021-12-19 19:17:38,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,250 INFO L85 PathProgramCache]: Analyzing trace with hash -1273998596, now seen corresponding path program 1 times [2021-12-19 19:17:38,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695785701] [2021-12-19 19:17:38,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695785701] [2021-12-19 19:17:38,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695785701] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:38,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104763548] [2021-12-19 19:17:38,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,327 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1066522925, now seen corresponding path program 1 times [2021-12-19 19:17:38,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527304164] [2021-12-19 19:17:38,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,329 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527304164] [2021-12-19 19:17:38,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527304164] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,369 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003671870] [2021-12-19 19:17:38,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,369 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:38,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:38,370 INFO L87 Difference]: Start difference. First operand 23847 states and 34642 transitions. cyclomatic complexity: 10803 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,889 INFO L93 Difference]: Finished difference Result 60154 states and 87679 transitions. [2021-12-19 19:17:38,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:38,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60154 states and 87679 transitions. [2021-12-19 19:17:39,470 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 59760 [2021-12-19 19:17:39,809 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60154 states to 60154 states and 87679 transitions. [2021-12-19 19:17:39,809 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60154 [2021-12-19 19:17:39,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60154 [2021-12-19 19:17:39,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60154 states and 87679 transitions. [2021-12-19 19:17:39,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,907 INFO L681 BuchiCegarLoop]: Abstraction has 60154 states and 87679 transitions. [2021-12-19 19:17:39,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60154 states and 87679 transitions. [2021-12-19 19:17:40,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60154 to 24642. [2021-12-19 19:17:40,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24642 states, 24642 states have (on average 1.4380732083434786) internal successors, (35437), 24641 states have internal predecessors, (35437), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24642 states to 24642 states and 35437 transitions. [2021-12-19 19:17:40,671 INFO L704 BuchiCegarLoop]: Abstraction has 24642 states and 35437 transitions. [2021-12-19 19:17:40,671 INFO L587 BuchiCegarLoop]: Abstraction has 24642 states and 35437 transitions. [2021-12-19 19:17:40,671 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:40,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24642 states and 35437 transitions. [2021-12-19 19:17:40,754 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 24460 [2021-12-19 19:17:40,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:40,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:40,756 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,757 INFO L791 eck$LassoCheckResult]: Stem: 186723#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 186724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 186266#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186267#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186922#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 186923#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 186901#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 186660#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186661#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186445#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186446#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 187018#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 186882#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 186511#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 186272#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186273#L922 assume !(0 == ~M_E~0); 187126#L922-2 assume !(0 == ~T1_E~0); 187127#L927-1 assume !(0 == ~T2_E~0); 186733#L932-1 assume !(0 == ~T3_E~0); 186595#L937-1 assume !(0 == ~T4_E~0); 186596#L942-1 assume !(0 == ~T5_E~0); 186659#L947-1 assume !(0 == ~T6_E~0); 186738#L952-1 assume !(0 == ~T7_E~0); 186739#L957-1 assume !(0 == ~T8_E~0); 186822#L962-1 assume !(0 == ~T9_E~0); 186569#L967-1 assume !(0 == ~E_1~0); 186570#L972-1 assume !(0 == ~E_2~0); 186906#L977-1 assume !(0 == ~E_3~0); 186907#L982-1 assume !(0 == ~E_4~0); 186042#L987-1 assume !(0 == ~E_5~0); 186043#L992-1 assume !(0 == ~E_6~0); 186049#L997-1 assume !(0 == ~E_7~0); 186488#L1002-1 assume !(0 == ~E_8~0); 186474#L1007-1 assume !(0 == ~E_9~0); 185835#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185836#L443 assume !(1 == ~m_pc~0); 186757#L443-2 is_master_triggered_~__retres1~0#1 := 0; 186747#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186748#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186203#L1140 assume !(0 != activate_threads_~tmp~1#1); 185950#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185951#L462 assume !(1 == ~t1_pc~0); 186590#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186591#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185921#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185922#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 186425#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186426#L481 assume !(1 == ~t2_pc~0); 186198#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186197#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186592#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186296#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 186297#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186398#L500 assume !(1 == ~t3_pc~0); 186978#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 186942#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186893#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186894#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 185840#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 185841#L519 assume !(1 == ~t4_pc~0); 186645#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186394#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186395#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186246#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 186247#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186007#L538 assume !(1 == ~t5_pc~0); 186008#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185911#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 185912#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186181#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 186182#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 186801#L557 assume 1 == ~t6_pc~0; 186554#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 186221#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186125#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 186126#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 186248#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187081#L576 assume !(1 == ~t7_pc~0); 186207#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 186208#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186476#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 186477#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 186868#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 186335#L595 assume 1 == ~t8_pc~0; 186336#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 186895#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186896#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 186690#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 186691#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 186132#L614 assume !(1 == ~t9_pc~0); 186133#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 186032#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 186033#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 186211#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 186298#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186299#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 186576#L1025-2 assume !(1 == ~T1_E~0); 186637#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 186945#L1035-1 assume !(1 == ~T3_E~0); 186293#L1040-1 assume !(1 == ~T4_E~0); 186294#L1045-1 assume !(1 == ~T5_E~0); 193490#L1050-1 assume !(1 == ~T6_E~0); 193488#L1055-1 assume !(1 == ~T7_E~0); 193486#L1060-1 assume !(1 == ~T8_E~0); 193484#L1065-1 assume !(1 == ~T9_E~0); 193482#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 193480#L1075-1 assume !(1 == ~E_2~0); 193382#L1080-1 assume !(1 == ~E_3~0); 193379#L1085-1 assume !(1 == ~E_4~0); 193219#L1090-1 assume !(1 == ~E_5~0); 193217#L1095-1 assume !(1 == ~E_6~0); 193216#L1100-1 assume !(1 == ~E_7~0); 193215#L1105-1 assume !(1 == ~E_8~0); 193214#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 193212#L1115-1 assume { :end_inline_reset_delta_events } true; 193161#L1396-2 [2021-12-19 19:17:40,757 INFO L793 eck$LassoCheckResult]: Loop: 193161#L1396-2 assume !false; 192983#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192978#L897 assume !false; 192976#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 192727#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 192717#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 192716#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 192586#L766 assume !(0 != eval_~tmp~0#1); 192587#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199881#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199877#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199872#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 199868#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 199863#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199859#L937-3 assume !(0 == ~T4_E~0); 199854#L942-3 assume !(0 == ~T5_E~0); 199850#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 199845#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 199841#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 199836#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 199832#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199827#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 199781#L977-3 assume !(0 == ~E_3~0); 199776#L982-3 assume !(0 == ~E_4~0); 199774#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199772#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 199526#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 199525#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 199524#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 199515#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199513#L443-30 assume !(1 == ~m_pc~0); 199511#L443-32 is_master_triggered_~__retres1~0#1 := 0; 199508#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199506#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199504#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 199502#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199500#L462-30 assume !(1 == ~t1_pc~0); 199497#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 199495#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199493#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199491#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 199489#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199487#L481-30 assume !(1 == ~t2_pc~0); 199486#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 199483#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199481#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 199479#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 199477#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189671#L500-30 assume !(1 == ~t3_pc~0); 189670#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 189669#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189668#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189667#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189666#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189665#L519-30 assume !(1 == ~t4_pc~0); 189664#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 189663#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189662#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189661#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189659#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189660#L538-30 assume !(1 == ~t5_pc~0); 189654#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 189655#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189646#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 189647#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 197982#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 197980#L557-30 assume !(1 == ~t6_pc~0); 197978#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 197975#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 197971#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 197969#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 197967#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 197966#L576-30 assume !(1 == ~t7_pc~0); 197965#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 197959#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 197956#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 197955#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 197954#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 197953#L595-30 assume !(1 == ~t8_pc~0); 197951#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 197949#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 197947#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 197942#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 197941#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 197547#L614-30 assume 1 == ~t9_pc~0; 197543#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 197540#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 197538#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 197536#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 197534#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197532#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 189174#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 197528#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 197526#L1035-3 assume !(1 == ~T3_E~0); 197524#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189165#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 197521#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 197519#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 197516#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 197514#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 197512#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 197510#L1075-3 assume !(1 == ~E_2~0); 195757#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 195014#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 195754#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 195753#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 195752#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 195278#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 195276#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 195274#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 194905#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 194904#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 194903#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 194902#L1415 assume !(0 == start_simulation_~tmp~3#1); 189579#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 194589#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 194579#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 194270#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 193805#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193568#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193378#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 193213#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 193161#L1396-2 [2021-12-19 19:17:40,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,758 INFO L85 PathProgramCache]: Analyzing trace with hash 654274106, now seen corresponding path program 1 times [2021-12-19 19:17:40,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,758 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112374017] [2021-12-19 19:17:40,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,800 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112374017] [2021-12-19 19:17:40,801 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112374017] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:40,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [162789409] [2021-12-19 19:17:40,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,802 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:40,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1339216646, now seen corresponding path program 1 times [2021-12-19 19:17:40,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535590478] [2021-12-19 19:17:40,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,833 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535590478] [2021-12-19 19:17:40,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535590478] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,834 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,834 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:40,834 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864761909] [2021-12-19 19:17:40,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,835 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:40,835 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:40,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:40,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:40,836 INFO L87 Difference]: Start difference. First operand 24642 states and 35437 transitions. cyclomatic complexity: 10803 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:41,319 INFO L93 Difference]: Finished difference Result 57657 states and 82442 transitions. [2021-12-19 19:17:41,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:41,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57657 states and 82442 transitions. [2021-12-19 19:17:41,604 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 57348 [2021-12-19 19:17:41,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57657 states to 57657 states and 82442 transitions. [2021-12-19 19:17:41,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57657 [2021-12-19 19:17:41,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57657 [2021-12-19 19:17:41,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57657 states and 82442 transitions. [2021-12-19 19:17:42,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:42,034 INFO L681 BuchiCegarLoop]: Abstraction has 57657 states and 82442 transitions. [2021-12-19 19:17:42,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57657 states and 82442 transitions. [2021-12-19 19:17:42,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57657 to 46437. [2021-12-19 19:17:42,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46437 states, 46437 states have (on average 1.433469001012124) internal successors, (66566), 46436 states have internal predecessors, (66566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:42,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46437 states to 46437 states and 66566 transitions. [2021-12-19 19:17:42,736 INFO L704 BuchiCegarLoop]: Abstraction has 46437 states and 66566 transitions. [2021-12-19 19:17:42,736 INFO L587 BuchiCegarLoop]: Abstraction has 46437 states and 66566 transitions. [2021-12-19 19:17:42,737 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:42,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46437 states and 66566 transitions. [2021-12-19 19:17:42,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 46240 [2021-12-19 19:17:42,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:42,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:42,911 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,911 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,911 INFO L791 eck$LassoCheckResult]: Stem: 269022#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 269023#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 268576#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 268577#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 269217#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 269218#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 269194#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 268965#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 268966#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 268756#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 268757#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 269309#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 269172#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 268818#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 268582#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 268583#L922 assume !(0 == ~M_E~0); 269391#L922-2 assume !(0 == ~T1_E~0); 269392#L927-1 assume !(0 == ~T2_E~0); 269030#L932-1 assume !(0 == ~T3_E~0); 268897#L937-1 assume !(0 == ~T4_E~0); 268898#L942-1 assume !(0 == ~T5_E~0); 268964#L947-1 assume !(0 == ~T6_E~0); 269034#L952-1 assume !(0 == ~T7_E~0); 269035#L957-1 assume !(0 == ~T8_E~0); 269115#L962-1 assume !(0 == ~T9_E~0); 268867#L967-1 assume !(0 == ~E_1~0); 268868#L972-1 assume !(0 == ~E_2~0); 269203#L977-1 assume !(0 == ~E_3~0); 269204#L982-1 assume !(0 == ~E_4~0); 268348#L987-1 assume !(0 == ~E_5~0); 268349#L992-1 assume !(0 == ~E_6~0); 268357#L997-1 assume !(0 == ~E_7~0); 268793#L1002-1 assume !(0 == ~E_8~0); 268781#L1007-1 assume !(0 == ~E_9~0); 268144#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 268145#L443 assume !(1 == ~m_pc~0); 269051#L443-2 is_master_triggered_~__retres1~0#1 := 0; 269040#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269041#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 268514#L1140 assume !(0 != activate_threads_~tmp~1#1); 268259#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 268260#L462 assume !(1 == ~t1_pc~0); 268891#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 268892#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 268230#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268231#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 268736#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 268737#L481 assume !(1 == ~t2_pc~0); 268509#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 268508#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 268894#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 268605#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 268606#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 268708#L500 assume !(1 == ~t3_pc~0); 269271#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 269235#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269184#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269185#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 268149#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 268150#L519 assume !(1 == ~t4_pc~0); 268947#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 268706#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 268707#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 268555#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 268556#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 268316#L538 assume !(1 == ~t5_pc~0); 268317#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 268220#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268221#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 268492#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 268493#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269096#L557 assume !(1 == ~t6_pc~0); 268531#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 268532#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 268430#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 268431#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 268557#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269358#L576 assume !(1 == ~t7_pc~0); 268518#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 268519#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 268783#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 268784#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 269162#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 268646#L595 assume 1 == ~t8_pc~0; 268647#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269186#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269187#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 268993#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 268994#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 268443#L614 assume !(1 == ~t9_pc~0); 268444#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 268341#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 268342#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 268522#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 268607#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268608#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 268877#L1025-2 assume !(1 == ~T1_E~0); 269088#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 269089#L1035-1 assume !(1 == ~T3_E~0); 268601#L1040-1 assume !(1 == ~T4_E~0); 268602#L1045-1 assume !(1 == ~T5_E~0); 268504#L1050-1 assume !(1 == ~T6_E~0); 268505#L1055-1 assume !(1 == ~T7_E~0); 268325#L1060-1 assume !(1 == ~T8_E~0); 268326#L1065-1 assume !(1 == ~T9_E~0); 268388#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 269036#L1075-1 assume !(1 == ~E_2~0); 269037#L1080-1 assume !(1 == ~E_3~0); 269409#L1085-1 assume !(1 == ~E_4~0); 269302#L1090-1 assume !(1 == ~E_5~0); 269303#L1095-1 assume !(1 == ~E_6~0); 269066#L1100-1 assume !(1 == ~E_7~0); 269067#L1105-1 assume !(1 == ~E_8~0); 268297#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 268298#L1115-1 assume { :end_inline_reset_delta_events } true; 308133#L1396-2 [2021-12-19 19:17:42,912 INFO L793 eck$LassoCheckResult]: Loop: 308133#L1396-2 assume !false; 308132#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308127#L897 assume !false; 308126#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 308124#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 308112#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 308110#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 308107#L766 assume !(0 != eval_~tmp~0#1); 308108#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 313143#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 313142#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 313139#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 313137#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 313135#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 313132#L937-3 assume !(0 == ~T4_E~0); 313130#L942-3 assume !(0 == ~T5_E~0); 313124#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 313121#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 313119#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 313117#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 313115#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 313113#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 313111#L977-3 assume !(0 == ~E_3~0); 313108#L982-3 assume !(0 == ~E_4~0); 313106#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 313104#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 313102#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 311858#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 311854#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 311852#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 311850#L443-30 assume 1 == ~m_pc~0; 311847#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 311844#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 311842#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 311840#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 311837#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 311835#L462-30 assume !(1 == ~t1_pc~0); 311833#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 311831#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 311829#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 311827#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 311824#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 311822#L481-30 assume !(1 == ~t2_pc~0); 311820#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 311817#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 311815#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 311813#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 311810#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 311808#L500-30 assume !(1 == ~t3_pc~0); 307803#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 311805#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 311803#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 311801#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 311798#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 311796#L519-30 assume !(1 == ~t4_pc~0); 309762#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 311787#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311786#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 311785#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 311784#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311783#L538-30 assume !(1 == ~t5_pc~0); 311781#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 311779#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311777#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 311776#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 311774#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 311773#L557-30 assume !(1 == ~t6_pc~0); 276717#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 311772#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311770#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 311767#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 311765#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 311763#L576-30 assume 1 == ~t7_pc~0; 311760#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 311758#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 311756#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 311753#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 311751#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 311749#L595-30 assume 1 == ~t8_pc~0; 311746#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 311744#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 311742#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 311739#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 311737#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 311735#L614-30 assume !(1 == ~t9_pc~0); 311732#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 311730#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 311729#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 311728#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 310234#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 268983#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 268738#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 268739#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 268940#L1035-3 assume !(1 == ~T3_E~0); 269314#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269388#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 308452#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 308450#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 308448#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 308445#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 308443#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 308441#L1075-3 assume !(1 == ~E_2~0); 308439#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 306098#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 308436#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 308433#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 308431#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 308429#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 308427#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 308425#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 308399#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 308397#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 308395#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 308393#L1415 assume !(0 == start_simulation_~tmp~3#1); 268944#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 308189#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 308179#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 308177#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 308175#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 308172#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 308170#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 308138#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 308133#L1396-2 [2021-12-19 19:17:42,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,913 INFO L85 PathProgramCache]: Analyzing trace with hash -620828583, now seen corresponding path program 1 times [2021-12-19 19:17:42,913 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,913 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591613290] [2021-12-19 19:17:42,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,913 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,954 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,954 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [591613290] [2021-12-19 19:17:42,955 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [591613290] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,955 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,955 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,955 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809314434] [2021-12-19 19:17:42,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,956 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:42,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,956 INFO L85 PathProgramCache]: Analyzing trace with hash -2095427768, now seen corresponding path program 1 times [2021-12-19 19:17:42,956 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,956 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055265358] [2021-12-19 19:17:42,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,993 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,993 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055265358] [2021-12-19 19:17:42,994 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055265358] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,994 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,994 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,994 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [805551858] [2021-12-19 19:17:42,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,995 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:42,995 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:42,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:42,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:42,996 INFO L87 Difference]: Start difference. First operand 46437 states and 66566 transitions. cyclomatic complexity: 20137 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:43,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:43,799 INFO L93 Difference]: Finished difference Result 107664 states and 153575 transitions. [2021-12-19 19:17:43,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:43,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107664 states and 153575 transitions. [2021-12-19 19:17:44,318 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 107212 [2021-12-19 19:17:44,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107664 states to 107664 states and 153575 transitions. [2021-12-19 19:17:44,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107664 [2021-12-19 19:17:45,055 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107664 [2021-12-19 19:17:45,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107664 states and 153575 transitions. [2021-12-19 19:17:45,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:45,142 INFO L681 BuchiCegarLoop]: Abstraction has 107664 states and 153575 transitions. [2021-12-19 19:17:45,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107664 states and 153575 transitions. [2021-12-19 19:17:46,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107664 to 87412. [2021-12-19 19:17:46,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87412 states, 87412 states have (on average 1.4297693680501533) internal successors, (124979), 87411 states have internal predecessors, (124979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:46,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87412 states to 87412 states and 124979 transitions. [2021-12-19 19:17:46,620 INFO L704 BuchiCegarLoop]: Abstraction has 87412 states and 124979 transitions. [2021-12-19 19:17:46,620 INFO L587 BuchiCegarLoop]: Abstraction has 87412 states and 124979 transitions. [2021-12-19 19:17:46,620 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:46,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87412 states and 124979 transitions. [2021-12-19 19:17:46,847 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 87184 [2021-12-19 19:17:46,848 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:46,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:46,853 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:46,853 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:46,853 INFO L791 eck$LassoCheckResult]: Stem: 423140#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 423141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 422683#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 422684#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 423334#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 423335#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 423310#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 423080#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 423081#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 422865#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 422866#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 423438#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 423286#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 422934#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 422691#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 422692#L922 assume !(0 == ~M_E~0); 423530#L922-2 assume !(0 == ~T1_E~0); 423531#L927-1 assume !(0 == ~T2_E~0); 423152#L932-1 assume !(0 == ~T3_E~0); 423016#L937-1 assume !(0 == ~T4_E~0); 423017#L942-1 assume !(0 == ~T5_E~0); 423079#L947-1 assume !(0 == ~T6_E~0); 423156#L952-1 assume !(0 == ~T7_E~0); 423157#L957-1 assume !(0 == ~T8_E~0); 423228#L962-1 assume !(0 == ~T9_E~0); 422986#L967-1 assume !(0 == ~E_1~0); 422987#L972-1 assume !(0 == ~E_2~0); 423318#L977-1 assume !(0 == ~E_3~0); 423319#L982-1 assume !(0 == ~E_4~0); 422456#L987-1 assume !(0 == ~E_5~0); 422457#L992-1 assume !(0 == ~E_6~0); 422465#L997-1 assume !(0 == ~E_7~0); 422910#L1002-1 assume !(0 == ~E_8~0); 422893#L1007-1 assume !(0 == ~E_9~0); 422255#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 422256#L443 assume !(1 == ~m_pc~0); 423174#L443-2 is_master_triggered_~__retres1~0#1 := 0; 423163#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 423164#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 422621#L1140 assume !(0 != activate_threads_~tmp~1#1); 422370#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422371#L462 assume !(1 == ~t1_pc~0); 423007#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 423008#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422341#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422342#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 422845#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422846#L481 assume !(1 == ~t2_pc~0); 422616#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 422615#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423013#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 422716#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 422717#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422819#L500 assume !(1 == ~t3_pc~0); 423395#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 423352#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 423299#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 423300#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 422257#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 422258#L519 assume !(1 == ~t4_pc~0); 423063#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 422817#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 422818#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422663#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 422664#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 422424#L538 assume !(1 == ~t5_pc~0); 422425#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 422331#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 422332#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 422599#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 422600#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 423212#L557 assume !(1 == ~t6_pc~0); 422638#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 422639#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 422535#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 422536#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 422665#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 423492#L576 assume !(1 == ~t7_pc~0); 422625#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 422626#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 422897#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 422898#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 423276#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 422758#L595 assume !(1 == ~t8_pc~0); 422759#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 423301#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 423302#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 423108#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 423109#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 422549#L614 assume !(1 == ~t9_pc~0); 422550#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 422448#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 422449#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 422629#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 422718#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 422719#L1025 assume 1 == ~M_E~0;~M_E~0 := 2; 422997#L1025-2 assume !(1 == ~T1_E~0); 423204#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 423205#L1035-1 assume !(1 == ~T3_E~0); 422711#L1040-1 assume !(1 == ~T4_E~0); 422712#L1045-1 assume !(1 == ~T5_E~0); 422611#L1050-1 assume !(1 == ~T6_E~0); 422612#L1055-1 assume !(1 == ~T7_E~0); 422433#L1060-1 assume !(1 == ~T8_E~0); 422434#L1065-1 assume !(1 == ~T9_E~0); 422496#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 423158#L1075-1 assume !(1 == ~E_2~0); 423159#L1080-1 assume !(1 == ~E_3~0); 423147#L1085-1 assume !(1 == ~E_4~0); 423148#L1090-1 assume !(1 == ~E_5~0); 423428#L1095-1 assume !(1 == ~E_6~0); 423185#L1100-1 assume !(1 == ~E_7~0); 423186#L1105-1 assume !(1 == ~E_8~0); 422406#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 422407#L1115-1 assume { :end_inline_reset_delta_events } true; 422770#L1396-2 [2021-12-19 19:17:46,854 INFO L793 eck$LassoCheckResult]: Loop: 422770#L1396-2 assume !false; 499855#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 499850#L897 assume !false; 499849#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 499848#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 499838#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 499837#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 498860#L766 assume !(0 != eval_~tmp~0#1); 498861#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 509109#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 509107#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 509104#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 509101#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 509097#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 509094#L937-3 assume !(0 == ~T4_E~0); 509091#L942-3 assume !(0 == ~T5_E~0); 509088#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 509085#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 509081#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 509079#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 509077#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 423442#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 423150#L977-3 assume !(0 == ~E_3~0); 423151#L982-3 assume !(0 == ~E_4~0); 423543#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 422729#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 422730#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 422724#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 422725#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 423098#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 508955#L443-30 assume 1 == ~m_pc~0; 508951#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 508948#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 508937#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 423499#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 423324#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 422874#L462-30 assume !(1 == ~t1_pc~0); 422875#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 423317#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 423296#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 423297#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423355#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 422859#L481-30 assume !(1 == ~t2_pc~0); 422558#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 422557#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423282#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 508561#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 422824#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 422825#L500-30 assume !(1 == ~t3_pc~0); 423168#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 508166#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 508164#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 508162#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 508160#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 508158#L519-30 assume !(1 == ~t4_pc~0); 504917#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 508157#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 508156#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 508154#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 504377#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 504376#L538-30 assume 1 == ~t5_pc~0; 504375#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 504373#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 504371#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 504368#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 504367#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 499990#L557-30 assume !(1 == ~t6_pc~0); 499988#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 499985#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 499983#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 499981#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 499980#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 499979#L576-30 assume !(1 == ~t7_pc~0); 499978#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 499976#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 499975#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 499974#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 499973#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 499972#L595-30 assume !(1 == ~t8_pc~0); 467183#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 499971#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 499969#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 499967#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 499965#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 499963#L614-30 assume !(1 == ~t9_pc~0); 499961#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 499957#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 499955#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 499953#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 499951#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 499949#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 482124#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 499947#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 499945#L1035-3 assume !(1 == ~T3_E~0); 499943#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 486684#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 499940#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 499938#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 499935#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 499933#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 499931#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 499929#L1075-3 assume !(1 == ~E_2~0); 499927#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 491597#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 499924#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 499922#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 499920#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 499918#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 499916#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 499914#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 499894#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 499892#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 499890#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 499889#L1415 assume !(0 == start_simulation_~tmp~3#1); 499887#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 499885#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 499876#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 499875#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 499873#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 499868#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 499864#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 499859#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 422770#L1396-2 [2021-12-19 19:17:46,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:46,855 INFO L85 PathProgramCache]: Analyzing trace with hash 298146040, now seen corresponding path program 1 times [2021-12-19 19:17:46,855 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:46,855 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797850775] [2021-12-19 19:17:46,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:46,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:46,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:46,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:46,885 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:46,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797850775] [2021-12-19 19:17:46,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797850775] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:46,886 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:46,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:46,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523940062] [2021-12-19 19:17:46,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:46,886 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:46,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:46,887 INFO L85 PathProgramCache]: Analyzing trace with hash 1235612073, now seen corresponding path program 1 times [2021-12-19 19:17:46,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:46,887 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607194151] [2021-12-19 19:17:46,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:46,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:46,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:46,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:46,918 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:46,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607194151] [2021-12-19 19:17:46,918 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607194151] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:46,919 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:46,919 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:46,919 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98865818] [2021-12-19 19:17:46,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:46,919 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:46,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:46,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:46,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:46,921 INFO L87 Difference]: Start difference. First operand 87412 states and 124979 transitions. cyclomatic complexity: 37575 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:47,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:47,403 INFO L93 Difference]: Finished difference Result 110248 states and 156761 transitions. [2021-12-19 19:17:47,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:47,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110248 states and 156761 transitions. [2021-12-19 19:17:48,291 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 110016 [2021-12-19 19:17:48,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110248 states to 110248 states and 156761 transitions. [2021-12-19 19:17:48,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110248 [2021-12-19 19:17:48,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110248 [2021-12-19 19:17:48,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110248 states and 156761 transitions. [2021-12-19 19:17:48,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:48,846 INFO L681 BuchiCegarLoop]: Abstraction has 110248 states and 156761 transitions. [2021-12-19 19:17:48,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110248 states and 156761 transitions. [2021-12-19 19:17:49,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110248 to 48139. [2021-12-19 19:17:49,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.4282390577286608) internal successors, (68754), 48138 states have internal predecessors, (68754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:49,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 68754 transitions. [2021-12-19 19:17:49,920 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 68754 transitions. [2021-12-19 19:17:49,920 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 68754 transitions. [2021-12-19 19:17:49,920 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:49,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 68754 transitions. [2021-12-19 19:17:50,032 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:17:50,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:50,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:50,036 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:50,037 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:50,037 INFO L791 eck$LassoCheckResult]: Stem: 620811#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 620812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 620354#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 620355#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 621037#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 621038#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 621007#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 620748#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 620749#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 620533#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 620534#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 621134#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 620980#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 620603#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 620360#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 620361#L922 assume !(0 == ~M_E~0); 621248#L922-2 assume !(0 == ~T1_E~0); 621249#L927-1 assume !(0 == ~T2_E~0); 620821#L932-1 assume !(0 == ~T3_E~0); 620680#L937-1 assume !(0 == ~T4_E~0); 620681#L942-1 assume !(0 == ~T5_E~0); 620747#L947-1 assume !(0 == ~T6_E~0); 620825#L952-1 assume !(0 == ~T7_E~0); 620826#L957-1 assume !(0 == ~T8_E~0); 620917#L962-1 assume !(0 == ~T9_E~0); 620659#L967-1 assume !(0 == ~E_1~0); 620660#L972-1 assume !(0 == ~E_2~0); 621017#L977-1 assume !(0 == ~E_3~0); 621018#L982-1 assume !(0 == ~E_4~0); 620128#L987-1 assume !(0 == ~E_5~0); 620129#L992-1 assume !(0 == ~E_6~0); 620135#L997-1 assume !(0 == ~E_7~0); 620577#L1002-1 assume !(0 == ~E_8~0); 620560#L1007-1 assume !(0 == ~E_9~0); 619922#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 619923#L443 assume !(1 == ~m_pc~0); 620843#L443-2 is_master_triggered_~__retres1~0#1 := 0; 620832#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 620833#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 620294#L1140 assume !(0 != activate_threads_~tmp~1#1); 620038#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 620039#L462 assume !(1 == ~t1_pc~0); 620675#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 620676#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 620008#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 620009#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 620515#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 620516#L481 assume !(1 == ~t2_pc~0); 620289#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 620288#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 620677#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 620384#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 620385#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 620489#L500 assume !(1 == ~t3_pc~0); 621095#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 621055#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 620993#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 620994#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 619927#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 619928#L519 assume !(1 == ~t4_pc~0); 620732#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 620485#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 620486#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 620337#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 620338#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 620094#L538 assume !(1 == ~t5_pc~0); 620095#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 619998#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 619999#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 620272#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 620273#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 620894#L557 assume !(1 == ~t6_pc~0); 620310#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 620311#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 620213#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 620214#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 620339#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 621187#L576 assume !(1 == ~t7_pc~0); 620298#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 620299#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 620562#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 620563#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 620964#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 620426#L595 assume !(1 == ~t8_pc~0); 620427#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 620995#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 620996#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 620782#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 620783#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 620220#L614 assume !(1 == ~t9_pc~0); 620221#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 620119#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 620120#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 620302#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 620386#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 620387#L1025 assume !(1 == ~M_E~0); 620665#L1025-2 assume !(1 == ~T1_E~0); 620722#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 620882#L1035-1 assume !(1 == ~T3_E~0); 620381#L1040-1 assume !(1 == ~T4_E~0); 620382#L1045-1 assume !(1 == ~T5_E~0); 620284#L1050-1 assume !(1 == ~T6_E~0); 620285#L1055-1 assume !(1 == ~T7_E~0); 620103#L1060-1 assume !(1 == ~T8_E~0); 620104#L1065-1 assume !(1 == ~T9_E~0); 620165#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 620827#L1075-1 assume !(1 == ~E_2~0); 620828#L1080-1 assume !(1 == ~E_3~0); 620816#L1085-1 assume !(1 == ~E_4~0); 620817#L1090-1 assume !(1 == ~E_5~0); 621126#L1095-1 assume !(1 == ~E_6~0); 620860#L1100-1 assume !(1 == ~E_7~0); 620861#L1105-1 assume !(1 == ~E_8~0); 620075#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 620076#L1115-1 assume { :end_inline_reset_delta_events } true; 620438#L1396-2 [2021-12-19 19:17:50,038 INFO L793 eck$LassoCheckResult]: Loop: 620438#L1396-2 assume !false; 655847#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 655840#L897 assume !false; 655838#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 655835#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 655824#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 655820#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 655817#L766 assume !(0 != eval_~tmp~0#1); 655818#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 661190#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 661188#L922-3 assume !(0 == ~M_E~0); 661185#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 661183#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 661181#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 661179#L937-3 assume !(0 == ~T4_E~0); 661177#L942-3 assume !(0 == ~T5_E~0); 661175#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 661172#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 661170#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 661168#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 661166#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 661164#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 661162#L977-3 assume !(0 == ~E_3~0); 661159#L982-3 assume !(0 == ~E_4~0); 661157#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 661155#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 661153#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 661151#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 661148#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 661147#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 661146#L443-30 assume !(1 == ~m_pc~0); 661142#L443-32 is_master_triggered_~__retres1~0#1 := 0; 661140#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 661138#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 661136#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 661134#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 661130#L462-30 assume !(1 == ~t1_pc~0); 661128#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 661126#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 661124#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 661121#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 661119#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 661117#L481-30 assume 1 == ~t2_pc~0; 661115#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 661113#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 661111#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 661109#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 661107#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 661105#L500-30 assume !(1 == ~t3_pc~0); 659390#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 661101#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 661100#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 661099#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 661098#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 634594#L519-30 assume !(1 == ~t4_pc~0); 634592#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 634589#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 634587#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 634585#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 634583#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 634581#L538-30 assume !(1 == ~t5_pc~0); 634579#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 634575#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 634572#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 634569#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 634566#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 634564#L557-30 assume !(1 == ~t6_pc~0); 634239#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 634552#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 634551#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 634550#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 634549#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 634548#L576-30 assume !(1 == ~t7_pc~0); 634547#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 634545#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634488#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 634487#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 634486#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 634484#L595-30 assume !(1 == ~t8_pc~0); 633888#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 634481#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 634479#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 634477#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 634475#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 634473#L614-30 assume 1 == ~t9_pc~0; 634469#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 634466#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 634463#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 634460#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 634458#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 634456#L1025-3 assume !(1 == ~M_E~0); 632164#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 634452#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 634450#L1035-3 assume !(1 == ~T3_E~0); 634448#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 634446#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 634444#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 634441#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 634439#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 634437#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 634435#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 634433#L1075-3 assume !(1 == ~E_2~0); 634431#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 634428#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 634426#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 634424#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 634422#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 634420#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 634418#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 634415#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 634403#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 634401#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 634399#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 634281#L1415 assume !(0 == start_simulation_~tmp~3#1); 634282#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 655869#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 655859#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 655857#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 655856#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 655854#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 655852#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 655850#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 620438#L1396-2 [2021-12-19 19:17:50,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:50,038 INFO L85 PathProgramCache]: Analyzing trace with hash -519502410, now seen corresponding path program 1 times [2021-12-19 19:17:50,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:50,039 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620137990] [2021-12-19 19:17:50,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:50,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:50,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:50,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:50,069 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:50,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620137990] [2021-12-19 19:17:50,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620137990] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:50,070 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:50,070 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:50,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891298029] [2021-12-19 19:17:50,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:50,071 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:50,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:50,071 INFO L85 PathProgramCache]: Analyzing trace with hash 1068404707, now seen corresponding path program 1 times [2021-12-19 19:17:50,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:50,071 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417961335] [2021-12-19 19:17:50,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:50,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:50,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:50,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:50,099 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:50,099 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417961335] [2021-12-19 19:17:50,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417961335] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:50,100 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:50,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:50,100 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106969543] [2021-12-19 19:17:50,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:50,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:50,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:50,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:50,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:50,102 INFO L87 Difference]: Start difference. First operand 48139 states and 68754 transitions. cyclomatic complexity: 20617 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:50,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:50,401 INFO L93 Difference]: Finished difference Result 76276 states and 108541 transitions. [2021-12-19 19:17:50,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:50,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76276 states and 108541 transitions. [2021-12-19 19:17:50,733 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 76000 [2021-12-19 19:17:50,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76276 states to 76276 states and 108541 transitions. [2021-12-19 19:17:50,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76276 [2021-12-19 19:17:50,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76276 [2021-12-19 19:17:50,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76276 states and 108541 transitions. [2021-12-19 19:17:51,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:51,344 INFO L681 BuchiCegarLoop]: Abstraction has 76276 states and 108541 transitions. [2021-12-19 19:17:51,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76276 states and 108541 transitions. [2021-12-19 19:17:51,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76276 to 54019. [2021-12-19 19:17:51,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54019 states, 54019 states have (on average 1.428460356541217) internal successors, (77164), 54018 states have internal predecessors, (77164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:51,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54019 states to 54019 states and 77164 transitions. [2021-12-19 19:17:51,887 INFO L704 BuchiCegarLoop]: Abstraction has 54019 states and 77164 transitions. [2021-12-19 19:17:51,887 INFO L587 BuchiCegarLoop]: Abstraction has 54019 states and 77164 transitions. [2021-12-19 19:17:51,888 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:51,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54019 states and 77164 transitions. [2021-12-19 19:17:52,060 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 53776 [2021-12-19 19:17:52,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:52,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:52,066 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:52,066 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:52,067 INFO L791 eck$LassoCheckResult]: Stem: 745237#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 745238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 744779#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 744780#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 745440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 745441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 745413#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 745174#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 745175#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 744956#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 744957#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 745540#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 745391#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 745026#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 744785#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 744786#L922 assume !(0 == ~M_E~0); 745637#L922-2 assume !(0 == ~T1_E~0); 745638#L927-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 745246#L932-1 assume !(0 == ~T3_E~0); 745247#L937-1 assume !(0 == ~T4_E~0); 745172#L942-1 assume !(0 == ~T5_E~0); 745173#L947-1 assume !(0 == ~T6_E~0); 745252#L952-1 assume !(0 == ~T7_E~0); 745253#L957-1 assume !(0 == ~T8_E~0); 745612#L962-1 assume !(0 == ~T9_E~0); 745613#L967-1 assume !(0 == ~E_1~0); 745592#L972-1 assume !(0 == ~E_2~0); 745593#L977-1 assume !(0 == ~E_3~0); 745643#L982-1 assume !(0 == ~E_4~0); 745644#L987-1 assume !(0 == ~E_5~0); 744558#L992-1 assume !(0 == ~E_6~0); 744559#L997-1 assume !(0 == ~E_7~0); 745561#L1002-1 assume !(0 == ~E_8~0); 745562#L1007-1 assume !(0 == ~E_9~0); 744347#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 744348#L443 assume !(1 == ~m_pc~0); 745270#L443-2 is_master_triggered_~__retres1~0#1 := 0; 745271#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 745608#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 745609#L1140 assume !(0 != activate_threads_~tmp~1#1); 744463#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 744464#L462 assume !(1 == ~t1_pc~0); 745095#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 745096#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 744433#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 744434#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 744938#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 744939#L481 assume !(1 == ~t2_pc~0); 744711#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 744710#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 745101#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745102#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 744909#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 744910#L500 assume !(1 == ~t3_pc~0); 745501#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 745502#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 745404#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 745405#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 744349#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 744350#L519 assume !(1 == ~t4_pc~0); 745155#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 745156#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 745286#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 745287#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 745202#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 745203#L538 assume !(1 == ~t5_pc~0); 744937#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 745527#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 745602#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 745603#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 745317#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 745318#L557 assume !(1 == ~t6_pc~0); 744734#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 744735#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 744627#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 744628#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 745587#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 745588#L576 assume !(1 == ~t7_pc~0); 744721#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 744722#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 744985#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 744986#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 745380#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 745381#L595 assume !(1 == ~t8_pc~0); 745683#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 745406#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 745407#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 745205#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 745206#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 745590#L614 assume !(1 == ~t9_pc~0); 745678#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 745677#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 745676#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 745389#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 744809#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 744810#L1025 assume !(1 == ~M_E~0); 745087#L1025-2 assume !(1 == ~T1_E~0); 745147#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 745309#L1035-1 assume !(1 == ~T3_E~0); 744803#L1040-1 assume !(1 == ~T4_E~0); 744804#L1045-1 assume !(1 == ~T5_E~0); 744706#L1050-1 assume !(1 == ~T6_E~0); 744707#L1055-1 assume !(1 == ~T7_E~0); 744526#L1060-1 assume !(1 == ~T8_E~0); 744527#L1065-1 assume !(1 == ~T9_E~0); 744589#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 745254#L1075-1 assume !(1 == ~E_2~0); 745255#L1080-1 assume !(1 == ~E_3~0); 745241#L1085-1 assume !(1 == ~E_4~0); 745242#L1090-1 assume !(1 == ~E_5~0); 745534#L1095-1 assume !(1 == ~E_6~0); 745283#L1100-1 assume !(1 == ~E_7~0); 745284#L1105-1 assume !(1 == ~E_8~0); 744499#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 744500#L1115-1 assume { :end_inline_reset_delta_events } true; 744861#L1396-2 [2021-12-19 19:17:52,067 INFO L793 eck$LassoCheckResult]: Loop: 744861#L1396-2 assume !false; 786371#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 786367#L897 assume !false; 786363#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 786360#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 786349#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 786346#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 786343#L766 assume !(0 != eval_~tmp~0#1); 786344#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 797573#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 744973#L922-3 assume !(0 == ~M_E~0); 744974#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 744685#L927-3 assume !(0 == ~T2_E~0); 744687#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 744875#L937-3 assume !(0 == ~T4_E~0); 744491#L942-3 assume !(0 == ~T5_E~0); 744492#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 744876#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 744877#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 745519#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 745348#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 745349#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 745244#L977-3 assume !(0 == ~E_3~0); 745245#L982-3 assume !(0 == ~E_4~0); 745652#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 745653#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 745006#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 744815#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 744816#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 798341#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 798340#L443-30 assume !(1 == ~m_pc~0); 798338#L443-32 is_master_triggered_~__retres1~0#1 := 0; 798337#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 745564#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 745565#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 745432#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 744962#L462-30 assume !(1 == ~t1_pc~0); 744963#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 745421#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745401#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 745402#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 798325#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 798261#L481-30 assume 1 == ~t2_pc~0; 798257#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 798254#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 798250#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 798246#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 798243#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 745264#L500-30 assume !(1 == ~t3_pc~0); 745265#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 798158#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 798144#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 798137#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 797932#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 796966#L519-30 assume !(1 == ~t4_pc~0); 796964#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 796962#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 796960#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 796958#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 796954#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796952#L538-30 assume !(1 == ~t5_pc~0); 796948#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 796946#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 796943#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796941#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 796938#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 796913#L557-30 assume !(1 == ~t6_pc~0); 775230#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 796912#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 795871#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 795870#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 795867#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 795865#L576-30 assume 1 == ~t7_pc~0; 795862#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 795861#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 795724#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 795723#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 795722#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 780683#L595-30 assume !(1 == ~t8_pc~0); 780680#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 780677#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 780676#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 780675#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 780674#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 780673#L614-30 assume 1 == ~t9_pc~0; 780671#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 780670#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 780669#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 780668#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 780667#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780666#L1025-3 assume !(1 == ~M_E~0); 768465#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 780399#L1030-3 assume !(1 == ~T2_E~0); 780395#L1035-3 assume !(1 == ~T3_E~0); 780393#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 780391#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 780389#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 780387#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 780383#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 780381#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 780379#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 780378#L1075-3 assume !(1 == ~E_2~0); 780377#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 771879#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 771639#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 771638#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 771634#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 771631#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 771628#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 771625#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 771563#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 771556#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 770726#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 745883#L1415 assume !(0 == start_simulation_~tmp~3#1); 745884#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 786395#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 786385#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 786383#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 786381#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 786378#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 786376#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 786374#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 744861#L1396-2 [2021-12-19 19:17:52,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:52,068 INFO L85 PathProgramCache]: Analyzing trace with hash 1386900856, now seen corresponding path program 1 times [2021-12-19 19:17:52,068 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:52,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455305841] [2021-12-19 19:17:52,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:52,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:52,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:52,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:52,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:52,093 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455305841] [2021-12-19 19:17:52,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455305841] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:52,093 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:52,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:52,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845267006] [2021-12-19 19:17:52,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:52,094 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:52,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:52,095 INFO L85 PathProgramCache]: Analyzing trace with hash 690023296, now seen corresponding path program 1 times [2021-12-19 19:17:52,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:52,095 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244832664] [2021-12-19 19:17:52,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:52,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:52,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:52,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:52,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:52,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244832664] [2021-12-19 19:17:52,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244832664] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:52,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:52,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:52,120 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442032694] [2021-12-19 19:17:52,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:52,121 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:52,121 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:52,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:52,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:52,122 INFO L87 Difference]: Start difference. First operand 54019 states and 77164 transitions. cyclomatic complexity: 23147 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:52,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:52,696 INFO L93 Difference]: Finished difference Result 70379 states and 99872 transitions. [2021-12-19 19:17:52,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:52,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70379 states and 99872 transitions. [2021-12-19 19:17:52,987 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 70208 [2021-12-19 19:17:53,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70379 states to 70379 states and 99872 transitions. [2021-12-19 19:17:53,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70379 [2021-12-19 19:17:53,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70379 [2021-12-19 19:17:53,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70379 states and 99872 transitions. [2021-12-19 19:17:53,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:53,260 INFO L681 BuchiCegarLoop]: Abstraction has 70379 states and 99872 transitions. [2021-12-19 19:17:53,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70379 states and 99872 transitions. [2021-12-19 19:17:53,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70379 to 48139. [2021-12-19 19:17:53,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.424209061260101) internal successors, (68560), 48138 states have internal predecessors, (68560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:53,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 68560 transitions. [2021-12-19 19:17:53,837 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 68560 transitions. [2021-12-19 19:17:53,837 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 68560 transitions. [2021-12-19 19:17:53,837 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:53,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 68560 transitions. [2021-12-19 19:17:54,241 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:17:54,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:54,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:54,245 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:54,246 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:54,246 INFO L791 eck$LassoCheckResult]: Stem: 869628#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 869629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 869183#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 869184#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 869830#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 869831#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 869806#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 869568#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 869569#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 869361#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 869362#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 869928#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 869781#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 869429#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 869189#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 869190#L922 assume !(0 == ~M_E~0); 870028#L922-2 assume !(0 == ~T1_E~0); 870029#L927-1 assume !(0 == ~T2_E~0); 869638#L932-1 assume !(0 == ~T3_E~0); 869506#L937-1 assume !(0 == ~T4_E~0); 869507#L942-1 assume !(0 == ~T5_E~0); 869567#L947-1 assume !(0 == ~T6_E~0); 869642#L952-1 assume !(0 == ~T7_E~0); 869643#L957-1 assume !(0 == ~T8_E~0); 869723#L962-1 assume !(0 == ~T9_E~0); 869479#L967-1 assume !(0 == ~E_1~0); 869480#L972-1 assume !(0 == ~E_2~0); 869812#L977-1 assume !(0 == ~E_3~0); 869813#L982-1 assume !(0 == ~E_4~0); 868958#L987-1 assume !(0 == ~E_5~0); 868959#L992-1 assume !(0 == ~E_6~0); 868967#L997-1 assume !(0 == ~E_7~0); 869402#L1002-1 assume !(0 == ~E_8~0); 869384#L1007-1 assume !(0 == ~E_9~0); 868755#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 868756#L443 assume !(1 == ~m_pc~0); 869660#L443-2 is_master_triggered_~__retres1~0#1 := 0; 869649#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 869650#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 869122#L1140 assume !(0 != activate_threads_~tmp~1#1); 868870#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 868871#L462 assume !(1 == ~t1_pc~0); 869496#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 869497#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 868841#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 868842#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 869341#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 869342#L481 assume !(1 == ~t2_pc~0); 869117#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 869116#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 869503#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 869214#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 869215#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 869316#L500 assume !(1 == ~t3_pc~0); 869888#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 869848#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 869796#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 869797#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 868757#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 868758#L519 assume !(1 == ~t4_pc~0); 869552#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 869314#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 869315#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 869163#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 869164#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 868926#L538 assume !(1 == ~t5_pc~0); 868927#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 868831#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 868832#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 869100#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 869101#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 869701#L557 assume !(1 == ~t6_pc~0); 869139#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 869140#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 869035#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 869036#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 869165#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 869982#L576 assume !(1 == ~t7_pc~0); 869126#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 869127#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 869388#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 869389#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 869772#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 869255#L595 assume !(1 == ~t8_pc~0); 869256#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 869798#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 869799#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 869596#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 869597#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 869051#L614 assume !(1 == ~t9_pc~0); 869052#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 868950#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 868951#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 869130#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 869216#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 869217#L1025 assume !(1 == ~M_E~0); 869489#L1025-2 assume !(1 == ~T1_E~0); 869544#L1030-1 assume !(1 == ~T2_E~0); 869692#L1035-1 assume !(1 == ~T3_E~0); 869209#L1040-1 assume !(1 == ~T4_E~0); 869210#L1045-1 assume !(1 == ~T5_E~0); 869112#L1050-1 assume !(1 == ~T6_E~0); 869113#L1055-1 assume !(1 == ~T7_E~0); 868935#L1060-1 assume !(1 == ~T8_E~0); 868936#L1065-1 assume !(1 == ~T9_E~0); 868997#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 869644#L1075-1 assume !(1 == ~E_2~0); 869645#L1080-1 assume !(1 == ~E_3~0); 869633#L1085-1 assume !(1 == ~E_4~0); 869634#L1090-1 assume !(1 == ~E_5~0); 869919#L1095-1 assume !(1 == ~E_6~0); 869673#L1100-1 assume !(1 == ~E_7~0); 869674#L1105-1 assume !(1 == ~E_8~0); 868908#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 868909#L1115-1 assume { :end_inline_reset_delta_events } true; 869268#L1396-2 [2021-12-19 19:17:54,246 INFO L793 eck$LassoCheckResult]: Loop: 869268#L1396-2 assume !false; 911833#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 911824#L897 assume !false; 911821#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 911732#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 911716#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 911709#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 911702#L766 assume !(0 != eval_~tmp~0#1); 911703#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 916693#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 916691#L922-3 assume !(0 == ~M_E~0); 916689#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 916687#L927-3 assume !(0 == ~T2_E~0); 916685#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 916683#L937-3 assume !(0 == ~T4_E~0); 916681#L942-3 assume !(0 == ~T5_E~0); 916679#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 916677#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 916675#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 916673#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 916671#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 916669#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 916668#L977-3 assume !(0 == ~E_3~0); 916667#L982-3 assume !(0 == ~E_4~0); 916666#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 916665#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 916664#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 916638#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 916637#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 916636#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 916635#L443-30 assume !(1 == ~m_pc~0); 916633#L443-32 is_master_triggered_~__retres1~0#1 := 0; 916632#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 869952#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 869953#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 916446#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 916444#L462-30 assume !(1 == ~t1_pc~0); 916442#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 916439#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 916437#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 916435#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 916434#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916433#L481-30 assume !(1 == ~t2_pc~0); 916431#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 916428#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916425#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 916423#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 916422#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 913859#L500-30 assume !(1 == ~t3_pc~0); 913857#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 913855#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 913853#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 913851#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 913849#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 913847#L519-30 assume !(1 == ~t4_pc~0); 906860#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 913843#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 913841#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 913839#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 913837#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 913835#L538-30 assume 1 == ~t5_pc~0; 913833#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 913834#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 913864#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 913825#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 913823#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 913821#L557-30 assume !(1 == ~t6_pc~0); 910789#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 913819#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 913817#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 913815#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 913813#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 913811#L576-30 assume 1 == ~t7_pc~0; 913773#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 913770#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 913768#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 913766#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 913764#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 869172#L595-30 assume !(1 == ~t8_pc~0); 869173#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 916344#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 916343#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 916342#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 916341#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 916340#L614-30 assume !(1 == ~t9_pc~0); 916339#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 916337#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 916336#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916335#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 916334#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 916333#L1025-3 assume !(1 == ~M_E~0); 881918#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 916332#L1030-3 assume !(1 == ~T2_E~0); 916331#L1035-3 assume !(1 == ~T3_E~0); 916330#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 916329#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 916328#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 916327#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 916326#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 916325#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 916324#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 916322#L1075-3 assume !(1 == ~E_2~0); 916321#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 869985#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 869986#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 913190#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 913189#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 913188#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 913187#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 912703#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 870305#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 870303#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 870264#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 870265#L1415 assume !(0 == start_simulation_~tmp~3#1); 882305#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 911919#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 911910#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 911909#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 911908#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 911905#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 911864#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 911853#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 869268#L1396-2 [2021-12-19 19:17:54,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:54,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1781320180, now seen corresponding path program 1 times [2021-12-19 19:17:54,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:54,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903165393] [2021-12-19 19:17:54,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:54,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:54,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:54,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:54,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:54,282 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903165393] [2021-12-19 19:17:54,282 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903165393] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:54,282 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:54,282 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:54,282 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362093978] [2021-12-19 19:17:54,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:54,283 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:54,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:54,283 INFO L85 PathProgramCache]: Analyzing trace with hash -23183135, now seen corresponding path program 1 times [2021-12-19 19:17:54,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:54,284 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404516662] [2021-12-19 19:17:54,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:54,286 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:54,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:54,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:54,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:54,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404516662] [2021-12-19 19:17:54,315 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404516662] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:54,315 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:54,315 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:54,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [247451418] [2021-12-19 19:17:54,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:54,316 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:54,316 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:54,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:54,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:54,317 INFO L87 Difference]: Start difference. First operand 48139 states and 68560 transitions. cyclomatic complexity: 20423 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:54,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:54,472 INFO L93 Difference]: Finished difference Result 48139 states and 68126 transitions. [2021-12-19 19:17:54,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:54,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48139 states and 68126 transitions. [2021-12-19 19:17:54,666 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:17:54,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48139 states to 48139 states and 68126 transitions. [2021-12-19 19:17:54,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48139 [2021-12-19 19:17:54,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48139 [2021-12-19 19:17:54,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48139 states and 68126 transitions. [2021-12-19 19:17:54,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:54,844 INFO L681 BuchiCegarLoop]: Abstraction has 48139 states and 68126 transitions. [2021-12-19 19:17:54,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48139 states and 68126 transitions. [2021-12-19 19:17:55,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48139 to 48139. [2021-12-19 19:17:55,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.415193502150024) internal successors, (68126), 48138 states have internal predecessors, (68126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:55,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 68126 transitions. [2021-12-19 19:17:55,231 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 68126 transitions. [2021-12-19 19:17:55,231 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 68126 transitions. [2021-12-19 19:17:55,231 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:55,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 68126 transitions. [2021-12-19 19:17:55,365 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:17:55,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:55,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:55,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:55,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:55,566 INFO L791 eck$LassoCheckResult]: Stem: 965917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 965918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 965469#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 965470#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 966121#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 966122#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 966095#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 965856#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 965857#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 965645#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 965646#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 966214#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 966071#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 965714#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 965475#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 965476#L922 assume !(0 == ~M_E~0); 966295#L922-2 assume !(0 == ~T1_E~0); 966296#L927-1 assume !(0 == ~T2_E~0); 965926#L932-1 assume !(0 == ~T3_E~0); 965792#L937-1 assume !(0 == ~T4_E~0); 965793#L942-1 assume !(0 == ~T5_E~0); 965855#L947-1 assume !(0 == ~T6_E~0); 965932#L952-1 assume !(0 == ~T7_E~0); 965933#L957-1 assume !(0 == ~T8_E~0); 966010#L962-1 assume !(0 == ~T9_E~0); 965767#L967-1 assume !(0 == ~E_1~0); 965768#L972-1 assume !(0 == ~E_2~0); 966106#L977-1 assume !(0 == ~E_3~0); 966107#L982-1 assume !(0 == ~E_4~0); 965246#L987-1 assume !(0 == ~E_5~0); 965247#L992-1 assume !(0 == ~E_6~0); 965253#L997-1 assume !(0 == ~E_7~0); 965689#L1002-1 assume !(0 == ~E_8~0); 965672#L1007-1 assume !(0 == ~E_9~0); 965040#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 965041#L443 assume !(1 == ~m_pc~0); 965949#L443-2 is_master_triggered_~__retres1~0#1 := 0; 965939#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 965940#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 965407#L1140 assume !(0 != activate_threads_~tmp~1#1); 965157#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 965158#L462 assume !(1 == ~t1_pc~0); 965787#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 965788#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 965126#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 965127#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 965625#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 965626#L481 assume !(1 == ~t2_pc~0); 965402#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 965401#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 965789#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 965499#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 965500#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 965600#L500 assume !(1 == ~t3_pc~0); 966173#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 966139#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966083#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 966084#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 965045#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 965046#L519 assume !(1 == ~t4_pc~0); 965839#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 965596#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 965597#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 965451#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 965452#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 965212#L538 assume !(1 == ~t5_pc~0); 965213#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 965116#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965117#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 965385#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 965386#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965993#L557 assume !(1 == ~t6_pc~0); 965424#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 965425#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 965329#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 965330#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 965453#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 966261#L576 assume !(1 == ~t7_pc~0); 965411#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 965412#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 965674#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 965675#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 966057#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 965541#L595 assume !(1 == ~t8_pc~0); 965542#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 966085#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 966086#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 965886#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 965887#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 965336#L614 assume !(1 == ~t9_pc~0); 965337#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 965237#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 965238#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 965415#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 965501#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 965502#L1025 assume !(1 == ~M_E~0); 965774#L1025-2 assume !(1 == ~T1_E~0); 965831#L1030-1 assume !(1 == ~T2_E~0); 965984#L1035-1 assume !(1 == ~T3_E~0); 965496#L1040-1 assume !(1 == ~T4_E~0); 965497#L1045-1 assume !(1 == ~T5_E~0); 965397#L1050-1 assume !(1 == ~T6_E~0); 965398#L1055-1 assume !(1 == ~T7_E~0); 965221#L1060-1 assume !(1 == ~T8_E~0); 965222#L1065-1 assume !(1 == ~T9_E~0); 965284#L1070-1 assume !(1 == ~E_1~0); 965934#L1075-1 assume !(1 == ~E_2~0); 965935#L1080-1 assume !(1 == ~E_3~0); 965921#L1085-1 assume !(1 == ~E_4~0); 965922#L1090-1 assume !(1 == ~E_5~0); 966203#L1095-1 assume !(1 == ~E_6~0); 965960#L1100-1 assume !(1 == ~E_7~0); 965961#L1105-1 assume !(1 == ~E_8~0); 965194#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 965195#L1115-1 assume { :end_inline_reset_delta_events } true; 965551#L1396-2 [2021-12-19 19:17:55,567 INFO L793 eck$LassoCheckResult]: Loop: 965551#L1396-2 assume !false; 1009688#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1002876#L897 assume !false; 1002823#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1002488#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1002477#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1002474#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1002471#L766 assume !(0 != eval_~tmp~0#1); 1002472#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1012378#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1012375#L922-3 assume !(0 == ~M_E~0); 1012373#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1012371#L927-3 assume !(0 == ~T2_E~0); 1012369#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1012367#L937-3 assume !(0 == ~T4_E~0); 1012366#L942-3 assume !(0 == ~T5_E~0); 1012365#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1012364#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1012363#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1012362#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1012361#L967-3 assume !(0 == ~E_1~0); 1012359#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1012358#L977-3 assume !(0 == ~E_3~0); 1012357#L982-3 assume !(0 == ~E_4~0); 1012356#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1012355#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1012354#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1012353#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1012352#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1012351#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1012350#L443-30 assume !(1 == ~m_pc~0); 1012348#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1012347#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1012346#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1012345#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1012344#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1012343#L462-30 assume !(1 == ~t1_pc~0); 1012342#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1010702#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1010005#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1010004#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1010003#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1010002#L481-30 assume !(1 == ~t2_pc~0); 1010001#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1009999#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1009998#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1009995#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1009993#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1009991#L500-30 assume !(1 == ~t3_pc~0); 999405#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1009988#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1009986#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1009985#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1009982#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1009980#L519-30 assume !(1 == ~t4_pc~0); 1008255#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1009977#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1009975#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1009973#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1009969#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1009965#L538-30 assume 1 == ~t5_pc~0; 1009964#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 965570#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 965571#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1009955#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1009954#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 965319#L557-30 assume !(1 == ~t6_pc~0); 965320#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 965702#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 965736#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 965796#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 965334#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 965335#L576-30 assume !(1 == ~t7_pc~0); 965114#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 965115#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 965730#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 966201#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 965495#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 965458#L595-30 assume !(1 == ~t8_pc~0); 965459#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1009049#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1009047#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1009045#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1009044#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1009042#L614-30 assume 1 == ~t9_pc~0; 1009039#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1009037#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1009035#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1009031#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1009029#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1009027#L1025-3 assume !(1 == ~M_E~0); 991241#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1009023#L1030-3 assume !(1 == ~T2_E~0); 1009021#L1035-3 assume !(1 == ~T3_E~0); 1009019#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1009018#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1009015#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1009013#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1009011#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1009009#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1009007#L1070-3 assume !(1 == ~E_1~0); 1009005#L1075-3 assume !(1 == ~E_2~0); 1009002#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1009000#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1008998#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1008996#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1008994#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1008993#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1008992#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1008991#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1008981#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1008979#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1008978#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1008976#L1415 assume !(0 == start_simulation_~tmp~3#1); 1008977#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1010748#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1010737#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1010735#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1010733#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1009952#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1009940#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1009936#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 965551#L1396-2 [2021-12-19 19:17:55,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:55,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293170, now seen corresponding path program 1 times [2021-12-19 19:17:55,567 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:55,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979434578] [2021-12-19 19:17:55,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:55,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:55,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:55,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:55,603 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:55,604 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979434578] [2021-12-19 19:17:55,604 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979434578] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:55,604 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:55,604 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:55,604 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [175557387] [2021-12-19 19:17:55,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:55,604 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:55,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:55,605 INFO L85 PathProgramCache]: Analyzing trace with hash 370272477, now seen corresponding path program 1 times [2021-12-19 19:17:55,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:55,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961219742] [2021-12-19 19:17:55,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:55,605 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:55,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:55,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:55,634 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:55,634 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961219742] [2021-12-19 19:17:55,634 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961219742] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:55,634 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:55,634 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:55,634 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327687817] [2021-12-19 19:17:55,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:55,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:55,635 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:55,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:55,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:55,636 INFO L87 Difference]: Start difference. First operand 48139 states and 68126 transitions. cyclomatic complexity: 19989 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:55,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:55,949 INFO L93 Difference]: Finished difference Result 75324 states and 105624 transitions. [2021-12-19 19:17:55,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:55,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75324 states and 105624 transitions. [2021-12-19 19:17:56,231 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 75024 [2021-12-19 19:17:56,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75324 states to 75324 states and 105624 transitions. [2021-12-19 19:17:56,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75324 [2021-12-19 19:17:56,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75324 [2021-12-19 19:17:56,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75324 states and 105624 transitions. [2021-12-19 19:17:56,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:56,503 INFO L681 BuchiCegarLoop]: Abstraction has 75324 states and 105624 transitions. [2021-12-19 19:17:56,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75324 states and 105624 transitions. [2021-12-19 19:17:57,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75324 to 54019. [2021-12-19 19:17:57,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54019 states, 54019 states have (on average 1.4073381587959792) internal successors, (76023), 54018 states have internal predecessors, (76023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:57,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54019 states to 54019 states and 76023 transitions. [2021-12-19 19:17:57,513 INFO L704 BuchiCegarLoop]: Abstraction has 54019 states and 76023 transitions. [2021-12-19 19:17:57,513 INFO L587 BuchiCegarLoop]: Abstraction has 54019 states and 76023 transitions. [2021-12-19 19:17:57,513 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:57,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54019 states and 76023 transitions. [2021-12-19 19:17:57,681 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 53776 [2021-12-19 19:17:57,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:57,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:57,688 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:57,688 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:57,689 INFO L791 eck$LassoCheckResult]: Stem: 1089380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1089381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1088937#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1088938#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1089579#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1089580#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1089555#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1089317#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1089318#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1089115#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1089116#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1089672#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1089531#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1089179#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1088943#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1088944#L922 assume !(0 == ~M_E~0); 1089762#L922-2 assume !(0 == ~T1_E~0); 1089763#L927-1 assume !(0 == ~T2_E~0); 1089388#L932-1 assume !(0 == ~T3_E~0); 1089251#L937-1 assume !(0 == ~T4_E~0); 1089252#L942-1 assume !(0 == ~T5_E~0); 1089316#L947-1 assume !(0 == ~T6_E~0); 1089394#L952-1 assume !(0 == ~T7_E~0); 1089395#L957-1 assume !(0 == ~T8_E~0); 1089477#L962-1 assume !(0 == ~T9_E~0); 1089231#L967-1 assume !(0 == ~E_1~0); 1089232#L972-1 assume !(0 == ~E_2~0); 1089563#L977-1 assume !(0 == ~E_3~0); 1089564#L982-1 assume !(0 == ~E_4~0); 1088715#L987-1 assume !(0 == ~E_5~0); 1088716#L992-1 assume !(0 == ~E_6~0); 1088722#L997-1 assume !(0 == ~E_7~0); 1089156#L1002-1 assume !(0 == ~E_8~0); 1089138#L1007-1 assume 0 == ~E_9~0;~E_9~0 := 1; 1088513#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1088514#L443 assume !(1 == ~m_pc~0); 1089688#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1089401#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1089402#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1088876#L1140 assume !(0 != activate_threads_~tmp~1#1); 1088627#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1088628#L462 assume !(1 == ~t1_pc~0); 1089246#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1089247#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1088598#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1088599#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1089862#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1089861#L481 assume !(1 == ~t2_pc~0); 1089859#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1089376#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1089248#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1088965#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1088966#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1089786#L500 assume !(1 == ~t3_pc~0); 1089632#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1089596#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1089544#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1089545#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1088518#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1088519#L519 assume !(1 == ~t4_pc~0); 1089300#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1089301#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1089430#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1088919#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1088920#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1088681#L538 assume !(1 == ~t5_pc~0); 1088682#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1088588#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1088589#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1088855#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1088856#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1089461#L557 assume !(1 == ~t6_pc~0); 1088892#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1088893#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1089647#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1089832#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1089831#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1089773#L576 assume !(1 == ~t7_pc~0); 1088880#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1088881#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1089141#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1089142#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1089826#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1089825#L595 assume !(1 == ~t8_pc~0); 1089824#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1089823#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1089822#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1089821#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1089820#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1089819#L614 assume !(1 == ~t9_pc~0); 1089817#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1089816#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1089815#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1089814#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1089813#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1089812#L1025 assume !(1 == ~M_E~0); 1089811#L1025-2 assume !(1 == ~T1_E~0); 1089810#L1030-1 assume !(1 == ~T2_E~0); 1089809#L1035-1 assume !(1 == ~T3_E~0); 1089808#L1040-1 assume !(1 == ~T4_E~0); 1089807#L1045-1 assume !(1 == ~T5_E~0); 1089806#L1050-1 assume !(1 == ~T6_E~0); 1089805#L1055-1 assume !(1 == ~T7_E~0); 1089804#L1060-1 assume !(1 == ~T8_E~0); 1089803#L1065-1 assume !(1 == ~T9_E~0); 1089802#L1070-1 assume !(1 == ~E_1~0); 1089801#L1075-1 assume !(1 == ~E_2~0); 1089800#L1080-1 assume !(1 == ~E_3~0); 1089799#L1085-1 assume !(1 == ~E_4~0); 1089798#L1090-1 assume !(1 == ~E_5~0); 1089797#L1095-1 assume !(1 == ~E_6~0); 1089796#L1100-1 assume !(1 == ~E_7~0); 1089795#L1105-1 assume !(1 == ~E_8~0); 1089794#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1088664#L1115-1 assume { :end_inline_reset_delta_events } true; 1089020#L1396-2 [2021-12-19 19:17:57,689 INFO L793 eck$LassoCheckResult]: Loop: 1089020#L1396-2 assume !false; 1113377#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1113367#L897 assume !false; 1113366#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1113318#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1113307#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1113305#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1113302#L766 assume !(0 != eval_~tmp~0#1); 1113300#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1113299#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1113297#L922-3 assume !(0 == ~M_E~0); 1113291#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1113282#L927-3 assume !(0 == ~T2_E~0); 1113275#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1113268#L937-3 assume !(0 == ~T4_E~0); 1113261#L942-3 assume !(0 == ~T5_E~0); 1113254#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1113247#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1113239#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1113232#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1113225#L967-3 assume !(0 == ~E_1~0); 1113218#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1113211#L977-3 assume !(0 == ~E_3~0); 1113204#L982-3 assume !(0 == ~E_4~0); 1113198#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1113189#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1113182#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1113175#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1106341#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1106342#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1106334#L443-30 assume !(1 == ~m_pc~0); 1106333#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1106326#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1106327#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1106218#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1106219#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1106212#L462-30 assume !(1 == ~t1_pc~0); 1106213#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1106206#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1106207#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1106180#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106181#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1106153#L481-30 assume 1 == ~t2_pc~0; 1106154#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1106130#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1106131#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1106112#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1106113#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1104521#L500-30 assume !(1 == ~t3_pc~0); 1104522#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1104514#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1104515#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1104508#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1104509#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1104503#L519-30 assume !(1 == ~t4_pc~0); 1103863#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1104499#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1104500#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1104493#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1104494#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1104488#L538-30 assume !(1 == ~t5_pc~0); 1104484#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1104482#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1104480#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1104478#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1104477#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1104471#L557-30 assume !(1 == ~t6_pc~0); 1104393#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1104464#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1104465#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1104458#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1104459#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1103697#L576-30 assume 1 == ~t7_pc~0; 1103698#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1103687#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1103688#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1103679#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1103680#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1103649#L595-30 assume !(1 == ~t8_pc~0); 1103647#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1103644#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1103642#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1103640#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1103638#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1103636#L614-30 assume 1 == ~t9_pc~0; 1103633#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1103632#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1103630#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1103628#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1103626#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1103624#L1025-3 assume !(1 == ~M_E~0); 1102099#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1103615#L1030-3 assume !(1 == ~T2_E~0); 1103611#L1035-3 assume !(1 == ~T3_E~0); 1103607#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1103603#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1103599#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1103595#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1103590#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1103585#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1103580#L1070-3 assume !(1 == ~E_1~0); 1103575#L1075-3 assume !(1 == ~E_2~0); 1103570#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1103567#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1103561#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1103556#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1103550#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1103545#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1103411#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1103409#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1103385#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1103318#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1103313#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1102887#L1415 assume !(0 == start_simulation_~tmp~3#1); 1102888#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1113401#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1113391#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1113389#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1113387#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1113385#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1113383#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1113380#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1089020#L1396-2 [2021-12-19 19:17:57,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:57,690 INFO L85 PathProgramCache]: Analyzing trace with hash -178464780, now seen corresponding path program 1 times [2021-12-19 19:17:57,690 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:57,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775662537] [2021-12-19 19:17:57,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:57,690 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:57,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:57,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:57,717 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:57,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775662537] [2021-12-19 19:17:57,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775662537] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:57,718 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:57,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:57,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034896378] [2021-12-19 19:17:57,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:57,719 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:57,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:57,720 INFO L85 PathProgramCache]: Analyzing trace with hash -957830660, now seen corresponding path program 1 times [2021-12-19 19:17:57,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:57,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481560423] [2021-12-19 19:17:57,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:57,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:57,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:57,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:57,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:57,747 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481560423] [2021-12-19 19:17:57,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481560423] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:57,748 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:57,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:57,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113153922] [2021-12-19 19:17:57,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:57,749 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:57,749 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:57,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:57,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:57,750 INFO L87 Difference]: Start difference. First operand 54019 states and 76023 transitions. cyclomatic complexity: 22006 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:58,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:58,044 INFO L93 Difference]: Finished difference Result 69227 states and 96755 transitions. [2021-12-19 19:17:58,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:58,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69227 states and 96755 transitions. [2021-12-19 19:17:58,345 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 69040 [2021-12-19 19:17:58,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69227 states to 69227 states and 96755 transitions. [2021-12-19 19:17:58,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69227 [2021-12-19 19:17:58,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69227 [2021-12-19 19:17:58,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69227 states and 96755 transitions. [2021-12-19 19:17:58,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:58,600 INFO L681 BuchiCegarLoop]: Abstraction has 69227 states and 96755 transitions. [2021-12-19 19:17:58,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69227 states and 96755 transitions. [2021-12-19 19:17:59,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69227 to 48139. [2021-12-19 19:17:59,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.4011716072207565) internal successors, (67451), 48138 states have internal predecessors, (67451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:59,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 67451 transitions. [2021-12-19 19:17:59,607 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 67451 transitions. [2021-12-19 19:17:59,607 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 67451 transitions. [2021-12-19 19:17:59,607 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:59,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 67451 transitions. [2021-12-19 19:17:59,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:17:59,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:59,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:59,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:59,765 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:59,766 INFO L791 eck$LassoCheckResult]: Stem: 1212637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1212638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1212195#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1212196#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1212847#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1212848#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1212819#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1212577#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1212578#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1212371#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1212372#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1212948#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1212793#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1212436#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1212201#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1212202#L922 assume !(0 == ~M_E~0); 1213047#L922-2 assume !(0 == ~T1_E~0); 1213048#L927-1 assume !(0 == ~T2_E~0); 1212650#L932-1 assume !(0 == ~T3_E~0); 1212513#L937-1 assume !(0 == ~T4_E~0); 1212514#L942-1 assume !(0 == ~T5_E~0); 1212576#L947-1 assume !(0 == ~T6_E~0); 1212654#L952-1 assume !(0 == ~T7_E~0); 1212655#L957-1 assume !(0 == ~T8_E~0); 1212733#L962-1 assume !(0 == ~T9_E~0); 1212488#L967-1 assume !(0 == ~E_1~0); 1212489#L972-1 assume !(0 == ~E_2~0); 1212829#L977-1 assume !(0 == ~E_3~0); 1212830#L982-1 assume !(0 == ~E_4~0); 1211971#L987-1 assume !(0 == ~E_5~0); 1211972#L992-1 assume !(0 == ~E_6~0); 1211978#L997-1 assume !(0 == ~E_7~0); 1212413#L1002-1 assume !(0 == ~E_8~0); 1212395#L1007-1 assume !(0 == ~E_9~0); 1211769#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1211770#L443 assume !(1 == ~m_pc~0); 1212672#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1212662#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1212663#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1212133#L1140 assume !(0 != activate_threads_~tmp~1#1); 1211883#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1211884#L462 assume !(1 == ~t1_pc~0); 1212507#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1212508#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1211854#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1211855#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1212353#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1212354#L481 assume !(1 == ~t2_pc~0); 1212128#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1212127#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1212510#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1212222#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1212223#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1212328#L500 assume !(1 == ~t3_pc~0); 1212906#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1212863#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1212809#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1212810#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1211774#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1211775#L519 assume !(1 == ~t4_pc~0); 1212562#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1212324#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1212325#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1212178#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1212179#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1211937#L538 assume !(1 == ~t5_pc~0); 1211938#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1211844#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1211845#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1212112#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1212113#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1212714#L557 assume !(1 == ~t6_pc~0); 1212150#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1212151#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1212051#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1212052#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1212177#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1213002#L576 assume !(1 == ~t7_pc~0); 1212137#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1212138#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1212397#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1212398#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1212778#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1212267#L595 assume !(1 == ~t8_pc~0); 1212268#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1212811#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1212812#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1212606#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1212607#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1212062#L614 assume !(1 == ~t9_pc~0); 1212063#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1211962#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1211963#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1212141#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1212224#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1212225#L1025 assume !(1 == ~M_E~0); 1212494#L1025-2 assume !(1 == ~T1_E~0); 1212554#L1030-1 assume !(1 == ~T2_E~0); 1212703#L1035-1 assume !(1 == ~T3_E~0); 1212219#L1040-1 assume !(1 == ~T4_E~0); 1212220#L1045-1 assume !(1 == ~T5_E~0); 1212123#L1050-1 assume !(1 == ~T6_E~0); 1212124#L1055-1 assume !(1 == ~T7_E~0); 1211946#L1060-1 assume !(1 == ~T8_E~0); 1211947#L1065-1 assume !(1 == ~T9_E~0); 1212008#L1070-1 assume !(1 == ~E_1~0); 1212656#L1075-1 assume !(1 == ~E_2~0); 1212657#L1080-1 assume !(1 == ~E_3~0); 1212645#L1085-1 assume !(1 == ~E_4~0); 1212646#L1090-1 assume !(1 == ~E_5~0); 1212937#L1095-1 assume !(1 == ~E_6~0); 1212684#L1100-1 assume !(1 == ~E_7~0); 1212685#L1105-1 assume !(1 == ~E_8~0); 1211919#L1110-1 assume !(1 == ~E_9~0); 1211920#L1115-1 assume { :end_inline_reset_delta_events } true; 1212278#L1396-2 [2021-12-19 19:17:59,766 INFO L793 eck$LassoCheckResult]: Loop: 1212278#L1396-2 assume !false; 1232813#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1232807#L897 assume !false; 1232804#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1232801#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1232790#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1232788#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1232785#L766 assume !(0 != eval_~tmp~0#1); 1232786#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1234758#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1234752#L922-3 assume !(0 == ~M_E~0); 1234746#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1234740#L927-3 assume !(0 == ~T2_E~0); 1234733#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1234726#L937-3 assume !(0 == ~T4_E~0); 1234720#L942-3 assume !(0 == ~T5_E~0); 1234713#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1234708#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1234703#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1234700#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1234695#L967-3 assume !(0 == ~E_1~0); 1234688#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1234271#L977-3 assume !(0 == ~E_3~0); 1234267#L982-3 assume !(0 == ~E_4~0); 1234265#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1234263#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1234261#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1234258#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1234251#L1007-3 assume !(0 == ~E_9~0); 1234244#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1234239#L443-30 assume !(1 == ~m_pc~0); 1234230#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1234223#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234216#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234209#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1234204#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1234197#L462-30 assume !(1 == ~t1_pc~0); 1234191#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1234184#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1234146#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1234131#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1234122#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1234121#L481-30 assume 1 == ~t2_pc~0; 1234119#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1234109#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1234102#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1234101#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1234100#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1234098#L500-30 assume !(1 == ~t3_pc~0); 1231395#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1234096#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1234095#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1234093#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1234091#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234087#L519-30 assume !(1 == ~t4_pc~0); 1230178#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1234084#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1234048#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1234046#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1234045#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1234044#L538-30 assume 1 == ~t5_pc~0; 1234042#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1234041#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1234040#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1234037#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1234035#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1234033#L557-30 assume !(1 == ~t6_pc~0); 1233704#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1234030#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1234028#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1234026#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1234024#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1234022#L576-30 assume 1 == ~t7_pc~0; 1234019#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1234017#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1234014#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1234012#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1234010#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1234008#L595-30 assume !(1 == ~t8_pc~0); 1227565#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1234005#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1234002#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1234000#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1233998#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1233996#L614-30 assume !(1 == ~t9_pc~0); 1233993#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1233991#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1233990#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1233987#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1233985#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1233983#L1025-3 assume !(1 == ~M_E~0); 1224617#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1233980#L1030-3 assume !(1 == ~T2_E~0); 1233978#L1035-3 assume !(1 == ~T3_E~0); 1233975#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1233973#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1233971#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1233970#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1233967#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1233965#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1233963#L1070-3 assume !(1 == ~E_1~0); 1233962#L1075-3 assume !(1 == ~E_2~0); 1233960#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1233958#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1233956#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1233954#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1233922#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1233916#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1233909#L1110-3 assume !(1 == ~E_9~0); 1233906#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1233824#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1233817#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1233813#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1232847#L1415 assume !(0 == start_simulation_~tmp~3#1); 1232844#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1232838#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1232826#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1232824#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1232822#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1232820#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1232818#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1232816#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1212278#L1396-2 [2021-12-19 19:17:59,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:59,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 1 times [2021-12-19 19:17:59,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:59,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597433233] [2021-12-19 19:17:59,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:59,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:59,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:59,778 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:17:59,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:17:59,842 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:17:59,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:59,843 INFO L85 PathProgramCache]: Analyzing trace with hash -1023089862, now seen corresponding path program 1 times [2021-12-19 19:17:59,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:59,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131324886] [2021-12-19 19:17:59,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:59,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:59,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:59,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:59,872 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:59,872 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131324886] [2021-12-19 19:17:59,872 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131324886] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:59,872 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:59,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:59,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004206017] [2021-12-19 19:17:59,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:59,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:59,873 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:59,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:59,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:59,874 INFO L87 Difference]: Start difference. First operand 48139 states and 67451 transitions. cyclomatic complexity: 19314 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:00,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:00,049 INFO L93 Difference]: Finished difference Result 54019 states and 75633 transitions. [2021-12-19 19:18:00,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:00,050 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54019 states and 75633 transitions. [2021-12-19 19:18:00,297 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 53776 [2021-12-19 19:18:00,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54019 states to 54019 states and 75633 transitions. [2021-12-19 19:18:00,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54019 [2021-12-19 19:18:00,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54019 [2021-12-19 19:18:00,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54019 states and 75633 transitions. [2021-12-19 19:18:00,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:00,512 INFO L681 BuchiCegarLoop]: Abstraction has 54019 states and 75633 transitions. [2021-12-19 19:18:00,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54019 states and 75633 transitions. [2021-12-19 19:18:01,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54019 to 54019. [2021-12-19 19:18:01,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54019 states, 54019 states have (on average 1.4001184768322257) internal successors, (75633), 54018 states have internal predecessors, (75633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:01,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54019 states to 54019 states and 75633 transitions. [2021-12-19 19:18:01,472 INFO L704 BuchiCegarLoop]: Abstraction has 54019 states and 75633 transitions. [2021-12-19 19:18:01,472 INFO L587 BuchiCegarLoop]: Abstraction has 54019 states and 75633 transitions. [2021-12-19 19:18:01,472 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:18:01,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54019 states and 75633 transitions. [2021-12-19 19:18:01,635 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 53776 [2021-12-19 19:18:01,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:01,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:01,641 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,641 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,642 INFO L791 eck$LassoCheckResult]: Stem: 1314794#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1314795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1314356#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1314357#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1315002#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1315003#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1314977#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1314733#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1314734#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1314528#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1314529#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1315100#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1314949#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1314595#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1314362#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1314363#L922 assume !(0 == ~M_E~0); 1315193#L922-2 assume !(0 == ~T1_E~0); 1315194#L927-1 assume !(0 == ~T2_E~0); 1314804#L932-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1314805#L937-1 assume !(0 == ~T4_E~0); 1314731#L942-1 assume !(0 == ~T5_E~0); 1314732#L947-1 assume !(0 == ~T6_E~0); 1314809#L952-1 assume !(0 == ~T7_E~0); 1314810#L957-1 assume !(0 == ~T8_E~0); 1315171#L962-1 assume !(0 == ~T9_E~0); 1315172#L967-1 assume !(0 == ~E_1~0); 1315155#L972-1 assume !(0 == ~E_2~0); 1315156#L977-1 assume !(0 == ~E_3~0); 1315201#L982-1 assume !(0 == ~E_4~0); 1315202#L987-1 assume !(0 == ~E_5~0); 1314143#L992-1 assume !(0 == ~E_6~0); 1314144#L997-1 assume !(0 == ~E_7~0); 1315121#L1002-1 assume !(0 == ~E_8~0); 1315122#L1007-1 assume !(0 == ~E_9~0); 1313933#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1313934#L443 assume !(1 == ~m_pc~0); 1314826#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1314827#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1315283#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1315282#L1140 assume !(0 != activate_threads_~tmp~1#1); 1315281#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1315280#L462 assume !(1 == ~t1_pc~0); 1315279#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1315278#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1314018#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1314019#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1314510#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1314511#L481 assume !(1 == ~t2_pc~0); 1314290#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1314289#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315274#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315273#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1314484#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1314485#L500 assume !(1 == ~t3_pc~0); 1315272#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1315271#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1315270#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1315269#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1315268#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1315267#L519 assume !(1 == ~t4_pc~0); 1315266#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1314482#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314483#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1315265#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1315264#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1315263#L538 assume !(1 == ~t5_pc~0); 1315260#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1315257#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1315255#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1315253#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1315252#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1315224#L557 assume !(1 == ~t6_pc~0); 1314312#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1314313#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1314214#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1314215#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1314340#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1315153#L576 assume !(1 == ~t7_pc~0); 1315245#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1315244#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1315243#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1315205#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1314940#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1314425#L595 assume !(1 == ~t8_pc~0); 1314426#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1314968#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1314969#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1314760#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1314761#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1314225#L614 assume !(1 == ~t9_pc~0); 1314226#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1314126#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1314127#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1314304#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1314386#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1314387#L1025 assume !(1 == ~M_E~0); 1314654#L1025-2 assume !(1 == ~T1_E~0); 1314711#L1030-1 assume !(1 == ~T2_E~0); 1314865#L1035-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1314381#L1040-1 assume !(1 == ~T4_E~0); 1314382#L1045-1 assume !(1 == ~T5_E~0); 1314285#L1050-1 assume !(1 == ~T6_E~0); 1314286#L1055-1 assume !(1 == ~T7_E~0); 1314111#L1060-1 assume !(1 == ~T8_E~0); 1314112#L1065-1 assume !(1 == ~T9_E~0); 1314174#L1070-1 assume !(1 == ~E_1~0); 1314811#L1075-1 assume !(1 == ~E_2~0); 1314812#L1080-1 assume !(1 == ~E_3~0); 1314799#L1085-1 assume !(1 == ~E_4~0); 1314800#L1090-1 assume !(1 == ~E_5~0); 1315093#L1095-1 assume !(1 == ~E_6~0); 1314840#L1100-1 assume !(1 == ~E_7~0); 1314841#L1105-1 assume !(1 == ~E_8~0); 1314084#L1110-1 assume !(1 == ~E_9~0); 1314085#L1115-1 assume { :end_inline_reset_delta_events } true; 1314438#L1396-2 [2021-12-19 19:18:01,642 INFO L793 eck$LassoCheckResult]: Loop: 1314438#L1396-2 assume !false; 1347106#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1347100#L897 assume !false; 1347098#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1347095#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1347084#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1347082#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1347080#L766 assume !(0 != eval_~tmp~0#1); 1315058#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1314024#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1314025#L922-3 assume !(0 == ~M_E~0); 1314544#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1314266#L927-3 assume !(0 == ~T2_E~0); 1314267#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1314452#L937-3 assume !(0 == ~T4_E~0); 1367898#L942-3 assume !(0 == ~T5_E~0); 1367897#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1367896#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1367895#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1367894#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1314905#L967-3 assume !(0 == ~E_1~0); 1314906#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1314802#L977-3 assume !(0 == ~E_3~0); 1314803#L982-3 assume !(0 == ~E_4~0); 1315217#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1366620#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1366619#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1366618#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1366617#L1007-3 assume !(0 == ~E_9~0); 1366616#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1366615#L443-30 assume !(1 == ~m_pc~0); 1366613#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1366612#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1366611#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1366610#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1366607#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1366605#L462-30 assume !(1 == ~t1_pc~0); 1366603#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1366601#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1366599#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1366597#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1366596#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366593#L481-30 assume 1 == ~t2_pc~0; 1366590#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1366588#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1366586#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1366584#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1366582#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1366580#L500-30 assume !(1 == ~t3_pc~0); 1337180#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1366576#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366573#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1366571#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1366569#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1314913#L519-30 assume !(1 == ~t4_pc~0); 1314664#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1314638#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1313981#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1313982#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1314650#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1314781#L538-30 assume !(1 == ~t5_pc~0); 1314125#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1314456#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1314423#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1314424#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1314198#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1314199#L557-30 assume !(1 == ~t6_pc~0); 1314211#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1314584#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1314618#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1314672#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1367789#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1367788#L576-30 assume 1 == ~t7_pc~0; 1367786#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1367785#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1367784#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1367783#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1367782#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1367781#L595-30 assume !(1 == ~t8_pc~0); 1333517#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1367780#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1367779#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1367778#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1367777#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1367776#L614-30 assume !(1 == ~t9_pc~0); 1367774#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1367773#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1367772#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1367771#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1367770#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1367769#L1025-3 assume !(1 == ~M_E~0); 1314513#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1314514#L1030-3 assume !(1 == ~T2_E~0); 1314713#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1315103#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1315190#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1315098#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1314963#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1314014#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1314015#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1314994#L1070-3 assume !(1 == ~E_1~0); 1314782#L1075-3 assume !(1 == ~E_2~0); 1314783#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1315104#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1314978#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1314979#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1315010#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1315011#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1314163#L1110-3 assume !(1 == ~E_9~0); 1314164#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1315029#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1314030#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1314020#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1314021#L1415 assume !(0 == start_simulation_~tmp~3#1); 1314990#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1347131#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1347120#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1347118#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1347116#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1347114#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1347112#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1347110#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1314438#L1396-2 [2021-12-19 19:18:01,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:01,643 INFO L85 PathProgramCache]: Analyzing trace with hash 1375570028, now seen corresponding path program 1 times [2021-12-19 19:18:01,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:01,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598126634] [2021-12-19 19:18:01,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:01,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:01,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:01,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:01,668 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:01,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598126634] [2021-12-19 19:18:01,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598126634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:01,669 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:01,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:01,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289231715] [2021-12-19 19:18:01,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:01,670 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:01,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:01,670 INFO L85 PathProgramCache]: Analyzing trace with hash -155838251, now seen corresponding path program 1 times [2021-12-19 19:18:01,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:01,670 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128113569] [2021-12-19 19:18:01,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:01,671 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:01,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:01,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:01,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:01,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128113569] [2021-12-19 19:18:01,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128113569] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:01,696 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:01,697 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:01,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658854524] [2021-12-19 19:18:01,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:01,697 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:01,697 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:01,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:18:01,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:18:01,698 INFO L87 Difference]: Start difference. First operand 54019 states and 75633 transitions. cyclomatic complexity: 21616 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:01,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:01,981 INFO L93 Difference]: Finished difference Result 70395 states and 98231 transitions. [2021-12-19 19:18:01,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:18:01,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70395 states and 98231 transitions. [2021-12-19 19:18:02,255 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 70208 [2021-12-19 19:18:02,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70395 states to 70395 states and 98231 transitions. [2021-12-19 19:18:02,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70395 [2021-12-19 19:18:02,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70395 [2021-12-19 19:18:02,483 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70395 states and 98231 transitions. [2021-12-19 19:18:03,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:03,012 INFO L681 BuchiCegarLoop]: Abstraction has 70395 states and 98231 transitions. [2021-12-19 19:18:03,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70395 states and 98231 transitions. [2021-12-19 19:18:03,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70395 to 48139. [2021-12-19 19:18:03,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.3998213506720123) internal successors, (67386), 48138 states have internal predecessors, (67386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:03,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 67386 transitions. [2021-12-19 19:18:03,504 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 67386 transitions. [2021-12-19 19:18:03,505 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 67386 transitions. [2021-12-19 19:18:03,505 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:18:03,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 67386 transitions. [2021-12-19 19:18:03,645 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:18:03,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:03,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:03,650 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:03,650 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:03,651 INFO L791 eck$LassoCheckResult]: Stem: 1439227#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1439228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1438779#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1438780#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1439432#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1439433#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1439403#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1439164#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1439165#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1438956#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1438957#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1439523#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1439376#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1439024#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1438785#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1438786#L922 assume !(0 == ~M_E~0); 1439603#L922-2 assume !(0 == ~T1_E~0); 1439604#L927-1 assume !(0 == ~T2_E~0); 1439236#L932-1 assume !(0 == ~T3_E~0); 1439099#L937-1 assume !(0 == ~T4_E~0); 1439100#L942-1 assume !(0 == ~T5_E~0); 1439163#L947-1 assume !(0 == ~T6_E~0); 1439241#L952-1 assume !(0 == ~T7_E~0); 1439242#L957-1 assume !(0 == ~T8_E~0); 1439318#L962-1 assume !(0 == ~T9_E~0); 1439073#L967-1 assume !(0 == ~E_1~0); 1439074#L972-1 assume !(0 == ~E_2~0); 1439413#L977-1 assume !(0 == ~E_3~0); 1439414#L982-1 assume !(0 == ~E_4~0); 1438557#L987-1 assume !(0 == ~E_5~0); 1438558#L992-1 assume !(0 == ~E_6~0); 1438566#L997-1 assume !(0 == ~E_7~0); 1438999#L1002-1 assume !(0 == ~E_8~0); 1438981#L1007-1 assume !(0 == ~E_9~0); 1438357#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1438358#L443 assume !(1 == ~m_pc~0); 1439259#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1439249#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1439250#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1438718#L1140 assume !(0 != activate_threads_~tmp~1#1); 1438471#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1438472#L462 assume !(1 == ~t1_pc~0); 1439090#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1439091#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1438442#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1438443#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1438938#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1438939#L481 assume !(1 == ~t2_pc~0); 1438713#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1438712#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1439096#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1438806#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1438807#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1438912#L500 assume !(1 == ~t3_pc~0); 1439484#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1439449#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1439392#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1439393#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1438359#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1438360#L519 assume !(1 == ~t4_pc~0); 1439148#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1438910#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1438911#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1438761#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1438762#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1438525#L538 assume !(1 == ~t5_pc~0); 1438526#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1438432#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1438433#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1438696#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1438697#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1439299#L557 assume !(1 == ~t6_pc~0); 1438735#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1438736#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1438634#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1438635#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1438760#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1439568#L576 assume !(1 == ~t7_pc~0); 1438722#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1438723#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1438986#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1438987#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1439365#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1438848#L595 assume !(1 == ~t8_pc~0); 1438849#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1439394#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1439395#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1439195#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1439196#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1438647#L614 assume !(1 == ~t9_pc~0); 1438648#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1438549#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1438550#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1438726#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1438808#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1438809#L1025 assume !(1 == ~M_E~0); 1439083#L1025-2 assume !(1 == ~T1_E~0); 1439139#L1030-1 assume !(1 == ~T2_E~0); 1439291#L1035-1 assume !(1 == ~T3_E~0); 1438802#L1040-1 assume !(1 == ~T4_E~0); 1438803#L1045-1 assume !(1 == ~T5_E~0); 1438707#L1050-1 assume !(1 == ~T6_E~0); 1438708#L1055-1 assume !(1 == ~T7_E~0); 1438534#L1060-1 assume !(1 == ~T8_E~0); 1438535#L1065-1 assume !(1 == ~T9_E~0); 1438596#L1070-1 assume !(1 == ~E_1~0); 1439243#L1075-1 assume !(1 == ~E_2~0); 1439244#L1080-1 assume !(1 == ~E_3~0); 1439231#L1085-1 assume !(1 == ~E_4~0); 1439232#L1090-1 assume !(1 == ~E_5~0); 1439516#L1095-1 assume !(1 == ~E_6~0); 1439270#L1100-1 assume !(1 == ~E_7~0); 1439271#L1105-1 assume !(1 == ~E_8~0); 1438507#L1110-1 assume !(1 == ~E_9~0); 1438508#L1115-1 assume { :end_inline_reset_delta_events } true; 1438861#L1396-2 [2021-12-19 19:18:03,651 INFO L793 eck$LassoCheckResult]: Loop: 1438861#L1396-2 assume !false; 1478484#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1478480#L897 assume !false; 1478469#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1478386#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1478376#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1478375#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1478374#L766 assume !(0 != eval_~tmp~0#1); 1439480#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1438448#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1438449#L922-3 assume !(0 == ~M_E~0); 1438974#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1439584#L927-3 assume !(0 == ~T2_E~0); 1438878#L932-3 assume !(0 == ~T3_E~0); 1438879#L937-3 assume !(0 == ~T4_E~0); 1438499#L942-3 assume !(0 == ~T5_E~0); 1438500#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1438880#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1438881#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1439503#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1439331#L967-3 assume !(0 == ~E_1~0); 1439332#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1439526#L977-3 assume !(0 == ~E_3~0); 1486341#L982-3 assume !(0 == ~E_4~0); 1486339#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1486336#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1486330#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1486329#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1486327#L1007-3 assume !(0 == ~E_9~0); 1486326#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1438871#L443-30 assume !(1 == ~m_pc~0); 1438570#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1438855#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1438856#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1439543#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1439420#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1439421#L462-30 assume !(1 == ~t1_pc~0); 1486321#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1439411#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1439412#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1439451#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1439452#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1486239#L481-30 assume !(1 == ~t2_pc~0); 1486238#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1486236#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1486074#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1486073#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1438917#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1438918#L500-30 assume !(1 == ~t3_pc~0); 1439254#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1486091#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486088#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1486086#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1486084#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486082#L519-30 assume !(1 == ~t4_pc~0); 1482355#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1486079#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1486078#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1486077#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1486075#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1485372#L538-30 assume 1 == ~t5_pc~0; 1485370#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1485371#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1485415#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1485361#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1485358#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1485356#L557-30 assume !(1 == ~t6_pc~0); 1485316#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1485352#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1485350#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1485348#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1485346#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1485344#L576-30 assume 1 == ~t7_pc~0; 1485342#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1485340#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1485338#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1485336#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1485314#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1465269#L595-30 assume !(1 == ~t8_pc~0); 1460088#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1460087#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1460086#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1460085#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1460084#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1460083#L614-30 assume !(1 == ~t9_pc~0); 1460080#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1460078#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1460076#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1460074#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1460072#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1460070#L1025-3 assume !(1 == ~M_E~0); 1453517#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1460067#L1030-3 assume !(1 == ~T2_E~0); 1460065#L1035-3 assume !(1 == ~T3_E~0); 1460063#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1460061#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1460059#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1460057#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1460055#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1460053#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1460051#L1070-3 assume !(1 == ~E_1~0); 1460049#L1075-3 assume !(1 == ~E_2~0); 1460047#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1460045#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1460043#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1460041#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1460037#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1460034#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1460032#L1110-3 assume !(1 == ~E_9~0); 1460030#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1460008#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1460006#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1460004#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1439822#L1415 assume !(0 == start_simulation_~tmp~3#1); 1439823#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1478510#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1478500#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1478498#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1478496#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1478494#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1478492#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1478487#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1438861#L1396-2 [2021-12-19 19:18:03,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:03,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 2 times [2021-12-19 19:18:03,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:03,652 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322973930] [2021-12-19 19:18:03,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:03,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:03,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:03,661 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:03,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:03,697 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:03,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:03,698 INFO L85 PathProgramCache]: Analyzing trace with hash -1044746533, now seen corresponding path program 1 times [2021-12-19 19:18:03,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:03,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481154743] [2021-12-19 19:18:03,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:03,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:03,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:03,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:03,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:03,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481154743] [2021-12-19 19:18:03,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481154743] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:03,724 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:03,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:03,725 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898953317] [2021-12-19 19:18:03,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:03,725 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:03,725 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:03,726 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:03,726 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:03,726 INFO L87 Difference]: Start difference. First operand 48139 states and 67386 transitions. cyclomatic complexity: 19249 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:04,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:04,028 INFO L93 Difference]: Finished difference Result 90307 states and 124976 transitions. [2021-12-19 19:18:04,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:04,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90307 states and 124976 transitions. [2021-12-19 19:18:04,801 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 90032 [2021-12-19 19:18:05,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90307 states to 90307 states and 124976 transitions. [2021-12-19 19:18:05,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90307 [2021-12-19 19:18:05,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90307 [2021-12-19 19:18:05,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90307 states and 124976 transitions. [2021-12-19 19:18:05,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:05,124 INFO L681 BuchiCegarLoop]: Abstraction has 90307 states and 124976 transitions. [2021-12-19 19:18:05,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90307 states and 124976 transitions. [2021-12-19 19:18:05,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90307 to 90275. [2021-12-19 19:18:05,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90275 states, 90275 states have (on average 1.3840376626973137) internal successors, (124944), 90274 states have internal predecessors, (124944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:05,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90275 states to 90275 states and 124944 transitions. [2021-12-19 19:18:05,915 INFO L704 BuchiCegarLoop]: Abstraction has 90275 states and 124944 transitions. [2021-12-19 19:18:05,915 INFO L587 BuchiCegarLoop]: Abstraction has 90275 states and 124944 transitions. [2021-12-19 19:18:05,915 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:18:05,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90275 states and 124944 transitions. [2021-12-19 19:18:06,547 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 90000 [2021-12-19 19:18:06,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:06,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:06,554 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:06,554 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:06,555 INFO L791 eck$LassoCheckResult]: Stem: 1577693#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1577694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1577239#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1577240#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1577906#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1577907#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1577877#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1577634#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1577635#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1577414#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1577415#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1578019#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1577852#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1577488#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1577246#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1577247#L922 assume !(0 == ~M_E~0); 1578128#L922-2 assume !(0 == ~T1_E~0); 1578129#L927-1 assume !(0 == ~T2_E~0); 1577703#L932-1 assume !(0 == ~T3_E~0); 1577566#L937-1 assume !(0 == ~T4_E~0); 1577567#L942-1 assume !(0 == ~T5_E~0); 1577633#L947-1 assume !(0 == ~T6_E~0); 1577709#L952-1 assume !(0 == ~T7_E~0); 1577710#L957-1 assume !(0 == ~T8_E~0); 1577793#L962-1 assume !(0 == ~T9_E~0); 1577544#L967-1 assume !(0 == ~E_1~0); 1577545#L972-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1578081#L977-1 assume !(0 == ~E_3~0); 1578132#L982-1 assume !(0 == ~E_4~0); 1578133#L987-1 assume !(0 == ~E_5~0); 1577019#L992-1 assume !(0 == ~E_6~0); 1577020#L997-1 assume !(0 == ~E_7~0); 1578043#L1002-1 assume !(0 == ~E_8~0); 1578044#L1007-1 assume !(0 == ~E_9~0); 1576809#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1576810#L443 assume !(1 == ~m_pc~0); 1577727#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1577728#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1578096#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1578097#L1140 assume !(0 != activate_threads_~tmp~1#1); 1576924#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1576925#L462 assume !(1 == ~t1_pc~0); 1577558#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1577559#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1576894#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1576895#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1577394#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1577395#L481 assume !(1 == ~t2_pc~0); 1578213#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1577170#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1577563#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1577268#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1577269#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1578148#L500 assume !(1 == ~t3_pc~0); 1577973#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1577924#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1577867#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1577868#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1576811#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1576812#L519 assume !(1 == ~t4_pc~0); 1577616#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1577617#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1577742#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1577218#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1577219#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1576978#L538 assume !(1 == ~t5_pc~0); 1576979#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1576884#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1576885#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1577154#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1577155#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1577772#L557 assume !(1 == ~t6_pc~0); 1578189#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1578188#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1578187#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1578186#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1578185#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1578139#L576 assume !(1 == ~t7_pc~0); 1577180#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1577181#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1577448#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1577449#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1578180#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1578179#L595 assume !(1 == ~t8_pc~0); 1578178#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1578177#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1578176#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1578175#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1578174#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1578172#L614 assume !(1 == ~t9_pc~0); 1578171#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1578170#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1578169#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1578168#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1578167#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1578166#L1025 assume !(1 == ~M_E~0); 1578165#L1025-2 assume !(1 == ~T1_E~0); 1578164#L1030-1 assume !(1 == ~T2_E~0); 1578163#L1035-1 assume !(1 == ~T3_E~0); 1578162#L1040-1 assume !(1 == ~T4_E~0); 1578161#L1045-1 assume !(1 == ~T5_E~0); 1578160#L1050-1 assume !(1 == ~T6_E~0); 1578159#L1055-1 assume !(1 == ~T7_E~0); 1578158#L1060-1 assume !(1 == ~T8_E~0); 1578157#L1065-1 assume !(1 == ~T9_E~0); 1578156#L1070-1 assume !(1 == ~E_1~0); 1577711#L1075-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1577712#L1080-1 assume !(1 == ~E_3~0); 1577698#L1085-1 assume !(1 == ~E_4~0); 1577699#L1090-1 assume !(1 == ~E_5~0); 1578012#L1095-1 assume !(1 == ~E_6~0); 1577740#L1100-1 assume !(1 == ~E_7~0); 1577741#L1105-1 assume !(1 == ~E_8~0); 1576960#L1110-1 assume !(1 == ~E_9~0); 1576961#L1115-1 assume { :end_inline_reset_delta_events } true; 1577320#L1396-2 [2021-12-19 19:18:06,555 INFO L793 eck$LassoCheckResult]: Loop: 1577320#L1396-2 assume !false; 1650022#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1650016#L897 assume !false; 1650013#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1650010#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1649999#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1649997#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1649994#L766 assume !(0 != eval_~tmp~0#1); 1649995#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1664331#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1664329#L922-3 assume !(0 == ~M_E~0); 1664327#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1664325#L927-3 assume !(0 == ~T2_E~0); 1664323#L932-3 assume !(0 == ~T3_E~0); 1664321#L937-3 assume !(0 == ~T4_E~0); 1664319#L942-3 assume !(0 == ~T5_E~0); 1664317#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1664315#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1664314#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1664313#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1664312#L967-3 assume !(0 == ~E_1~0); 1664309#L972-3 assume !(0 == ~E_2~0); 1664307#L977-3 assume !(0 == ~E_3~0); 1664305#L982-3 assume !(0 == ~E_4~0); 1664303#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1664301#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1664299#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1664297#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1664295#L1007-3 assume !(0 == ~E_9~0); 1664293#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1664291#L443-30 assume !(1 == ~m_pc~0); 1664288#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1664286#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1664282#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1664280#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1664278#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1664276#L462-30 assume !(1 == ~t1_pc~0); 1664274#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1664272#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1664270#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1664268#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1664266#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664263#L481-30 assume !(1 == ~t2_pc~0); 1664259#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1664257#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1664255#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1664253#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1664251#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1664249#L500-30 assume !(1 == ~t3_pc~0); 1657538#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1664246#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1664244#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1664242#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1664240#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1577815#L519-30 assume !(1 == ~t4_pc~0); 1577560#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1577533#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1576857#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1576858#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1577546#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1577679#L538-30 assume !(1 == ~t5_pc~0); 1577001#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1577339#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1577306#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1577307#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1577844#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1655910#L557-30 assume !(1 == ~t6_pc~0); 1655908#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1655907#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1655906#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1655905#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1655903#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1655901#L576-30 assume !(1 == ~t7_pc~0); 1655899#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1655896#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1655894#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1655892#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1655890#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1655888#L595-30 assume !(1 == ~t8_pc~0); 1624023#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1655884#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1655882#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1655880#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1655878#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1655876#L614-30 assume !(1 == ~t9_pc~0); 1655873#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1655871#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1655869#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1655868#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1655867#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1655866#L1025-3 assume !(1 == ~M_E~0); 1624743#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1655863#L1030-3 assume !(1 == ~T2_E~0); 1655861#L1035-3 assume !(1 == ~T3_E~0); 1655859#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1655857#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1655855#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1655853#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1655850#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1655848#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1655846#L1070-3 assume !(1 == ~E_1~0); 1655759#L1075-3 assume !(1 == ~E_2~0); 1655757#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1655755#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1655754#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1655752#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1655750#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1655748#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1655746#L1110-3 assume !(1 == ~E_9~0); 1655744#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1655715#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1655713#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1655711#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1655709#L1415 assume !(0 == start_simulation_~tmp~3#1); 1655706#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1655701#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1655691#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1655689#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1655688#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1655687#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1655684#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1655679#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1577320#L1396-2 [2021-12-19 19:18:06,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:06,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1478968428, now seen corresponding path program 1 times [2021-12-19 19:18:06,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:06,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800021760] [2021-12-19 19:18:06,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:06,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:06,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:06,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:06,582 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:06,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800021760] [2021-12-19 19:18:06,582 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800021760] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:06,583 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:06,583 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:18:06,583 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795678233] [2021-12-19 19:18:06,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:06,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:06,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:06,584 INFO L85 PathProgramCache]: Analyzing trace with hash -1828770983, now seen corresponding path program 1 times [2021-12-19 19:18:06,584 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:06,584 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067154957] [2021-12-19 19:18:06,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:06,584 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:06,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:06,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:06,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:06,616 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067154957] [2021-12-19 19:18:06,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067154957] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:06,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:06,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:06,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176293282] [2021-12-19 19:18:06,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:06,618 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:06,618 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:06,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:06,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:06,618 INFO L87 Difference]: Start difference. First operand 90275 states and 124944 transitions. cyclomatic complexity: 34671 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:06,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:06,784 INFO L93 Difference]: Finished difference Result 48139 states and 66679 transitions. [2021-12-19 19:18:06,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:06,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48139 states and 66679 transitions. [2021-12-19 19:18:06,985 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:18:07,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48139 states to 48139 states and 66679 transitions. [2021-12-19 19:18:07,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48139 [2021-12-19 19:18:07,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48139 [2021-12-19 19:18:07,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48139 states and 66679 transitions. [2021-12-19 19:18:07,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:07,175 INFO L681 BuchiCegarLoop]: Abstraction has 48139 states and 66679 transitions. [2021-12-19 19:18:07,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48139 states and 66679 transitions. [2021-12-19 19:18:07,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48139 to 48139. [2021-12-19 19:18:07,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48139 states, 48139 states have (on average 1.3851347140572092) internal successors, (66679), 48138 states have internal predecessors, (66679), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:07,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48139 states to 48139 states and 66679 transitions. [2021-12-19 19:18:07,636 INFO L704 BuchiCegarLoop]: Abstraction has 48139 states and 66679 transitions. [2021-12-19 19:18:07,636 INFO L587 BuchiCegarLoop]: Abstraction has 48139 states and 66679 transitions. [2021-12-19 19:18:07,636 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:18:07,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48139 states and 66679 transitions. [2021-12-19 19:18:07,778 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 47984 [2021-12-19 19:18:07,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:07,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:07,783 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:07,783 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:07,784 INFO L791 eck$LassoCheckResult]: Stem: 1716099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1716100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1715653#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1715654#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1716299#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1716300#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1716274#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1716041#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1716042#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1715830#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1715831#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1716406#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1716247#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1715900#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1715659#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1715660#L922 assume !(0 == ~M_E~0); 1716488#L922-2 assume !(0 == ~T1_E~0); 1716489#L927-1 assume !(0 == ~T2_E~0); 1716108#L932-1 assume !(0 == ~T3_E~0); 1715975#L937-1 assume !(0 == ~T4_E~0); 1715976#L942-1 assume !(0 == ~T5_E~0); 1716040#L947-1 assume !(0 == ~T6_E~0); 1716112#L952-1 assume !(0 == ~T7_E~0); 1716113#L957-1 assume !(0 == ~T8_E~0); 1716190#L962-1 assume !(0 == ~T9_E~0); 1715949#L967-1 assume !(0 == ~E_1~0); 1715950#L972-1 assume !(0 == ~E_2~0); 1716285#L977-1 assume !(0 == ~E_3~0); 1716286#L982-1 assume !(0 == ~E_4~0); 1715433#L987-1 assume !(0 == ~E_5~0); 1715434#L992-1 assume !(0 == ~E_6~0); 1715442#L997-1 assume !(0 == ~E_7~0); 1715876#L1002-1 assume !(0 == ~E_8~0); 1715858#L1007-1 assume !(0 == ~E_9~0); 1715232#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1715233#L443 assume !(1 == ~m_pc~0); 1716130#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1716118#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1716119#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1715592#L1140 assume !(0 != activate_threads_~tmp~1#1); 1715346#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1715347#L462 assume !(1 == ~t1_pc~0); 1715969#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1715970#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1715317#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1715318#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1715812#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1715813#L481 assume !(1 == ~t2_pc~0); 1715587#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1716096#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1715972#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1715681#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1715682#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1715788#L500 assume !(1 == ~t3_pc~0); 1716358#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1716316#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1716263#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1716264#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1715237#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1715238#L519 assume !(1 == ~t4_pc~0); 1716024#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1715784#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1715785#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1715636#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1715637#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1715401#L538 assume !(1 == ~t5_pc~0); 1715402#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1715307#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1715308#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1715572#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1715573#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1716167#L557 assume !(1 == ~t6_pc~0); 1715609#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1715610#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1715513#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1715514#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1715635#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1716448#L576 assume !(1 == ~t7_pc~0); 1715596#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1715597#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1715860#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1715861#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1716237#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1715724#L595 assume !(1 == ~t8_pc~0); 1715725#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1716265#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1716266#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1716072#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1716073#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1715524#L614 assume !(1 == ~t9_pc~0); 1715525#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1715425#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1715426#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1715600#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1715683#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1715684#L1025 assume !(1 == ~M_E~0); 1715959#L1025-2 assume !(1 == ~T1_E~0); 1716015#L1030-1 assume !(1 == ~T2_E~0); 1716159#L1035-1 assume !(1 == ~T3_E~0); 1715678#L1040-1 assume !(1 == ~T4_E~0); 1715679#L1045-1 assume !(1 == ~T5_E~0); 1715583#L1050-1 assume !(1 == ~T6_E~0); 1715584#L1055-1 assume !(1 == ~T7_E~0); 1715410#L1060-1 assume !(1 == ~T8_E~0); 1715411#L1065-1 assume !(1 == ~T9_E~0); 1715472#L1070-1 assume !(1 == ~E_1~0); 1716114#L1075-1 assume !(1 == ~E_2~0); 1716115#L1080-1 assume !(1 == ~E_3~0); 1716103#L1085-1 assume !(1 == ~E_4~0); 1716104#L1090-1 assume !(1 == ~E_5~0); 1716397#L1095-1 assume !(1 == ~E_6~0); 1716140#L1100-1 assume !(1 == ~E_7~0); 1716141#L1105-1 assume !(1 == ~E_8~0); 1715382#L1110-1 assume !(1 == ~E_9~0); 1715383#L1115-1 assume { :end_inline_reset_delta_events } true; 1715736#L1396-2 [2021-12-19 19:18:07,784 INFO L793 eck$LassoCheckResult]: Loop: 1715736#L1396-2 assume !false; 1749674#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1749669#L897 assume !false; 1749668#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1749667#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1749657#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1749656#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1749654#L766 assume !(0 != eval_~tmp~0#1); 1749655#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1753131#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1753129#L922-3 assume !(0 == ~M_E~0); 1753127#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1753125#L927-3 assume !(0 == ~T2_E~0); 1753123#L932-3 assume !(0 == ~T3_E~0); 1753120#L937-3 assume !(0 == ~T4_E~0); 1753118#L942-3 assume !(0 == ~T5_E~0); 1753115#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1753113#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1753111#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1753109#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1753106#L967-3 assume !(0 == ~E_1~0); 1753107#L972-3 assume !(0 == ~E_2~0); 1761813#L977-3 assume !(0 == ~E_3~0); 1761811#L982-3 assume !(0 == ~E_4~0); 1753097#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1753095#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1753090#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1753091#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1761800#L1007-3 assume !(0 == ~E_9~0); 1761799#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1753081#L443-30 assume !(1 == ~m_pc~0); 1753077#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1753078#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1761783#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1761781#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1761779#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1761777#L462-30 assume !(1 == ~t1_pc~0); 1761775#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1761773#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1761771#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1761769#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1761767#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1761765#L481-30 assume !(1 == ~t2_pc~0); 1761762#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1761760#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1761758#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1761756#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1761754#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1749841#L500-30 assume !(1 == ~t3_pc~0); 1749840#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1749839#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1749838#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1749837#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1749836#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1749835#L519-30 assume !(1 == ~t4_pc~0); 1740836#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1749834#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1749833#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1749832#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1749831#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1749829#L538-30 assume !(1 == ~t5_pc~0); 1749826#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1749825#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1749823#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1749821#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1749818#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1749816#L557-30 assume !(1 == ~t6_pc~0); 1739668#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1749813#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1749811#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1749809#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1749807#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1749805#L576-30 assume 1 == ~t7_pc~0; 1749802#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1749800#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1749798#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1749796#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1749794#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1749792#L595-30 assume !(1 == ~t8_pc~0); 1739136#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1749790#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1749789#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1749788#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1749787#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1749785#L614-30 assume !(1 == ~t9_pc~0); 1749783#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1749782#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1749780#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1749778#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1749776#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1749774#L1025-3 assume !(1 == ~M_E~0); 1742905#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1749771#L1030-3 assume !(1 == ~T2_E~0); 1749769#L1035-3 assume !(1 == ~T3_E~0); 1749768#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1749766#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1749764#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1749762#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1749760#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1749756#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1749754#L1070-3 assume !(1 == ~E_1~0); 1749752#L1075-3 assume !(1 == ~E_2~0); 1749750#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1749747#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1749745#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1749743#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1749742#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1749740#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1749738#L1110-3 assume !(1 == ~E_9~0); 1749736#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1749715#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1749713#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1749711#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1749708#L1415 assume !(0 == start_simulation_~tmp~3#1); 1749705#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1749699#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1749687#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1749685#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1749683#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1749682#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1749681#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1749677#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1715736#L1396-2 [2021-12-19 19:18:07,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:07,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 3 times [2021-12-19 19:18:07,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:07,785 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446545326] [2021-12-19 19:18:07,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:07,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:07,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:07,795 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:07,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:07,831 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:07,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:07,832 INFO L85 PathProgramCache]: Analyzing trace with hash -98433926, now seen corresponding path program 1 times [2021-12-19 19:18:07,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:07,832 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618468463] [2021-12-19 19:18:07,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:07,832 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:07,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:07,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:07,864 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:07,864 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618468463] [2021-12-19 19:18:07,865 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618468463] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:07,865 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:07,865 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:07,865 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2095834170] [2021-12-19 19:18:07,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:07,866 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:07,866 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:07,866 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:18:07,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:18:07,867 INFO L87 Difference]: Start difference. First operand 48139 states and 66679 transitions. cyclomatic complexity: 18542 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:08,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:08,443 INFO L93 Difference]: Finished difference Result 88059 states and 120679 transitions. [2021-12-19 19:18:08,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:18:08,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88059 states and 120679 transitions. [2021-12-19 19:18:08,811 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87872 [2021-12-19 19:18:09,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88059 states to 88059 states and 120679 transitions. [2021-12-19 19:18:09,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88059 [2021-12-19 19:18:09,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88059 [2021-12-19 19:18:09,085 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88059 states and 120679 transitions. [2021-12-19 19:18:09,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:09,132 INFO L681 BuchiCegarLoop]: Abstraction has 88059 states and 120679 transitions. [2021-12-19 19:18:09,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88059 states and 120679 transitions. [2021-12-19 19:18:09,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88059 to 48331. [2021-12-19 19:18:09,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48331 states, 48331 states have (on average 1.3836047257453807) internal successors, (66871), 48330 states have internal predecessors, (66871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:10,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48331 states to 48331 states and 66871 transitions. [2021-12-19 19:18:10,222 INFO L704 BuchiCegarLoop]: Abstraction has 48331 states and 66871 transitions. [2021-12-19 19:18:10,222 INFO L587 BuchiCegarLoop]: Abstraction has 48331 states and 66871 transitions. [2021-12-19 19:18:10,222 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:18:10,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48331 states and 66871 transitions. [2021-12-19 19:18:10,363 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 48176 [2021-12-19 19:18:10,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:10,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:10,367 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:10,367 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:10,367 INFO L791 eck$LassoCheckResult]: Stem: 1852313#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1852314#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1851872#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1851873#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1852506#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1852507#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1852483#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1852255#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1852256#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1852044#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1852045#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1852602#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1852462#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1852114#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1851878#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1851879#L922 assume !(0 == ~M_E~0); 1852689#L922-2 assume !(0 == ~T1_E~0); 1852690#L927-1 assume !(0 == ~T2_E~0); 1852324#L932-1 assume !(0 == ~T3_E~0); 1852196#L937-1 assume !(0 == ~T4_E~0); 1852197#L942-1 assume !(0 == ~T5_E~0); 1852254#L947-1 assume !(0 == ~T6_E~0); 1852328#L952-1 assume !(0 == ~T7_E~0); 1852329#L957-1 assume !(0 == ~T8_E~0); 1852409#L962-1 assume !(0 == ~T9_E~0); 1852166#L967-1 assume !(0 == ~E_1~0); 1852167#L972-1 assume !(0 == ~E_2~0); 1852490#L977-1 assume !(0 == ~E_3~0); 1852491#L982-1 assume !(0 == ~E_4~0); 1851646#L987-1 assume !(0 == ~E_5~0); 1851647#L992-1 assume !(0 == ~E_6~0); 1851655#L997-1 assume !(0 == ~E_7~0); 1852091#L1002-1 assume !(0 == ~E_8~0); 1852073#L1007-1 assume !(0 == ~E_9~0); 1851446#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1851447#L443 assume !(1 == ~m_pc~0); 1852346#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1852335#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1852336#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1851810#L1140 assume !(0 != activate_threads_~tmp~1#1); 1851560#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1851561#L462 assume !(1 == ~t1_pc~0); 1852189#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1852190#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1851531#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1851532#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1852026#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1852027#L481 assume !(1 == ~t2_pc~0); 1851805#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1852310#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1852192#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1851899#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1851900#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1852003#L500 assume !(1 == ~t3_pc~0); 1852562#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1852523#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1852475#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1852476#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1851451#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1851452#L519 assume !(1 == ~t4_pc~0); 1852241#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1851999#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1852000#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1851855#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1851856#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1851614#L538 assume !(1 == ~t5_pc~0); 1851615#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1851521#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1851522#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1851790#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1851791#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1852390#L557 assume !(1 == ~t6_pc~0); 1851827#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1851828#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1851727#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1851728#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1851854#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1852652#L576 assume !(1 == ~t7_pc~0); 1851814#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1851815#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1852075#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1852076#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1852451#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1851941#L595 assume !(1 == ~t8_pc~0); 1851942#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1852477#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1852478#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1852283#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1852284#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1851740#L614 assume !(1 == ~t9_pc~0); 1851741#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1851638#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1851639#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1851818#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1851901#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1851902#L1025 assume !(1 == ~M_E~0); 1852176#L1025-2 assume !(1 == ~T1_E~0); 1852234#L1030-1 assume !(1 == ~T2_E~0); 1852381#L1035-1 assume !(1 == ~T3_E~0); 1851896#L1040-1 assume !(1 == ~T4_E~0); 1851897#L1045-1 assume !(1 == ~T5_E~0); 1851801#L1050-1 assume !(1 == ~T6_E~0); 1851802#L1055-1 assume !(1 == ~T7_E~0); 1851623#L1060-1 assume !(1 == ~T8_E~0); 1851624#L1065-1 assume !(1 == ~T9_E~0); 1851685#L1070-1 assume !(1 == ~E_1~0); 1852330#L1075-1 assume !(1 == ~E_2~0); 1852331#L1080-1 assume !(1 == ~E_3~0); 1852319#L1085-1 assume !(1 == ~E_4~0); 1852320#L1090-1 assume !(1 == ~E_5~0); 1852593#L1095-1 assume !(1 == ~E_6~0); 1852360#L1100-1 assume !(1 == ~E_7~0); 1852361#L1105-1 assume !(1 == ~E_8~0); 1851596#L1110-1 assume !(1 == ~E_9~0); 1851597#L1115-1 assume { :end_inline_reset_delta_events } true; 1851952#L1396-2 [2021-12-19 19:18:10,367 INFO L793 eck$LassoCheckResult]: Loop: 1851952#L1396-2 assume !false; 1897082#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1897078#L897 assume !false; 1897077#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1897076#L699 assume !(0 == ~m_st~0); 1897069#L703 assume !(0 == ~t1_st~0); 1897070#L707 assume !(0 == ~t2_st~0); 1897074#L711 assume !(0 == ~t3_st~0); 1897066#L715 assume !(0 == ~t4_st~0); 1897068#L719 assume !(0 == ~t5_st~0); 1897073#L723 assume !(0 == ~t6_st~0); 1897075#L727 assume !(0 == ~t7_st~0); 1897071#L731 assume !(0 == ~t8_st~0); 1897072#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1897065#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1870722#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1870723#L766 assume !(0 != eval_~tmp~0#1); 1897855#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1897850#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1897845#L922-3 assume !(0 == ~M_E~0); 1897840#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1897834#L927-3 assume !(0 == ~T2_E~0); 1897828#L932-3 assume !(0 == ~T3_E~0); 1897822#L937-3 assume !(0 == ~T4_E~0); 1897816#L942-3 assume !(0 == ~T5_E~0); 1897810#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1897804#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1897798#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1897792#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1897786#L967-3 assume !(0 == ~E_1~0); 1897780#L972-3 assume !(0 == ~E_2~0); 1897773#L977-3 assume !(0 == ~E_3~0); 1897766#L982-3 assume !(0 == ~E_4~0); 1897760#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1897753#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1897746#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1897739#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1897732#L1007-3 assume !(0 == ~E_9~0); 1897723#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1897716#L443-30 assume !(1 == ~m_pc~0); 1897708#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1897632#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1897629#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1897627#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1897625#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1897623#L462-30 assume !(1 == ~t1_pc~0); 1897621#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1897619#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1897617#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1897615#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1897613#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1897611#L481-30 assume !(1 == ~t2_pc~0); 1897573#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1897565#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1897557#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1897549#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1897541#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1897532#L500-30 assume !(1 == ~t3_pc~0); 1897523#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1897519#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1897515#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1897511#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1897507#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1897503#L519-30 assume !(1 == ~t4_pc~0); 1895240#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1897499#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1897495#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1897491#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1897487#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1897483#L538-30 assume 1 == ~t5_pc~0; 1897477#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1897469#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1897461#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1897453#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1897447#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1897443#L557-30 assume !(1 == ~t6_pc~0); 1897439#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1897437#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1897435#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1897433#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 1897431#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1897429#L576-30 assume 1 == ~t7_pc~0; 1897426#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1897423#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1897421#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1897419#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1897417#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1897415#L595-30 assume !(1 == ~t8_pc~0); 1893470#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1897413#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1897411#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1897409#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1897407#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1897405#L614-30 assume !(1 == ~t9_pc~0); 1897401#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1897399#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1897397#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1897395#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1897393#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897391#L1025-3 assume !(1 == ~M_E~0); 1897388#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1897387#L1030-3 assume !(1 == ~T2_E~0); 1897386#L1035-3 assume !(1 == ~T3_E~0); 1897385#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1897384#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1897383#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1897382#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1897381#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1897380#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1897379#L1070-3 assume !(1 == ~E_1~0); 1897378#L1075-3 assume !(1 == ~E_2~0); 1897377#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1897376#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1897375#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1897374#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1897373#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1897372#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1897371#L1110-3 assume !(1 == ~E_9~0); 1897370#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1897360#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1897322#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1897311#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1897304#L1415 assume !(0 == start_simulation_~tmp~3#1); 1897102#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1897100#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1897091#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1897090#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1897088#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1897086#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1897084#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1897083#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1851952#L1396-2 [2021-12-19 19:18:10,368 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:10,368 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 4 times [2021-12-19 19:18:10,368 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:10,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664469305] [2021-12-19 19:18:10,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:10,369 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:10,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,377 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:10,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:10,407 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:10,408 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:10,408 INFO L85 PathProgramCache]: Analyzing trace with hash -1980759130, now seen corresponding path program 1 times [2021-12-19 19:18:10,408 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:10,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903667939] [2021-12-19 19:18:10,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:10,409 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:10,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:10,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:10,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:10,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1903667939] [2021-12-19 19:18:10,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1903667939] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:10,467 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:10,467 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:10,467 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25427782] [2021-12-19 19:18:10,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:10,467 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:10,468 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:10,468 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:18:10,468 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:18:10,468 INFO L87 Difference]: Start difference. First operand 48331 states and 66871 transitions. cyclomatic complexity: 18542 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:10,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:10,940 INFO L93 Difference]: Finished difference Result 107899 states and 151030 transitions. [2021-12-19 19:18:10,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:18:10,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107899 states and 151030 transitions. [2021-12-19 19:18:11,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 107680 [2021-12-19 19:18:11,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107899 states to 107899 states and 151030 transitions. [2021-12-19 19:18:11,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107899 [2021-12-19 19:18:11,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107899 [2021-12-19 19:18:11,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107899 states and 151030 transitions. [2021-12-19 19:18:11,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:11,946 INFO L681 BuchiCegarLoop]: Abstraction has 107899 states and 151030 transitions. [2021-12-19 19:18:12,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107899 states and 151030 transitions. [2021-12-19 19:18:13,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107899 to 49147. [2021-12-19 19:18:13,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49147 states, 49147 states have (on average 1.372331983640914) internal successors, (67446), 49146 states have internal predecessors, (67446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:13,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49147 states to 49147 states and 67446 transitions. [2021-12-19 19:18:13,139 INFO L704 BuchiCegarLoop]: Abstraction has 49147 states and 67446 transitions. [2021-12-19 19:18:13,139 INFO L587 BuchiCegarLoop]: Abstraction has 49147 states and 67446 transitions. [2021-12-19 19:18:13,139 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:18:13,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49147 states and 67446 transitions. [2021-12-19 19:18:13,272 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 48992 [2021-12-19 19:18:13,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:13,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:13,276 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:13,277 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:13,277 INFO L791 eck$LassoCheckResult]: Stem: 2008560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2008561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2008114#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2008115#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2008765#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2008766#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2008742#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2008504#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2008505#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2008295#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2008296#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2008862#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2008716#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2008357#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2008121#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2008122#L922 assume !(0 == ~M_E~0); 2008947#L922-2 assume !(0 == ~T1_E~0); 2008948#L927-1 assume !(0 == ~T2_E~0); 2008570#L932-1 assume !(0 == ~T3_E~0); 2008436#L937-1 assume !(0 == ~T4_E~0); 2008437#L942-1 assume !(0 == ~T5_E~0); 2008503#L947-1 assume !(0 == ~T6_E~0); 2008576#L952-1 assume !(0 == ~T7_E~0); 2008577#L957-1 assume !(0 == ~T8_E~0); 2008658#L962-1 assume !(0 == ~T9_E~0); 2008410#L967-1 assume !(0 == ~E_1~0); 2008411#L972-1 assume !(0 == ~E_2~0); 2008750#L977-1 assume !(0 == ~E_3~0); 2008751#L982-1 assume !(0 == ~E_4~0); 2007889#L987-1 assume !(0 == ~E_5~0); 2007890#L992-1 assume !(0 == ~E_6~0); 2007898#L997-1 assume !(0 == ~E_7~0); 2008332#L1002-1 assume !(0 == ~E_8~0); 2008315#L1007-1 assume !(0 == ~E_9~0); 2007689#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2007690#L443 assume !(1 == ~m_pc~0); 2008597#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2008585#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2008586#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2008051#L1140 assume !(0 != activate_threads_~tmp~1#1); 2007803#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2007804#L462 assume !(1 == ~t1_pc~0); 2008427#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2008428#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2007774#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2007775#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2008277#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2008278#L481 assume !(1 == ~t2_pc~0); 2008046#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2008557#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2008433#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2008143#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2008144#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2008251#L500 assume !(1 == ~t3_pc~0); 2008825#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2008782#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2008732#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2008733#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2007691#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2007692#L519 assume !(1 == ~t4_pc~0); 2008487#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2008249#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2008250#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2008095#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2008096#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2007857#L538 assume !(1 == ~t5_pc~0); 2007858#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2007764#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2007765#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2008032#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2008033#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2008639#L557 assume !(1 == ~t6_pc~0); 2008068#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2008069#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2007967#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2007968#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2008094#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2008911#L576 assume !(1 == ~t7_pc~0); 2008055#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2008056#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2008319#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2008320#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2008705#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2008185#L595 assume !(1 == ~t8_pc~0); 2008186#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2008734#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2008735#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2008531#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2008532#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2007982#L614 assume !(1 == ~t9_pc~0); 2007983#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2007881#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2007882#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2008059#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2008145#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2008146#L1025 assume !(1 == ~M_E~0); 2008420#L1025-2 assume !(1 == ~T1_E~0); 2008480#L1030-1 assume !(1 == ~T2_E~0); 2008632#L1035-1 assume !(1 == ~T3_E~0); 2008139#L1040-1 assume !(1 == ~T4_E~0); 2008140#L1045-1 assume !(1 == ~T5_E~0); 2008042#L1050-1 assume !(1 == ~T6_E~0); 2008043#L1055-1 assume !(1 == ~T7_E~0); 2007866#L1060-1 assume !(1 == ~T8_E~0); 2007867#L1065-1 assume !(1 == ~T9_E~0); 2007929#L1070-1 assume !(1 == ~E_1~0); 2008578#L1075-1 assume !(1 == ~E_2~0); 2008579#L1080-1 assume !(1 == ~E_3~0); 2008564#L1085-1 assume !(1 == ~E_4~0); 2008565#L1090-1 assume !(1 == ~E_5~0); 2008854#L1095-1 assume !(1 == ~E_6~0); 2008610#L1100-1 assume !(1 == ~E_7~0); 2008611#L1105-1 assume !(1 == ~E_8~0); 2007839#L1110-1 assume !(1 == ~E_9~0); 2007840#L1115-1 assume { :end_inline_reset_delta_events } true; 2008198#L1396-2 [2021-12-19 19:18:13,277 INFO L793 eck$LassoCheckResult]: Loop: 2008198#L1396-2 assume !false; 2031105#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2031099#L897 assume !false; 2031096#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2031093#L699 assume !(0 == ~m_st~0); 2031085#L703 assume !(0 == ~t1_st~0); 2031086#L707 assume !(0 == ~t2_st~0); 2031090#L711 assume !(0 == ~t3_st~0); 2031083#L715 assume !(0 == ~t4_st~0); 2031084#L719 assume !(0 == ~t5_st~0); 2031089#L723 assume !(0 == ~t6_st~0); 2031092#L727 assume !(0 == ~t7_st~0); 2031087#L731 assume !(0 == ~t8_st~0); 2031088#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2031091#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2026386#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2026387#L766 assume !(0 != eval_~tmp~0#1); 2031298#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2031297#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2031296#L922-3 assume !(0 == ~M_E~0); 2031295#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2031294#L927-3 assume !(0 == ~T2_E~0); 2031293#L932-3 assume !(0 == ~T3_E~0); 2031292#L937-3 assume !(0 == ~T4_E~0); 2031291#L942-3 assume !(0 == ~T5_E~0); 2031290#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2031289#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2031288#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2031287#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2031286#L967-3 assume !(0 == ~E_1~0); 2031285#L972-3 assume !(0 == ~E_2~0); 2031284#L977-3 assume !(0 == ~E_3~0); 2031283#L982-3 assume !(0 == ~E_4~0); 2031282#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2031281#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2031280#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2031279#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2031278#L1007-3 assume !(0 == ~E_9~0); 2031277#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2031276#L443-30 assume !(1 == ~m_pc~0); 2031274#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2031273#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2031272#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2031271#L1140-30 assume !(0 != activate_threads_~tmp~1#1); 2031270#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2031269#L462-30 assume !(1 == ~t1_pc~0); 2031268#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2031267#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2031266#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2031265#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2031264#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2031263#L481-30 assume !(1 == ~t2_pc~0); 2031261#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2031260#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2031259#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2031258#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2031257#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2031256#L500-30 assume !(1 == ~t3_pc~0); 2029700#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2031255#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2031254#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2031253#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2031252#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2031251#L519-30 assume !(1 == ~t4_pc~0); 2026712#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2031250#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031249#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2031248#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2031247#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2031246#L538-30 assume 1 == ~t5_pc~0; 2031244#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2031242#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2031240#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2031238#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2031237#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2031236#L557-30 assume !(1 == ~t6_pc~0); 2028719#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2031235#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2031234#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2031233#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2031232#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2031231#L576-30 assume !(1 == ~t7_pc~0); 2031230#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2031228#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2031227#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2031226#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2031225#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2031224#L595-30 assume !(1 == ~t8_pc~0); 2021999#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2031223#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2031222#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2031221#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2031220#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2031219#L614-30 assume !(1 == ~t9_pc~0); 2031217#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2031216#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2031215#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2031214#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2031213#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2031212#L1025-3 assume !(1 == ~M_E~0); 2019239#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2031211#L1030-3 assume !(1 == ~T2_E~0); 2031210#L1035-3 assume !(1 == ~T3_E~0); 2031209#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2031208#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2031207#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2031205#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2031194#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2031191#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2031188#L1070-3 assume !(1 == ~E_1~0); 2031185#L1075-3 assume !(1 == ~E_2~0); 2031182#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2031179#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2031176#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2031173#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2031169#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2031166#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2031163#L1110-3 assume !(1 == ~E_9~0); 2031160#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2031148#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2031145#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2031142#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2031140#L1415 assume !(0 == start_simulation_~tmp~3#1); 2031137#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2031133#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2031123#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2031120#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2031117#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2031115#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2031113#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2031110#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2008198#L1396-2 [2021-12-19 19:18:13,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:13,278 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 5 times [2021-12-19 19:18:13,278 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:13,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830826438] [2021-12-19 19:18:13,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:13,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:13,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:13,293 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:13,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:13,336 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:13,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:13,337 INFO L85 PathProgramCache]: Analyzing trace with hash -410822589, now seen corresponding path program 1 times [2021-12-19 19:18:13,337 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:13,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559517780] [2021-12-19 19:18:13,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:13,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:13,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:13,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:13,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:13,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559517780] [2021-12-19 19:18:13,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559517780] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:13,364 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:13,365 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:13,365 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [186687317] [2021-12-19 19:18:13,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:13,365 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:13,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:13,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:13,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:13,366 INFO L87 Difference]: Start difference. First operand 49147 states and 67446 transitions. cyclomatic complexity: 18301 Second operand has 3 states, 3 states have (on average 43.666666666666664) internal successors, (131), 3 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:13,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:13,590 INFO L93 Difference]: Finished difference Result 89243 states and 121302 transitions. [2021-12-19 19:18:13,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:13,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89243 states and 121302 transitions. [2021-12-19 19:18:13,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 89056 [2021-12-19 19:18:14,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89243 states to 89243 states and 121302 transitions. [2021-12-19 19:18:14,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89243 [2021-12-19 19:18:14,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89243 [2021-12-19 19:18:14,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89243 states and 121302 transitions. [2021-12-19 19:18:14,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:14,721 INFO L681 BuchiCegarLoop]: Abstraction has 89243 states and 121302 transitions. [2021-12-19 19:18:14,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89243 states and 121302 transitions. [2021-12-19 19:18:15,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89243 to 87083. [2021-12-19 19:18:15,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87083 states, 87083 states have (on average 1.3607937255262221) internal successors, (118502), 87082 states have internal predecessors, (118502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:15,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87083 states to 87083 states and 118502 transitions. [2021-12-19 19:18:15,600 INFO L704 BuchiCegarLoop]: Abstraction has 87083 states and 118502 transitions. [2021-12-19 19:18:15,600 INFO L587 BuchiCegarLoop]: Abstraction has 87083 states and 118502 transitions. [2021-12-19 19:18:15,600 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-12-19 19:18:15,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87083 states and 118502 transitions. [2021-12-19 19:18:15,858 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 86896 [2021-12-19 19:18:15,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:15,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:15,879 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:15,879 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:15,879 INFO L791 eck$LassoCheckResult]: Stem: 2146957#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2146958#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2146509#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2146510#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2147156#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2147157#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2147130#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2146895#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2146896#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2146689#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2146690#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2147260#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2147102#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2146755#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2146515#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2146516#L922 assume !(0 == ~M_E~0); 2147362#L922-2 assume !(0 == ~T1_E~0); 2147363#L927-1 assume !(0 == ~T2_E~0); 2146967#L932-1 assume !(0 == ~T3_E~0); 2146828#L937-1 assume !(0 == ~T4_E~0); 2146829#L942-1 assume !(0 == ~T5_E~0); 2146894#L947-1 assume !(0 == ~T6_E~0); 2146971#L952-1 assume !(0 == ~T7_E~0); 2146972#L957-1 assume !(0 == ~T8_E~0); 2147050#L962-1 assume !(0 == ~T9_E~0); 2146807#L967-1 assume !(0 == ~E_1~0); 2146808#L972-1 assume !(0 == ~E_2~0); 2147139#L977-1 assume !(0 == ~E_3~0); 2147140#L982-1 assume !(0 == ~E_4~0); 2146289#L987-1 assume !(0 == ~E_5~0); 2146290#L992-1 assume !(0 == ~E_6~0); 2146296#L997-1 assume !(0 == ~E_7~0); 2146732#L1002-1 assume !(0 == ~E_8~0); 2146714#L1007-1 assume !(0 == ~E_9~0); 2146085#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2146086#L443 assume !(1 == ~m_pc~0); 2146988#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2146978#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2146979#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2146447#L1140 assume !(0 != activate_threads_~tmp~1#1); 2146200#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2146201#L462 assume !(1 == ~t1_pc~0); 2146823#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2146824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2146170#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2146171#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2146671#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2146672#L481 assume !(1 == ~t2_pc~0); 2146442#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2146953#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2146825#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2146537#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2146538#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2146646#L500 assume !(1 == ~t3_pc~0); 2147219#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2147170#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2147119#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2147120#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2146090#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2146091#L519 assume !(1 == ~t4_pc~0); 2146878#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2146642#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2146643#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2146490#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2146491#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2146255#L538 assume !(1 == ~t5_pc~0); 2146256#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2146160#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2146161#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2146427#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2146428#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2147031#L557 assume !(1 == ~t6_pc~0); 2146463#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2146464#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2146369#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2146370#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2146492#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2147315#L576 assume !(1 == ~t7_pc~0); 2146451#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2146452#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2146717#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2146718#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2147092#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2146579#L595 assume !(1 == ~t8_pc~0); 2146580#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2147121#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2147122#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2146921#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2146922#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2146378#L614 assume !(1 == ~t9_pc~0); 2146379#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2146280#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2146281#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2146455#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2146539#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2146540#L1025 assume !(1 == ~M_E~0); 2146813#L1025-2 assume !(1 == ~T1_E~0); 2146869#L1030-1 assume !(1 == ~T2_E~0); 2147022#L1035-1 assume !(1 == ~T3_E~0); 2146534#L1040-1 assume !(1 == ~T4_E~0); 2146535#L1045-1 assume !(1 == ~T5_E~0); 2146438#L1050-1 assume !(1 == ~T6_E~0); 2146439#L1055-1 assume !(1 == ~T7_E~0); 2146264#L1060-1 assume !(1 == ~T8_E~0); 2146265#L1065-1 assume !(1 == ~T9_E~0); 2146326#L1070-1 assume !(1 == ~E_1~0); 2146973#L1075-1 assume !(1 == ~E_2~0); 2146974#L1080-1 assume !(1 == ~E_3~0); 2146961#L1085-1 assume !(1 == ~E_4~0); 2146962#L1090-1 assume !(1 == ~E_5~0); 2147249#L1095-1 assume !(1 == ~E_6~0); 2147000#L1100-1 assume !(1 == ~E_7~0); 2147001#L1105-1 assume !(1 == ~E_8~0); 2146236#L1110-1 assume !(1 == ~E_9~0); 2146237#L1115-1 assume { :end_inline_reset_delta_events } true; 2146590#L1396-2 [2021-12-19 19:18:15,880 INFO L793 eck$LassoCheckResult]: Loop: 2146590#L1396-2 assume !false; 2186883#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2186876#L897 assume !false; 2186874#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2186871#L699 assume !(0 == ~m_st~0); 2186872#L703 assume !(0 == ~t1_st~0); 2210649#L707 assume !(0 == ~t2_st~0); 2210653#L711 assume !(0 == ~t3_st~0); 2210647#L715 assume !(0 == ~t4_st~0); 2210648#L719 assume !(0 == ~t5_st~0); 2210652#L723 assume !(0 == ~t6_st~0); 2210655#L727 assume !(0 == ~t7_st~0); 2210650#L731 assume !(0 == ~t8_st~0); 2210651#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2210654#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2228782#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2228780#L766 assume !(0 != eval_~tmp~0#1); 2228778#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2228776#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2228774#L922-3 assume !(0 == ~M_E~0); 2228772#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2228770#L927-3 assume !(0 == ~T2_E~0); 2228768#L932-3 assume !(0 == ~T3_E~0); 2228766#L937-3 assume !(0 == ~T4_E~0); 2228764#L942-3 assume !(0 == ~T5_E~0); 2228762#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2228761#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2228759#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2228757#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2228755#L967-3 assume !(0 == ~E_1~0); 2228753#L972-3 assume !(0 == ~E_2~0); 2228749#L977-3 assume !(0 == ~E_3~0); 2228747#L982-3 assume !(0 == ~E_4~0); 2228745#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2228743#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2228740#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2228738#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2228736#L1007-3 assume !(0 == ~E_9~0); 2228735#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2228734#L443-30 assume !(1 == ~m_pc~0); 2228730#L443-32 is_master_triggered_~__retres1~0#1 := 0; 2228728#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2228726#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2228724#L1140-30 assume !(0 != activate_threads_~tmp~1#1); 2228722#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2228720#L462-30 assume !(1 == ~t1_pc~0); 2228719#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2228716#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2228714#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2228712#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2228710#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2228708#L481-30 assume !(1 == ~t2_pc~0); 2228706#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2228704#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2228703#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2228699#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2228697#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2205739#L500-30 assume !(1 == ~t3_pc~0); 2205735#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2205609#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2205605#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2205603#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2205601#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2205592#L519-30 assume !(1 == ~t4_pc~0); 2182622#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2205589#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2205587#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2205585#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2205583#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2205581#L538-30 assume !(1 == ~t5_pc~0); 2205577#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2205575#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2205573#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2205571#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2205554#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2205549#L557-30 assume !(1 == ~t6_pc~0); 2187965#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2205523#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2205518#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2205516#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2205514#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2205512#L576-30 assume 1 == ~t7_pc~0; 2205509#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2205507#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2205505#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2205503#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2205501#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2205499#L595-30 assume !(1 == ~t8_pc~0); 2190548#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2205495#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2205493#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2205491#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2205489#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2205487#L614-30 assume !(1 == ~t9_pc~0); 2205484#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2205482#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2205462#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2205436#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2205431#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2189982#L1025-3 assume !(1 == ~M_E~0); 2189981#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2210782#L1030-3 assume !(1 == ~T2_E~0); 2210780#L1035-3 assume !(1 == ~T3_E~0); 2210778#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2210775#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2210773#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2210771#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2210769#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2210767#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2210765#L1070-3 assume !(1 == ~E_1~0); 2210761#L1075-3 assume !(1 == ~E_2~0); 2210759#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2210757#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2210755#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2210753#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2210751#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2210749#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2210747#L1110-3 assume !(1 == ~E_9~0); 2210745#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2210743#L699-1 assume !(0 == ~m_st~0); 2182378#L703-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2210711#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2210709#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2210707#L1415 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 2189767#L1238 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2189765#L443-33 assume 1 == ~m_pc~0; 2189762#L444-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2189760#L454-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2170887#L455-11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2170809#L1140-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2170806#L1140-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2170804#L462-33 assume !(1 == ~t1_pc~0); 2170802#L462-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2170799#L473-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2170797#L474-11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2170795#L1148-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2170793#L1148-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2170791#L481-33 assume !(1 == ~t2_pc~0); 2170788#L481-35 is_transmit2_triggered_~__retres1~2#1 := 0; 2170785#L492-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2170786#L493-11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2170780#L1156-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2170778#L1156-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2170776#L500-33 assume !(1 == ~t3_pc~0); 2170775#L500-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2170774#L511-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2170773#L512-11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2170772#L1164-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2170771#L1164-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2170770#L519-33 assume !(1 == ~t4_pc~0); 2169748#L519-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2170767#L530-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2170765#L531-11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2170763#L1172-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2170761#L1172-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2170759#L538-33 assume !(1 == ~t5_pc~0); 2170757#L538-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2170889#L549-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2170888#L550-11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2170748#L1180-33 assume !(0 != activate_threads_~tmp___4~0#1); 2170745#L1180-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2170743#L557-33 assume !(1 == ~t6_pc~0); 2170269#L557-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2170741#L568-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2170739#L569-11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2170737#L1188-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2170735#L1188-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2170733#L576-33 assume 1 == ~t7_pc~0; 2170731#L577-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2170726#L587-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2170723#L588-11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2170720#L1196-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2170717#L1196-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2170714#L595-33 assume !(1 == ~t8_pc~0); 2170710#L595-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2170707#L606-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2170705#L607-11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2170703#L1204-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2170701#L1204-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2170698#L614-33 assume !(1 == ~t9_pc~0); 2170696#L614-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2170693#L625-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2170691#L626-11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2170689#L1212-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2170687#L1212-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 2170684#L1245 assume 1 == ~M_E~0;~M_E~0 := 2; 2170685#L1245-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2187042#L1250-1 assume !(1 == ~T2_E~0); 2187041#L1255-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2187039#L1260-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2187037#L1265-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2187035#L1270-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2187033#L1275-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2187031#L1280-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2187024#L1285-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2187015#L1290-1 assume !(1 == ~E_1~0); 2186999#L1295-1 assume !(1 == ~E_2~0); 2186991#L1300-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2186986#L1305-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2186981#L1310-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2186975#L1315-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2186968#L1320-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2186962#L1325-1 assume 1 == ~E_8~0;~E_8~0 := 2; 2186956#L1330-1 assume !(1 == ~E_9~0); 2186948#L1335-1 assume { :end_inline_reset_time_events } true; 2170832#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2186935#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2186929#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2186923#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2186917#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2186909#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2186904#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2186898#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2146590#L1396-2 [2021-12-19 19:18:15,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:15,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 6 times [2021-12-19 19:18:15,881 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:15,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800951720] [2021-12-19 19:18:15,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:15,881 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:15,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:15,889 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:15,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:15,920 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:15,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:15,921 INFO L85 PathProgramCache]: Analyzing trace with hash -245809443, now seen corresponding path program 1 times [2021-12-19 19:18:15,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:15,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743968708] [2021-12-19 19:18:15,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:15,922 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:15,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:15,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:15,951 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:15,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743968708] [2021-12-19 19:18:15,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743968708] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:15,952 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:15,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:15,952 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327496023] [2021-12-19 19:18:15,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:15,952 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:15,952 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:15,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:15,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:15,954 INFO L87 Difference]: Start difference. First operand 87083 states and 118502 transitions. cyclomatic complexity: 31421 Second operand has 3 states, 3 states have (on average 71.0) internal successors, (213), 3 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:16,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:16,847 INFO L93 Difference]: Finished difference Result 163210 states and 220996 transitions. [2021-12-19 19:18:16,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:16,848 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163210 states and 220996 transitions. [2021-12-19 19:18:17,464 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 162960 [2021-12-19 19:18:17,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163210 states to 163210 states and 220996 transitions. [2021-12-19 19:18:17,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 163210 [2021-12-19 19:18:17,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 163210 [2021-12-19 19:18:17,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163210 states and 220996 transitions. [2021-12-19 19:18:18,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:18,043 INFO L681 BuchiCegarLoop]: Abstraction has 163210 states and 220996 transitions. [2021-12-19 19:18:18,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163210 states and 220996 transitions. [2021-12-19 19:18:19,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163210 to 163082. [2021-12-19 19:18:19,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163082 states, 163082 states have (on average 1.3543370819587692) internal successors, (220868), 163081 states have internal predecessors, (220868), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)