./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:33,348 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:33,359 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:33,401 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:33,401 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:33,404 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:33,406 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:33,411 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:33,412 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:33,417 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:33,417 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:33,418 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:33,419 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:33,420 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:33,421 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:33,423 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:33,425 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:33,426 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:33,427 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:33,431 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:33,434 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:33,435 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:33,435 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:33,436 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:33,438 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:33,439 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:33,439 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:33,440 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:33,441 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:33,441 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:33,442 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:33,442 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:33,443 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:33,444 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:33,445 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:33,445 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:33,446 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:33,446 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:33,446 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:33,447 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:33,447 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:33,448 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:33,474 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:33,476 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:33,476 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:33,476 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:33,477 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:33,477 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:33,477 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:33,477 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:33,478 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:33,478 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:33,478 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:33,479 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:33,479 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:33,480 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:33,481 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:33,481 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:33,481 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:33,481 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:33,481 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:33,481 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:33,482 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:33,482 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:33,482 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2021-12-19 19:17:33,715 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:33,728 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:33,729 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:33,730 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:33,730 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:33,731 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-12-19 19:17:33,781 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/02cee8fa6/89db03fcf215479eb5e3238b22368159/FLAG439722281 [2021-12-19 19:17:34,190 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:34,191 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-12-19 19:17:34,209 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/02cee8fa6/89db03fcf215479eb5e3238b22368159/FLAG439722281 [2021-12-19 19:17:34,595 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/02cee8fa6/89db03fcf215479eb5e3238b22368159 [2021-12-19 19:17:34,597 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:34,599 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:34,601 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:34,601 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:34,603 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:34,603 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,604 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1421c3d8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34, skipping insertion in model container [2021-12-19 19:17:34,604 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,608 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:34,630 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:34,748 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-12-19 19:17:34,828 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:34,835 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:34,842 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-12-19 19:17:34,879 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:34,893 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:34,893 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34 WrapperNode [2021-12-19 19:17:34,893 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:34,894 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:34,894 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:34,894 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:34,899 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,907 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,964 INFO L137 Inliner]: procedures = 50, calls = 63, calls flagged for inlining = 58, calls inlined = 224, statements flattened = 3437 [2021-12-19 19:17:34,965 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:34,965 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:34,965 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:34,965 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:34,971 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,971 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,992 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,993 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,015 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,042 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,046 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,054 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:35,054 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:35,054 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:35,054 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:35,061 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,066 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:35,073 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:35,082 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:35,087 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:35,107 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:35,107 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:35,107 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:35,107 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:35,221 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:35,222 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:36,582 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:36,598 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:36,598 INFO L301 CfgBuilder]: Removed 15 assume(true) statements. [2021-12-19 19:17:36,601 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:36 BoogieIcfgContainer [2021-12-19 19:17:36,601 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:36,602 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:36,602 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:36,604 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:36,604 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,605 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:34" (1/3) ... [2021-12-19 19:17:36,606 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@539cb2e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:36, skipping insertion in model container [2021-12-19 19:17:36,606 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,606 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (2/3) ... [2021-12-19 19:17:36,606 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@539cb2e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:36, skipping insertion in model container [2021-12-19 19:17:36,606 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,606 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:36" (3/3) ... [2021-12-19 19:17:36,607 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2021-12-19 19:17:36,645 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:36,646 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:36,646 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:36,646 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:36,646 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:36,646 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:36,646 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:36,646 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:36,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-12-19 19:17:36,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,809 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,811 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,811 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:36,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,825 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1330 [2021-12-19 19:17:36,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,836 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,836 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,847 INFO L791 eck$LassoCheckResult]: Stem: 715#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1355#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 725#L1607true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1298#L754true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 511#L761true assume !(1 == ~m_i~0);~m_st~0 := 2; 527#L761-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 424#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 366#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 204#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 44#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 646#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 612#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 655#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1335#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 262#L816-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1145#L1090true assume !(0 == ~M_E~0); 288#L1090-2true assume !(0 == ~T1_E~0); 1306#L1095-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 785#L1100-1true assume !(0 == ~T3_E~0); 811#L1105-1true assume !(0 == ~T4_E~0); 157#L1110-1true assume !(0 == ~T5_E~0); 386#L1115-1true assume !(0 == ~T6_E~0); 595#L1120-1true assume !(0 == ~T7_E~0); 1343#L1125-1true assume !(0 == ~T8_E~0); 1336#L1130-1true assume !(0 == ~T9_E~0); 809#L1135-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 265#L1140-1true assume !(0 == ~T11_E~0); 739#L1145-1true assume !(0 == ~E_1~0); 781#L1150-1true assume !(0 == ~E_2~0); 374#L1155-1true assume !(0 == ~E_3~0); 1315#L1160-1true assume !(0 == ~E_4~0); 430#L1165-1true assume !(0 == ~E_5~0); 1070#L1170-1true assume !(0 == ~E_6~0); 1255#L1175-1true assume 0 == ~E_7~0;~E_7~0 := 1; 480#L1180-1true assume !(0 == ~E_8~0); 895#L1185-1true assume !(0 == ~E_9~0); 263#L1190-1true assume !(0 == ~E_10~0); 490#L1195-1true assume !(0 == ~E_11~0); 1013#L1200-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381#L525true assume !(1 == ~m_pc~0); 62#L525-2true is_master_triggered_~__retres1~0#1 := 0; 1009#L536true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 492#L537true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 874#L1350true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 254#L1350-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 531#L544true assume 1 == ~t1_pc~0; 412#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 736#L555true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1466#L556true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 168#L1358true assume !(0 != activate_threads_~tmp___0~0#1); 574#L1358-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1004#L563true assume !(1 == ~t2_pc~0); 726#L563-2true is_transmit2_triggered_~__retres1~2#1 := 0; 73#L574true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#L575true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 304#L1366true assume !(0 != activate_threads_~tmp___1~0#1); 634#L1366-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 737#L582true assume 1 == ~t3_pc~0; 141#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1214#L593true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1427#L594true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1082#L1374true assume !(0 != activate_threads_~tmp___2~0#1); 108#L1374-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1378#L601true assume !(1 == ~t4_pc~0); 829#L601-2true is_transmit4_triggered_~__retres1~4#1 := 0; 387#L612true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 791#L613true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 748#L1382true assume !(0 != activate_threads_~tmp___3~0#1); 1387#L1382-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1186#L620true assume 1 == ~t5_pc~0; 87#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 652#L631true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 592#L632true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1460#L1390true assume !(0 != activate_threads_~tmp___4~0#1); 1244#L1390-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1348#L639true assume !(1 == ~t6_pc~0); 593#L639-2true is_transmit6_triggered_~__retres1~6#1 := 0; 325#L650true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1086#L651true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1239#L1398true assume !(0 != activate_threads_~tmp___5~0#1); 391#L1398-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 940#L658true assume 1 == ~t7_pc~0; 594#L659true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1262#L669true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 621#L670true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 687#L1406true assume !(0 != activate_threads_~tmp___6~0#1); 259#L1406-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 394#L677true assume 1 == ~t8_pc~0; 864#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 148#L688true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1034#L689true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 302#L1414true assume !(0 != activate_threads_~tmp___7~0#1); 865#L1414-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 972#L696true assume !(1 == ~t9_pc~0); 582#L696-2true is_transmit9_triggered_~__retres1~9#1 := 0; 662#L707true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 755#L708true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 598#L1422true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 789#L1422-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1123#L715true assume 1 == ~t10_pc~0; 797#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 677#L726true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 576#L727true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 766#L1430true assume !(0 != activate_threads_~tmp___9~0#1); 475#L1430-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 145#L734true assume !(1 == ~t11_pc~0); 432#L734-2true is_transmit11_triggered_~__retres1~11#1 := 0; 483#L745true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 496#L746true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15#L1438true assume !(0 != activate_threads_~tmp___10~0#1); 653#L1438-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182#L1213true assume !(1 == ~M_E~0); 473#L1213-2true assume !(1 == ~T1_E~0); 958#L1218-1true assume !(1 == ~T2_E~0); 33#L1223-1true assume !(1 == ~T3_E~0); 458#L1228-1true assume !(1 == ~T4_E~0); 1245#L1233-1true assume !(1 == ~T5_E~0); 1440#L1238-1true assume !(1 == ~T6_E~0); 747#L1243-1true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1393#L1248-1true assume !(1 == ~T8_E~0); 795#L1253-1true assume !(1 == ~T9_E~0); 1087#L1258-1true assume !(1 == ~T10_E~0); 773#L1263-1true assume !(1 == ~T11_E~0); 1129#L1268-1true assume !(1 == ~E_1~0); 611#L1273-1true assume !(1 == ~E_2~0); 1225#L1278-1true assume !(1 == ~E_3~0); 324#L1283-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1276#L1288-1true assume !(1 == ~E_5~0); 916#L1293-1true assume !(1 == ~E_6~0); 870#L1298-1true assume !(1 == ~E_7~0); 637#L1303-1true assume !(1 == ~E_8~0); 331#L1308-1true assume !(1 == ~E_9~0); 268#L1313-1true assume !(1 == ~E_10~0); 1361#L1318-1true assume !(1 == ~E_11~0); 274#L1323-1true assume { :end_inline_reset_delta_events } true; 1135#L1644-2true [2021-12-19 19:17:36,857 INFO L793 eck$LassoCheckResult]: Loop: 1135#L1644-2true assume !false; 685#L1645true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 765#L1065true assume !true; 867#L1080true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 762#L754-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 946#L1090-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1025#L1090-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1364#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 975#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1237#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 201#L1110-3true assume !(0 == ~T5_E~0); 1075#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 367#L1120-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 744#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1115#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1273#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 318#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 49#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 498#L1150-3true assume !(0 == ~E_2~0); 109#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1421#L1160-3true assume 0 == ~E_4~0;~E_4~0 := 1; 308#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1480#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 567#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 256#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 124#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1278#L1190-3true assume !(0 == ~E_10~0); 1095#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1478#L1200-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 447#L525-36true assume !(1 == ~m_pc~0); 1132#L525-38true is_master_triggered_~__retres1~0#1 := 0; 174#L536-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1351#L537-12true activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 339#L1350-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 566#L1350-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L544-36true assume 1 == ~t1_pc~0; 792#L545-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 667#L555-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221#L556-12true activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1257#L1358-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1066#L1358-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 906#L563-36true assume 1 == ~t2_pc~0; 167#L564-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47#L574-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752#L575-12true activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1254#L1366-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 457#L1366-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1363#L582-36true assume 1 == ~t3_pc~0; 361#L583-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 510#L593-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1366#L594-12true activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 660#L1374-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 482#L1374-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 444#L601-36true assume 1 == ~t4_pc~0; 378#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1456#L612-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1265#L613-12true activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1035#L1382-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1177#L1382-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 891#L620-36true assume !(1 == ~t5_pc~0); 1453#L620-38true is_transmit5_triggered_~__retres1~5#1 := 0; 729#L631-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 953#L632-12true activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393#L1390-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180#L1390-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70#L639-36true assume 1 == ~t6_pc~0; 717#L640-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 89#L650-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1005#L651-12true activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 212#L1398-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 597#L1398-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1176#L658-36true assume !(1 == ~t7_pc~0); 75#L658-38true is_transmit7_triggered_~__retres1~7#1 := 0; 1006#L669-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1046#L670-12true activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64#L1406-36true assume !(0 != activate_threads_~tmp___6~0#1); 712#L1406-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 927#L677-36true assume !(1 == ~t8_pc~0); 534#L677-38true is_transmit8_triggered_~__retres1~8#1 := 0; 635#L688-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1187#L689-12true activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1174#L1414-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 555#L1414-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1092#L696-36true assume 1 == ~t9_pc~0; 471#L697-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 827#L707-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 98#L708-12true activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1007#L1422-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 568#L1422-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1251#L715-36true assume !(1 == ~t10_pc~0); 543#L715-38true is_transmit10_triggered_~__retres1~10#1 := 0; 16#L726-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 127#L727-12true activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4#L1430-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1052#L1430-38true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 206#L734-36true assume 1 == ~t11_pc~0; 799#L735-12true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 216#L745-12true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 460#L746-12true activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12#L1438-36true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 616#L1438-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1098#L1213-3true assume 1 == ~M_E~0;~M_E~0 := 2; 372#L1213-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 710#L1218-3true assume !(1 == ~T2_E~0); 233#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 753#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 345#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1263#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 508#L1243-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1033#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1400#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1042#L1258-3true assume !(1 == ~T10_E~0); 222#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 989#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1012#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1454#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1015#L1283-3true assume 1 == ~E_4~0;~E_4~0 := 2; 428#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1285#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 338#L1298-3true assume !(1 == ~E_7~0); 1136#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 683#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 336#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1037#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 223#L1323-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1428#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 440#L891-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 836#L892-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1429#L1663true assume !(0 == start_simulation_~tmp~3#1); 1329#L1663-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 596#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 526#L891-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 703#L892-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 80#L1618true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 261#L1625true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1299#L1626true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1164#L1676true assume !(0 != start_simulation_~tmp___0~1#1); 1135#L1644-2true [2021-12-19 19:17:36,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,862 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 1 times [2021-12-19 19:17:36,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56237126] [2021-12-19 19:17:36,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:36,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,075 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56237126] [2021-12-19 19:17:37,075 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56237126] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,075 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,075 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,077 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799597462] [2021-12-19 19:17:37,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,080 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,080 INFO L85 PathProgramCache]: Analyzing trace with hash 862291405, now seen corresponding path program 1 times [2021-12-19 19:17:37,080 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,081 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315572435] [2021-12-19 19:17:37,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,120 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315572435] [2021-12-19 19:17:37,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315572435] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,120 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,120 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:37,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470645398] [2021-12-19 19:17:37,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,122 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,122 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-19 19:17:37,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-19 19:17:37,146 INFO L87 Difference]: Start difference. First operand has 1483 states, 1482 states have (on average 1.5053981106612686) internal successors, (2231), 1482 states have internal predecessors, (2231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 68.5) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,255 INFO L93 Difference]: Finished difference Result 1482 states and 2199 transitions. [2021-12-19 19:17:37,256 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-19 19:17:37,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1482 states and 2199 transitions. [2021-12-19 19:17:37,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1482 states to 1476 states and 2193 transitions. [2021-12-19 19:17:37,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:37,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:37,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2193 transitions. [2021-12-19 19:17:37,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,313 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-12-19 19:17:37,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2193 transitions. [2021-12-19 19:17:37,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:37,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4857723577235773) internal successors, (2193), 1475 states have internal predecessors, (2193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2193 transitions. [2021-12-19 19:17:37,420 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-12-19 19:17:37,420 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2193 transitions. [2021-12-19 19:17:37,420 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:37,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2193 transitions. [2021-12-19 19:17:37,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,428 INFO L791 eck$LassoCheckResult]: Stem: 4096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4106#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4107#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3872#L761 assume !(1 == ~m_i~0);~m_st~0 := 2; 3873#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3742#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3654#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3377#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3012#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3013#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3061#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3062#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3990#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3991#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4029#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3477#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3478#L1090 assume !(0 == ~M_E~0); 3523#L1090-2 assume !(0 == ~T1_E~0); 3524#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4167#L1100-1 assume !(0 == ~T3_E~0); 4168#L1105-1 assume !(0 == ~T4_E~0); 3296#L1110-1 assume !(0 == ~T5_E~0); 3297#L1115-1 assume !(0 == ~T6_E~0); 3692#L1120-1 assume !(0 == ~T7_E~0); 3969#L1125-1 assume !(0 == ~T8_E~0); 4438#L1130-1 assume !(0 == ~T9_E~0); 4187#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3482#L1140-1 assume !(0 == ~T11_E~0); 3483#L1145-1 assume !(0 == ~E_1~0); 4121#L1150-1 assume !(0 == ~E_2~0); 3667#L1155-1 assume !(0 == ~E_3~0); 3668#L1160-1 assume !(0 == ~E_4~0); 3750#L1165-1 assume !(0 == ~E_5~0); 3751#L1170-1 assume !(0 == ~E_6~0); 4359#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3828#L1180-1 assume !(0 == ~E_8~0); 3829#L1185-1 assume !(0 == ~E_9~0); 3479#L1190-1 assume !(0 == ~E_10~0); 3480#L1195-1 assume !(0 == ~E_11~0); 3842#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3689#L525 assume !(1 == ~m_pc~0); 3100#L525-2 is_master_triggered_~__retres1~0#1 := 0; 3101#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3846#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3847#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3466#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3467#L544 assume 1 == ~t1_pc~0; 3727#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3691#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4119#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3317#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 3318#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3940#L563 assume !(1 == ~t2_pc~0); 4108#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3121#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3122#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3553#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 3554#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4013#L582 assume 1 == ~t3_pc~0; 3261#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3262#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4410#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4368#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 3195#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3196#L601 assume !(1 == ~t4_pc~0); 4136#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3693#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3694#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4130#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 4131#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4402#L620 assume 1 == ~t5_pc~0; 3154#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3155#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3965#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3966#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 4417#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4418#L639 assume !(1 == ~t6_pc~0); 3967#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3590#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3591#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4371#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 3701#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3702#L658 assume 1 == ~t7_pc~0; 3968#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3895#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4000#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4001#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 3473#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3474#L677 assume 1 == ~t8_pc~0; 3706#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3276#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3277#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3547#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 3548#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4226#L696 assume !(1 == ~t9_pc~0); 3953#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3954#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4044#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3973#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3974#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4171#L715 assume 1 == ~t10_pc~0; 4175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4058#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3943#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3944#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 3820#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3270#L734 assume !(1 == ~t11_pc~0); 3271#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3754#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3833#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3002#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 3003#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4028#L1213 assume !(1 == ~M_E~0); 3818#L1213-2 assume !(1 == ~T1_E~0); 3819#L1218-1 assume !(1 == ~T2_E~0); 3037#L1223-1 assume !(1 == ~T3_E~0); 3038#L1228-1 assume !(1 == ~T4_E~0); 3797#L1233-1 assume !(1 == ~T5_E~0); 4419#L1238-1 assume !(1 == ~T6_E~0); 4128#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4129#L1248-1 assume !(1 == ~T8_E~0); 4173#L1253-1 assume !(1 == ~T9_E~0); 4174#L1258-1 assume !(1 == ~T10_E~0); 4152#L1263-1 assume !(1 == ~T11_E~0); 4153#L1268-1 assume !(1 == ~E_1~0); 3988#L1273-1 assume !(1 == ~E_2~0); 3989#L1278-1 assume !(1 == ~E_3~0); 3588#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3589#L1288-1 assume !(1 == ~E_5~0); 4266#L1293-1 assume !(1 == ~E_6~0); 4230#L1298-1 assume !(1 == ~E_7~0); 4016#L1303-1 assume !(1 == ~E_8~0); 3599#L1308-1 assume !(1 == ~E_9~0); 3488#L1313-1 assume !(1 == ~E_10~0); 3489#L1318-1 assume !(1 == ~E_11~0); 3501#L1323-1 assume { :end_inline_reset_delta_events } true; 3502#L1644-2 [2021-12-19 19:17:37,429 INFO L793 eck$LassoCheckResult]: Loop: 3502#L1644-2 assume !false; 4069#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4070#L1065 assume !false; 4145#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4415#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3119#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4331#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3604#L906 assume !(0 != eval_~tmp~0#1); 3606#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4143#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4144#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4283#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4335#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4298#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4299#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3372#L1110-3 assume !(0 == ~T5_E~0); 3373#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3655#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3656#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4126#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4380#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3580#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3075#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3076#L1150-3 assume !(0 == ~E_2~0); 3198#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3199#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3559#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3560#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3932#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3469#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3230#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3231#L1190-3 assume !(0 == ~E_10~0); 4374#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4375#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3782#L525-36 assume !(1 == ~m_pc~0); 3783#L525-38 is_master_triggered_~__retres1~0#1 := 0; 3333#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3334#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3614#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3615#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3520#L544-36 assume 1 == ~t1_pc~0; 3521#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4047#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3412#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3413#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4356#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4259#L563-36 assume 1 == ~t2_pc~0; 3315#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3071#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3072#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4134#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3795#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3796#L582-36 assume !(1 == ~t3_pc~0); 3648#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 3647#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3871#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4038#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3832#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3776#L601-36 assume 1 == ~t4_pc~0; 3675#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3676#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4423#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4341#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4342#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4247#L620-36 assume 1 == ~t5_pc~0; 3715#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3716#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4109#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3703#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3337#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3115#L639-36 assume 1 == ~t6_pc~0; 3116#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3152#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3153#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3393#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3394#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3972#L658-36 assume 1 == ~t7_pc~0; 3232#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3127#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4326#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3102#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 3103#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4093#L677-36 assume !(1 == ~t8_pc~0); 3897#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 3898#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4014#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4398#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3920#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3921#L696-36 assume 1 == ~t9_pc~0; 3814#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3816#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3175#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3176#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3933#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3934#L715-36 assume !(1 == ~t10_pc~0); 3904#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3000#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3001#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2976#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2977#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3381#L734-36 assume 1 == ~t11_pc~0; 3382#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3081#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3403#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2994#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2995#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3994#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3661#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3662#L1218-3 assume !(1 == ~T2_E~0); 3432#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3433#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3622#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3623#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3867#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3868#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4339#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4344#L1258-3 assume !(1 == ~T10_E~0); 3414#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3415#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4310#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4328#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4330#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3746#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3747#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3612#L1298-3 assume !(1 == ~E_7~0); 3613#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4068#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3609#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3610#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3416#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3417#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3356#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3767#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 4206#L1663 assume !(0 == start_simulation_~tmp~3#1); 3249#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3970#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3193#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3889#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3137#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3138#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3476#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4395#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 3502#L1644-2 [2021-12-19 19:17:37,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,430 INFO L85 PathProgramCache]: Analyzing trace with hash -92888918, now seen corresponding path program 2 times [2021-12-19 19:17:37,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,435 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513567093] [2021-12-19 19:17:37,435 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,435 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513567093] [2021-12-19 19:17:37,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513567093] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,494 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,494 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,494 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [463422616] [2021-12-19 19:17:37,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,495 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,495 INFO L85 PathProgramCache]: Analyzing trace with hash -852141939, now seen corresponding path program 1 times [2021-12-19 19:17:37,495 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535973660] [2021-12-19 19:17:37,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535973660] [2021-12-19 19:17:37,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535973660] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,591 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,591 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469473302] [2021-12-19 19:17:37,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,592 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,592 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:37,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:37,593 INFO L87 Difference]: Start difference. First operand 1476 states and 2193 transitions. cyclomatic complexity: 718 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,656 INFO L93 Difference]: Finished difference Result 1476 states and 2192 transitions. [2021-12-19 19:17:37,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:37,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2192 transitions. [2021-12-19 19:17:37,663 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-12-19 19:17:37,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:37,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:37,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2192 transitions. [2021-12-19 19:17:37,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,673 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-12-19 19:17:37,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2192 transitions. [2021-12-19 19:17:37,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:37,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4850948509485096) internal successors, (2192), 1475 states have internal predecessors, (2192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2192 transitions. [2021-12-19 19:17:37,714 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-12-19 19:17:37,714 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2192 transitions. [2021-12-19 19:17:37,715 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:37,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2192 transitions. [2021-12-19 19:17:37,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,724 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,724 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,727 INFO L791 eck$LassoCheckResult]: Stem: 7055#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 7056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7063#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7064#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6831#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 6832#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6701#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6613#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6336#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5971#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5972#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6020#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6021#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6949#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6950#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6988#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6436#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6437#L1090 assume !(0 == ~M_E~0); 6479#L1090-2 assume !(0 == ~T1_E~0); 6480#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7125#L1100-1 assume !(0 == ~T3_E~0); 7126#L1105-1 assume !(0 == ~T4_E~0); 6254#L1110-1 assume !(0 == ~T5_E~0); 6255#L1115-1 assume !(0 == ~T6_E~0); 6651#L1120-1 assume !(0 == ~T7_E~0); 6928#L1125-1 assume !(0 == ~T8_E~0); 7397#L1130-1 assume !(0 == ~T9_E~0); 7146#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6441#L1140-1 assume !(0 == ~T11_E~0); 6442#L1145-1 assume !(0 == ~E_1~0); 7080#L1150-1 assume !(0 == ~E_2~0); 6626#L1155-1 assume !(0 == ~E_3~0); 6627#L1160-1 assume !(0 == ~E_4~0); 6709#L1165-1 assume !(0 == ~E_5~0); 6710#L1170-1 assume !(0 == ~E_6~0); 7318#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6787#L1180-1 assume !(0 == ~E_8~0); 6788#L1185-1 assume !(0 == ~E_9~0); 6438#L1190-1 assume !(0 == ~E_10~0); 6439#L1195-1 assume !(0 == ~E_11~0); 6801#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6641#L525 assume !(1 == ~m_pc~0); 6059#L525-2 is_master_triggered_~__retres1~0#1 := 0; 6060#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6805#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6806#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6425#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6426#L544 assume 1 == ~t1_pc~0; 6686#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6650#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7078#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6276#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 6277#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6899#L563 assume !(1 == ~t2_pc~0); 7065#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6080#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6081#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6509#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 6510#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6972#L582 assume 1 == ~t3_pc~0; 6218#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6219#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7369#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7327#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 6154#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6155#L601 assume !(1 == ~t4_pc~0); 7095#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6652#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6653#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7089#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 7090#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7361#L620 assume 1 == ~t5_pc~0; 6109#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6110#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6924#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6925#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 7376#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7377#L639 assume !(1 == ~t6_pc~0); 6926#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6549#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6550#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7330#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 6660#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6661#L658 assume 1 == ~t7_pc~0; 6927#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6852#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6959#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6960#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 6432#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6433#L677 assume 1 == ~t8_pc~0; 6663#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6235#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6236#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6506#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 6507#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7185#L696 assume !(1 == ~t9_pc~0); 6910#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6911#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7000#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6932#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6933#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7130#L715 assume 1 == ~t10_pc~0; 7134#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7017#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6902#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6903#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 6779#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6227#L734 assume !(1 == ~t11_pc~0); 6228#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 6713#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6792#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5959#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 5960#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6987#L1213 assume !(1 == ~M_E~0); 6776#L1213-2 assume !(1 == ~T1_E~0); 6777#L1218-1 assume !(1 == ~T2_E~0); 5996#L1223-1 assume !(1 == ~T3_E~0); 5997#L1228-1 assume !(1 == ~T4_E~0); 6756#L1233-1 assume !(1 == ~T5_E~0); 7378#L1238-1 assume !(1 == ~T6_E~0); 7087#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7088#L1248-1 assume !(1 == ~T8_E~0); 7132#L1253-1 assume !(1 == ~T9_E~0); 7133#L1258-1 assume !(1 == ~T10_E~0); 7111#L1263-1 assume !(1 == ~T11_E~0); 7112#L1268-1 assume !(1 == ~E_1~0); 6947#L1273-1 assume !(1 == ~E_2~0); 6948#L1278-1 assume !(1 == ~E_3~0); 6547#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6548#L1288-1 assume !(1 == ~E_5~0); 7225#L1293-1 assume !(1 == ~E_6~0); 7189#L1298-1 assume !(1 == ~E_7~0); 6975#L1303-1 assume !(1 == ~E_8~0); 6558#L1308-1 assume !(1 == ~E_9~0); 6447#L1313-1 assume !(1 == ~E_10~0); 6448#L1318-1 assume !(1 == ~E_11~0); 6457#L1323-1 assume { :end_inline_reset_delta_events } true; 6458#L1644-2 [2021-12-19 19:17:37,728 INFO L793 eck$LassoCheckResult]: Loop: 6458#L1644-2 assume !false; 7028#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7029#L1065 assume !false; 7104#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7374#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6078#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7290#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6563#L906 assume !(0 != eval_~tmp~0#1); 6565#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7101#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7102#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7242#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7294#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7257#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7258#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6331#L1110-3 assume !(0 == ~T5_E~0); 6332#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6614#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6615#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7085#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7339#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6537#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 6032#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6033#L1150-3 assume !(0 == ~E_2~0); 6156#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6157#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6518#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6519#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6891#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6428#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6186#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6187#L1190-3 assume !(0 == ~E_10~0); 7333#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7334#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6741#L525-36 assume !(1 == ~m_pc~0); 6742#L525-38 is_master_triggered_~__retres1~0#1 := 0; 6287#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6288#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6573#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6574#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6482#L544-36 assume 1 == ~t1_pc~0; 6483#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7006#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6371#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6372#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7315#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7218#L563-36 assume 1 == ~t2_pc~0; 6274#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6030#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6031#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7093#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6754#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6755#L582-36 assume 1 == ~t3_pc~0; 6605#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6606#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6997#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6791#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6735#L601-36 assume 1 == ~t4_pc~0; 6634#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6635#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7382#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7300#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7301#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7206#L620-36 assume 1 == ~t5_pc~0; 6676#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6677#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7068#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6662#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6296#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6074#L639-36 assume 1 == ~t6_pc~0; 6075#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6114#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6115#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6354#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6355#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6931#L658-36 assume 1 == ~t7_pc~0; 6193#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6086#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7285#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6061#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 6062#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7052#L677-36 assume !(1 == ~t8_pc~0); 6856#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 6857#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6973#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7357#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6879#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6880#L696-36 assume 1 == ~t9_pc~0; 6773#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6775#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6134#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6135#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6892#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6893#L715-36 assume 1 == ~t10_pc~0; 7026#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5961#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5962#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5935#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5936#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6340#L734-36 assume 1 == ~t11_pc~0; 6341#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6040#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6362#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5953#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5954#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6953#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6622#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6623#L1218-3 assume !(1 == ~T2_E~0); 6391#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6392#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6581#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6582#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6826#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6827#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7299#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7304#L1258-3 assume !(1 == ~T10_E~0); 6373#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6374#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7269#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7287#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7289#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6705#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6706#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6571#L1298-3 assume !(1 == ~E_7~0); 6572#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7027#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6568#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6569#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6375#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6376#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6315#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6726#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 7165#L1663 assume !(0 == start_simulation_~tmp~3#1); 6208#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6929#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6152#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6850#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6096#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6097#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6435#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7354#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 6458#L1644-2 [2021-12-19 19:17:37,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,731 INFO L85 PathProgramCache]: Analyzing trace with hash -456355416, now seen corresponding path program 1 times [2021-12-19 19:17:37,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81516284] [2021-12-19 19:17:37,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,767 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,768 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81516284] [2021-12-19 19:17:37,768 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81516284] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,768 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,768 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,769 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529262224] [2021-12-19 19:17:37,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,769 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,770 INFO L85 PathProgramCache]: Analyzing trace with hash 2047437327, now seen corresponding path program 1 times [2021-12-19 19:17:37,770 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441286995] [2021-12-19 19:17:37,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,771 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [441286995] [2021-12-19 19:17:37,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [441286995] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,825 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302812350] [2021-12-19 19:17:37,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,826 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:37,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:37,827 INFO L87 Difference]: Start difference. First operand 1476 states and 2192 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,846 INFO L93 Difference]: Finished difference Result 1476 states and 2191 transitions. [2021-12-19 19:17:37,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:37,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2191 transitions. [2021-12-19 19:17:37,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-12-19 19:17:37,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:37,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:37,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2191 transitions. [2021-12-19 19:17:37,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,860 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-12-19 19:17:37,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2191 transitions. [2021-12-19 19:17:37,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:37,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4844173441734418) internal successors, (2191), 1475 states have internal predecessors, (2191), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2191 transitions. [2021-12-19 19:17:37,876 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-12-19 19:17:37,876 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2191 transitions. [2021-12-19 19:17:37,876 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:37,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2191 transitions. [2021-12-19 19:17:37,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:37,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,882 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,882 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,882 INFO L791 eck$LassoCheckResult]: Stem: 10014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 10015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10024#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10025#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9790#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 9791#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9660#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9572#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9295#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8930#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8931#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8979#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8980#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9908#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9909#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9947#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9395#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9396#L1090 assume !(0 == ~M_E~0); 9438#L1090-2 assume !(0 == ~T1_E~0); 9439#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10085#L1100-1 assume !(0 == ~T3_E~0); 10086#L1105-1 assume !(0 == ~T4_E~0); 9214#L1110-1 assume !(0 == ~T5_E~0); 9215#L1115-1 assume !(0 == ~T6_E~0); 9610#L1120-1 assume !(0 == ~T7_E~0); 9887#L1125-1 assume !(0 == ~T8_E~0); 10356#L1130-1 assume !(0 == ~T9_E~0); 10105#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9400#L1140-1 assume !(0 == ~T11_E~0); 9401#L1145-1 assume !(0 == ~E_1~0); 10039#L1150-1 assume !(0 == ~E_2~0); 9585#L1155-1 assume !(0 == ~E_3~0); 9586#L1160-1 assume !(0 == ~E_4~0); 9668#L1165-1 assume !(0 == ~E_5~0); 9669#L1170-1 assume !(0 == ~E_6~0); 10277#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9746#L1180-1 assume !(0 == ~E_8~0); 9747#L1185-1 assume !(0 == ~E_9~0); 9397#L1190-1 assume !(0 == ~E_10~0); 9398#L1195-1 assume !(0 == ~E_11~0); 9760#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9607#L525 assume !(1 == ~m_pc~0); 9018#L525-2 is_master_triggered_~__retres1~0#1 := 0; 9019#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9764#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9765#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9384#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9385#L544 assume 1 == ~t1_pc~0; 9645#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10037#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9235#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 9236#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9858#L563 assume !(1 == ~t2_pc~0); 10026#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9039#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9040#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9468#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 9469#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9931#L582 assume 1 == ~t3_pc~0; 9179#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9180#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10328#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10286#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 9113#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9114#L601 assume !(1 == ~t4_pc~0); 10054#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9611#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9612#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10048#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 10049#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10320#L620 assume 1 == ~t5_pc~0; 9070#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9071#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9883#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9884#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 10335#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10336#L639 assume !(1 == ~t6_pc~0); 9885#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9508#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9509#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10289#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 9619#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9620#L658 assume 1 == ~t7_pc~0; 9886#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9813#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9918#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9919#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 9391#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9392#L677 assume 1 == ~t8_pc~0; 9624#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9194#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9195#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9465#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 9466#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10144#L696 assume !(1 == ~t9_pc~0); 9871#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9872#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9959#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9891#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9892#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10089#L715 assume 1 == ~t10_pc~0; 10093#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9976#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9861#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9862#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 9738#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9188#L734 assume !(1 == ~t11_pc~0); 9189#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9672#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9751#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8920#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 8921#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9946#L1213 assume !(1 == ~M_E~0); 9736#L1213-2 assume !(1 == ~T1_E~0); 9737#L1218-1 assume !(1 == ~T2_E~0); 8955#L1223-1 assume !(1 == ~T3_E~0); 8956#L1228-1 assume !(1 == ~T4_E~0); 9715#L1233-1 assume !(1 == ~T5_E~0); 10337#L1238-1 assume !(1 == ~T6_E~0); 10046#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10047#L1248-1 assume !(1 == ~T8_E~0); 10091#L1253-1 assume !(1 == ~T9_E~0); 10092#L1258-1 assume !(1 == ~T10_E~0); 10070#L1263-1 assume !(1 == ~T11_E~0); 10071#L1268-1 assume !(1 == ~E_1~0); 9906#L1273-1 assume !(1 == ~E_2~0); 9907#L1278-1 assume !(1 == ~E_3~0); 9506#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9507#L1288-1 assume !(1 == ~E_5~0); 10184#L1293-1 assume !(1 == ~E_6~0); 10148#L1298-1 assume !(1 == ~E_7~0); 9934#L1303-1 assume !(1 == ~E_8~0); 9517#L1308-1 assume !(1 == ~E_9~0); 9406#L1313-1 assume !(1 == ~E_10~0); 9407#L1318-1 assume !(1 == ~E_11~0); 9419#L1323-1 assume { :end_inline_reset_delta_events } true; 9420#L1644-2 [2021-12-19 19:17:37,883 INFO L793 eck$LassoCheckResult]: Loop: 9420#L1644-2 assume !false; 9987#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9988#L1065 assume !false; 10063#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10333#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9037#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10249#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9522#L906 assume !(0 != eval_~tmp~0#1); 9524#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10061#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10062#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10201#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10253#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10216#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10217#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9290#L1110-3 assume !(0 == ~T5_E~0); 9291#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9573#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9574#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10044#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10298#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9498#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8993#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8994#L1150-3 assume !(0 == ~E_2~0); 9116#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9117#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9477#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9850#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9146#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9147#L1190-3 assume !(0 == ~E_10~0); 10292#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10293#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9700#L525-36 assume !(1 == ~m_pc~0); 9701#L525-38 is_master_triggered_~__retres1~0#1 := 0; 9251#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9252#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9533#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9534#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9441#L544-36 assume 1 == ~t1_pc~0; 9442#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9965#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9336#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9337#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10275#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10177#L563-36 assume 1 == ~t2_pc~0; 9233#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8989#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8990#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10052#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9713#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9714#L582-36 assume 1 == ~t3_pc~0; 9564#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9565#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9789#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9956#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9750#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9691#L601-36 assume 1 == ~t4_pc~0; 9593#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9594#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10341#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10259#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10260#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10163#L620-36 assume 1 == ~t5_pc~0; 9633#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9634#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10027#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9621#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9255#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9033#L639-36 assume 1 == ~t6_pc~0; 9034#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9068#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9069#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9311#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9312#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9890#L658-36 assume !(1 == ~t7_pc~0); 9044#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 9045#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10244#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9020#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 9021#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10011#L677-36 assume !(1 == ~t8_pc~0); 9815#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 9816#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9932#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10316#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9838#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9839#L696-36 assume 1 == ~t9_pc~0; 9732#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9734#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9090#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9091#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9851#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9852#L715-36 assume 1 == ~t10_pc~0; 9985#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8918#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8919#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8894#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8895#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9299#L734-36 assume 1 == ~t11_pc~0; 9300#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8999#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9321#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8912#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8913#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9912#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9579#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9580#L1218-3 assume !(1 == ~T2_E~0); 9350#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9351#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9540#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9541#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9785#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9786#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10257#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10262#L1258-3 assume !(1 == ~T10_E~0); 9330#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9331#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10228#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10246#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10248#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9664#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9665#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9530#L1298-3 assume !(1 == ~E_7~0); 9531#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9986#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9527#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9528#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9332#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9333#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9274#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9685#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 10124#L1663 assume !(0 == start_simulation_~tmp~3#1); 9162#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9888#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9111#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9807#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9052#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9053#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9394#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 10313#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 9420#L1644-2 [2021-12-19 19:17:37,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,885 INFO L85 PathProgramCache]: Analyzing trace with hash 88517158, now seen corresponding path program 1 times [2021-12-19 19:17:37,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,886 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604840347] [2021-12-19 19:17:37,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,886 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,941 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1604840347] [2021-12-19 19:17:37,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1604840347] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,942 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,942 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,943 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708771168] [2021-12-19 19:17:37,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,944 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,945 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 1 times [2021-12-19 19:17:37,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974303170] [2021-12-19 19:17:37,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,999 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,999 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974303170] [2021-12-19 19:17:38,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974303170] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,000 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,000 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,000 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [248691678] [2021-12-19 19:17:38,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,001 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,001 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,003 INFO L87 Difference]: Start difference. First operand 1476 states and 2191 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,046 INFO L93 Difference]: Finished difference Result 1476 states and 2190 transitions. [2021-12-19 19:17:38,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2190 transitions. [2021-12-19 19:17:38,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-12-19 19:17:38,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2190 transitions. [2021-12-19 19:17:38,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,060 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-12-19 19:17:38,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2190 transitions. [2021-12-19 19:17:38,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.483739837398374) internal successors, (2190), 1475 states have internal predecessors, (2190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2190 transitions. [2021-12-19 19:17:38,075 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-12-19 19:17:38,075 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2190 transitions. [2021-12-19 19:17:38,075 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:38,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2190 transitions. [2021-12-19 19:17:38,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,081 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,082 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,082 INFO L791 eck$LassoCheckResult]: Stem: 12973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12974#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 12981#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12982#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12749#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 12750#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12619#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12531#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12254#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11889#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11890#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11938#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11939#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12867#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12868#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12906#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12354#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12355#L1090 assume !(0 == ~M_E~0); 12397#L1090-2 assume !(0 == ~T1_E~0); 12398#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13043#L1100-1 assume !(0 == ~T3_E~0); 13044#L1105-1 assume !(0 == ~T4_E~0); 12172#L1110-1 assume !(0 == ~T5_E~0); 12173#L1115-1 assume !(0 == ~T6_E~0); 12569#L1120-1 assume !(0 == ~T7_E~0); 12846#L1125-1 assume !(0 == ~T8_E~0); 13315#L1130-1 assume !(0 == ~T9_E~0); 13064#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12359#L1140-1 assume !(0 == ~T11_E~0); 12360#L1145-1 assume !(0 == ~E_1~0); 12998#L1150-1 assume !(0 == ~E_2~0); 12544#L1155-1 assume !(0 == ~E_3~0); 12545#L1160-1 assume !(0 == ~E_4~0); 12627#L1165-1 assume !(0 == ~E_5~0); 12628#L1170-1 assume !(0 == ~E_6~0); 13236#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12705#L1180-1 assume !(0 == ~E_8~0); 12706#L1185-1 assume !(0 == ~E_9~0); 12356#L1190-1 assume !(0 == ~E_10~0); 12357#L1195-1 assume !(0 == ~E_11~0); 12719#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12559#L525 assume !(1 == ~m_pc~0); 11977#L525-2 is_master_triggered_~__retres1~0#1 := 0; 11978#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12723#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12724#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12343#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12344#L544 assume 1 == ~t1_pc~0; 12604#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12568#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12996#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12194#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 12195#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12817#L563 assume !(1 == ~t2_pc~0); 12983#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11998#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11999#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12427#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 12428#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12890#L582 assume 1 == ~t3_pc~0; 12136#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12137#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13287#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13245#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 12072#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12073#L601 assume !(1 == ~t4_pc~0); 13013#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12570#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12571#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13007#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 13008#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13279#L620 assume 1 == ~t5_pc~0; 12027#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12028#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12842#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12843#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 13294#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13295#L639 assume !(1 == ~t6_pc~0); 12844#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12467#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12468#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13248#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 12578#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12579#L658 assume 1 == ~t7_pc~0; 12845#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12770#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12877#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12878#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 12350#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12351#L677 assume 1 == ~t8_pc~0; 12581#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12153#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12154#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12424#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 12425#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13103#L696 assume !(1 == ~t9_pc~0); 12828#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12829#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12918#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12850#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12851#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13048#L715 assume 1 == ~t10_pc~0; 13052#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12935#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12820#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12821#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 12697#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12145#L734 assume !(1 == ~t11_pc~0); 12146#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12631#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12710#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11877#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 11878#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12905#L1213 assume !(1 == ~M_E~0); 12694#L1213-2 assume !(1 == ~T1_E~0); 12695#L1218-1 assume !(1 == ~T2_E~0); 11914#L1223-1 assume !(1 == ~T3_E~0); 11915#L1228-1 assume !(1 == ~T4_E~0); 12674#L1233-1 assume !(1 == ~T5_E~0); 13296#L1238-1 assume !(1 == ~T6_E~0); 13005#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13006#L1248-1 assume !(1 == ~T8_E~0); 13050#L1253-1 assume !(1 == ~T9_E~0); 13051#L1258-1 assume !(1 == ~T10_E~0); 13029#L1263-1 assume !(1 == ~T11_E~0); 13030#L1268-1 assume !(1 == ~E_1~0); 12865#L1273-1 assume !(1 == ~E_2~0); 12866#L1278-1 assume !(1 == ~E_3~0); 12465#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12466#L1288-1 assume !(1 == ~E_5~0); 13143#L1293-1 assume !(1 == ~E_6~0); 13107#L1298-1 assume !(1 == ~E_7~0); 12893#L1303-1 assume !(1 == ~E_8~0); 12476#L1308-1 assume !(1 == ~E_9~0); 12365#L1313-1 assume !(1 == ~E_10~0); 12366#L1318-1 assume !(1 == ~E_11~0); 12375#L1323-1 assume { :end_inline_reset_delta_events } true; 12376#L1644-2 [2021-12-19 19:17:38,082 INFO L793 eck$LassoCheckResult]: Loop: 12376#L1644-2 assume !false; 12946#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12947#L1065 assume !false; 13022#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13292#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 11996#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13208#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12481#L906 assume !(0 != eval_~tmp~0#1); 12483#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13019#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13020#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13160#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13212#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13175#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13176#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12249#L1110-3 assume !(0 == ~T5_E~0); 12250#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12532#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12533#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13003#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13257#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12455#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11950#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11951#L1150-3 assume !(0 == ~E_2~0); 12074#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12075#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12436#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12437#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12809#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12346#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12104#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12105#L1190-3 assume !(0 == ~E_10~0); 13251#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13252#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12659#L525-36 assume !(1 == ~m_pc~0); 12660#L525-38 is_master_triggered_~__retres1~0#1 := 0; 12205#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12206#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12491#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12492#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L544-36 assume 1 == ~t1_pc~0; 12401#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12924#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12289#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12290#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13233#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13136#L563-36 assume 1 == ~t2_pc~0; 12192#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11948#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11949#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13011#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12672#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12673#L582-36 assume 1 == ~t3_pc~0; 12523#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12524#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12748#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12915#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12709#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12653#L601-36 assume 1 == ~t4_pc~0; 12552#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12553#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13300#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13218#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13219#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13124#L620-36 assume 1 == ~t5_pc~0; 12594#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12595#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12986#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12580#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12214#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11992#L639-36 assume 1 == ~t6_pc~0; 11993#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12032#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12033#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12272#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12273#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12849#L658-36 assume !(1 == ~t7_pc~0); 12003#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 12004#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13203#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11979#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 11980#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L677-36 assume !(1 == ~t8_pc~0); 12774#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 12775#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12891#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13275#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12797#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12798#L696-36 assume 1 == ~t9_pc~0; 12691#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12693#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12052#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12053#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12810#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12811#L715-36 assume 1 == ~t10_pc~0; 12944#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11879#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11880#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11853#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11854#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12258#L734-36 assume 1 == ~t11_pc~0; 12259#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11958#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12280#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11871#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11872#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12871#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12540#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12541#L1218-3 assume !(1 == ~T2_E~0); 12309#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12310#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12499#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12500#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12744#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12745#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13217#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13222#L1258-3 assume !(1 == ~T10_E~0); 12291#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12292#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13187#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13205#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13207#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12623#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12624#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12489#L1298-3 assume !(1 == ~E_7~0); 12490#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12945#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12486#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12487#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12293#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12294#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12233#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12644#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 13083#L1663 assume !(0 == start_simulation_~tmp~3#1); 12126#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12847#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12070#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12768#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12014#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12015#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12353#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13272#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 12376#L1644-2 [2021-12-19 19:17:38,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,083 INFO L85 PathProgramCache]: Analyzing trace with hash -586642968, now seen corresponding path program 1 times [2021-12-19 19:17:38,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,083 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035508499] [2021-12-19 19:17:38,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,110 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035508499] [2021-12-19 19:17:38,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035508499] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,110 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,111 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180480560] [2021-12-19 19:17:38,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,111 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,112 INFO L85 PathProgramCache]: Analyzing trace with hash 869462766, now seen corresponding path program 2 times [2021-12-19 19:17:38,112 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646166953] [2021-12-19 19:17:38,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,159 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,159 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646166953] [2021-12-19 19:17:38,160 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646166953] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,160 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,160 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,160 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570041151] [2021-12-19 19:17:38,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,160 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,161 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,161 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,161 INFO L87 Difference]: Start difference. First operand 1476 states and 2190 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,180 INFO L93 Difference]: Finished difference Result 1476 states and 2189 transitions. [2021-12-19 19:17:38,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2189 transitions. [2021-12-19 19:17:38,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-12-19 19:17:38,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2189 transitions. [2021-12-19 19:17:38,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,194 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-12-19 19:17:38,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2189 transitions. [2021-12-19 19:17:38,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4830623306233062) internal successors, (2189), 1475 states have internal predecessors, (2189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2189 transitions. [2021-12-19 19:17:38,208 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-12-19 19:17:38,209 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2189 transitions. [2021-12-19 19:17:38,209 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:38,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2189 transitions. [2021-12-19 19:17:38,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,214 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,214 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,214 INFO L791 eck$LassoCheckResult]: Stem: 15932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 15942#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15943#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15708#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 15709#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15578#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15490#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15213#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14848#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14849#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14897#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14898#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15826#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15827#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15865#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15313#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15314#L1090 assume !(0 == ~M_E~0); 15356#L1090-2 assume !(0 == ~T1_E~0); 15357#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16003#L1100-1 assume !(0 == ~T3_E~0); 16004#L1105-1 assume !(0 == ~T4_E~0); 15132#L1110-1 assume !(0 == ~T5_E~0); 15133#L1115-1 assume !(0 == ~T6_E~0); 15528#L1120-1 assume !(0 == ~T7_E~0); 15805#L1125-1 assume !(0 == ~T8_E~0); 16274#L1130-1 assume !(0 == ~T9_E~0); 16023#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15318#L1140-1 assume !(0 == ~T11_E~0); 15319#L1145-1 assume !(0 == ~E_1~0); 15957#L1150-1 assume !(0 == ~E_2~0); 15503#L1155-1 assume !(0 == ~E_3~0); 15504#L1160-1 assume !(0 == ~E_4~0); 15586#L1165-1 assume !(0 == ~E_5~0); 15587#L1170-1 assume !(0 == ~E_6~0); 16195#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15664#L1180-1 assume !(0 == ~E_8~0); 15665#L1185-1 assume !(0 == ~E_9~0); 15315#L1190-1 assume !(0 == ~E_10~0); 15316#L1195-1 assume !(0 == ~E_11~0); 15678#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15525#L525 assume !(1 == ~m_pc~0); 14936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 14937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15682#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15683#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15302#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15303#L544 assume 1 == ~t1_pc~0; 15563#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15527#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15955#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15153#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 15154#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15776#L563 assume !(1 == ~t2_pc~0); 15944#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14957#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14958#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15386#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 15387#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15849#L582 assume 1 == ~t3_pc~0; 15097#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15098#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16246#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16204#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 15031#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15032#L601 assume !(1 == ~t4_pc~0); 15972#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15529#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15530#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15966#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 15967#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16238#L620 assume 1 == ~t5_pc~0; 14988#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14989#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15801#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15802#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 16253#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16254#L639 assume !(1 == ~t6_pc~0); 15803#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15426#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15427#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16207#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 15537#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15538#L658 assume 1 == ~t7_pc~0; 15804#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15729#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15836#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15837#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 15309#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15310#L677 assume 1 == ~t8_pc~0; 15540#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15112#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15113#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15383#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 15384#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16062#L696 assume !(1 == ~t9_pc~0); 15789#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15790#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15877#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15809#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15810#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16007#L715 assume 1 == ~t10_pc~0; 16011#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15894#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15779#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15780#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 15656#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15106#L734 assume !(1 == ~t11_pc~0); 15107#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 15590#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15669#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14838#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 14839#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15864#L1213 assume !(1 == ~M_E~0); 15654#L1213-2 assume !(1 == ~T1_E~0); 15655#L1218-1 assume !(1 == ~T2_E~0); 14873#L1223-1 assume !(1 == ~T3_E~0); 14874#L1228-1 assume !(1 == ~T4_E~0); 15633#L1233-1 assume !(1 == ~T5_E~0); 16255#L1238-1 assume !(1 == ~T6_E~0); 15964#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15965#L1248-1 assume !(1 == ~T8_E~0); 16009#L1253-1 assume !(1 == ~T9_E~0); 16010#L1258-1 assume !(1 == ~T10_E~0); 15988#L1263-1 assume !(1 == ~T11_E~0); 15989#L1268-1 assume !(1 == ~E_1~0); 15824#L1273-1 assume !(1 == ~E_2~0); 15825#L1278-1 assume !(1 == ~E_3~0); 15424#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15425#L1288-1 assume !(1 == ~E_5~0); 16102#L1293-1 assume !(1 == ~E_6~0); 16066#L1298-1 assume !(1 == ~E_7~0); 15852#L1303-1 assume !(1 == ~E_8~0); 15435#L1308-1 assume !(1 == ~E_9~0); 15324#L1313-1 assume !(1 == ~E_10~0); 15325#L1318-1 assume !(1 == ~E_11~0); 15337#L1323-1 assume { :end_inline_reset_delta_events } true; 15338#L1644-2 [2021-12-19 19:17:38,215 INFO L793 eck$LassoCheckResult]: Loop: 15338#L1644-2 assume !false; 15905#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15906#L1065 assume !false; 15981#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16251#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 14955#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16167#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15440#L906 assume !(0 != eval_~tmp~0#1); 15442#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15978#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15979#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16119#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16171#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16134#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16135#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15208#L1110-3 assume !(0 == ~T5_E~0); 15209#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15491#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15492#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15962#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16216#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15414#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14911#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1150-3 assume !(0 == ~E_2~0); 15034#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15035#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15395#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15396#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15768#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15305#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15064#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15065#L1190-3 assume !(0 == ~E_10~0); 16210#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16211#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15618#L525-36 assume !(1 == ~m_pc~0); 15619#L525-38 is_master_triggered_~__retres1~0#1 := 0; 15169#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15170#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15451#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15452#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15359#L544-36 assume 1 == ~t1_pc~0; 15360#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15883#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15254#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15255#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16193#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16095#L563-36 assume !(1 == ~t2_pc~0); 15152#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 14907#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14908#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15970#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15631#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15632#L582-36 assume 1 == ~t3_pc~0; 15482#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15483#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15707#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15874#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15668#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15612#L601-36 assume 1 == ~t4_pc~0; 15511#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15512#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16259#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16177#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16178#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16083#L620-36 assume 1 == ~t5_pc~0; 15554#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15555#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15947#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15539#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15173#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14948#L639-36 assume 1 == ~t6_pc~0; 14949#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14986#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14987#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15227#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15228#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15808#L658-36 assume 1 == ~t7_pc~0; 15068#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14960#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16162#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14938#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 14939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15929#L677-36 assume !(1 == ~t8_pc~0); 15732#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 15733#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15850#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16234#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15756#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15757#L696-36 assume 1 == ~t9_pc~0; 15650#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15652#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15008#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15009#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15769#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15770#L715-36 assume !(1 == ~t10_pc~0); 15740#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 14836#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14837#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15217#L734-36 assume 1 == ~t11_pc~0; 15218#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14917#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15239#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14830#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14831#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15830#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15497#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15498#L1218-3 assume !(1 == ~T2_E~0); 15268#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15269#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15458#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15459#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15703#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15704#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16175#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16180#L1258-3 assume !(1 == ~T10_E~0); 15248#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15249#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16146#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16164#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16166#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15582#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15583#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15447#L1298-3 assume !(1 == ~E_7~0); 15448#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15904#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15445#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15446#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15250#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15251#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15192#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15603#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 16042#L1663 assume !(0 == start_simulation_~tmp~3#1); 15078#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15806#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15029#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15725#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14970#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14971#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15312#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16231#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 15338#L1644-2 [2021-12-19 19:17:38,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,216 INFO L85 PathProgramCache]: Analyzing trace with hash 361408998, now seen corresponding path program 1 times [2021-12-19 19:17:38,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,216 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218550617] [2021-12-19 19:17:38,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,216 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [218550617] [2021-12-19 19:17:38,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [218550617] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,251 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560862420] [2021-12-19 19:17:38,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,253 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,254 INFO L85 PathProgramCache]: Analyzing trace with hash -459098803, now seen corresponding path program 1 times [2021-12-19 19:17:38,255 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,257 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040729171] [2021-12-19 19:17:38,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,258 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040729171] [2021-12-19 19:17:38,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040729171] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,286 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,286 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [509892500] [2021-12-19 19:17:38,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,287 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,287 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,288 INFO L87 Difference]: Start difference. First operand 1476 states and 2189 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,303 INFO L93 Difference]: Finished difference Result 1476 states and 2188 transitions. [2021-12-19 19:17:38,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2188 transitions. [2021-12-19 19:17:38,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,315 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-12-19 19:17:38,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2188 transitions. [2021-12-19 19:17:38,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,318 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-12-19 19:17:38,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2188 transitions. [2021-12-19 19:17:38,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4823848238482384) internal successors, (2188), 1475 states have internal predecessors, (2188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2188 transitions. [2021-12-19 19:17:38,333 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-12-19 19:17:38,334 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2188 transitions. [2021-12-19 19:17:38,334 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:38,334 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2188 transitions. [2021-12-19 19:17:38,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,339 INFO L791 eck$LassoCheckResult]: Stem: 18891#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 18901#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18902#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18667#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 18668#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18537#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18449#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18172#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17807#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17808#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17856#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17857#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18787#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18788#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18831#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18272#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18273#L1090 assume !(0 == ~M_E~0); 18319#L1090-2 assume !(0 == ~T1_E~0); 18320#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18962#L1100-1 assume !(0 == ~T3_E~0); 18963#L1105-1 assume !(0 == ~T4_E~0); 18091#L1110-1 assume !(0 == ~T5_E~0); 18092#L1115-1 assume !(0 == ~T6_E~0); 18490#L1120-1 assume !(0 == ~T7_E~0); 18764#L1125-1 assume !(0 == ~T8_E~0); 19233#L1130-1 assume !(0 == ~T9_E~0); 18982#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18279#L1140-1 assume !(0 == ~T11_E~0); 18280#L1145-1 assume !(0 == ~E_1~0); 18916#L1150-1 assume !(0 == ~E_2~0); 18462#L1155-1 assume !(0 == ~E_3~0); 18463#L1160-1 assume !(0 == ~E_4~0); 18545#L1165-1 assume !(0 == ~E_5~0); 18546#L1170-1 assume !(0 == ~E_6~0); 19154#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 18623#L1180-1 assume !(0 == ~E_8~0); 18624#L1185-1 assume !(0 == ~E_9~0); 18274#L1190-1 assume !(0 == ~E_10~0); 18275#L1195-1 assume !(0 == ~E_11~0); 18637#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18484#L525 assume !(1 == ~m_pc~0); 17895#L525-2 is_master_triggered_~__retres1~0#1 := 0; 17896#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18641#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18642#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18262#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18263#L544 assume 1 == ~t1_pc~0; 18522#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18486#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18914#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18112#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 18113#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18735#L563 assume !(1 == ~t2_pc~0); 18903#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17916#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17917#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18348#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 18349#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18808#L582 assume 1 == ~t3_pc~0; 18056#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18057#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19205#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19164#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 17990#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17991#L601 assume !(1 == ~t4_pc~0); 18931#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18491#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18492#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18925#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 18926#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19197#L620 assume 1 == ~t5_pc~0; 17949#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17950#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18761#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18762#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 19212#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19213#L639 assume !(1 == ~t6_pc~0); 18763#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 18385#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18386#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19166#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 18496#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18497#L658 assume 1 == ~t7_pc~0; 18760#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18688#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18795#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18796#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 18268#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18269#L677 assume 1 == ~t8_pc~0; 18499#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18071#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18072#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18342#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 18343#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19021#L696 assume !(1 == ~t9_pc~0); 18746#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18747#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18836#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18768#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18769#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18966#L715 assume 1 == ~t10_pc~0; 18970#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18853#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18738#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18739#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 18615#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18063#L734 assume !(1 == ~t11_pc~0); 18064#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 18549#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18628#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17795#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 17796#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18823#L1213 assume !(1 == ~M_E~0); 18612#L1213-2 assume !(1 == ~T1_E~0); 18613#L1218-1 assume !(1 == ~T2_E~0); 17832#L1223-1 assume !(1 == ~T3_E~0); 17833#L1228-1 assume !(1 == ~T4_E~0); 18592#L1233-1 assume !(1 == ~T5_E~0); 19214#L1238-1 assume !(1 == ~T6_E~0); 18923#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18924#L1248-1 assume !(1 == ~T8_E~0); 18968#L1253-1 assume !(1 == ~T9_E~0); 18969#L1258-1 assume !(1 == ~T10_E~0); 18947#L1263-1 assume !(1 == ~T11_E~0); 18948#L1268-1 assume !(1 == ~E_1~0); 18783#L1273-1 assume !(1 == ~E_2~0); 18784#L1278-1 assume !(1 == ~E_3~0); 18383#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18384#L1288-1 assume !(1 == ~E_5~0); 19061#L1293-1 assume !(1 == ~E_6~0); 19025#L1298-1 assume !(1 == ~E_7~0); 18811#L1303-1 assume !(1 == ~E_8~0); 18394#L1308-1 assume !(1 == ~E_9~0); 18283#L1313-1 assume !(1 == ~E_10~0); 18284#L1318-1 assume !(1 == ~E_11~0); 18293#L1323-1 assume { :end_inline_reset_delta_events } true; 18294#L1644-2 [2021-12-19 19:17:38,339 INFO L793 eck$LassoCheckResult]: Loop: 18294#L1644-2 assume !false; 18864#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18865#L1065 assume !false; 18940#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19210#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17914#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19126#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18399#L906 assume !(0 != eval_~tmp~0#1); 18401#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18937#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18938#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19078#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19130#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19093#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19094#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18167#L1110-3 assume !(0 == ~T5_E~0); 18168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18450#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18451#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18921#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19175#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18373#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17868#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17869#L1150-3 assume !(0 == ~E_2~0); 17992#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17993#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18354#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18355#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18727#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18264#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18022#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18023#L1190-3 assume !(0 == ~E_10~0); 19169#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19170#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18577#L525-36 assume !(1 == ~m_pc~0); 18578#L525-38 is_master_triggered_~__retres1~0#1 := 0; 18123#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18124#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18409#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18410#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18316#L544-36 assume 1 == ~t1_pc~0; 18317#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18842#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18207#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18208#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19151#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19054#L563-36 assume 1 == ~t2_pc~0; 18110#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17866#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17867#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18929#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18590#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18591#L582-36 assume 1 == ~t3_pc~0; 18441#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18442#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18666#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18833#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18627#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18571#L601-36 assume 1 == ~t4_pc~0; 18470#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18471#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19218#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19136#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19137#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19042#L620-36 assume 1 == ~t5_pc~0; 18512#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18513#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18904#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18498#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18132#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17910#L639-36 assume 1 == ~t6_pc~0; 17911#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17947#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17948#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18190#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18191#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18767#L658-36 assume !(1 == ~t7_pc~0); 17921#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 17922#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19121#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17897#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 17898#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18888#L677-36 assume !(1 == ~t8_pc~0); 18692#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 18693#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18809#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19193#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18715#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18716#L696-36 assume 1 == ~t9_pc~0; 18609#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18611#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17970#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17971#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18728#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18729#L715-36 assume !(1 == ~t10_pc~0); 18699#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 17797#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17798#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17771#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17772#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18176#L734-36 assume 1 == ~t11_pc~0; 18177#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17876#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18198#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17789#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17790#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18789#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18458#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18459#L1218-3 assume !(1 == ~T2_E~0); 18227#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18228#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18417#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18418#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18662#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18663#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19135#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19140#L1258-3 assume !(1 == ~T10_E~0); 18209#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18210#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19105#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19123#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19125#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18541#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18542#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18407#L1298-3 assume !(1 == ~E_7~0); 18408#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18863#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18404#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18405#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18211#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18212#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 18151#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18562#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 19001#L1663 assume !(0 == start_simulation_~tmp~3#1); 18044#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 18765#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 17988#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 18686#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 17932#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17933#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18271#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19190#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 18294#L1644-2 [2021-12-19 19:17:38,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,340 INFO L85 PathProgramCache]: Analyzing trace with hash 946180648, now seen corresponding path program 1 times [2021-12-19 19:17:38,341 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,341 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1642261050] [2021-12-19 19:17:38,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,341 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,359 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,360 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1642261050] [2021-12-19 19:17:38,360 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1642261050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,360 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,360 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,360 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261964921] [2021-12-19 19:17:38,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,360 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,361 INFO L85 PathProgramCache]: Analyzing trace with hash -1992669811, now seen corresponding path program 1 times [2021-12-19 19:17:38,361 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236669673] [2021-12-19 19:17:38,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,361 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,390 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236669673] [2021-12-19 19:17:38,390 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1236669673] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,390 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,390 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,390 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769861786] [2021-12-19 19:17:38,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,391 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,391 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,392 INFO L87 Difference]: Start difference. First operand 1476 states and 2188 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,407 INFO L93 Difference]: Finished difference Result 1476 states and 2187 transitions. [2021-12-19 19:17:38,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2187 transitions. [2021-12-19 19:17:38,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-12-19 19:17:38,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2187 transitions. [2021-12-19 19:17:38,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,419 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-12-19 19:17:38,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2187 transitions. [2021-12-19 19:17:38,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4817073170731707) internal successors, (2187), 1475 states have internal predecessors, (2187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2187 transitions. [2021-12-19 19:17:38,435 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-12-19 19:17:38,436 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2187 transitions. [2021-12-19 19:17:38,436 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:38,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2187 transitions. [2021-12-19 19:17:38,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,440 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,440 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,440 INFO L791 eck$LassoCheckResult]: Stem: 21850#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21851#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 21858#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21859#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21626#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 21627#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21496#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21408#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21131#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20766#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20767#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20815#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20816#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21744#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21745#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21783#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21231#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21232#L1090 assume !(0 == ~M_E~0); 21274#L1090-2 assume !(0 == ~T1_E~0); 21275#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21920#L1100-1 assume !(0 == ~T3_E~0); 21921#L1105-1 assume !(0 == ~T4_E~0); 21049#L1110-1 assume !(0 == ~T5_E~0); 21050#L1115-1 assume !(0 == ~T6_E~0); 21446#L1120-1 assume !(0 == ~T7_E~0); 21723#L1125-1 assume !(0 == ~T8_E~0); 22192#L1130-1 assume !(0 == ~T9_E~0); 21941#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21236#L1140-1 assume !(0 == ~T11_E~0); 21237#L1145-1 assume !(0 == ~E_1~0); 21875#L1150-1 assume !(0 == ~E_2~0); 21421#L1155-1 assume !(0 == ~E_3~0); 21422#L1160-1 assume !(0 == ~E_4~0); 21504#L1165-1 assume !(0 == ~E_5~0); 21505#L1170-1 assume !(0 == ~E_6~0); 22113#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 21582#L1180-1 assume !(0 == ~E_8~0); 21583#L1185-1 assume !(0 == ~E_9~0); 21233#L1190-1 assume !(0 == ~E_10~0); 21234#L1195-1 assume !(0 == ~E_11~0); 21596#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21438#L525 assume !(1 == ~m_pc~0); 20854#L525-2 is_master_triggered_~__retres1~0#1 := 0; 20855#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21600#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21601#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21220#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21221#L544 assume 1 == ~t1_pc~0; 21481#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21445#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21873#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21071#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 21072#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21694#L563 assume !(1 == ~t2_pc~0); 21860#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20875#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20876#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21304#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 21305#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21767#L582 assume 1 == ~t3_pc~0; 21013#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21014#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22164#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22122#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 20949#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20950#L601 assume !(1 == ~t4_pc~0); 21890#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21447#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21448#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21884#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 21885#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22156#L620 assume 1 == ~t5_pc~0; 20904#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20905#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21719#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21720#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 22171#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22172#L639 assume !(1 == ~t6_pc~0); 21721#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21344#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21345#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22125#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 21455#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21456#L658 assume 1 == ~t7_pc~0; 21722#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21647#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21754#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21755#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 21227#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21228#L677 assume 1 == ~t8_pc~0; 21458#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21030#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21031#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21301#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 21302#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21980#L696 assume !(1 == ~t9_pc~0); 21705#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21706#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21795#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21727#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21728#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21925#L715 assume 1 == ~t10_pc~0; 21929#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21812#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21697#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 21574#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21022#L734 assume !(1 == ~t11_pc~0); 21023#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21508#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21587#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20756#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 20757#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21782#L1213 assume !(1 == ~M_E~0); 21571#L1213-2 assume !(1 == ~T1_E~0); 21572#L1218-1 assume !(1 == ~T2_E~0); 20791#L1223-1 assume !(1 == ~T3_E~0); 20792#L1228-1 assume !(1 == ~T4_E~0); 21551#L1233-1 assume !(1 == ~T5_E~0); 22173#L1238-1 assume !(1 == ~T6_E~0); 21882#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21883#L1248-1 assume !(1 == ~T8_E~0); 21927#L1253-1 assume !(1 == ~T9_E~0); 21928#L1258-1 assume !(1 == ~T10_E~0); 21906#L1263-1 assume !(1 == ~T11_E~0); 21907#L1268-1 assume !(1 == ~E_1~0); 21742#L1273-1 assume !(1 == ~E_2~0); 21743#L1278-1 assume !(1 == ~E_3~0); 21342#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21343#L1288-1 assume !(1 == ~E_5~0); 22020#L1293-1 assume !(1 == ~E_6~0); 21984#L1298-1 assume !(1 == ~E_7~0); 21770#L1303-1 assume !(1 == ~E_8~0); 21353#L1308-1 assume !(1 == ~E_9~0); 21242#L1313-1 assume !(1 == ~E_10~0); 21243#L1318-1 assume !(1 == ~E_11~0); 21252#L1323-1 assume { :end_inline_reset_delta_events } true; 21253#L1644-2 [2021-12-19 19:17:38,441 INFO L793 eck$LassoCheckResult]: Loop: 21253#L1644-2 assume !false; 21823#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21824#L1065 assume !false; 21899#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22169#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20873#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22085#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21358#L906 assume !(0 != eval_~tmp~0#1); 21360#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21896#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21897#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22037#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22089#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22052#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22053#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21126#L1110-3 assume !(0 == ~T5_E~0); 21127#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21409#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21410#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21880#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22134#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21332#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20827#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20828#L1150-3 assume !(0 == ~E_2~0); 20952#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20953#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21313#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21314#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21686#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21223#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20981#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20982#L1190-3 assume !(0 == ~E_10~0); 22128#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22129#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21536#L525-36 assume !(1 == ~m_pc~0); 21537#L525-38 is_master_triggered_~__retres1~0#1 := 0; 21082#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21083#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21368#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21369#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21277#L544-36 assume 1 == ~t1_pc~0; 21278#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21801#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21172#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21173#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22111#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22013#L563-36 assume 1 == ~t2_pc~0; 21069#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20825#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20826#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21888#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21549#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21550#L582-36 assume 1 == ~t3_pc~0; 21400#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21401#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21625#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21792#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21586#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21530#L601-36 assume 1 == ~t4_pc~0; 21429#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21430#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22177#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22095#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22096#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22001#L620-36 assume 1 == ~t5_pc~0; 21472#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21473#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21865#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21457#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21091#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20869#L639-36 assume 1 == ~t6_pc~0; 20870#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20909#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20910#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21149#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21150#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21726#L658-36 assume !(1 == ~t7_pc~0); 20880#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22080#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20856#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 20857#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21847#L677-36 assume !(1 == ~t8_pc~0); 21651#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 21652#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21768#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22152#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21674#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21675#L696-36 assume 1 == ~t9_pc~0; 21568#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21570#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20926#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20927#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21687#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21688#L715-36 assume !(1 == ~t10_pc~0); 21658#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 20754#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20755#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20730#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20731#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21132#L734-36 assume !(1 == ~t11_pc~0); 20834#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 20835#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21157#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20748#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20749#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21748#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21415#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21416#L1218-3 assume !(1 == ~T2_E~0); 21186#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21187#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21376#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21377#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21621#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21622#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22093#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22098#L1258-3 assume !(1 == ~T10_E~0); 21166#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21167#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22064#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22082#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22083#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21500#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21501#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21365#L1298-3 assume !(1 == ~E_7~0); 21366#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21822#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21363#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21364#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21168#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21169#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 21110#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21521#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 21960#L1663 assume !(0 == start_simulation_~tmp~3#1); 20996#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 21724#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 20947#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 21643#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20888#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20889#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21230#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22149#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 21253#L1644-2 [2021-12-19 19:17:38,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1380686246, now seen corresponding path program 1 times [2021-12-19 19:17:38,442 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805527066] [2021-12-19 19:17:38,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,442 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805527066] [2021-12-19 19:17:38,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805527066] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,476 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096550757] [2021-12-19 19:17:38,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,477 INFO L85 PathProgramCache]: Analyzing trace with hash 146783084, now seen corresponding path program 1 times [2021-12-19 19:17:38,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209484122] [2021-12-19 19:17:38,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,521 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,522 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209484122] [2021-12-19 19:17:38,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209484122] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,523 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,524 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,524 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700297989] [2021-12-19 19:17:38,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,525 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,525 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,526 INFO L87 Difference]: Start difference. First operand 1476 states and 2187 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,540 INFO L93 Difference]: Finished difference Result 1476 states and 2186 transitions. [2021-12-19 19:17:38,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,542 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2186 transitions. [2021-12-19 19:17:38,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-12-19 19:17:38,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2186 transitions. [2021-12-19 19:17:38,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,554 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-12-19 19:17:38,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2186 transitions. [2021-12-19 19:17:38,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.481029810298103) internal successors, (2186), 1475 states have internal predecessors, (2186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2186 transitions. [2021-12-19 19:17:38,569 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-12-19 19:17:38,569 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2186 transitions. [2021-12-19 19:17:38,569 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:38,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2186 transitions. [2021-12-19 19:17:38,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,574 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,574 INFO L791 eck$LassoCheckResult]: Stem: 24809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24810#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 24819#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24820#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24585#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 24586#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24455#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24367#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24090#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23725#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23726#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23774#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23775#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24705#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24706#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24749#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24190#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24191#L1090 assume !(0 == ~M_E~0); 24237#L1090-2 assume !(0 == ~T1_E~0); 24238#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24880#L1100-1 assume !(0 == ~T3_E~0); 24881#L1105-1 assume !(0 == ~T4_E~0); 24009#L1110-1 assume !(0 == ~T5_E~0); 24010#L1115-1 assume !(0 == ~T6_E~0); 24408#L1120-1 assume !(0 == ~T7_E~0); 24682#L1125-1 assume !(0 == ~T8_E~0); 25151#L1130-1 assume !(0 == ~T9_E~0); 24900#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24197#L1140-1 assume !(0 == ~T11_E~0); 24198#L1145-1 assume !(0 == ~E_1~0); 24834#L1150-1 assume !(0 == ~E_2~0); 24380#L1155-1 assume !(0 == ~E_3~0); 24381#L1160-1 assume !(0 == ~E_4~0); 24463#L1165-1 assume !(0 == ~E_5~0); 24464#L1170-1 assume !(0 == ~E_6~0); 25072#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 24541#L1180-1 assume !(0 == ~E_8~0); 24542#L1185-1 assume !(0 == ~E_9~0); 24192#L1190-1 assume !(0 == ~E_10~0); 24193#L1195-1 assume !(0 == ~E_11~0); 24555#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24402#L525 assume !(1 == ~m_pc~0); 23813#L525-2 is_master_triggered_~__retres1~0#1 := 0; 23814#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24559#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24560#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24179#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24180#L544 assume 1 == ~t1_pc~0; 24440#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24404#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24832#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24030#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 24031#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24653#L563 assume !(1 == ~t2_pc~0); 24821#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23834#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23835#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24266#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 24267#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24726#L582 assume 1 == ~t3_pc~0; 23974#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23975#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25123#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25081#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 23908#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23909#L601 assume !(1 == ~t4_pc~0); 24849#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24410#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24843#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 24844#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25115#L620 assume 1 == ~t5_pc~0; 23867#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23868#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24678#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24679#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 25130#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25131#L639 assume !(1 == ~t6_pc~0); 24680#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24303#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24304#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25084#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 24414#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24415#L658 assume 1 == ~t7_pc~0; 24681#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24713#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24714#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 24186#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24187#L677 assume 1 == ~t8_pc~0; 24419#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23992#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23993#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24260#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 24261#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24939#L696 assume !(1 == ~t9_pc~0); 24667#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24668#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24757#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24688#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24689#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24884#L715 assume 1 == ~t10_pc~0; 24888#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24771#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24656#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24657#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 24533#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23983#L734 assume !(1 == ~t11_pc~0); 23984#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24467#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24546#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23715#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 23716#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24741#L1213 assume !(1 == ~M_E~0); 24531#L1213-2 assume !(1 == ~T1_E~0); 24532#L1218-1 assume !(1 == ~T2_E~0); 23750#L1223-1 assume !(1 == ~T3_E~0); 23751#L1228-1 assume !(1 == ~T4_E~0); 24510#L1233-1 assume !(1 == ~T5_E~0); 25132#L1238-1 assume !(1 == ~T6_E~0); 24841#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1248-1 assume !(1 == ~T8_E~0); 24886#L1253-1 assume !(1 == ~T9_E~0); 24887#L1258-1 assume !(1 == ~T10_E~0); 24865#L1263-1 assume !(1 == ~T11_E~0); 24866#L1268-1 assume !(1 == ~E_1~0); 24701#L1273-1 assume !(1 == ~E_2~0); 24702#L1278-1 assume !(1 == ~E_3~0); 24301#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 24302#L1288-1 assume !(1 == ~E_5~0); 24979#L1293-1 assume !(1 == ~E_6~0); 24943#L1298-1 assume !(1 == ~E_7~0); 24729#L1303-1 assume !(1 == ~E_8~0); 24312#L1308-1 assume !(1 == ~E_9~0); 24201#L1313-1 assume !(1 == ~E_10~0); 24202#L1318-1 assume !(1 == ~E_11~0); 24214#L1323-1 assume { :end_inline_reset_delta_events } true; 24215#L1644-2 [2021-12-19 19:17:38,575 INFO L793 eck$LassoCheckResult]: Loop: 24215#L1644-2 assume !false; 24782#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24783#L1065 assume !false; 24858#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25128#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23832#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25044#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24317#L906 assume !(0 != eval_~tmp~0#1); 24319#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24856#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24857#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24996#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25011#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25012#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24085#L1110-3 assume !(0 == ~T5_E~0); 24086#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24368#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24369#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24839#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25093#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24291#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23786#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23787#L1150-3 assume !(0 == ~E_2~0); 23910#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23911#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24272#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24273#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24645#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24182#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23940#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23941#L1190-3 assume !(0 == ~E_10~0); 25087#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25088#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24492#L525-36 assume !(1 == ~m_pc~0); 24493#L525-38 is_master_triggered_~__retres1~0#1 := 0; 24041#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24042#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24327#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24328#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24234#L544-36 assume 1 == ~t1_pc~0; 24235#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24760#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24125#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24126#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25069#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24972#L563-36 assume 1 == ~t2_pc~0; 24028#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23784#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23785#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24847#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24508#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24509#L582-36 assume 1 == ~t3_pc~0; 24359#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24360#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24584#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24751#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24545#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24489#L601-36 assume 1 == ~t4_pc~0; 24388#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24389#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25136#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25054#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25055#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24960#L620-36 assume 1 == ~t5_pc~0; 24428#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24429#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24822#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24416#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24050#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23828#L639-36 assume 1 == ~t6_pc~0; 23829#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23865#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23866#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24106#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24107#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24685#L658-36 assume 1 == ~t7_pc~0; 23947#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23840#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25039#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23815#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 23816#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24806#L677-36 assume !(1 == ~t8_pc~0); 24610#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 24611#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24727#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25111#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24633#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24634#L696-36 assume !(1 == ~t9_pc~0); 24528#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24529#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23888#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23889#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24646#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L715-36 assume !(1 == ~t10_pc~0); 24617#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 23713#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23714#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23689#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23690#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24094#L734-36 assume !(1 == ~t11_pc~0); 23793#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 23794#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24116#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23707#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23708#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24707#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24374#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24375#L1218-3 assume !(1 == ~T2_E~0); 24145#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24146#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24335#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24336#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24580#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24581#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25052#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25057#L1258-3 assume !(1 == ~T10_E~0); 24127#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24128#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25023#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25041#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25043#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24459#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24460#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24325#L1298-3 assume !(1 == ~E_7~0); 24326#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24781#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24322#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24323#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24129#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24130#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 24069#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24480#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 24919#L1663 assume !(0 == start_simulation_~tmp~3#1); 23962#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 24683#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 23906#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 24602#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23850#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23851#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24189#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25108#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 24215#L1644-2 [2021-12-19 19:17:38,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1810344552, now seen corresponding path program 1 times [2021-12-19 19:17:38,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683257749] [2021-12-19 19:17:38,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,576 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,594 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683257749] [2021-12-19 19:17:38,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683257749] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,594 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867376271] [2021-12-19 19:17:38,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,595 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1427558892, now seen corresponding path program 1 times [2021-12-19 19:17:38,595 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544810238] [2021-12-19 19:17:38,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,595 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,620 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544810238] [2021-12-19 19:17:38,620 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544810238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,620 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,620 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763516518] [2021-12-19 19:17:38,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,621 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,621 INFO L87 Difference]: Start difference. First operand 1476 states and 2186 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,638 INFO L93 Difference]: Finished difference Result 1476 states and 2185 transitions. [2021-12-19 19:17:38,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2185 transitions. [2021-12-19 19:17:38,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-12-19 19:17:38,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2185 transitions. [2021-12-19 19:17:38,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,650 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-12-19 19:17:38,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2185 transitions. [2021-12-19 19:17:38,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4803523035230353) internal successors, (2185), 1475 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2185 transitions. [2021-12-19 19:17:38,665 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-12-19 19:17:38,665 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2185 transitions. [2021-12-19 19:17:38,665 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:38,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2185 transitions. [2021-12-19 19:17:38,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,670 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,670 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,670 INFO L791 eck$LassoCheckResult]: Stem: 27768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 27776#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27777#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27544#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 27545#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27414#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27326#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27049#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26684#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26685#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26733#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26734#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27662#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27663#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27701#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27149#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27150#L1090 assume !(0 == ~M_E~0); 27192#L1090-2 assume !(0 == ~T1_E~0); 27193#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27838#L1100-1 assume !(0 == ~T3_E~0); 27839#L1105-1 assume !(0 == ~T4_E~0); 26967#L1110-1 assume !(0 == ~T5_E~0); 26968#L1115-1 assume !(0 == ~T6_E~0); 27364#L1120-1 assume !(0 == ~T7_E~0); 27641#L1125-1 assume !(0 == ~T8_E~0); 28110#L1130-1 assume !(0 == ~T9_E~0); 27859#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27154#L1140-1 assume !(0 == ~T11_E~0); 27155#L1145-1 assume !(0 == ~E_1~0); 27793#L1150-1 assume !(0 == ~E_2~0); 27339#L1155-1 assume !(0 == ~E_3~0); 27340#L1160-1 assume !(0 == ~E_4~0); 27422#L1165-1 assume !(0 == ~E_5~0); 27423#L1170-1 assume !(0 == ~E_6~0); 28031#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 27500#L1180-1 assume !(0 == ~E_8~0); 27501#L1185-1 assume !(0 == ~E_9~0); 27151#L1190-1 assume !(0 == ~E_10~0); 27152#L1195-1 assume !(0 == ~E_11~0); 27514#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27354#L525 assume !(1 == ~m_pc~0); 26772#L525-2 is_master_triggered_~__retres1~0#1 := 0; 26773#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27518#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27519#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27138#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27139#L544 assume 1 == ~t1_pc~0; 27399#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27363#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27791#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26989#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 26990#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27612#L563 assume !(1 == ~t2_pc~0); 27778#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26793#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26794#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27222#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 27223#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27685#L582 assume 1 == ~t3_pc~0; 26931#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26932#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28082#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28040#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 26867#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26868#L601 assume !(1 == ~t4_pc~0); 27808#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27365#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27366#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27802#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 27803#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28074#L620 assume 1 == ~t5_pc~0; 26822#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26823#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27637#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27638#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 28089#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28090#L639 assume !(1 == ~t6_pc~0); 27639#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27262#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27263#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28043#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 27373#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27374#L658 assume 1 == ~t7_pc~0; 27640#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27565#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27672#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27673#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 27145#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27146#L677 assume 1 == ~t8_pc~0; 27376#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26948#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26949#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27219#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 27220#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27898#L696 assume !(1 == ~t9_pc~0); 27623#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27624#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27713#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27645#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27646#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27843#L715 assume 1 == ~t10_pc~0; 27847#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27730#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27615#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27616#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 27492#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26940#L734 assume !(1 == ~t11_pc~0); 26941#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27426#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27505#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26672#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 26673#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27700#L1213 assume !(1 == ~M_E~0); 27489#L1213-2 assume !(1 == ~T1_E~0); 27490#L1218-1 assume !(1 == ~T2_E~0); 26709#L1223-1 assume !(1 == ~T3_E~0); 26710#L1228-1 assume !(1 == ~T4_E~0); 27469#L1233-1 assume !(1 == ~T5_E~0); 28091#L1238-1 assume !(1 == ~T6_E~0); 27800#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27801#L1248-1 assume !(1 == ~T8_E~0); 27845#L1253-1 assume !(1 == ~T9_E~0); 27846#L1258-1 assume !(1 == ~T10_E~0); 27824#L1263-1 assume !(1 == ~T11_E~0); 27825#L1268-1 assume !(1 == ~E_1~0); 27660#L1273-1 assume !(1 == ~E_2~0); 27661#L1278-1 assume !(1 == ~E_3~0); 27260#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27261#L1288-1 assume !(1 == ~E_5~0); 27938#L1293-1 assume !(1 == ~E_6~0); 27902#L1298-1 assume !(1 == ~E_7~0); 27688#L1303-1 assume !(1 == ~E_8~0); 27271#L1308-1 assume !(1 == ~E_9~0); 27160#L1313-1 assume !(1 == ~E_10~0); 27161#L1318-1 assume !(1 == ~E_11~0); 27170#L1323-1 assume { :end_inline_reset_delta_events } true; 27171#L1644-2 [2021-12-19 19:17:38,671 INFO L793 eck$LassoCheckResult]: Loop: 27171#L1644-2 assume !false; 27741#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27742#L1065 assume !false; 27817#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28087#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26791#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28003#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27276#L906 assume !(0 != eval_~tmp~0#1); 27278#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27814#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27815#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27955#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28007#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27970#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27971#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27044#L1110-3 assume !(0 == ~T5_E~0); 27045#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27327#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27328#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27798#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28052#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27250#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26745#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26746#L1150-3 assume !(0 == ~E_2~0); 26869#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26870#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27231#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27232#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27604#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27141#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26899#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26900#L1190-3 assume !(0 == ~E_10~0); 28046#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28047#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27454#L525-36 assume 1 == ~m_pc~0; 27456#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27000#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27001#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27287#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27195#L544-36 assume 1 == ~t1_pc~0; 27196#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27719#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27084#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27085#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28028#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27931#L563-36 assume 1 == ~t2_pc~0; 26987#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26743#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26744#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27806#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27467#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27468#L582-36 assume 1 == ~t3_pc~0; 27318#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27319#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27543#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27710#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27504#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27448#L601-36 assume 1 == ~t4_pc~0; 27347#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27348#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28095#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28013#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28014#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27919#L620-36 assume 1 == ~t5_pc~0; 27389#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27390#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27781#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27375#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27009#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26787#L639-36 assume 1 == ~t6_pc~0; 26788#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26827#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26828#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27067#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27068#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27644#L658-36 assume 1 == ~t7_pc~0; 26906#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26799#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27998#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26774#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 26775#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27765#L677-36 assume !(1 == ~t8_pc~0); 27569#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 27570#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27686#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28070#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27592#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27593#L696-36 assume 1 == ~t9_pc~0; 27486#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27488#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26847#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26848#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27605#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27606#L715-36 assume !(1 == ~t10_pc~0); 27576#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 26674#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26675#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26648#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26649#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27053#L734-36 assume !(1 == ~t11_pc~0); 26752#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 26753#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27075#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26666#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26667#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27666#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27335#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27336#L1218-3 assume !(1 == ~T2_E~0); 27104#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27105#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27294#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27295#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27539#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27540#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28012#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28017#L1258-3 assume !(1 == ~T10_E~0); 27086#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27087#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27982#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28000#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28002#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27418#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27419#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27284#L1298-3 assume !(1 == ~E_7~0); 27285#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27740#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27281#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27282#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 27088#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27089#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 27028#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27439#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 27878#L1663 assume !(0 == start_simulation_~tmp~3#1); 26914#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 27642#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 26865#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 27563#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26809#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26810#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27148#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28067#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 27171#L1644-2 [2021-12-19 19:17:38,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,671 INFO L85 PathProgramCache]: Analyzing trace with hash -1778026138, now seen corresponding path program 1 times [2021-12-19 19:17:38,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29455270] [2021-12-19 19:17:38,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,712 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29455270] [2021-12-19 19:17:38,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29455270] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,712 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2120582245] [2021-12-19 19:17:38,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,714 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1771516014, now seen corresponding path program 1 times [2021-12-19 19:17:38,715 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,715 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407870427] [2021-12-19 19:17:38,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,746 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407870427] [2021-12-19 19:17:38,746 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407870427] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,746 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,746 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,746 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679361818] [2021-12-19 19:17:38,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,747 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,747 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,748 INFO L87 Difference]: Start difference. First operand 1476 states and 2185 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,765 INFO L93 Difference]: Finished difference Result 1476 states and 2184 transitions. [2021-12-19 19:17:38,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2184 transitions. [2021-12-19 19:17:38,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-12-19 19:17:38,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2184 transitions. [2021-12-19 19:17:38,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,781 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-12-19 19:17:38,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2184 transitions. [2021-12-19 19:17:38,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4796747967479675) internal successors, (2184), 1475 states have internal predecessors, (2184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2184 transitions. [2021-12-19 19:17:38,797 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-12-19 19:17:38,797 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2184 transitions. [2021-12-19 19:17:38,797 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:38,798 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2184 transitions. [2021-12-19 19:17:38,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,804 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,805 INFO L791 eck$LassoCheckResult]: Stem: 30727#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 30737#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30738#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30503#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 30504#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30373#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30285#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30008#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29643#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29644#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29692#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29693#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30621#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30622#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30660#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30108#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30109#L1090 assume !(0 == ~M_E~0); 30154#L1090-2 assume !(0 == ~T1_E~0); 30155#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30798#L1100-1 assume !(0 == ~T3_E~0); 30799#L1105-1 assume !(0 == ~T4_E~0); 29927#L1110-1 assume !(0 == ~T5_E~0); 29928#L1115-1 assume !(0 == ~T6_E~0); 30323#L1120-1 assume !(0 == ~T7_E~0); 30600#L1125-1 assume !(0 == ~T8_E~0); 31069#L1130-1 assume !(0 == ~T9_E~0); 30818#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30113#L1140-1 assume !(0 == ~T11_E~0); 30114#L1145-1 assume !(0 == ~E_1~0); 30752#L1150-1 assume !(0 == ~E_2~0); 30298#L1155-1 assume !(0 == ~E_3~0); 30299#L1160-1 assume !(0 == ~E_4~0); 30381#L1165-1 assume !(0 == ~E_5~0); 30382#L1170-1 assume !(0 == ~E_6~0); 30990#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 30459#L1180-1 assume !(0 == ~E_8~0); 30460#L1185-1 assume !(0 == ~E_9~0); 30110#L1190-1 assume !(0 == ~E_10~0); 30111#L1195-1 assume !(0 == ~E_11~0); 30473#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30320#L525 assume !(1 == ~m_pc~0); 29731#L525-2 is_master_triggered_~__retres1~0#1 := 0; 29732#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30477#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30478#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30097#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30098#L544 assume 1 == ~t1_pc~0; 30358#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30322#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30750#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29948#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 29949#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30571#L563 assume !(1 == ~t2_pc~0); 30739#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29752#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29753#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30184#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 30185#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30644#L582 assume 1 == ~t3_pc~0; 29892#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29893#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31041#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30999#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 29826#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29827#L601 assume !(1 == ~t4_pc~0); 30767#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30324#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30325#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30761#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 30762#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31033#L620 assume 1 == ~t5_pc~0; 29785#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29786#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30596#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30597#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 31048#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31049#L639 assume !(1 == ~t6_pc~0); 30598#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 30221#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30222#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31002#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 30332#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30333#L658 assume 1 == ~t7_pc~0; 30599#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30526#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30631#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30632#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 30104#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30105#L677 assume 1 == ~t8_pc~0; 30337#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29907#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29908#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30178#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 30179#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30857#L696 assume !(1 == ~t9_pc~0); 30584#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 30585#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30675#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30604#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30605#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30802#L715 assume 1 == ~t10_pc~0; 30806#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30689#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30574#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30575#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 30451#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29901#L734 assume !(1 == ~t11_pc~0); 29902#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 30385#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30464#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29633#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 29634#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30659#L1213 assume !(1 == ~M_E~0); 30449#L1213-2 assume !(1 == ~T1_E~0); 30450#L1218-1 assume !(1 == ~T2_E~0); 29668#L1223-1 assume !(1 == ~T3_E~0); 29669#L1228-1 assume !(1 == ~T4_E~0); 30428#L1233-1 assume !(1 == ~T5_E~0); 31050#L1238-1 assume !(1 == ~T6_E~0); 30759#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30760#L1248-1 assume !(1 == ~T8_E~0); 30804#L1253-1 assume !(1 == ~T9_E~0); 30805#L1258-1 assume !(1 == ~T10_E~0); 30783#L1263-1 assume !(1 == ~T11_E~0); 30784#L1268-1 assume !(1 == ~E_1~0); 30619#L1273-1 assume !(1 == ~E_2~0); 30620#L1278-1 assume !(1 == ~E_3~0); 30219#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 30220#L1288-1 assume !(1 == ~E_5~0); 30897#L1293-1 assume !(1 == ~E_6~0); 30861#L1298-1 assume !(1 == ~E_7~0); 30647#L1303-1 assume !(1 == ~E_8~0); 30230#L1308-1 assume !(1 == ~E_9~0); 30119#L1313-1 assume !(1 == ~E_10~0); 30120#L1318-1 assume !(1 == ~E_11~0); 30132#L1323-1 assume { :end_inline_reset_delta_events } true; 30133#L1644-2 [2021-12-19 19:17:38,805 INFO L793 eck$LassoCheckResult]: Loop: 30133#L1644-2 assume !false; 30700#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30701#L1065 assume !false; 30776#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31046#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29750#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30962#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30235#L906 assume !(0 != eval_~tmp~0#1); 30237#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30774#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30775#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30966#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30929#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30930#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30003#L1110-3 assume !(0 == ~T5_E~0); 30004#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30286#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30287#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30757#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31011#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30211#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29706#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29707#L1150-3 assume !(0 == ~E_2~0); 29829#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29830#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30190#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30191#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30563#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30100#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29861#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29862#L1190-3 assume !(0 == ~E_10~0); 31005#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31006#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30413#L525-36 assume !(1 == ~m_pc~0); 30414#L525-38 is_master_triggered_~__retres1~0#1 := 0; 29964#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29965#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30245#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30246#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30151#L544-36 assume 1 == ~t1_pc~0; 30152#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30678#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30044#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30987#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30890#L563-36 assume 1 == ~t2_pc~0; 29946#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29702#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29703#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30765#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30426#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30427#L582-36 assume 1 == ~t3_pc~0; 30277#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30278#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30502#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30669#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30463#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30407#L601-36 assume 1 == ~t4_pc~0; 30306#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30307#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31054#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30972#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30973#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30878#L620-36 assume 1 == ~t5_pc~0; 30346#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30347#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30740#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30334#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29968#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29746#L639-36 assume 1 == ~t6_pc~0; 29747#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29783#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29784#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30024#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30603#L658-36 assume 1 == ~t7_pc~0; 29863#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29758#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30957#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29733#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 29734#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30724#L677-36 assume !(1 == ~t8_pc~0); 30528#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 30529#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30645#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31029#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30551#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30552#L696-36 assume 1 == ~t9_pc~0; 30445#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30447#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29806#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29807#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30564#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30565#L715-36 assume !(1 == ~t10_pc~0); 30535#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 29631#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29632#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29607#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29608#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30012#L734-36 assume 1 == ~t11_pc~0; 30013#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29712#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30034#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29625#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29626#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30625#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30292#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30293#L1218-3 assume !(1 == ~T2_E~0); 30063#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30064#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30253#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30254#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30498#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30499#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30970#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30975#L1258-3 assume !(1 == ~T10_E~0); 30045#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30046#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30941#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30959#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30961#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30377#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30378#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30243#L1298-3 assume !(1 == ~E_7~0); 30244#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30699#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30240#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30241#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30047#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30048#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29987#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30398#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 30837#L1663 assume !(0 == start_simulation_~tmp~3#1); 29880#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 30601#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 29824#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 30520#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29768#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29769#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30107#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 31026#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 30133#L1644-2 [2021-12-19 19:17:38,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,806 INFO L85 PathProgramCache]: Analyzing trace with hash 1655107556, now seen corresponding path program 1 times [2021-12-19 19:17:38,806 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,806 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002805030] [2021-12-19 19:17:38,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,807 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,831 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002805030] [2021-12-19 19:17:38,831 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002805030] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,831 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,831 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,832 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589841268] [2021-12-19 19:17:38,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,832 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,833 INFO L85 PathProgramCache]: Analyzing trace with hash -814695250, now seen corresponding path program 1 times [2021-12-19 19:17:38,833 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,833 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344076043] [2021-12-19 19:17:38,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,862 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,862 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344076043] [2021-12-19 19:17:38,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344076043] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422530184] [2021-12-19 19:17:38,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,864 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,864 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,865 INFO L87 Difference]: Start difference. First operand 1476 states and 2184 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,882 INFO L93 Difference]: Finished difference Result 1476 states and 2183 transitions. [2021-12-19 19:17:38,882 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1476 states and 2183 transitions. [2021-12-19 19:17:38,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-12-19 19:17:38,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1476 [2021-12-19 19:17:38,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1476 [2021-12-19 19:17:38,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1476 states and 2183 transitions. [2021-12-19 19:17:38,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,894 INFO L681 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-12-19 19:17:38,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1476 states and 2183 transitions. [2021-12-19 19:17:38,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1476 to 1476. [2021-12-19 19:17:38,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1476 states, 1476 states have (on average 1.4789972899728998) internal successors, (2183), 1475 states have internal predecessors, (2183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 1476 states and 2183 transitions. [2021-12-19 19:17:38,909 INFO L704 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-12-19 19:17:38,909 INFO L587 BuchiCegarLoop]: Abstraction has 1476 states and 2183 transitions. [2021-12-19 19:17:38,909 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:38,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1476 states and 2183 transitions. [2021-12-19 19:17:38,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1327 [2021-12-19 19:17:38,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,913 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,913 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,914 INFO L791 eck$LassoCheckResult]: Stem: 33686#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 33687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33694#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33695#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33462#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 33463#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33332#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33244#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32967#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32602#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32603#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32651#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32652#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33580#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33581#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33619#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 33067#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33068#L1090 assume !(0 == ~M_E~0); 33110#L1090-2 assume !(0 == ~T1_E~0); 33111#L1095-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33756#L1100-1 assume !(0 == ~T3_E~0); 33757#L1105-1 assume !(0 == ~T4_E~0); 32885#L1110-1 assume !(0 == ~T5_E~0); 32886#L1115-1 assume !(0 == ~T6_E~0); 33282#L1120-1 assume !(0 == ~T7_E~0); 33559#L1125-1 assume !(0 == ~T8_E~0); 34028#L1130-1 assume !(0 == ~T9_E~0); 33777#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33072#L1140-1 assume !(0 == ~T11_E~0); 33073#L1145-1 assume !(0 == ~E_1~0); 33711#L1150-1 assume !(0 == ~E_2~0); 33257#L1155-1 assume !(0 == ~E_3~0); 33258#L1160-1 assume !(0 == ~E_4~0); 33340#L1165-1 assume !(0 == ~E_5~0); 33341#L1170-1 assume !(0 == ~E_6~0); 33949#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 33418#L1180-1 assume !(0 == ~E_8~0); 33419#L1185-1 assume !(0 == ~E_9~0); 33069#L1190-1 assume !(0 == ~E_10~0); 33070#L1195-1 assume !(0 == ~E_11~0); 33432#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33272#L525 assume !(1 == ~m_pc~0); 32690#L525-2 is_master_triggered_~__retres1~0#1 := 0; 32691#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33436#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33437#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33056#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33057#L544 assume 1 == ~t1_pc~0; 33317#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33281#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33709#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32907#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 32908#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33530#L563 assume !(1 == ~t2_pc~0); 33696#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32711#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32712#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33140#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 33141#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L582 assume 1 == ~t3_pc~0; 32849#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32850#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34000#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33958#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 32785#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32786#L601 assume !(1 == ~t4_pc~0); 33726#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33283#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33284#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33720#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 33721#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33992#L620 assume 1 == ~t5_pc~0; 32740#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32741#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33555#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33556#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 34007#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34008#L639 assume !(1 == ~t6_pc~0); 33557#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 33180#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33181#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33961#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 33291#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33292#L658 assume 1 == ~t7_pc~0; 33558#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33483#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33590#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33591#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 33063#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33064#L677 assume 1 == ~t8_pc~0; 33294#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32866#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32867#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33137#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 33138#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33816#L696 assume !(1 == ~t9_pc~0); 33541#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33542#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33631#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33563#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33564#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33761#L715 assume 1 == ~t10_pc~0; 33765#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33648#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33533#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33534#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 33410#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32858#L734 assume !(1 == ~t11_pc~0); 32859#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 33344#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33423#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32590#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 32591#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33618#L1213 assume !(1 == ~M_E~0); 33407#L1213-2 assume !(1 == ~T1_E~0); 33408#L1218-1 assume !(1 == ~T2_E~0); 32627#L1223-1 assume !(1 == ~T3_E~0); 32628#L1228-1 assume !(1 == ~T4_E~0); 33387#L1233-1 assume !(1 == ~T5_E~0); 34009#L1238-1 assume !(1 == ~T6_E~0); 33718#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33719#L1248-1 assume !(1 == ~T8_E~0); 33763#L1253-1 assume !(1 == ~T9_E~0); 33764#L1258-1 assume !(1 == ~T10_E~0); 33742#L1263-1 assume !(1 == ~T11_E~0); 33743#L1268-1 assume !(1 == ~E_1~0); 33578#L1273-1 assume !(1 == ~E_2~0); 33579#L1278-1 assume !(1 == ~E_3~0); 33178#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33179#L1288-1 assume !(1 == ~E_5~0); 33856#L1293-1 assume !(1 == ~E_6~0); 33820#L1298-1 assume !(1 == ~E_7~0); 33606#L1303-1 assume !(1 == ~E_8~0); 33189#L1308-1 assume !(1 == ~E_9~0); 33078#L1313-1 assume !(1 == ~E_10~0); 33079#L1318-1 assume !(1 == ~E_11~0); 33088#L1323-1 assume { :end_inline_reset_delta_events } true; 33089#L1644-2 [2021-12-19 19:17:38,914 INFO L793 eck$LassoCheckResult]: Loop: 33089#L1644-2 assume !false; 33659#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33660#L1065 assume !false; 33735#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34005#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32709#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33921#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33194#L906 assume !(0 != eval_~tmp~0#1); 33196#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33732#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33733#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33873#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33925#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33888#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33889#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32962#L1110-3 assume !(0 == ~T5_E~0); 32963#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33245#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33246#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33716#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33970#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33168#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32663#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32664#L1150-3 assume !(0 == ~E_2~0); 32787#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32788#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33149#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33150#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33522#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33059#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32817#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32818#L1190-3 assume !(0 == ~E_10~0); 33964#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33965#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33372#L525-36 assume !(1 == ~m_pc~0); 33373#L525-38 is_master_triggered_~__retres1~0#1 := 0; 32918#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32919#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33204#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33205#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33113#L544-36 assume 1 == ~t1_pc~0; 33114#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33637#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33002#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33003#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33946#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33849#L563-36 assume 1 == ~t2_pc~0; 32905#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32661#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32662#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33724#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33385#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33386#L582-36 assume 1 == ~t3_pc~0; 33236#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33237#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33461#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33628#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33422#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33366#L601-36 assume 1 == ~t4_pc~0; 33265#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33266#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34013#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33931#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33932#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33837#L620-36 assume 1 == ~t5_pc~0; 33307#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33308#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33699#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33293#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32927#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32705#L639-36 assume 1 == ~t6_pc~0; 32706#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32745#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32746#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32985#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32986#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33562#L658-36 assume 1 == ~t7_pc~0; 32824#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32717#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32692#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 32693#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33683#L677-36 assume 1 == ~t8_pc~0; 33861#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33488#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33604#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33988#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33510#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33511#L696-36 assume 1 == ~t9_pc~0; 33404#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33406#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32765#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32766#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33523#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33524#L715-36 assume !(1 == ~t10_pc~0); 33494#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 32592#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32593#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32566#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32567#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32971#L734-36 assume 1 == ~t11_pc~0; 32972#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32671#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32993#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32584#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32585#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33584#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33253#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33254#L1218-3 assume !(1 == ~T2_E~0); 33022#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33023#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33212#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33213#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33457#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33458#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33930#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33935#L1258-3 assume !(1 == ~T10_E~0); 33004#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33005#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33900#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33918#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33920#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33336#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33337#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33202#L1298-3 assume !(1 == ~E_7~0); 33203#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33658#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33199#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33200#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33006#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33007#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32946#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33357#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 33796#L1663 assume !(0 == start_simulation_~tmp~3#1); 32839#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 33560#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 32783#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33481#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 32727#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32728#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33066#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 33985#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 33089#L1644-2 [2021-12-19 19:17:38,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,915 INFO L85 PathProgramCache]: Analyzing trace with hash -589450842, now seen corresponding path program 1 times [2021-12-19 19:17:38,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736803135] [2021-12-19 19:17:38,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,942 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,942 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736803135] [2021-12-19 19:17:38,942 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736803135] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,943 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,944 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,944 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913676784] [2021-12-19 19:17:38,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,945 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1091788943, now seen corresponding path program 1 times [2021-12-19 19:17:38,945 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,945 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217418770] [2021-12-19 19:17:38,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,946 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,969 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217418770] [2021-12-19 19:17:38,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217418770] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,969 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,969 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,969 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445945233] [2021-12-19 19:17:38,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,970 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,970 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:38,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:38,971 INFO L87 Difference]: Start difference. First operand 1476 states and 2183 transitions. cyclomatic complexity: 708 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,076 INFO L93 Difference]: Finished difference Result 2717 states and 4005 transitions. [2021-12-19 19:17:39,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,077 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2717 states and 4005 transitions. [2021-12-19 19:17:39,085 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2545 [2021-12-19 19:17:39,097 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2717 states to 2717 states and 4005 transitions. [2021-12-19 19:17:39,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2717 [2021-12-19 19:17:39,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2717 [2021-12-19 19:17:39,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2717 states and 4005 transitions. [2021-12-19 19:17:39,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,101 INFO L681 BuchiCegarLoop]: Abstraction has 2717 states and 4005 transitions. [2021-12-19 19:17:39,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2717 states and 4005 transitions. [2021-12-19 19:17:39,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2717 to 2717. [2021-12-19 19:17:39,132 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2717 states, 2717 states have (on average 1.4740522635259476) internal successors, (4005), 2716 states have internal predecessors, (4005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2717 states to 2717 states and 4005 transitions. [2021-12-19 19:17:39,136 INFO L704 BuchiCegarLoop]: Abstraction has 2717 states and 4005 transitions. [2021-12-19 19:17:39,136 INFO L587 BuchiCegarLoop]: Abstraction has 2717 states and 4005 transitions. [2021-12-19 19:17:39,136 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:39,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2717 states and 4005 transitions. [2021-12-19 19:17:39,141 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2545 [2021-12-19 19:17:39,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,143 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,143 INFO L791 eck$LassoCheckResult]: Stem: 37899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 37900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 37907#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37908#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37671#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 37672#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37540#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37452#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37172#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36805#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36806#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36854#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36855#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37791#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37792#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37831#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37274#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37275#L1090 assume !(0 == ~M_E~0); 37318#L1090-2 assume !(0 == ~T1_E~0); 37319#L1095-1 assume !(0 == ~T2_E~0); 37971#L1100-1 assume !(0 == ~T3_E~0); 37972#L1105-1 assume !(0 == ~T4_E~0); 37088#L1110-1 assume !(0 == ~T5_E~0); 37089#L1115-1 assume !(0 == ~T6_E~0); 37490#L1120-1 assume !(0 == ~T7_E~0); 37770#L1125-1 assume !(0 == ~T8_E~0); 38271#L1130-1 assume !(0 == ~T9_E~0); 37992#L1135-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37279#L1140-1 assume !(0 == ~T11_E~0); 37280#L1145-1 assume !(0 == ~E_1~0); 37924#L1150-1 assume !(0 == ~E_2~0); 37465#L1155-1 assume !(0 == ~E_3~0); 37466#L1160-1 assume !(0 == ~E_4~0); 37548#L1165-1 assume !(0 == ~E_5~0); 37549#L1170-1 assume !(0 == ~E_6~0); 38174#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 37627#L1180-1 assume !(0 == ~E_8~0); 37628#L1185-1 assume !(0 == ~E_9~0); 37276#L1190-1 assume !(0 == ~E_10~0); 37277#L1195-1 assume !(0 == ~E_11~0); 37641#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37480#L525 assume !(1 == ~m_pc~0); 36893#L525-2 is_master_triggered_~__retres1~0#1 := 0; 36894#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37645#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37646#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37262#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37263#L544 assume 1 == ~t1_pc~0; 37525#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37489#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37922#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37110#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 37111#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37741#L563 assume !(1 == ~t2_pc~0); 37909#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36914#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36915#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37348#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 37349#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37815#L582 assume 1 == ~t3_pc~0; 37052#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37053#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38236#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38183#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 36988#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36989#L601 assume !(1 == ~t4_pc~0); 37939#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37491#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37492#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37933#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 37934#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38224#L620 assume 1 == ~t5_pc~0; 36943#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36944#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37766#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37767#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 38247#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38248#L639 assume !(1 == ~t6_pc~0); 37768#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37388#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37389#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38186#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 37499#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37500#L658 assume 1 == ~t7_pc~0; 37769#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37692#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37802#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37803#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 37269#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37270#L677 assume 1 == ~t8_pc~0; 37502#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37069#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37070#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37345#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 37346#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38031#L696 assume !(1 == ~t9_pc~0); 37752#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 37753#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37843#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37774#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37775#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37976#L715 assume 1 == ~t10_pc~0; 37980#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37861#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37744#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37745#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 37619#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37061#L734 assume !(1 == ~t11_pc~0); 37062#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 37552#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37632#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36793#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 36794#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37830#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 38222#L1213-2 assume !(1 == ~T1_E~0); 38880#L1218-1 assume !(1 == ~T2_E~0); 38094#L1223-1 assume !(1 == ~T3_E~0); 38879#L1228-1 assume !(1 == ~T4_E~0); 38878#L1233-1 assume !(1 == ~T5_E~0); 38877#L1238-1 assume !(1 == ~T6_E~0); 38876#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38872#L1248-1 assume !(1 == ~T8_E~0); 37978#L1253-1 assume !(1 == ~T9_E~0); 37979#L1258-1 assume !(1 == ~T10_E~0); 38187#L1263-1 assume !(1 == ~T11_E~0); 38512#L1268-1 assume !(1 == ~E_1~0); 37789#L1273-1 assume !(1 == ~E_2~0); 37790#L1278-1 assume !(1 == ~E_3~0); 38403#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 38402#L1288-1 assume !(1 == ~E_5~0); 38401#L1293-1 assume !(1 == ~E_6~0); 38400#L1298-1 assume !(1 == ~E_7~0); 38399#L1303-1 assume !(1 == ~E_8~0); 38398#L1308-1 assume !(1 == ~E_9~0); 38397#L1313-1 assume !(1 == ~E_10~0); 38396#L1318-1 assume !(1 == ~E_11~0); 38394#L1323-1 assume { :end_inline_reset_delta_events } true; 38314#L1644-2 [2021-12-19 19:17:39,144 INFO L793 eck$LassoCheckResult]: Loop: 38314#L1644-2 assume !false; 38309#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38305#L1065 assume !false; 38244#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38245#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 36912#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38139#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38290#L906 assume !(0 != eval_~tmp~0#1); 38289#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38288#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38287#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38145#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38146#L1095-3 assume !(0 == ~T2_E~0); 38106#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38107#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37167#L1110-3 assume !(0 == ~T5_E~0); 37168#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37453#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37454#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37929#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38197#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37376#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36866#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36867#L1150-3 assume !(0 == ~E_2~0); 36990#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36991#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37357#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37358#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37732#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37265#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37020#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37021#L1190-3 assume !(0 == ~E_10~0); 38191#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38192#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37580#L525-36 assume !(1 == ~m_pc~0); 37581#L525-38 is_master_triggered_~__retres1~0#1 := 0; 37121#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37122#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37412#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37413#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37321#L544-36 assume 1 == ~t1_pc~0; 37322#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37850#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37208#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37209#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38171#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38064#L563-36 assume 1 == ~t2_pc~0; 37108#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36864#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36865#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37937#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37593#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37594#L582-36 assume 1 == ~t3_pc~0; 37444#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37445#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37670#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37840#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37631#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37574#L601-36 assume 1 == ~t4_pc~0; 37473#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37474#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38253#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38152#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38153#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38052#L620-36 assume 1 == ~t5_pc~0; 37515#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37516#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37912#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37501#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37130#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36908#L639-36 assume 1 == ~t6_pc~0; 36909#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36948#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36949#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37191#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37192#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37773#L658-36 assume 1 == ~t7_pc~0; 37027#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36920#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38134#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36895#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 36896#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37896#L677-36 assume !(1 == ~t8_pc~0); 37696#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 37697#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37816#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38219#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37719#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37720#L696-36 assume 1 == ~t9_pc~0; 37613#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37615#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36968#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36969#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37733#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37734#L715-36 assume !(1 == ~t10_pc~0); 37703#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 36795#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36796#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36769#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36770#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37176#L734-36 assume !(1 == ~t11_pc~0); 36873#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 36874#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37199#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36787#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36788#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37795#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37461#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37462#L1218-3 assume !(1 == ~T2_E~0); 37228#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37229#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37420#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37421#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37666#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37667#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38151#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38158#L1258-3 assume !(1 == ~T10_E~0); 37210#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37211#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38118#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38136#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38138#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37544#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37545#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37410#L1298-3 assume !(1 == ~E_7~0); 37411#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37871#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37407#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37408#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37212#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37213#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37151#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 37565#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 38011#L1663 assume !(0 == start_simulation_~tmp~3#1); 37042#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38270#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 38406#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38405#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 38404#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37272#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37273#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 38264#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 38314#L1644-2 [2021-12-19 19:17:39,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1997054246, now seen corresponding path program 1 times [2021-12-19 19:17:39,144 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244577600] [2021-12-19 19:17:39,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244577600] [2021-12-19 19:17:39,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244577600] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295269360] [2021-12-19 19:17:39,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,191 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,192 INFO L85 PathProgramCache]: Analyzing trace with hash 1999917771, now seen corresponding path program 1 times [2021-12-19 19:17:39,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847968014] [2021-12-19 19:17:39,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,213 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,213 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [847968014] [2021-12-19 19:17:39,213 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [847968014] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,213 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,214 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079766119] [2021-12-19 19:17:39,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,214 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,214 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:39,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:39,215 INFO L87 Difference]: Start difference. First operand 2717 states and 4005 transitions. cyclomatic complexity: 1290 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,314 INFO L93 Difference]: Finished difference Result 5187 states and 7626 transitions. [2021-12-19 19:17:39,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,315 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5187 states and 7626 transitions. [2021-12-19 19:17:39,330 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4981 [2021-12-19 19:17:39,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5187 states to 5187 states and 7626 transitions. [2021-12-19 19:17:39,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5187 [2021-12-19 19:17:39,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5187 [2021-12-19 19:17:39,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5187 states and 7626 transitions. [2021-12-19 19:17:39,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,349 INFO L681 BuchiCegarLoop]: Abstraction has 5187 states and 7626 transitions. [2021-12-19 19:17:39,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5187 states and 7626 transitions. [2021-12-19 19:17:39,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5187 to 5187. [2021-12-19 19:17:39,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5187 states, 5187 states have (on average 1.470213996529786) internal successors, (7626), 5186 states have internal predecessors, (7626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5187 states to 5187 states and 7626 transitions. [2021-12-19 19:17:39,414 INFO L704 BuchiCegarLoop]: Abstraction has 5187 states and 7626 transitions. [2021-12-19 19:17:39,414 INFO L587 BuchiCegarLoop]: Abstraction has 5187 states and 7626 transitions. [2021-12-19 19:17:39,414 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:39,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5187 states and 7626 transitions. [2021-12-19 19:17:39,425 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4981 [2021-12-19 19:17:39,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,426 INFO L791 eck$LassoCheckResult]: Stem: 45808#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 45809#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 45820#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45821#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45581#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 45582#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45450#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45362#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45084#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44719#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44720#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44768#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44769#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45701#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45702#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45742#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45184#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45185#L1090 assume !(0 == ~M_E~0); 45231#L1090-2 assume !(0 == ~T1_E~0); 45232#L1095-1 assume !(0 == ~T2_E~0); 45882#L1100-1 assume !(0 == ~T3_E~0); 45883#L1105-1 assume !(0 == ~T4_E~0); 45003#L1110-1 assume !(0 == ~T5_E~0); 45004#L1115-1 assume !(0 == ~T6_E~0); 45400#L1120-1 assume !(0 == ~T7_E~0); 45679#L1125-1 assume !(0 == ~T8_E~0); 46175#L1130-1 assume !(0 == ~T9_E~0); 45902#L1135-1 assume !(0 == ~T10_E~0); 45189#L1140-1 assume !(0 == ~T11_E~0); 45190#L1145-1 assume !(0 == ~E_1~0); 45836#L1150-1 assume !(0 == ~E_2~0); 45375#L1155-1 assume !(0 == ~E_3~0); 45376#L1160-1 assume !(0 == ~E_4~0); 45458#L1165-1 assume !(0 == ~E_5~0); 45459#L1170-1 assume !(0 == ~E_6~0); 46080#L1175-1 assume 0 == ~E_7~0;~E_7~0 := 1; 45537#L1180-1 assume !(0 == ~E_8~0); 45538#L1185-1 assume !(0 == ~E_9~0); 45186#L1190-1 assume !(0 == ~E_10~0); 45187#L1195-1 assume !(0 == ~E_11~0); 45551#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45397#L525 assume !(1 == ~m_pc~0); 44807#L525-2 is_master_triggered_~__retres1~0#1 := 0; 44808#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45555#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45556#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45173#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45174#L544 assume 1 == ~t1_pc~0; 45435#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45399#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45833#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45024#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 45025#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45650#L563 assume !(1 == ~t2_pc~0); 45822#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44828#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44829#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45261#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 45262#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45723#L582 assume 1 == ~t3_pc~0; 44968#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44969#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46140#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46089#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 44902#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44903#L601 assume !(1 == ~t4_pc~0); 45851#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45401#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45402#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45845#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 45846#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46131#L620 assume 1 == ~t5_pc~0; 44861#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44862#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45675#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45676#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 46151#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46152#L639 assume !(1 == ~t6_pc~0); 45677#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45298#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45299#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46093#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 45409#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45410#L658 assume 1 == ~t7_pc~0; 45678#L659 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45604#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45710#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45711#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 45180#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45181#L677 assume 1 == ~t8_pc~0; 45414#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44983#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44984#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45255#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 45256#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45942#L696 assume !(1 == ~t9_pc~0); 45663#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 45664#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45754#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45685#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45686#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45886#L715 assume 1 == ~t10_pc~0; 45890#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45768#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45653#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45654#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 45529#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44977#L734 assume !(1 == ~t11_pc~0); 44978#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 45462#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45542#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44709#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 44710#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45738#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 46129#L1213-2 assume !(1 == ~T1_E~0); 46005#L1218-1 assume !(1 == ~T2_E~0); 46006#L1223-1 assume !(1 == ~T3_E~0); 46458#L1228-1 assume !(1 == ~T4_E~0); 46153#L1233-1 assume !(1 == ~T5_E~0); 46154#L1238-1 assume !(1 == ~T6_E~0); 45843#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45844#L1248-1 assume !(1 == ~T8_E~0); 45888#L1253-1 assume !(1 == ~T9_E~0); 45889#L1258-1 assume !(1 == ~T10_E~0); 46352#L1263-1 assume !(1 == ~T11_E~0); 46350#L1268-1 assume !(1 == ~E_1~0); 46348#L1273-1 assume !(1 == ~E_2~0); 46345#L1278-1 assume !(1 == ~E_3~0); 46343#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46341#L1288-1 assume !(1 == ~E_5~0); 46339#L1293-1 assume !(1 == ~E_6~0); 46287#L1298-1 assume !(1 == ~E_7~0); 46274#L1303-1 assume !(1 == ~E_8~0); 46272#L1308-1 assume !(1 == ~E_9~0); 46255#L1313-1 assume !(1 == ~E_10~0); 46244#L1318-1 assume !(1 == ~E_11~0); 46235#L1323-1 assume { :end_inline_reset_delta_events } true; 46227#L1644-2 [2021-12-19 19:17:39,427 INFO L793 eck$LassoCheckResult]: Loop: 46227#L1644-2 assume !false; 46221#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46216#L1065 assume !false; 46215#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46212#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46202#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46201#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46199#L906 assume !(0 != eval_~tmp~0#1); 46198#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46197#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46195#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46196#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47569#L1095-3 assume !(0 == ~T2_E~0); 47560#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47552#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47545#L1110-3 assume !(0 == ~T5_E~0); 47536#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47531#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47526#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47517#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47515#L1135-3 assume !(0 == ~T10_E~0); 47513#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47511#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47509#L1150-3 assume !(0 == ~E_2~0); 47507#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47505#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47503#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47501#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47499#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47497#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47495#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47493#L1190-3 assume !(0 == ~E_10~0); 47487#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47482#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47476#L525-36 assume 1 == ~m_pc~0; 47470#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47465#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47459#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47452#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47447#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47441#L544-36 assume 1 == ~t1_pc~0; 47435#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47430#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47424#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47417#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47412#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47406#L563-36 assume !(1 == ~t2_pc~0); 47400#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 47395#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47384#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47375#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47269#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47266#L582-36 assume !(1 == ~t3_pc~0); 47264#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 47261#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47259#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47257#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47255#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47254#L601-36 assume !(1 == ~t4_pc~0); 47252#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 47249#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47247#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47245#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47243#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47241#L620-36 assume 1 == ~t5_pc~0; 47238#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47235#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47233#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47231#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47229#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47227#L639-36 assume !(1 == ~t6_pc~0); 47223#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 47221#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47219#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47216#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47215#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47213#L658-36 assume 1 == ~t7_pc~0; 47210#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47207#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47205#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47203#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 47201#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47199#L677-36 assume 1 == ~t8_pc~0; 47196#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47193#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47191#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47189#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47187#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47075#L696-36 assume !(1 == ~t9_pc~0); 47072#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 47070#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47068#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46984#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46982#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46980#L715-36 assume 1 == ~t10_pc~0; 46977#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46976#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46973#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46971#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46969#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46967#L734-36 assume !(1 == ~t11_pc~0); 46964#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 46882#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46829#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46826#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46824#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46822#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46101#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46819#L1218-3 assume !(1 == ~T2_E~0); 45804#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46815#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46813#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46811#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46799#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46785#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46736#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46629#L1258-3 assume !(1 == ~T10_E~0); 46627#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46625#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46623#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46622#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46526#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46469#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46462#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46456#L1298-3 assume !(1 == ~E_7~0); 46449#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46443#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46436#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46429#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46424#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46327#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46314#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46312#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 46310#L1663 assume !(0 == start_simulation_~tmp~3#1); 44956#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46279#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46273#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46271#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 46266#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46254#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46243#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 46234#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 46227#L1644-2 [2021-12-19 19:17:39,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,428 INFO L85 PathProgramCache]: Analyzing trace with hash -134296476, now seen corresponding path program 1 times [2021-12-19 19:17:39,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584283391] [2021-12-19 19:17:39,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,458 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,458 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584283391] [2021-12-19 19:17:39,458 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584283391] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,458 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,458 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:39,459 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651031258] [2021-12-19 19:17:39,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,460 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,460 INFO L85 PathProgramCache]: Analyzing trace with hash 350546119, now seen corresponding path program 1 times [2021-12-19 19:17:39,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644912298] [2021-12-19 19:17:39,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,461 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644912298] [2021-12-19 19:17:39,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644912298] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835542016] [2021-12-19 19:17:39,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,488 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,489 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:39,489 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:39,490 INFO L87 Difference]: Start difference. First operand 5187 states and 7626 transitions. cyclomatic complexity: 2443 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,537 INFO L93 Difference]: Finished difference Result 5187 states and 7566 transitions. [2021-12-19 19:17:39,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:39,539 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5187 states and 7566 transitions. [2021-12-19 19:17:39,553 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4981 [2021-12-19 19:17:39,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5187 states to 5187 states and 7566 transitions. [2021-12-19 19:17:39,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5187 [2021-12-19 19:17:39,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5187 [2021-12-19 19:17:39,572 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5187 states and 7566 transitions. [2021-12-19 19:17:39,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,576 INFO L681 BuchiCegarLoop]: Abstraction has 5187 states and 7566 transitions. [2021-12-19 19:17:39,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5187 states and 7566 transitions. [2021-12-19 19:17:39,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5187 to 5187. [2021-12-19 19:17:39,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5187 states, 5187 states have (on average 1.4586466165413534) internal successors, (7566), 5186 states have internal predecessors, (7566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5187 states to 5187 states and 7566 transitions. [2021-12-19 19:17:39,685 INFO L704 BuchiCegarLoop]: Abstraction has 5187 states and 7566 transitions. [2021-12-19 19:17:39,685 INFO L587 BuchiCegarLoop]: Abstraction has 5187 states and 7566 transitions. [2021-12-19 19:17:39,686 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:39,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5187 states and 7566 transitions. [2021-12-19 19:17:39,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4981 [2021-12-19 19:17:39,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,699 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,699 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,700 INFO L791 eck$LassoCheckResult]: Stem: 56190#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 56191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 56199#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56200#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55960#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 55961#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55830#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55742#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55465#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55100#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55101#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55149#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55150#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56081#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56082#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56121#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 55565#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55566#L1090 assume !(0 == ~M_E~0); 55608#L1090-2 assume !(0 == ~T1_E~0); 55609#L1095-1 assume !(0 == ~T2_E~0); 56262#L1100-1 assume !(0 == ~T3_E~0); 56263#L1105-1 assume !(0 == ~T4_E~0); 55383#L1110-1 assume !(0 == ~T5_E~0); 55384#L1115-1 assume !(0 == ~T6_E~0); 55780#L1120-1 assume !(0 == ~T7_E~0); 56059#L1125-1 assume !(0 == ~T8_E~0); 56551#L1130-1 assume !(0 == ~T9_E~0); 56283#L1135-1 assume !(0 == ~T10_E~0); 55570#L1140-1 assume !(0 == ~T11_E~0); 55571#L1145-1 assume !(0 == ~E_1~0); 56216#L1150-1 assume !(0 == ~E_2~0); 55755#L1155-1 assume !(0 == ~E_3~0); 55756#L1160-1 assume !(0 == ~E_4~0); 55838#L1165-1 assume !(0 == ~E_5~0); 55839#L1170-1 assume !(0 == ~E_6~0); 56461#L1175-1 assume !(0 == ~E_7~0); 55916#L1180-1 assume !(0 == ~E_8~0); 55917#L1185-1 assume !(0 == ~E_9~0); 55567#L1190-1 assume !(0 == ~E_10~0); 55568#L1195-1 assume !(0 == ~E_11~0); 55930#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55770#L525 assume !(1 == ~m_pc~0); 55188#L525-2 is_master_triggered_~__retres1~0#1 := 0; 55189#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55934#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55935#L1350 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55554#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55555#L544 assume 1 == ~t1_pc~0; 55815#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55779#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56214#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55405#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 55406#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56030#L563 assume !(1 == ~t2_pc~0); 56201#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55209#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55210#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55638#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 55639#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56105#L582 assume 1 == ~t3_pc~0; 55347#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55348#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56519#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56470#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 55283#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55284#L601 assume !(1 == ~t4_pc~0); 56231#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55781#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55782#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56225#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 56226#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56510#L620 assume 1 == ~t5_pc~0; 55238#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55239#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56055#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56056#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 56527#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56528#L639 assume !(1 == ~t6_pc~0); 56057#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55678#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55679#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56473#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 55789#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55790#L658 assume !(1 == ~t7_pc~0); 55980#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 55981#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56091#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56092#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 55561#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55562#L677 assume 1 == ~t8_pc~0; 55792#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55364#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55365#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55635#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 55636#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56323#L696 assume !(1 == ~t9_pc~0); 56041#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 56042#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56133#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56063#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56064#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56267#L715 assume 1 == ~t10_pc~0; 56271#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56150#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56033#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56034#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 55908#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55356#L734 assume !(1 == ~t11_pc~0); 55357#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 55842#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55921#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55088#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 55089#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56120#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 56508#L1213-2 assume !(1 == ~T1_E~0); 56388#L1218-1 assume !(1 == ~T2_E~0); 55125#L1223-1 assume !(1 == ~T3_E~0); 55126#L1228-1 assume !(1 == ~T4_E~0); 56529#L1233-1 assume !(1 == ~T5_E~0); 56530#L1238-1 assume !(1 == ~T6_E~0); 56223#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56224#L1248-1 assume !(1 == ~T8_E~0); 56269#L1253-1 assume !(1 == ~T9_E~0); 56270#L1258-1 assume !(1 == ~T10_E~0); 56730#L1263-1 assume !(1 == ~T11_E~0); 56728#L1268-1 assume !(1 == ~E_1~0); 56726#L1273-1 assume !(1 == ~E_2~0); 56723#L1278-1 assume !(1 == ~E_3~0); 56721#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56719#L1288-1 assume !(1 == ~E_5~0); 56717#L1293-1 assume !(1 == ~E_6~0); 56665#L1298-1 assume !(1 == ~E_7~0); 56652#L1303-1 assume !(1 == ~E_8~0); 56650#L1308-1 assume !(1 == ~E_9~0); 56633#L1313-1 assume !(1 == ~E_10~0); 56622#L1318-1 assume !(1 == ~E_11~0); 56613#L1323-1 assume { :end_inline_reset_delta_events } true; 56605#L1644-2 [2021-12-19 19:17:39,700 INFO L793 eck$LassoCheckResult]: Loop: 56605#L1644-2 assume !false; 56599#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56594#L1065 assume !false; 56593#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 56590#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56580#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 56579#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56577#L906 assume !(0 != eval_~tmp~0#1); 56576#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56575#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56573#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 56574#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58127#L1095-3 assume !(0 == ~T2_E~0); 58125#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58123#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58121#L1110-3 assume !(0 == ~T5_E~0); 58118#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58038#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58036#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58033#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 58031#L1135-3 assume !(0 == ~T10_E~0); 58018#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58007#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57998#L1150-3 assume !(0 == ~E_2~0); 57994#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56563#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56564#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57959#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57953#L1175-3 assume !(0 == ~E_7~0); 57948#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57942#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57936#L1190-3 assume !(0 == ~E_10~0); 56479#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 56480#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55869#L525-36 assume !(1 == ~m_pc~0); 55870#L525-38 is_master_triggered_~__retres1~0#1 := 0; 55416#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55417#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55702#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55703#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55611#L544-36 assume 1 == ~t1_pc~0; 55612#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56139#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55500#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55501#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56458#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56358#L563-36 assume 1 == ~t2_pc~0; 55403#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55159#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55160#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56229#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55882#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55883#L582-36 assume 1 == ~t3_pc~0; 55734#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55735#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55959#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56130#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55920#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55863#L601-36 assume 1 == ~t4_pc~0; 55763#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55764#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56534#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56442#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56443#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56346#L620-36 assume 1 == ~t5_pc~0; 55805#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55806#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56204#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55791#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55425#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55203#L639-36 assume 1 == ~t6_pc~0; 55204#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55243#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55244#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55483#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 55484#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56062#L658-36 assume !(1 == ~t7_pc~0); 57512#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 57504#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57341#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57338#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 57336#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57334#L677-36 assume 1 == ~t8_pc~0; 57331#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57329#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57327#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57176#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57174#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57171#L696-36 assume 1 == ~t9_pc~0; 57168#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57165#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57163#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57161#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57045#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57043#L715-36 assume 1 == ~t10_pc~0; 57040#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 57038#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57036#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57034#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56984#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56982#L734-36 assume !(1 == ~t11_pc~0); 56979#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 56977#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56975#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56973#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56970#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56968#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56481#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56933#L1218-3 assume !(1 == ~T2_E~0); 56931#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56929#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56927#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56925#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56922#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56920#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56918#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56889#L1258-3 assume !(1 == ~T10_E~0); 56882#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56875#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56868#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56862#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56855#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56848#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56839#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56833#L1298-3 assume !(1 == ~E_7~0); 56826#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56820#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56812#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56806#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56801#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 56705#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56692#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 56690#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 56688#L1663 assume !(0 == start_simulation_~tmp~3#1); 55337#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 56657#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 56651#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 56649#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 56644#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56632#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56621#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 56612#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 56605#L1644-2 [2021-12-19 19:17:39,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1898203903, now seen corresponding path program 1 times [2021-12-19 19:17:39,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,701 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562909406] [2021-12-19 19:17:39,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,732 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,732 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562909406] [2021-12-19 19:17:39,732 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562909406] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,733 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,733 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:39,733 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755434338] [2021-12-19 19:17:39,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,733 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1247070056, now seen corresponding path program 1 times [2021-12-19 19:17:39,734 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,734 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805323663] [2021-12-19 19:17:39,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,734 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,765 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805323663] [2021-12-19 19:17:39,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805323663] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:39,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075012638] [2021-12-19 19:17:39,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,767 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,767 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:39,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:39,768 INFO L87 Difference]: Start difference. First operand 5187 states and 7566 transitions. cyclomatic complexity: 2383 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,984 INFO L93 Difference]: Finished difference Result 15029 states and 21824 transitions. [2021-12-19 19:17:39,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:39,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15029 states and 21824 transitions. [2021-12-19 19:17:40,140 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 14502 [2021-12-19 19:17:40,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15029 states to 15029 states and 21824 transitions. [2021-12-19 19:17:40,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15029 [2021-12-19 19:17:40,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15029 [2021-12-19 19:17:40,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15029 states and 21824 transitions. [2021-12-19 19:17:40,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:40,194 INFO L681 BuchiCegarLoop]: Abstraction has 15029 states and 21824 transitions. [2021-12-19 19:17:40,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15029 states and 21824 transitions. [2021-12-19 19:17:40,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15029 to 5337. [2021-12-19 19:17:40,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5337 states, 5337 states have (on average 1.4457560427206295) internal successors, (7716), 5336 states have internal predecessors, (7716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5337 states to 5337 states and 7716 transitions. [2021-12-19 19:17:40,278 INFO L704 BuchiCegarLoop]: Abstraction has 5337 states and 7716 transitions. [2021-12-19 19:17:40,278 INFO L587 BuchiCegarLoop]: Abstraction has 5337 states and 7716 transitions. [2021-12-19 19:17:40,278 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:40,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5337 states and 7716 transitions. [2021-12-19 19:17:40,288 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5128 [2021-12-19 19:17:40,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:40,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:40,289 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,290 INFO L791 eck$LassoCheckResult]: Stem: 76448#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 76449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 76460#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76461#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76207#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 76208#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76073#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75982#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75699#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75331#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75332#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75380#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75381#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76331#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76332#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76372#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75801#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75802#L1090 assume !(0 == ~M_E~0); 75847#L1090-2 assume !(0 == ~T1_E~0); 75848#L1095-1 assume !(0 == ~T2_E~0); 76523#L1100-1 assume !(0 == ~T3_E~0); 76524#L1105-1 assume !(0 == ~T4_E~0); 75615#L1110-1 assume !(0 == ~T5_E~0); 75616#L1115-1 assume !(0 == ~T6_E~0); 76021#L1120-1 assume !(0 == ~T7_E~0); 76308#L1125-1 assume !(0 == ~T8_E~0); 76867#L1130-1 assume !(0 == ~T9_E~0); 76543#L1135-1 assume !(0 == ~T10_E~0); 75806#L1140-1 assume !(0 == ~T11_E~0); 75807#L1145-1 assume !(0 == ~E_1~0); 76475#L1150-1 assume !(0 == ~E_2~0); 75996#L1155-1 assume !(0 == ~E_3~0); 75997#L1160-1 assume !(0 == ~E_4~0); 76081#L1165-1 assume !(0 == ~E_5~0); 76082#L1170-1 assume !(0 == ~E_6~0); 76744#L1175-1 assume !(0 == ~E_7~0); 76160#L1180-1 assume !(0 == ~E_8~0); 76161#L1185-1 assume !(0 == ~E_9~0); 75803#L1190-1 assume !(0 == ~E_10~0); 75804#L1195-1 assume !(0 == ~E_11~0); 76175#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76018#L525 assume !(1 == ~m_pc~0); 75419#L525-2 is_master_triggered_~__retres1~0#1 := 0; 75420#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76703#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76594#L1350 assume !(0 != activate_threads_~tmp~1#1); 75790#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75791#L544 assume 1 == ~t1_pc~0; 76056#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76020#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76473#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75636#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 75637#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76278#L563 assume !(1 == ~t2_pc~0); 76462#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75440#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75441#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75877#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 75878#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76356#L582 assume 1 == ~t3_pc~0; 75580#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75581#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76817#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76754#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 75514#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75515#L601 assume !(1 == ~t4_pc~0); 76490#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76022#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76023#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76484#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 76485#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76806#L620 assume 1 == ~t5_pc~0; 75473#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75474#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76304#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76305#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 76833#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76834#L639 assume !(1 == ~t6_pc~0); 76306#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75915#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75916#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76757#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 76030#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76031#L658 assume !(1 == ~t7_pc~0); 76229#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76230#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76341#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76342#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 75797#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75798#L677 assume 1 == ~t8_pc~0; 76035#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75595#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75596#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75871#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 75872#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76586#L696 assume !(1 == ~t9_pc~0); 76291#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 76292#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76387#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76313#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76314#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76527#L715 assume 1 == ~t10_pc~0; 76531#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 76401#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76281#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76282#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 76152#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75589#L734 assume !(1 == ~t11_pc~0); 75590#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 76085#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76165#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75321#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 75322#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76371#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 76150#L1213-2 assume !(1 == ~T1_E~0); 76151#L1218-1 assume !(1 == ~T2_E~0); 76659#L1223-1 assume !(1 == ~T3_E~0); 77096#L1228-1 assume !(1 == ~T4_E~0); 77094#L1233-1 assume !(1 == ~T5_E~0); 77092#L1238-1 assume !(1 == ~T6_E~0); 77091#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77090#L1248-1 assume !(1 == ~T8_E~0); 76529#L1253-1 assume !(1 == ~T9_E~0); 76530#L1258-1 assume !(1 == ~T10_E~0); 76999#L1263-1 assume !(1 == ~T11_E~0); 76996#L1268-1 assume !(1 == ~E_1~0); 76994#L1273-1 assume !(1 == ~E_2~0); 76992#L1278-1 assume !(1 == ~E_3~0); 76990#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 76988#L1288-1 assume !(1 == ~E_5~0); 76986#L1293-1 assume !(1 == ~E_6~0); 76973#L1298-1 assume !(1 == ~E_7~0); 76971#L1303-1 assume !(1 == ~E_8~0); 76969#L1308-1 assume !(1 == ~E_9~0); 76957#L1313-1 assume !(1 == ~E_10~0); 76946#L1318-1 assume !(1 == ~E_11~0); 76938#L1323-1 assume { :end_inline_reset_delta_events } true; 76931#L1644-2 [2021-12-19 19:17:40,290 INFO L793 eck$LassoCheckResult]: Loop: 76931#L1644-2 assume !false; 76926#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76921#L1065 assume !false; 76920#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 76917#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76907#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76906#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76904#L906 assume !(0 != eval_~tmp~0#1); 76903#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76902#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76900#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76901#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78131#L1095-3 assume !(0 == ~T2_E~0); 78128#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78127#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78125#L1110-3 assume !(0 == ~T5_E~0); 78056#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78054#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78052#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78050#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78048#L1135-3 assume !(0 == ~T10_E~0); 78046#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78043#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 78041#L1150-3 assume !(0 == ~E_2~0); 78039#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78037#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78035#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78033#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78030#L1175-3 assume !(0 == ~E_7~0); 78028#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 78027#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78026#L1190-3 assume !(0 == ~E_10~0); 78025#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78024#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78023#L525-36 assume 1 == ~m_pc~0; 78021#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 78019#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78017#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78015#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78014#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78013#L544-36 assume 1 == ~t1_pc~0; 78011#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77807#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77804#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77802#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77800#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77798#L563-36 assume !(1 == ~t2_pc~0); 77795#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 77793#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77790#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77788#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77786#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77784#L582-36 assume 1 == ~t3_pc~0; 77781#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77778#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77776#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77774#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77772#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77770#L601-36 assume !(1 == ~t4_pc~0); 77767#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 77765#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77762#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77760#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77758#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77757#L620-36 assume 1 == ~t5_pc~0; 77755#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77754#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77753#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77752#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77751#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77750#L639-36 assume 1 == ~t6_pc~0; 77749#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77747#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77746#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77745#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77744#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77742#L658-36 assume !(1 == ~t7_pc~0); 77739#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 77737#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77734#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77732#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 77730#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77728#L677-36 assume 1 == ~t8_pc~0; 77725#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77723#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77720#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77718#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77716#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77714#L696-36 assume 1 == ~t9_pc~0; 77712#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77708#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77551#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77548#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77546#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77544#L715-36 assume !(1 == ~t10_pc~0); 77369#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 77366#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77364#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77362#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77360#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77358#L734-36 assume !(1 == ~t11_pc~0); 77355#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 77353#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77352#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77350#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77348#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77346#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76764#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77266#L1218-3 assume !(1 == ~T2_E~0); 77264#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77262#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77260#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77258#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77256#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77253#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77251#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77239#L1258-3 assume !(1 == ~T10_E~0); 77237#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77235#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77233#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77231#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77228#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77226#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77224#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77222#L1298-3 assume !(1 == ~E_7~0); 77220#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77218#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77215#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77213#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 77211#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 77041#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 77028#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 77025#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 77023#L1663 assume !(0 == start_simulation_~tmp~3#1); 75568#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 76978#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 76972#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 76970#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 76968#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76956#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76945#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 76937#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 76931#L1644-2 [2021-12-19 19:17:40,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1926704193, now seen corresponding path program 1 times [2021-12-19 19:17:40,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,291 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2038519113] [2021-12-19 19:17:40,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,291 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,318 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2038519113] [2021-12-19 19:17:40,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2038519113] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,318 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,318 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:40,318 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157920496] [2021-12-19 19:17:40,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,319 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:40,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,319 INFO L85 PathProgramCache]: Analyzing trace with hash -1267613786, now seen corresponding path program 1 times [2021-12-19 19:17:40,319 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981103366] [2021-12-19 19:17:40,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981103366] [2021-12-19 19:17:40,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981103366] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,345 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:40,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [800799617] [2021-12-19 19:17:40,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,346 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:40,346 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:40,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:40,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:40,346 INFO L87 Difference]: Start difference. First operand 5337 states and 7716 transitions. cyclomatic complexity: 2383 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:40,464 INFO L93 Difference]: Finished difference Result 10055 states and 14444 transitions. [2021-12-19 19:17:40,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:40,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10055 states and 14444 transitions. [2021-12-19 19:17:40,491 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9843 [2021-12-19 19:17:40,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10055 states to 10055 states and 14444 transitions. [2021-12-19 19:17:40,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10055 [2021-12-19 19:17:40,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10055 [2021-12-19 19:17:40,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10055 states and 14444 transitions. [2021-12-19 19:17:40,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:40,523 INFO L681 BuchiCegarLoop]: Abstraction has 10055 states and 14444 transitions. [2021-12-19 19:17:40,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10055 states and 14444 transitions. [2021-12-19 19:17:40,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10055 to 10047. [2021-12-19 19:17:40,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10047 states, 10047 states have (on average 1.4368468199462525) internal successors, (14436), 10046 states have internal predecessors, (14436), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10047 states to 10047 states and 14436 transitions. [2021-12-19 19:17:40,660 INFO L704 BuchiCegarLoop]: Abstraction has 10047 states and 14436 transitions. [2021-12-19 19:17:40,661 INFO L587 BuchiCegarLoop]: Abstraction has 10047 states and 14436 transitions. [2021-12-19 19:17:40,661 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:40,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10047 states and 14436 transitions. [2021-12-19 19:17:40,679 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9835 [2021-12-19 19:17:40,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:40,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:40,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,681 INFO L791 eck$LassoCheckResult]: Stem: 91894#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 91895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 91904#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91905#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91636#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 91637#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91495#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91394#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91105#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90732#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90733#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 90782#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 90783#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 91766#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 91767#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 91818#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 91208#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91209#L1090 assume !(0 == ~M_E~0); 91258#L1090-2 assume !(0 == ~T1_E~0); 91259#L1095-1 assume !(0 == ~T2_E~0); 91974#L1100-1 assume !(0 == ~T3_E~0); 91975#L1105-1 assume !(0 == ~T4_E~0); 91020#L1110-1 assume !(0 == ~T5_E~0); 91021#L1115-1 assume !(0 == ~T6_E~0); 91437#L1120-1 assume !(0 == ~T7_E~0); 91741#L1125-1 assume !(0 == ~T8_E~0); 92408#L1130-1 assume !(0 == ~T9_E~0); 91999#L1135-1 assume !(0 == ~T10_E~0); 91215#L1140-1 assume !(0 == ~T11_E~0); 91216#L1145-1 assume !(0 == ~E_1~0); 91919#L1150-1 assume !(0 == ~E_2~0); 91408#L1155-1 assume !(0 == ~E_3~0); 91409#L1160-1 assume !(0 == ~E_4~0); 91504#L1165-1 assume !(0 == ~E_5~0); 91505#L1170-1 assume !(0 == ~E_6~0); 92237#L1175-1 assume !(0 == ~E_7~0); 91586#L1180-1 assume !(0 == ~E_8~0); 91587#L1185-1 assume !(0 == ~E_9~0); 91210#L1190-1 assume !(0 == ~E_10~0); 91211#L1195-1 assume !(0 == ~E_11~0); 91603#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91432#L525 assume !(1 == ~m_pc~0); 90822#L525-2 is_master_triggered_~__retres1~0#1 := 0; 90823#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91607#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 91608#L1350 assume !(0 != activate_threads_~tmp~1#1); 91198#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91199#L544 assume !(1 == ~t1_pc~0); 91433#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91434#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91917#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 91040#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 91041#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91710#L563 assume !(1 == ~t2_pc~0); 91906#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 90843#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90844#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 91287#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 91288#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91790#L582 assume 1 == ~t3_pc~0; 90986#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 90987#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92341#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 92247#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 90919#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90920#L601 assume !(1 == ~t4_pc~0); 91939#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91438#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91439#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 91932#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 91933#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92322#L620 assume 1 == ~t5_pc~0; 90876#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90877#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91737#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 91738#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 92358#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92359#L639 assume !(1 == ~t6_pc~0); 91739#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 91326#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91327#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 92251#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 91443#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 91444#L658 assume !(1 == ~t7_pc~0); 91659#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 91660#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 91774#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 91775#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 91204#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 91205#L677 assume 1 == ~t8_pc~0; 91450#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 91006#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 91007#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 91281#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 91282#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 92052#L696 assume !(1 == ~t9_pc~0); 91726#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 91727#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 91827#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 91747#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 91748#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 91978#L715 assume 1 == ~t10_pc~0; 91985#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 91842#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 91713#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 91714#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 91577#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 90995#L734 assume !(1 == ~t11_pc~0); 90996#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 91511#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 91591#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 90722#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 90723#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91808#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 91575#L1213-2 assume !(1 == ~T1_E~0); 91576#L1218-1 assume !(1 == ~T2_E~0); 92145#L1223-1 assume !(1 == ~T3_E~0); 94895#L1228-1 assume !(1 == ~T4_E~0); 92360#L1233-1 assume !(1 == ~T5_E~0); 92361#L1238-1 assume !(1 == ~T6_E~0); 91930#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 91931#L1248-1 assume !(1 == ~T8_E~0); 91983#L1253-1 assume !(1 == ~T9_E~0); 91984#L1258-1 assume !(1 == ~T10_E~0); 92252#L1263-1 assume !(1 == ~T11_E~0); 92285#L1268-1 assume !(1 == ~E_1~0); 92286#L1273-1 assume !(1 == ~E_2~0); 96665#L1278-1 assume !(1 == ~E_3~0); 94034#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 94033#L1288-1 assume !(1 == ~E_5~0); 94031#L1293-1 assume !(1 == ~E_6~0); 94014#L1298-1 assume !(1 == ~E_7~0); 93996#L1303-1 assume !(1 == ~E_8~0); 93983#L1308-1 assume !(1 == ~E_9~0); 93728#L1313-1 assume !(1 == ~E_10~0); 93713#L1318-1 assume !(1 == ~E_11~0); 93704#L1323-1 assume { :end_inline_reset_delta_events } true; 93696#L1644-2 [2021-12-19 19:17:40,682 INFO L793 eck$LassoCheckResult]: Loop: 93696#L1644-2 assume !false; 93690#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93685#L1065 assume !false; 93684#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 93681#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 93671#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 93670#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 93668#L906 assume !(0 != eval_~tmp~0#1); 93667#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 93666#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 93662#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 93663#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 93658#L1095-3 assume !(0 == ~T2_E~0); 93659#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94539#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93652#L1110-3 assume !(0 == ~T5_E~0); 93653#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94533#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93646#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 93647#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94527#L1135-3 assume !(0 == ~T10_E~0); 93640#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93641#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 94521#L1150-3 assume !(0 == ~E_2~0); 93634#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93635#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 94515#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 93628#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 93629#L1175-3 assume !(0 == ~E_7~0); 94509#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93622#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 93623#L1190-3 assume !(0 == ~E_10~0); 94503#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 94501#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94498#L525-36 assume 1 == ~m_pc~0; 94493#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 94487#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94481#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94475#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94471#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94467#L544-36 assume !(1 == ~t1_pc~0); 94463#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 94459#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94455#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94451#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94446#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94442#L563-36 assume 1 == ~t2_pc~0; 94437#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94431#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94427#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 94423#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94418#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94414#L582-36 assume !(1 == ~t3_pc~0); 94409#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 94403#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94399#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94395#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94390#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94386#L601-36 assume 1 == ~t4_pc~0; 94381#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94375#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94371#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94367#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94362#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94358#L620-36 assume !(1 == ~t5_pc~0); 94353#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 94347#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94343#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94340#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 94337#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94332#L639-36 assume 1 == ~t6_pc~0; 94325#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94319#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94313#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94307#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94302#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94294#L658-36 assume !(1 == ~t7_pc~0); 94287#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 94282#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94277#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94272#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 94267#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94262#L677-36 assume !(1 == ~t8_pc~0); 94255#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 94248#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94242#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94237#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 94232#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94227#L696-36 assume !(1 == ~t9_pc~0); 94219#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 94213#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94207#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94202#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 94197#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94192#L715-36 assume !(1 == ~t10_pc~0); 94185#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 94178#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94172#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94167#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94162#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94157#L734-36 assume !(1 == ~t11_pc~0); 94149#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 94143#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94137#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94132#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 94127#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94122#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94116#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94109#L1218-3 assume !(1 == ~T2_E~0); 94105#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94102#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94099#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94096#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94093#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94089#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94086#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94082#L1258-3 assume !(1 == ~T10_E~0); 94080#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94078#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94076#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 94074#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94071#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94069#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94067#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94065#L1298-3 assume !(1 == ~E_7~0); 94063#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 94061#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 94058#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 94056#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 94054#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 94052#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 94039#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 94037#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 94036#L1663 assume !(0 == start_simulation_~tmp~3#1); 90974#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 93737#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 93731#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 93730#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 93729#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93727#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93712#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 93703#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 93696#L1644-2 [2021-12-19 19:17:40,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1964150882, now seen corresponding path program 1 times [2021-12-19 19:17:40,683 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,683 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332234400] [2021-12-19 19:17:40,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,684 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,707 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332234400] [2021-12-19 19:17:40,707 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332234400] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,708 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,708 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:40,708 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168545949] [2021-12-19 19:17:40,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,708 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:40,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,709 INFO L85 PathProgramCache]: Analyzing trace with hash -1856592125, now seen corresponding path program 1 times [2021-12-19 19:17:40,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584752444] [2021-12-19 19:17:40,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,709 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,735 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,735 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584752444] [2021-12-19 19:17:40,735 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584752444] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,735 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,735 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:40,736 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939266106] [2021-12-19 19:17:40,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,736 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:40,736 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:40,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:40,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:40,737 INFO L87 Difference]: Start difference. First operand 10047 states and 14436 transitions. cyclomatic complexity: 4397 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:41,016 INFO L93 Difference]: Finished difference Result 23901 states and 34084 transitions. [2021-12-19 19:17:41,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:41,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23901 states and 34084 transitions. [2021-12-19 19:17:41,092 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 23658 [2021-12-19 19:17:41,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23901 states to 23901 states and 34084 transitions. [2021-12-19 19:17:41,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23901 [2021-12-19 19:17:41,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23901 [2021-12-19 19:17:41,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23901 states and 34084 transitions. [2021-12-19 19:17:41,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:41,172 INFO L681 BuchiCegarLoop]: Abstraction has 23901 states and 34084 transitions. [2021-12-19 19:17:41,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23901 states and 34084 transitions. [2021-12-19 19:17:41,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23901 to 19067. [2021-12-19 19:17:41,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19067 states, 19067 states have (on average 1.4299050715896575) internal successors, (27264), 19066 states have internal predecessors, (27264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19067 states to 19067 states and 27264 transitions. [2021-12-19 19:17:41,390 INFO L704 BuchiCegarLoop]: Abstraction has 19067 states and 27264 transitions. [2021-12-19 19:17:41,390 INFO L587 BuchiCegarLoop]: Abstraction has 19067 states and 27264 transitions. [2021-12-19 19:17:41,390 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:41,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19067 states and 27264 transitions. [2021-12-19 19:17:41,480 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18852 [2021-12-19 19:17:41,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:41,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:41,482 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:41,482 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:41,482 INFO L791 eck$LassoCheckResult]: Stem: 125840#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 125841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 125851#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125852#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125586#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 125587#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 125448#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125353#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125065#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 124692#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 124693#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 124742#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 124743#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 125713#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 125714#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 125763#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 125169#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 125170#L1090 assume !(0 == ~M_E~0); 125214#L1090-2 assume !(0 == ~T1_E~0); 125215#L1095-1 assume !(0 == ~T2_E~0); 125922#L1100-1 assume !(0 == ~T3_E~0); 125923#L1105-1 assume !(0 == ~T4_E~0); 124977#L1110-1 assume !(0 == ~T5_E~0); 124978#L1115-1 assume !(0 == ~T6_E~0); 125392#L1120-1 assume !(0 == ~T7_E~0); 125689#L1125-1 assume !(0 == ~T8_E~0); 126339#L1130-1 assume !(0 == ~T9_E~0); 125949#L1135-1 assume !(0 == ~T10_E~0); 125174#L1140-1 assume !(0 == ~T11_E~0); 125175#L1145-1 assume !(0 == ~E_1~0); 125869#L1150-1 assume !(0 == ~E_2~0); 125366#L1155-1 assume !(0 == ~E_3~0); 125367#L1160-1 assume !(0 == ~E_4~0); 125456#L1165-1 assume !(0 == ~E_5~0); 125457#L1170-1 assume !(0 == ~E_6~0); 126186#L1175-1 assume !(0 == ~E_7~0); 125538#L1180-1 assume !(0 == ~E_8~0); 125539#L1185-1 assume !(0 == ~E_9~0); 125171#L1190-1 assume !(0 == ~E_10~0); 125172#L1195-1 assume !(0 == ~E_11~0); 125553#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125382#L525 assume !(1 == ~m_pc~0); 124780#L525-2 is_master_triggered_~__retres1~0#1 := 0; 124781#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125557#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125558#L1350 assume !(0 != activate_threads_~tmp~1#1); 125158#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125159#L544 assume !(1 == ~t1_pc~0); 125390#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 125391#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125866#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 124999#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 125000#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125659#L563 assume !(1 == ~t2_pc~0); 125853#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 124801#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 124802#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125242#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 125243#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125741#L582 assume !(1 == ~t3_pc~0); 125867#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126272#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126273#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126199#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 124879#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124880#L601 assume !(1 == ~t4_pc~0); 125886#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 125393#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125394#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125880#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 125881#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126257#L620 assume 1 == ~t5_pc~0; 124830#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 124831#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125685#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125686#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 126289#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126290#L639 assume !(1 == ~t6_pc~0); 125687#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 125284#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125285#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126202#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 125401#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125402#L658 assume !(1 == ~t7_pc~0); 125606#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 125607#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125725#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125726#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 125165#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125166#L677 assume 1 == ~t8_pc~0; 125404#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 124959#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124960#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125239#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 125240#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 126009#L696 assume !(1 == ~t9_pc~0); 125671#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 125672#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125776#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125693#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 125694#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125927#L715 assume 1 == ~t10_pc~0; 125933#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 125794#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 125662#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 125663#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 125530#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 124951#L734 assume !(1 == ~t11_pc~0); 124952#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 125460#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 125543#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 124680#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 124681#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125761#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 126255#L1213-2 assume !(1 == ~T1_E~0); 126091#L1218-1 assume !(1 == ~T2_E~0); 126092#L1223-1 assume !(1 == ~T3_E~0); 125507#L1228-1 assume !(1 == ~T4_E~0); 125508#L1233-1 assume !(1 == ~T5_E~0); 126384#L1238-1 assume !(1 == ~T6_E~0); 126385#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 126363#L1248-1 assume !(1 == ~T8_E~0); 126364#L1253-1 assume !(1 == ~T9_E~0); 126203#L1258-1 assume !(1 == ~T10_E~0); 125906#L1263-1 assume !(1 == ~T11_E~0); 125907#L1268-1 assume !(1 == ~E_1~0); 125711#L1273-1 assume !(1 == ~E_2~0); 125712#L1278-1 assume !(1 == ~E_3~0); 125282#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 125283#L1288-1 assume !(1 == ~E_5~0); 132914#L1293-1 assume !(1 == ~E_6~0); 132913#L1298-1 assume !(1 == ~E_7~0); 125745#L1303-1 assume !(1 == ~E_8~0); 125746#L1308-1 assume !(1 == ~E_9~0); 125180#L1313-1 assume !(1 == ~E_10~0); 125181#L1318-1 assume !(1 == ~E_11~0); 125190#L1323-1 assume { :end_inline_reset_delta_events } true; 125191#L1644-2 [2021-12-19 19:17:41,483 INFO L793 eck$LassoCheckResult]: Loop: 125191#L1644-2 assume !false; 134291#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134281#L1065 assume !false; 134279#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 134142#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 134123#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 134115#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134104#L906 assume !(0 != eval_~tmp~0#1); 134105#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136361#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136359#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136356#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136354#L1095-3 assume !(0 == ~T2_E~0); 136352#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136350#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136348#L1110-3 assume !(0 == ~T5_E~0); 136346#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136345#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136343#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 136342#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 136340#L1135-3 assume !(0 == ~T10_E~0); 136338#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136336#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136334#L1150-3 assume !(0 == ~E_2~0); 136332#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136330#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136328#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136327#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136325#L1175-3 assume !(0 == ~E_7~0); 136323#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 136321#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 136319#L1190-3 assume !(0 == ~E_10~0); 136317#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 136315#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136313#L525-36 assume 1 == ~m_pc~0; 136310#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 136307#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136304#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136301#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136299#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125217#L544-36 assume !(1 == ~t1_pc~0); 125218#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 136426#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136425#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136424#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136423#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136422#L563-36 assume !(1 == ~t2_pc~0); 136420#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 136419#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136418#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136417#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136416#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136415#L582-36 assume !(1 == ~t3_pc~0); 128214#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 136414#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136413#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136412#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136411#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136410#L601-36 assume !(1 == ~t4_pc~0); 136408#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 136407#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136406#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136405#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136404#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136403#L620-36 assume !(1 == ~t5_pc~0); 136402#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 136400#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136399#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136398#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 136397#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136396#L639-36 assume !(1 == ~t6_pc~0); 136394#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 136393#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136392#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136391#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136390#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136389#L658-36 assume !(1 == ~t7_pc~0); 136387#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 136386#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136385#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136384#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 136383#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 136382#L677-36 assume 1 == ~t8_pc~0; 136380#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 136379#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 136378#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 136377#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 136376#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 136375#L696-36 assume 1 == ~t9_pc~0; 136374#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 136372#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 136371#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 136370#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 136369#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 136368#L715-36 assume 1 == ~t10_pc~0; 136366#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 136365#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 136364#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 136363#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 136362#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 136360#L734-36 assume 1 == ~t11_pc~0; 136358#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 136355#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 136353#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 136351#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 136349#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136347#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 133661#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 136344#L1218-3 assume !(1 == ~T2_E~0); 135464#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 136341#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 136339#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 136337#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136335#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 136333#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 136331#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 136329#L1258-3 assume !(1 == ~T10_E~0); 135377#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 136326#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136324#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136322#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 136320#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 136318#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 136316#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136314#L1298-3 assume !(1 == ~E_7~0); 136312#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 136309#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 136306#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 136303#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 136300#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 126378#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 125040#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 125473#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 125979#L1663 assume !(0 == start_simulation_~tmp~3#1); 126379#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 134379#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 134373#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 134371#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 134369#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134367#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134365#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 134312#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 125191#L1644-2 [2021-12-19 19:17:41,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:41,483 INFO L85 PathProgramCache]: Analyzing trace with hash 1053663741, now seen corresponding path program 1 times [2021-12-19 19:17:41,483 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:41,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246160030] [2021-12-19 19:17:41,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:41,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:41,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:41,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:41,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:41,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246160030] [2021-12-19 19:17:41,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246160030] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:41,507 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:41,507 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:41,507 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788940689] [2021-12-19 19:17:41,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:41,507 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:41,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:41,508 INFO L85 PathProgramCache]: Analyzing trace with hash 85045348, now seen corresponding path program 1 times [2021-12-19 19:17:41,508 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:41,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127420461] [2021-12-19 19:17:41,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:41,508 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:41,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:41,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:41,531 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:41,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127420461] [2021-12-19 19:17:41,532 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127420461] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:41,532 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:41,532 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:41,532 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822217939] [2021-12-19 19:17:41,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:41,532 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:41,532 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:41,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:41,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:41,533 INFO L87 Difference]: Start difference. First operand 19067 states and 27264 transitions. cyclomatic complexity: 8205 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:41,768 INFO L93 Difference]: Finished difference Result 45353 states and 64422 transitions. [2021-12-19 19:17:41,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:41,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45353 states and 64422 transitions. [2021-12-19 19:17:42,134 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 45075 [2021-12-19 19:17:42,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45353 states to 45353 states and 64422 transitions. [2021-12-19 19:17:42,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45353 [2021-12-19 19:17:42,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45353 [2021-12-19 19:17:42,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45353 states and 64422 transitions. [2021-12-19 19:17:42,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:42,318 INFO L681 BuchiCegarLoop]: Abstraction has 45353 states and 64422 transitions. [2021-12-19 19:17:42,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45353 states and 64422 transitions. [2021-12-19 19:17:42,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45353 to 36306. [2021-12-19 19:17:42,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36306 states, 36306 states have (on average 1.42403459483281) internal successors, (51701), 36305 states have internal predecessors, (51701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:42,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36306 states to 36306 states and 51701 transitions. [2021-12-19 19:17:42,840 INFO L704 BuchiCegarLoop]: Abstraction has 36306 states and 51701 transitions. [2021-12-19 19:17:42,840 INFO L587 BuchiCegarLoop]: Abstraction has 36306 states and 51701 transitions. [2021-12-19 19:17:42,840 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:42,840 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36306 states and 51701 transitions. [2021-12-19 19:17:43,168 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 36084 [2021-12-19 19:17:43,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:43,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:43,170 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:43,170 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:43,171 INFO L791 eck$LassoCheckResult]: Stem: 190248#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 190249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 190256#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 190257#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 189999#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 190000#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 189862#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 189769#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 189483#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 189124#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 189125#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 189173#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 189174#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 190132#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 190133#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 190175#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 189586#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 189587#L1090 assume !(0 == ~M_E~0); 189631#L1090-2 assume !(0 == ~T1_E~0); 189632#L1095-1 assume !(0 == ~T2_E~0); 190327#L1100-1 assume !(0 == ~T3_E~0); 190328#L1105-1 assume !(0 == ~T4_E~0); 189400#L1110-1 assume !(0 == ~T5_E~0); 189401#L1115-1 assume !(0 == ~T6_E~0); 189809#L1120-1 assume !(0 == ~T7_E~0); 190104#L1125-1 assume !(0 == ~T8_E~0); 190741#L1130-1 assume !(0 == ~T9_E~0); 190352#L1135-1 assume !(0 == ~T10_E~0); 189591#L1140-1 assume !(0 == ~T11_E~0); 189592#L1145-1 assume !(0 == ~E_1~0); 190274#L1150-1 assume !(0 == ~E_2~0); 189783#L1155-1 assume !(0 == ~E_3~0); 189784#L1160-1 assume !(0 == ~E_4~0); 189870#L1165-1 assume !(0 == ~E_5~0); 189871#L1170-1 assume !(0 == ~E_6~0); 190580#L1175-1 assume !(0 == ~E_7~0); 189953#L1180-1 assume !(0 == ~E_8~0); 189954#L1185-1 assume !(0 == ~E_9~0); 189588#L1190-1 assume !(0 == ~E_10~0); 189589#L1195-1 assume !(0 == ~E_11~0); 189967#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189799#L525 assume !(1 == ~m_pc~0); 189210#L525-2 is_master_triggered_~__retres1~0#1 := 0; 189211#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189971#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189972#L1350 assume !(0 != activate_threads_~tmp~1#1); 189575#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189576#L544 assume !(1 == ~t1_pc~0); 189807#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 189808#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190271#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 189422#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 189423#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190073#L563 assume !(1 == ~t2_pc~0); 190258#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 189234#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189235#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 189660#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 189661#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 190158#L582 assume !(1 == ~t3_pc~0); 190272#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 190674#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 190675#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190593#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 189304#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189305#L601 assume !(1 == ~t4_pc~0); 190292#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 189810#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189811#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 190286#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 190287#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190655#L620 assume !(1 == ~t5_pc~0); 190122#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190123#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190100#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 190101#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 190693#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 190694#L639 assume !(1 == ~t6_pc~0); 190102#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 189702#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189703#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 190596#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 189817#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 189818#L658 assume !(1 == ~t7_pc~0); 190021#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 190022#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190143#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 190144#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 189582#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 189583#L677 assume 1 == ~t8_pc~0; 189820#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 189382#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 189383#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 189657#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 189658#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 190399#L696 assume !(1 == ~t9_pc~0); 190085#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 190086#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 190187#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 190108#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 190109#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 190332#L715 assume 1 == ~t10_pc~0; 190339#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 190206#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 190076#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 190077#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 189944#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 189374#L734 assume !(1 == ~t11_pc~0); 189375#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 189874#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 189958#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 189112#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 189113#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190174#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 190652#L1213-2 assume !(1 == ~T1_E~0); 190489#L1218-1 assume !(1 == ~T2_E~0); 190490#L1223-1 assume !(1 == ~T3_E~0); 200172#L1228-1 assume !(1 == ~T4_E~0); 200170#L1233-1 assume !(1 == ~T5_E~0); 200168#L1238-1 assume !(1 == ~T6_E~0); 200166#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 200164#L1248-1 assume !(1 == ~T8_E~0); 200162#L1253-1 assume !(1 == ~T9_E~0); 200160#L1258-1 assume !(1 == ~T10_E~0); 200159#L1263-1 assume !(1 == ~T11_E~0); 200158#L1268-1 assume !(1 == ~E_1~0); 200157#L1273-1 assume !(1 == ~E_2~0); 200156#L1278-1 assume !(1 == ~E_3~0); 200155#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 200154#L1288-1 assume !(1 == ~E_5~0); 200153#L1293-1 assume !(1 == ~E_6~0); 200152#L1298-1 assume !(1 == ~E_7~0); 200151#L1303-1 assume !(1 == ~E_8~0); 200150#L1308-1 assume !(1 == ~E_9~0); 200149#L1313-1 assume !(1 == ~E_10~0); 200148#L1318-1 assume !(1 == ~E_11~0); 200147#L1323-1 assume { :end_inline_reset_delta_events } true; 200141#L1644-2 [2021-12-19 19:17:43,171 INFO L793 eck$LassoCheckResult]: Loop: 200141#L1644-2 assume !false; 200129#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200122#L1065 assume !false; 200117#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 199989#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 199978#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 199976#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 199973#L906 assume !(0 != eval_~tmp~0#1); 199974#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 204512#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 204510#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 204508#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 204506#L1095-3 assume !(0 == ~T2_E~0); 204504#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 204501#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 204499#L1110-3 assume !(0 == ~T5_E~0); 204497#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 204495#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 204493#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 204491#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 204489#L1135-3 assume !(0 == ~T10_E~0); 204486#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 204484#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 204482#L1150-3 assume !(0 == ~E_2~0); 204480#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 204478#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 204476#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 204473#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 204471#L1175-3 assume !(0 == ~E_7~0); 204469#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 204467#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 204465#L1190-3 assume !(0 == ~E_10~0); 204463#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 204460#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204458#L525-36 assume !(1 == ~m_pc~0); 204454#L525-38 is_master_triggered_~__retres1~0#1 := 0; 204452#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 204450#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204448#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 204444#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 204442#L544-36 assume !(1 == ~t1_pc~0); 204440#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 204438#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 204436#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 204435#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 204432#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 204430#L563-36 assume 1 == ~t2_pc~0; 204130#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 204127#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204124#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 204110#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 204100#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 201869#L582-36 assume !(1 == ~t3_pc~0); 201863#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 201857#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201851#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 201845#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 201839#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 201832#L601-36 assume 1 == ~t4_pc~0; 201825#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 201817#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201811#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201805#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 201798#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201792#L620-36 assume !(1 == ~t5_pc~0); 191465#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 201781#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 201775#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 201769#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 201762#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 201756#L639-36 assume 1 == ~t6_pc~0; 201750#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 201742#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201736#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 201730#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 201723#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 201715#L658-36 assume !(1 == ~t7_pc~0); 201708#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 201703#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 201696#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 201690#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 201684#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 201676#L677-36 assume !(1 == ~t8_pc~0); 201669#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 201661#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 201657#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 201652#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 201649#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 201646#L696-36 assume 1 == ~t9_pc~0; 201641#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 201634#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 201625#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 201615#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 201605#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 201604#L715-36 assume !(1 == ~t10_pc~0); 201594#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 201583#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 201574#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 201567#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 201560#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 201553#L734-36 assume 1 == ~t11_pc~0; 201546#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 201537#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 201530#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 201520#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 201512#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201504#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 201436#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 201489#L1218-3 assume !(1 == ~T2_E~0); 201484#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201413#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 201405#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 201398#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 201391#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 201384#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 201376#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 201370#L1258-3 assume !(1 == ~T10_E~0); 201362#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 201355#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 201349#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 201343#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 201338#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 201331#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 201328#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 201322#L1298-3 assume !(1 == ~E_7~0); 201318#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 201314#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 201055#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 201045#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 201037#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 200889#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 200873#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 200869#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 200864#L1663 assume !(0 == start_simulation_~tmp~3#1); 200861#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 200241#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 200235#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 200233#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 200230#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200228#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 200178#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 200146#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 200141#L1644-2 [2021-12-19 19:17:43,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:43,172 INFO L85 PathProgramCache]: Analyzing trace with hash -124310820, now seen corresponding path program 1 times [2021-12-19 19:17:43,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:43,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15011631] [2021-12-19 19:17:43,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:43,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:43,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:43,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:43,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:43,202 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15011631] [2021-12-19 19:17:43,202 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15011631] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:43,202 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:43,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:43,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928388796] [2021-12-19 19:17:43,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:43,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:43,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:43,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1138656674, now seen corresponding path program 1 times [2021-12-19 19:17:43,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:43,205 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321019608] [2021-12-19 19:17:43,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:43,206 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:43,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:43,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:43,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:43,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321019608] [2021-12-19 19:17:43,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321019608] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:43,234 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:43,234 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:43,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923542234] [2021-12-19 19:17:43,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:43,235 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:43,236 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:43,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:43,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:43,236 INFO L87 Difference]: Start difference. First operand 36306 states and 51701 transitions. cyclomatic complexity: 15403 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:43,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:43,739 INFO L93 Difference]: Finished difference Result 85833 states and 121522 transitions. [2021-12-19 19:17:43,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:43,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85833 states and 121522 transitions. [2021-12-19 19:17:44,131 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 85484 [2021-12-19 19:17:44,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85833 states to 85833 states and 121522 transitions. [2021-12-19 19:17:44,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85833 [2021-12-19 19:17:44,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85833 [2021-12-19 19:17:44,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85833 states and 121522 transitions. [2021-12-19 19:17:44,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:44,491 INFO L681 BuchiCegarLoop]: Abstraction has 85833 states and 121522 transitions. [2021-12-19 19:17:44,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85833 states and 121522 transitions. [2021-12-19 19:17:45,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85833 to 69197. [2021-12-19 19:17:45,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69197 states, 69197 states have (on average 1.418876540890501) internal successors, (98182), 69196 states have internal predecessors, (98182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:45,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69197 states to 69197 states and 98182 transitions. [2021-12-19 19:17:45,285 INFO L704 BuchiCegarLoop]: Abstraction has 69197 states and 98182 transitions. [2021-12-19 19:17:45,285 INFO L587 BuchiCegarLoop]: Abstraction has 69197 states and 98182 transitions. [2021-12-19 19:17:45,285 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:45,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69197 states and 98182 transitions. [2021-12-19 19:17:45,627 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 68960 [2021-12-19 19:17:45,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:45,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:45,631 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,631 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,631 INFO L791 eck$LassoCheckResult]: Stem: 312401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 312402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 312411#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 312412#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 312146#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 312147#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 312013#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 311921#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 311635#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 311275#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 311276#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 311324#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 311325#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 312282#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 312283#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 312328#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 311738#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 311739#L1090 assume !(0 == ~M_E~0); 311784#L1090-2 assume !(0 == ~T1_E~0); 311785#L1095-1 assume !(0 == ~T2_E~0); 312480#L1100-1 assume !(0 == ~T3_E~0); 312481#L1105-1 assume !(0 == ~T4_E~0); 311551#L1110-1 assume !(0 == ~T5_E~0); 311552#L1115-1 assume !(0 == ~T6_E~0); 311963#L1120-1 assume !(0 == ~T7_E~0); 312254#L1125-1 assume !(0 == ~T8_E~0); 312880#L1130-1 assume !(0 == ~T9_E~0); 312503#L1135-1 assume !(0 == ~T10_E~0); 311746#L1140-1 assume !(0 == ~T11_E~0); 311747#L1145-1 assume !(0 == ~E_1~0); 312427#L1150-1 assume !(0 == ~E_2~0); 311935#L1155-1 assume !(0 == ~E_3~0); 311936#L1160-1 assume !(0 == ~E_4~0); 312021#L1165-1 assume !(0 == ~E_5~0); 312022#L1170-1 assume !(0 == ~E_6~0); 312725#L1175-1 assume !(0 == ~E_7~0); 312103#L1180-1 assume !(0 == ~E_8~0); 312104#L1185-1 assume !(0 == ~E_9~0); 311740#L1190-1 assume !(0 == ~E_10~0); 311741#L1195-1 assume !(0 == ~E_11~0); 312117#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 311958#L525 assume !(1 == ~m_pc~0); 311362#L525-2 is_master_triggered_~__retres1~0#1 := 0; 311363#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312120#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 312121#L1350 assume !(0 != activate_threads_~tmp~1#1); 311728#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 311729#L544 assume !(1 == ~t1_pc~0); 311959#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 311960#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312424#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 311572#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 311573#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312223#L563 assume !(1 == ~t2_pc~0); 312413#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 311384#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 311385#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 311816#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 311817#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312307#L582 assume !(1 == ~t3_pc~0); 312425#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 312821#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312822#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 312740#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 311454#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 311455#L601 assume !(1 == ~t4_pc~0); 312446#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 311964#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311965#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 312440#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 312441#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 312803#L620 assume !(1 == ~t5_pc~0); 312274#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 312275#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 312250#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 312251#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 312837#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 312838#L639 assume !(1 == ~t6_pc~0); 312252#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 311854#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311855#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 312742#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 311969#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 311970#L658 assume !(1 == ~t7_pc~0); 312170#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 312171#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 312291#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 312292#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 311734#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 311735#L677 assume !(1 == ~t8_pc~0); 311761#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 311537#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 311538#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 311810#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 311811#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 312546#L696 assume !(1 == ~t9_pc~0); 312237#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 312238#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 312339#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 312260#L1422 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 312261#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 312484#L715 assume 1 == ~t10_pc~0; 312491#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 312356#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 312226#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 312227#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 312094#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311526#L734 assume !(1 == ~t11_pc~0); 311527#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 312028#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 312108#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 311265#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 311266#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312324#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 312801#L1213-2 assume !(1 == ~T1_E~0); 359082#L1218-1 assume !(1 == ~T2_E~0); 359081#L1223-1 assume !(1 == ~T3_E~0); 359079#L1228-1 assume !(1 == ~T4_E~0); 359073#L1233-1 assume !(1 == ~T5_E~0); 359070#L1238-1 assume !(1 == ~T6_E~0); 359067#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 359064#L1248-1 assume !(1 == ~T8_E~0); 359060#L1253-1 assume !(1 == ~T9_E~0); 359057#L1258-1 assume !(1 == ~T10_E~0); 359051#L1263-1 assume !(1 == ~T11_E~0); 359047#L1268-1 assume !(1 == ~E_1~0); 359044#L1273-1 assume !(1 == ~E_2~0); 359041#L1278-1 assume !(1 == ~E_3~0); 359038#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 359035#L1288-1 assume !(1 == ~E_5~0); 359034#L1293-1 assume !(1 == ~E_6~0); 359029#L1298-1 assume !(1 == ~E_7~0); 359025#L1303-1 assume !(1 == ~E_8~0); 359020#L1308-1 assume !(1 == ~E_9~0); 359015#L1313-1 assume !(1 == ~E_10~0); 359011#L1318-1 assume !(1 == ~E_11~0); 359006#L1323-1 assume { :end_inline_reset_delta_events } true; 359000#L1644-2 [2021-12-19 19:17:45,631 INFO L793 eck$LassoCheckResult]: Loop: 359000#L1644-2 assume !false; 358999#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 358994#L1065 assume !false; 358993#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 358987#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 358977#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 358972#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 358969#L906 assume !(0 != eval_~tmp~0#1); 358970#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 379631#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 379630#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 379628#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 379627#L1095-3 assume !(0 == ~T2_E~0); 379626#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 379625#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 379623#L1110-3 assume !(0 == ~T5_E~0); 379621#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 379619#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 379617#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 379615#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 379613#L1135-3 assume !(0 == ~T10_E~0); 379611#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 379609#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 379607#L1150-3 assume !(0 == ~E_2~0); 379605#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 379603#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 379601#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 379599#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 379597#L1175-3 assume !(0 == ~E_7~0); 379595#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 379593#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 379591#L1190-3 assume !(0 == ~E_10~0); 379589#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 379587#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379585#L525-36 assume !(1 == ~m_pc~0); 379581#L525-38 is_master_triggered_~__retres1~0#1 := 0; 379579#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 379577#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 379575#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 379572#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 379570#L544-36 assume !(1 == ~t1_pc~0); 379567#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 379565#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 379563#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 379562#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 379561#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 379560#L563-36 assume !(1 == ~t2_pc~0); 379557#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 379554#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379552#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 379550#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 379549#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312889#L582-36 assume !(1 == ~t3_pc~0); 312890#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 368011#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368009#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 368007#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 368005#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368003#L601-36 assume 1 == ~t4_pc~0; 368000#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 367998#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 367997#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 367995#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 367994#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 361215#L620-36 assume !(1 == ~t5_pc~0); 361213#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 361211#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 361209#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 361207#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 361205#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 361203#L639-36 assume 1 == ~t6_pc~0; 361201#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 361198#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 361196#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 361194#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 361192#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 361190#L658-36 assume !(1 == ~t7_pc~0); 361187#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 361185#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 361183#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 361181#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 361179#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 361177#L677-36 assume !(1 == ~t8_pc~0); 332508#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 361174#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 361172#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 361170#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 361168#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 361166#L696-36 assume 1 == ~t9_pc~0; 361164#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 361161#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 361159#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 361158#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 361157#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 361156#L715-36 assume !(1 == ~t10_pc~0); 361155#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 361153#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 361152#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 361151#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 361150#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 361149#L734-36 assume 1 == ~t11_pc~0; 361148#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 361146#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 361145#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 361144#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 361143#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 361142#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 360741#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 360878#L1218-3 assume !(1 == ~T2_E~0); 360876#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 360874#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 360871#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 360869#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 360867#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 360865#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 360863#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 360715#L1258-3 assume !(1 == ~T10_E~0); 360713#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 360710#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 360708#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 360706#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 360704#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 360702#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 360700#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 360698#L1298-3 assume !(1 == ~E_7~0); 360697#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 360695#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 360693#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 360691#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 360689#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 360687#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 360673#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 360671#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 360669#L1663 assume !(0 == start_simulation_~tmp~3#1); 360666#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 360645#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 360639#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 360637#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 360636#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 360635#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 360631#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 359005#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 359000#L1644-2 [2021-12-19 19:17:45,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1308523899, now seen corresponding path program 1 times [2021-12-19 19:17:45,632 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,632 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497881244] [2021-12-19 19:17:45,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,632 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:45,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:45,664 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:45,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497881244] [2021-12-19 19:17:45,665 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497881244] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:45,665 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:45,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:45,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959560336] [2021-12-19 19:17:45,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:45,667 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:45,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,667 INFO L85 PathProgramCache]: Analyzing trace with hash 1494253121, now seen corresponding path program 1 times [2021-12-19 19:17:45,667 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,667 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64011810] [2021-12-19 19:17:45,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,668 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:45,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:45,692 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:45,692 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64011810] [2021-12-19 19:17:45,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64011810] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:45,693 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:45,693 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:45,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560800474] [2021-12-19 19:17:45,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:45,693 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:45,693 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:45,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:45,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:45,694 INFO L87 Difference]: Start difference. First operand 69197 states and 98182 transitions. cyclomatic complexity: 28993 Second operand has 5 states, 5 states have (on average 27.4) internal successors, (137), 5 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:46,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:46,363 INFO L93 Difference]: Finished difference Result 159424 states and 227735 transitions. [2021-12-19 19:17:46,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:46,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 159424 states and 227735 transitions. [2021-12-19 19:17:47,238 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 158928 [2021-12-19 19:17:47,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 159424 states to 159424 states and 227735 transitions. [2021-12-19 19:17:47,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159424 [2021-12-19 19:17:47,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159424 [2021-12-19 19:17:47,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 159424 states and 227735 transitions. [2021-12-19 19:17:47,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:47,938 INFO L681 BuchiCegarLoop]: Abstraction has 159424 states and 227735 transitions. [2021-12-19 19:17:48,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159424 states and 227735 transitions. [2021-12-19 19:17:48,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159424 to 71168. [2021-12-19 19:17:48,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71168 states, 71168 states have (on average 1.4072757419064748) internal successors, (100153), 71167 states have internal predecessors, (100153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:49,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71168 states to 71168 states and 100153 transitions. [2021-12-19 19:17:49,169 INFO L704 BuchiCegarLoop]: Abstraction has 71168 states and 100153 transitions. [2021-12-19 19:17:49,169 INFO L587 BuchiCegarLoop]: Abstraction has 71168 states and 100153 transitions. [2021-12-19 19:17:49,176 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:49,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71168 states and 100153 transitions. [2021-12-19 19:17:49,338 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 70928 [2021-12-19 19:17:49,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:49,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:49,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:49,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:49,357 INFO L791 eck$LassoCheckResult]: Stem: 541029#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 541030#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 541037#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 541038#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 540780#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 540781#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 540648#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 540561#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 540274#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 539911#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 539912#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 539960#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 539961#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 540907#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 540908#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 540953#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 540378#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 540379#L1090 assume !(0 == ~M_E~0); 540425#L1090-2 assume !(0 == ~T1_E~0); 540426#L1095-1 assume !(0 == ~T2_E~0); 541114#L1100-1 assume !(0 == ~T3_E~0); 541115#L1105-1 assume !(0 == ~T4_E~0); 540189#L1110-1 assume !(0 == ~T5_E~0); 540190#L1115-1 assume !(0 == ~T6_E~0); 540598#L1120-1 assume !(0 == ~T7_E~0); 540882#L1125-1 assume !(0 == ~T8_E~0); 541529#L1130-1 assume !(0 == ~T9_E~0); 541138#L1135-1 assume !(0 == ~T10_E~0); 540384#L1140-1 assume !(0 == ~T11_E~0); 540385#L1145-1 assume !(0 == ~E_1~0); 541057#L1150-1 assume !(0 == ~E_2~0); 540574#L1155-1 assume !(0 == ~E_3~0); 540575#L1160-1 assume !(0 == ~E_4~0); 540656#L1165-1 assume !(0 == ~E_5~0); 540657#L1170-1 assume !(0 == ~E_6~0); 541377#L1175-1 assume !(0 == ~E_7~0); 540735#L1180-1 assume !(0 == ~E_8~0); 540736#L1185-1 assume !(0 == ~E_9~0); 540380#L1190-1 assume !(0 == ~E_10~0); 540381#L1195-1 assume !(0 == ~E_11~0); 540750#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 540588#L525 assume !(1 == ~m_pc~0); 539997#L525-2 is_master_triggered_~__retres1~0#1 := 0; 539998#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 540753#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 540754#L1350 assume !(0 != activate_threads_~tmp~1#1); 540367#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 540368#L544 assume !(1 == ~t1_pc~0); 540596#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 540597#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 541054#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 540213#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 540214#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 540852#L563 assume !(1 == ~t2_pc~0); 541039#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 540021#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 540022#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 540454#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 540455#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 540934#L582 assume !(1 == ~t3_pc~0); 541055#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 541464#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 541465#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 541387#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 540093#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 540094#L601 assume !(1 == ~t4_pc~0); 541077#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 540599#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 540600#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 541069#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 541070#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 541445#L620 assume !(1 == ~t5_pc~0); 540897#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 540898#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 540878#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 540879#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 541482#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 541483#L639 assume !(1 == ~t6_pc~0); 540880#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 540495#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 540496#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 541391#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 540607#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 540608#L658 assume !(1 == ~t7_pc~0); 540800#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 540801#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 540917#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 540918#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 540374#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 540375#L677 assume !(1 == ~t8_pc~0); 540400#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 540171#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 540172#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 540451#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 540452#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 541193#L696 assume !(1 == ~t9_pc~0); 540863#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 540864#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 540965#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 540886#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 540887#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 541120#L715 assume 1 == ~t10_pc~0; 541126#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 540983#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 540855#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 540856#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 540727#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 540163#L734 assume !(1 == ~t11_pc~0); 540164#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 540660#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 540740#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 539901#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 539902#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 540952#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 541443#L1213-2 assume !(1 == ~T1_E~0); 552512#L1218-1 assume !(1 == ~T2_E~0); 552510#L1223-1 assume !(1 == ~T3_E~0); 552509#L1228-1 assume !(1 == ~T4_E~0); 552505#L1233-1 assume !(1 == ~T5_E~0); 552503#L1238-1 assume !(1 == ~T6_E~0); 552501#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 552500#L1248-1 assume !(1 == ~T8_E~0); 551429#L1253-1 assume !(1 == ~T9_E~0); 551426#L1258-1 assume !(1 == ~T10_E~0); 550498#L1263-1 assume !(1 == ~T11_E~0); 550496#L1268-1 assume !(1 == ~E_1~0); 548240#L1273-1 assume !(1 == ~E_2~0); 548237#L1278-1 assume !(1 == ~E_3~0); 548233#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 548231#L1288-1 assume !(1 == ~E_5~0); 548228#L1293-1 assume !(1 == ~E_6~0); 548226#L1298-1 assume !(1 == ~E_7~0); 548224#L1303-1 assume !(1 == ~E_8~0); 548222#L1308-1 assume !(1 == ~E_9~0); 548132#L1313-1 assume !(1 == ~E_10~0); 547504#L1318-1 assume !(1 == ~E_11~0); 547499#L1323-1 assume { :end_inline_reset_delta_events } true; 547493#L1644-2 [2021-12-19 19:17:49,358 INFO L793 eck$LassoCheckResult]: Loop: 547493#L1644-2 assume !false; 547492#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 547487#L1065 assume !false; 547486#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 547483#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 547473#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 547472#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 547470#L906 assume !(0 != eval_~tmp~0#1); 547471#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 567248#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 567246#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 567244#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 567242#L1095-3 assume !(0 == ~T2_E~0); 567240#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 567238#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 567236#L1110-3 assume !(0 == ~T5_E~0); 567234#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 567232#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 567230#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 567228#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 567226#L1135-3 assume !(0 == ~T10_E~0); 567224#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 567222#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 567220#L1150-3 assume !(0 == ~E_2~0); 567218#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 567216#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 567214#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 567210#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 567206#L1175-3 assume !(0 == ~E_7~0); 567202#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 567197#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 567192#L1190-3 assume !(0 == ~E_10~0); 567187#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 567182#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 567178#L525-36 assume 1 == ~m_pc~0; 567170#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 567162#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567154#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 567146#L1350-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 567142#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567137#L544-36 assume !(1 == ~t1_pc~0); 567131#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 567125#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 567119#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 567113#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 567108#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567103#L563-36 assume !(1 == ~t2_pc~0); 567094#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 567089#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 567084#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 567079#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 567074#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567068#L582-36 assume !(1 == ~t3_pc~0); 557141#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 567058#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 567052#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 567047#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 567042#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 567038#L601-36 assume !(1 == ~t4_pc~0); 567033#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 567029#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 567027#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 566975#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 566974#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 551890#L620-36 assume !(1 == ~t5_pc~0); 551889#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 551888#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 551887#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 551886#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 551885#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 551884#L639-36 assume !(1 == ~t6_pc~0); 551882#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 551881#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 551880#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 551879#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 551878#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 551877#L658-36 assume !(1 == ~t7_pc~0); 551875#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 551874#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 551873#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 551872#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 551871#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 551870#L677-36 assume !(1 == ~t8_pc~0); 548900#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 551869#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 551868#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 551867#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 551866#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 551865#L696-36 assume !(1 == ~t9_pc~0); 551864#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 551862#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 551860#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 551858#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 551855#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 551853#L715-36 assume 1 == ~t10_pc~0; 551427#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 551425#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 551424#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 551422#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 551420#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 551418#L734-36 assume 1 == ~t11_pc~0; 551416#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 551377#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 551375#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 551373#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 551370#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 551368#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 549477#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 551343#L1218-3 assume !(1 == ~T2_E~0); 551341#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 551339#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 551338#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 551337#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 551333#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 551329#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 551327#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 549450#L1258-3 assume !(1 == ~T10_E~0); 549448#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 549446#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 549444#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 549442#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 549441#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 549350#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 549348#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 549346#L1298-3 assume !(1 == ~E_7~0); 549344#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 549341#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 549339#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 549337#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 549335#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 548537#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 548523#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 548521#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 548519#L1663 assume !(0 == start_simulation_~tmp~3#1); 548516#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 548450#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 548445#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 548444#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 548440#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 548438#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 548436#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 547498#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 547493#L1644-2 [2021-12-19 19:17:49,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:49,358 INFO L85 PathProgramCache]: Analyzing trace with hash 279164601, now seen corresponding path program 1 times [2021-12-19 19:17:49,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:49,358 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277482593] [2021-12-19 19:17:49,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:49,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:49,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:49,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:49,389 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:49,389 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277482593] [2021-12-19 19:17:49,389 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277482593] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:49,389 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:49,389 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:49,389 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089674875] [2021-12-19 19:17:49,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:49,390 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:49,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:49,390 INFO L85 PathProgramCache]: Analyzing trace with hash 2095249440, now seen corresponding path program 1 times [2021-12-19 19:17:49,390 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:49,390 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611000535] [2021-12-19 19:17:49,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:49,390 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:49,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:49,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:49,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:49,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611000535] [2021-12-19 19:17:49,421 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611000535] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:49,421 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:49,421 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:49,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107267578] [2021-12-19 19:17:49,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:49,421 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:49,422 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:49,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:49,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:49,422 INFO L87 Difference]: Start difference. First operand 71168 states and 100153 transitions. cyclomatic complexity: 28993 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:50,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:50,182 INFO L93 Difference]: Finished difference Result 167243 states and 234138 transitions. [2021-12-19 19:17:50,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:50,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167243 states and 234138 transitions. [2021-12-19 19:17:50,755 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 166748 [2021-12-19 19:17:51,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167243 states to 167243 states and 234138 transitions. [2021-12-19 19:17:51,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 167243 [2021-12-19 19:17:51,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 167243 [2021-12-19 19:17:51,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167243 states and 234138 transitions. [2021-12-19 19:17:51,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:51,604 INFO L681 BuchiCegarLoop]: Abstraction has 167243 states and 234138 transitions. [2021-12-19 19:17:51,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167243 states and 234138 transitions. [2021-12-19 19:17:52,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167243 to 135583. [2021-12-19 19:17:52,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 135583 states, 135583 states have (on average 1.4028159872550394) internal successors, (190198), 135582 states have internal predecessors, (190198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:53,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135583 states to 135583 states and 190198 transitions. [2021-12-19 19:17:53,162 INFO L704 BuchiCegarLoop]: Abstraction has 135583 states and 190198 transitions. [2021-12-19 19:17:53,162 INFO L587 BuchiCegarLoop]: Abstraction has 135583 states and 190198 transitions. [2021-12-19 19:17:53,162 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:17:53,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 135583 states and 190198 transitions. [2021-12-19 19:17:53,525 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 135312 [2021-12-19 19:17:53,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:53,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:53,529 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,530 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:53,530 INFO L791 eck$LassoCheckResult]: Stem: 779474#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 779475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 779483#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 779484#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 779217#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 779218#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 779080#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 778989#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 778697#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 778334#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 778335#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 778384#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 778385#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 779358#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 779359#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 779399#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 778804#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 778805#L1090 assume !(0 == ~M_E~0); 778848#L1090-2 assume !(0 == ~T1_E~0); 778849#L1095-1 assume !(0 == ~T2_E~0); 779553#L1100-1 assume !(0 == ~T3_E~0); 779554#L1105-1 assume !(0 == ~T4_E~0); 778612#L1110-1 assume !(0 == ~T5_E~0); 778613#L1115-1 assume !(0 == ~T6_E~0); 779031#L1120-1 assume !(0 == ~T7_E~0); 779331#L1125-1 assume !(0 == ~T8_E~0); 779961#L1130-1 assume !(0 == ~T9_E~0); 779576#L1135-1 assume !(0 == ~T10_E~0); 778810#L1140-1 assume !(0 == ~T11_E~0); 778811#L1145-1 assume !(0 == ~E_1~0); 779501#L1150-1 assume !(0 == ~E_2~0); 779005#L1155-1 assume !(0 == ~E_3~0); 779006#L1160-1 assume !(0 == ~E_4~0); 779088#L1165-1 assume !(0 == ~E_5~0); 779089#L1170-1 assume !(0 == ~E_6~0); 779805#L1175-1 assume !(0 == ~E_7~0); 779171#L1180-1 assume !(0 == ~E_8~0); 779172#L1185-1 assume !(0 == ~E_9~0); 778806#L1190-1 assume !(0 == ~E_10~0); 778807#L1195-1 assume !(0 == ~E_11~0); 779185#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 779021#L525 assume !(1 == ~m_pc~0); 778422#L525-2 is_master_triggered_~__retres1~0#1 := 0; 778423#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 779765#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 779639#L1350 assume !(0 != activate_threads_~tmp~1#1); 778793#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 778794#L544 assume !(1 == ~t1_pc~0); 779029#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 779030#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 779498#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 778635#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 778636#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 779298#L563 assume !(1 == ~t2_pc~0); 779485#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 778446#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 778447#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 778878#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 778879#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 779383#L582 assume !(1 == ~t3_pc~0); 779499#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 779898#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 779899#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 779818#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 778516#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 778517#L601 assume !(1 == ~t4_pc~0); 779519#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 779032#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 779033#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 779513#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 779514#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 779884#L620 assume !(1 == ~t5_pc~0); 779348#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 779349#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 779327#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 779328#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 779918#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 779919#L639 assume !(1 == ~t6_pc~0); 779330#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 778921#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 778922#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 779824#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 779039#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 779040#L658 assume !(1 == ~t7_pc~0); 779241#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 779242#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 779368#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 779369#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 778800#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 778801#L677 assume !(1 == ~t8_pc~0); 778825#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 778594#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 778595#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 778875#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 778876#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 779629#L696 assume !(1 == ~t9_pc~0); 779309#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 779310#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 779411#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 779335#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 779336#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 779558#L715 assume !(1 == ~t10_pc~0); 779848#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 779428#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 779301#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 779302#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 779162#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 778586#L734 assume !(1 == ~t11_pc~0); 778587#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 779092#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 779176#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 778322#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 778323#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 779398#L1213 assume 1 == ~M_E~0;~M_E~0 := 2; 779882#L1213-2 assume !(1 == ~T1_E~0); 779721#L1218-1 assume !(1 == ~T2_E~0); 779722#L1223-1 assume !(1 == ~T3_E~0); 853040#L1228-1 assume !(1 == ~T4_E~0); 853038#L1233-1 assume !(1 == ~T5_E~0); 853035#L1238-1 assume !(1 == ~T6_E~0); 853033#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 853031#L1248-1 assume !(1 == ~T8_E~0); 853030#L1253-1 assume !(1 == ~T9_E~0); 853028#L1258-1 assume !(1 == ~T10_E~0); 779825#L1263-1 assume !(1 == ~T11_E~0); 853025#L1268-1 assume !(1 == ~E_1~0); 853023#L1273-1 assume !(1 == ~E_2~0); 853021#L1278-1 assume !(1 == ~E_3~0); 853018#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 853016#L1288-1 assume !(1 == ~E_5~0); 853014#L1293-1 assume !(1 == ~E_6~0); 853012#L1298-1 assume !(1 == ~E_7~0); 853010#L1303-1 assume !(1 == ~E_8~0); 853006#L1308-1 assume !(1 == ~E_9~0); 853004#L1313-1 assume !(1 == ~E_10~0); 853002#L1318-1 assume !(1 == ~E_11~0); 852997#L1323-1 assume { :end_inline_reset_delta_events } true; 852994#L1644-2 [2021-12-19 19:17:53,530 INFO L793 eck$LassoCheckResult]: Loop: 852994#L1644-2 assume !false; 852991#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 852985#L1065 assume !false; 852983#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 852973#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 852962#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 852960#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 852957#L906 assume !(0 != eval_~tmp~0#1); 852958#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 912079#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 912076#L1090-3 assume 0 == ~M_E~0;~M_E~0 := 1; 912073#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 912069#L1095-3 assume !(0 == ~T2_E~0); 912066#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 912063#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 912061#L1110-3 assume !(0 == ~T5_E~0); 912058#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 912057#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 912056#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 912054#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 912049#L1135-3 assume !(0 == ~T10_E~0); 912044#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 912039#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 912034#L1150-3 assume !(0 == ~E_2~0); 912030#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 912026#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 912022#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 912018#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 912014#L1175-3 assume !(0 == ~E_7~0); 912010#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 912006#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 912002#L1190-3 assume !(0 == ~E_10~0); 911997#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 911994#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 911991#L525-36 assume !(1 == ~m_pc~0); 911988#L525-38 is_master_triggered_~__retres1~0#1 := 0; 911984#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 911979#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 911973#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 911967#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 911962#L544-36 assume !(1 == ~t1_pc~0); 911957#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 911953#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 911949#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 911946#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 911942#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 911941#L563-36 assume 1 == ~t2_pc~0; 911937#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 911934#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 911896#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 911694#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 911693#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 779970#L582-36 assume !(1 == ~t3_pc~0); 779971#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 909497#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 909494#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 909491#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 909488#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 909485#L601-36 assume 1 == ~t4_pc~0; 909483#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 909479#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 909476#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 909473#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 909470#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 909466#L620-36 assume !(1 == ~t5_pc~0); 903124#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 909461#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 909457#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 909453#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 909448#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 909444#L639-36 assume 1 == ~t6_pc~0; 909439#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 909433#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 909429#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 909280#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 909279#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 909278#L658-36 assume !(1 == ~t7_pc~0); 909276#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 909272#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 909267#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 909262#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 909223#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 779690#L677-36 assume !(1 == ~t8_pc~0); 779245#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 779246#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 779384#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 779876#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 779275#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 779276#L696-36 assume !(1 == ~t9_pc~0); 779153#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 779593#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 778496#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 778497#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 779292#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 779293#L715-36 assume !(1 == ~t10_pc~0); 779257#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 778324#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 778325#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 778298#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 778299#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 778701#L734-36 assume 1 == ~t11_pc~0; 778702#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 778403#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 778724#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 778316#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 778317#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 779362#L1213-3 assume 1 == ~M_E~0;~M_E~0 := 2; 779001#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 779002#L1218-3 assume !(1 == ~T2_E~0); 778756#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 778757#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 778953#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 778954#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 779212#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 779213#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 779781#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 779788#L1258-3 assume !(1 == ~T10_E~0); 778736#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 778737#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 779748#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 779770#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 780012#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 911680#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 911640#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 911638#L1298-3 assume !(1 == ~E_7~0); 911637#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 909501#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 909500#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 909499#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 778738#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 778739#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 778674#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 779600#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 779601#L1663 assume !(0 == start_simulation_~tmp~3#1); 778570#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 854227#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 854221#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 854220#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 854219#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 854218#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 854205#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 852996#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 852994#L1644-2 [2021-12-19 19:17:53,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1485652008, now seen corresponding path program 1 times [2021-12-19 19:17:53,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109523616] [2021-12-19 19:17:53,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,531 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:53,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:53,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:53,550 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109523616] [2021-12-19 19:17:53,550 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109523616] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:53,550 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:53,550 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:53,551 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23266740] [2021-12-19 19:17:53,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:53,551 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:53,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:53,551 INFO L85 PathProgramCache]: Analyzing trace with hash 760377663, now seen corresponding path program 1 times [2021-12-19 19:17:53,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:53,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286990139] [2021-12-19 19:17:53,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:53,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:53,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:53,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:53,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:53,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286990139] [2021-12-19 19:17:53,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286990139] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:53,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:53,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:53,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951731341] [2021-12-19 19:17:53,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:53,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:53,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:53,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:53,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:53,574 INFO L87 Difference]: Start difference. First operand 135583 states and 190198 transitions. cyclomatic complexity: 54623 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 2 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:54,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:54,459 INFO L93 Difference]: Finished difference Result 165602 states and 231516 transitions. [2021-12-19 19:17:54,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:54,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 165602 states and 231516 transitions. [2021-12-19 19:17:55,060 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 165328 [2021-12-19 19:17:55,925 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 165602 states to 165602 states and 231516 transitions. [2021-12-19 19:17:55,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 165602 [2021-12-19 19:17:56,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 165602 [2021-12-19 19:17:56,019 INFO L73 IsDeterministic]: Start isDeterministic. Operand 165602 states and 231516 transitions. [2021-12-19 19:17:56,106 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:56,106 INFO L681 BuchiCegarLoop]: Abstraction has 165602 states and 231516 transitions. [2021-12-19 19:17:56,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165602 states and 231516 transitions. [2021-12-19 19:17:57,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165602 to 69459. [2021-12-19 19:17:57,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69459 states, 69459 states have (on average 1.4058941245914856) internal successors, (97652), 69458 states have internal predecessors, (97652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:57,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69459 states to 69459 states and 97652 transitions. [2021-12-19 19:17:57,414 INFO L704 BuchiCegarLoop]: Abstraction has 69459 states and 97652 transitions. [2021-12-19 19:17:57,414 INFO L587 BuchiCegarLoop]: Abstraction has 69459 states and 97652 transitions. [2021-12-19 19:17:57,414 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-19 19:17:57,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69459 states and 97652 transitions. [2021-12-19 19:17:57,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69280 [2021-12-19 19:17:57,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:57,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:57,604 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:57,604 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:57,604 INFO L791 eck$LassoCheckResult]: Stem: 1080668#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1080669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1080683#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1080684#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1080402#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1080403#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1080264#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1080171#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1079890#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1079528#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1079529#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1079578#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1079579#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1080542#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1080543#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1080595#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1079991#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1079992#L1090 assume !(0 == ~M_E~0); 1080039#L1090-2 assume !(0 == ~T1_E~0); 1080040#L1095-1 assume !(0 == ~T2_E~0); 1080755#L1100-1 assume !(0 == ~T3_E~0); 1080756#L1105-1 assume !(0 == ~T4_E~0); 1079808#L1110-1 assume !(0 == ~T5_E~0); 1079809#L1115-1 assume !(0 == ~T6_E~0); 1080214#L1120-1 assume !(0 == ~T7_E~0); 1080513#L1125-1 assume !(0 == ~T8_E~0); 1081178#L1130-1 assume !(0 == ~T9_E~0); 1080780#L1135-1 assume !(0 == ~T10_E~0); 1079999#L1140-1 assume !(0 == ~T11_E~0); 1080000#L1145-1 assume !(0 == ~E_1~0); 1080700#L1150-1 assume !(0 == ~E_2~0); 1080188#L1155-1 assume !(0 == ~E_3~0); 1080189#L1160-1 assume !(0 == ~E_4~0); 1080273#L1165-1 assume !(0 == ~E_5~0); 1080274#L1170-1 assume !(0 == ~E_6~0); 1081020#L1175-1 assume !(0 == ~E_7~0); 1080357#L1180-1 assume !(0 == ~E_8~0); 1080358#L1185-1 assume !(0 == ~E_9~0); 1079993#L1190-1 assume !(0 == ~E_10~0); 1079994#L1195-1 assume !(0 == ~E_11~0); 1080372#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080209#L525 assume !(1 == ~m_pc~0); 1079616#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1079617#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1080375#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1080376#L1350 assume !(0 != activate_threads_~tmp~1#1); 1079981#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1079982#L544 assume !(1 == ~t1_pc~0); 1080210#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1080211#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1080696#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1079829#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1079830#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1080481#L563 assume !(1 == ~t2_pc~0); 1080685#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1079638#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1079639#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1080067#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1080068#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1080565#L582 assume !(1 == ~t3_pc~0); 1080697#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1081112#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1081113#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1081036#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1079709#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1079710#L601 assume !(1 == ~t4_pc~0); 1080723#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1080215#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1080216#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1080714#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1080715#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1081097#L620 assume !(1 == ~t5_pc~0); 1080533#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1080534#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1080509#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1080510#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1081128#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1081129#L639 assume !(1 == ~t6_pc~0); 1080512#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1080106#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1080107#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1081038#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1080220#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1080221#L658 assume !(1 == ~t7_pc~0); 1080425#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1080426#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1080549#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1080550#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1079987#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1079988#L677 assume !(1 == ~t8_pc~0); 1080014#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1079793#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1079794#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1080061#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1080062#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1080832#L696 assume !(1 == ~t9_pc~0); 1080497#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1080498#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1080603#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1080522#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1080523#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1080759#L715 assume !(1 == ~t10_pc~0); 1081060#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1080620#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1080484#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1080485#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1080348#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1079782#L734 assume !(1 == ~t11_pc~0); 1079783#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1080280#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1080362#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1079518#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1079519#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1080586#L1213 assume !(1 == ~M_E~0); 1080346#L1213-2 assume !(1 == ~T1_E~0); 1080347#L1218-1 assume !(1 == ~T2_E~0); 1079553#L1223-1 assume !(1 == ~T3_E~0); 1079554#L1228-1 assume !(1 == ~T4_E~0); 1080322#L1233-1 assume !(1 == ~T5_E~0); 1081130#L1238-1 assume !(1 == ~T6_E~0); 1080712#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1080713#L1248-1 assume !(1 == ~T8_E~0); 1080764#L1253-1 assume !(1 == ~T9_E~0); 1080765#L1258-1 assume !(1 == ~T10_E~0); 1080740#L1263-1 assume !(1 == ~T11_E~0); 1080741#L1268-1 assume !(1 == ~E_1~0); 1080538#L1273-1 assume !(1 == ~E_2~0); 1080539#L1278-1 assume !(1 == ~E_3~0); 1080104#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1080105#L1288-1 assume !(1 == ~E_5~0); 1080886#L1293-1 assume !(1 == ~E_6~0); 1080840#L1298-1 assume !(1 == ~E_7~0); 1080568#L1303-1 assume !(1 == ~E_8~0); 1080115#L1308-1 assume !(1 == ~E_9~0); 1080005#L1313-1 assume !(1 == ~E_10~0); 1080006#L1318-1 assume !(1 == ~E_11~0); 1080015#L1323-1 assume { :end_inline_reset_delta_events } true; 1080016#L1644-2 [2021-12-19 19:17:57,605 INFO L793 eck$LassoCheckResult]: Loop: 1080016#L1644-2 assume !false; 1080633#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1080634#L1065 assume !false; 1080732#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1081126#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1079635#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1080979#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1080120#L906 assume !(0 != eval_~tmp~0#1); 1080122#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1148164#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1148163#L1090-3 assume !(0 == ~M_E~0); 1148162#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1148161#L1095-3 assume !(0 == ~T2_E~0); 1148160#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1148159#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1148158#L1110-3 assume !(0 == ~T5_E~0); 1148157#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1148156#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1148155#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1148154#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1148152#L1135-3 assume !(0 == ~T10_E~0); 1148150#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1148148#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1148146#L1150-3 assume !(0 == ~E_2~0); 1148144#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1148142#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1148139#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1148138#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1148137#L1175-3 assume !(0 == ~E_7~0); 1148136#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1148135#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1148134#L1190-3 assume !(0 == ~E_10~0); 1148133#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1148132#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1148131#L525-36 assume !(1 == ~m_pc~0); 1148129#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1146779#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1146778#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1146777#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1146776#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1146775#L544-36 assume !(1 == ~t1_pc~0); 1146774#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1146773#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1146772#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1146771#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1146769#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1146767#L563-36 assume 1 == ~t2_pc~0; 1146765#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1146762#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1146760#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1146758#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1146755#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1146753#L582-36 assume !(1 == ~t3_pc~0); 1144109#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1146750#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1146748#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1146746#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1146745#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1146743#L601-36 assume 1 == ~t4_pc~0; 1146741#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1146738#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1146736#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1146734#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1146733#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1146732#L620-36 assume !(1 == ~t5_pc~0); 1140881#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1146731#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1146730#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1146729#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1146728#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1146727#L639-36 assume !(1 == ~t6_pc~0); 1146725#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1146724#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1146723#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1146722#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1146721#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1146720#L658-36 assume !(1 == ~t7_pc~0); 1146718#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1146717#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1146716#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1146715#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1146714#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1146713#L677-36 assume !(1 == ~t8_pc~0); 1129772#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1146711#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1146710#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1146709#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1146708#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1146705#L696-36 assume !(1 == ~t9_pc~0); 1146701#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1146699#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1146697#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1146695#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1146692#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1146690#L715-36 assume !(1 == ~t10_pc~0); 1143745#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1146687#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1146685#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1146683#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1146681#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1146679#L734-36 assume !(1 == ~t11_pc~0); 1146675#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1146673#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1146671#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1146669#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1146667#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1146665#L1213-3 assume !(1 == ~M_E~0); 1095312#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1146661#L1218-3 assume !(1 == ~T2_E~0); 1146659#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1146657#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1146655#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1146653#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1146650#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1146648#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1146646#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1146644#L1258-3 assume !(1 == ~T10_E~0); 1146642#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1146639#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1146638#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1146637#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1146636#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1146635#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1146634#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1146633#L1298-3 assume !(1 == ~E_7~0); 1146632#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1146631#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1146630#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1146629#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1146628#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1146627#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1080289#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1080290#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1080805#L1663 assume !(0 == start_simulation_~tmp~3#1); 1079764#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1080514#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1079707#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1080420#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1079651#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1079652#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1079990#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1081078#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1080016#L1644-2 [2021-12-19 19:17:57,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:57,605 INFO L85 PathProgramCache]: Analyzing trace with hash -1619665514, now seen corresponding path program 1 times [2021-12-19 19:17:57,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:57,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463244011] [2021-12-19 19:17:57,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:57,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:57,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:57,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:57,629 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:57,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463244011] [2021-12-19 19:17:57,629 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463244011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:57,629 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:57,629 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:57,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058714214] [2021-12-19 19:17:57,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:57,630 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:57,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:57,630 INFO L85 PathProgramCache]: Analyzing trace with hash -1986099655, now seen corresponding path program 1 times [2021-12-19 19:17:57,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:57,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143608109] [2021-12-19 19:17:57,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:57,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:57,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:57,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:57,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:57,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143608109] [2021-12-19 19:17:57,658 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143608109] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:57,659 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:57,659 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:57,659 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14963555] [2021-12-19 19:17:57,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:57,659 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:57,659 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:57,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:57,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:57,660 INFO L87 Difference]: Start difference. First operand 69459 states and 97652 transitions. cyclomatic complexity: 28195 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:58,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:58,014 INFO L93 Difference]: Finished difference Result 108653 states and 152470 transitions. [2021-12-19 19:17:58,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:58,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108653 states and 152470 transitions. [2021-12-19 19:17:58,486 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108336 [2021-12-19 19:17:59,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108653 states to 108653 states and 152470 transitions. [2021-12-19 19:17:59,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108653 [2021-12-19 19:17:59,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108653 [2021-12-19 19:17:59,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108653 states and 152470 transitions. [2021-12-19 19:17:59,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:59,366 INFO L681 BuchiCegarLoop]: Abstraction has 108653 states and 152470 transitions. [2021-12-19 19:17:59,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108653 states and 152470 transitions. [2021-12-19 19:17:59,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108653 to 76605. [2021-12-19 19:17:59,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76605 states, 76605 states have (on average 1.4082631682005091) internal successors, (107880), 76604 states have internal predecessors, (107880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:00,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76605 states to 76605 states and 107880 transitions. [2021-12-19 19:18:00,092 INFO L704 BuchiCegarLoop]: Abstraction has 76605 states and 107880 transitions. [2021-12-19 19:18:00,092 INFO L587 BuchiCegarLoop]: Abstraction has 76605 states and 107880 transitions. [2021-12-19 19:18:00,092 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-12-19 19:18:00,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76605 states and 107880 transitions. [2021-12-19 19:18:00,295 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 76320 [2021-12-19 19:18:00,296 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:00,296 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:00,301 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,301 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:00,301 INFO L791 eck$LassoCheckResult]: Stem: 1258816#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1258817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1258825#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258826#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1258538#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1258539#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1258400#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1258307#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1258018#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1257652#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1257653#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1257702#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1257703#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1258688#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1258689#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1258740#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1258119#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1258120#L1090 assume !(0 == ~M_E~0); 1258165#L1090-2 assume !(0 == ~T1_E~0); 1258166#L1095-1 assume !(0 == ~T2_E~0); 1258905#L1100-1 assume !(0 == ~T3_E~0); 1258906#L1105-1 assume !(0 == ~T4_E~0); 1257930#L1110-1 assume !(0 == ~T5_E~0); 1257931#L1115-1 assume !(0 == ~T6_E~0); 1258348#L1120-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1258661#L1125-1 assume !(0 == ~T8_E~0); 1259339#L1130-1 assume !(0 == ~T9_E~0); 1258928#L1135-1 assume !(0 == ~T10_E~0); 1258929#L1140-1 assume !(0 == ~T11_E~0); 1258847#L1145-1 assume !(0 == ~E_1~0); 1258848#L1150-1 assume !(0 == ~E_2~0); 1258900#L1155-1 assume !(0 == ~E_3~0); 1259327#L1160-1 assume !(0 == ~E_4~0); 1258408#L1165-1 assume !(0 == ~E_5~0); 1258409#L1170-1 assume !(0 == ~E_6~0); 1259293#L1175-1 assume !(0 == ~E_7~0); 1258491#L1180-1 assume !(0 == ~E_8~0); 1258492#L1185-1 assume !(0 == ~E_9~0); 1259011#L1190-1 assume !(0 == ~E_10~0); 1259450#L1195-1 assume !(0 == ~E_11~0); 1259449#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1258338#L525 assume !(1 == ~m_pc~0); 1257739#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1257740#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1258510#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1258511#L1350 assume !(0 != activate_threads_~tmp~1#1); 1258108#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1258109#L544 assume !(1 == ~t1_pc~0); 1258346#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1258347#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1259407#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1259408#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1258625#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1258626#L563 assume !(1 == ~t2_pc~0); 1259108#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1257763#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1257764#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1258196#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1258197#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1258844#L582 assume !(1 == ~t3_pc~0); 1258845#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1259262#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1259263#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1259170#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1257833#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1257834#L601 assume !(1 == ~t4_pc~0); 1259439#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1258349#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1258350#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1258911#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1259364#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1259365#L620 assume !(1 == ~t5_pc~0); 1258678#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1258679#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1258657#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1258658#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1259280#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1259281#L639 assume !(1 == ~t6_pc~0); 1258659#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1258660#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1259176#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1259177#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1259437#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1259436#L658 assume !(1 == ~t7_pc~0); 1258563#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1258564#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1258698#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1258699#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1259434#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1259433#L677 assume !(1 == ~t8_pc~0); 1258141#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1258142#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1259131#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1259132#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1259432#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1259431#L696 assume !(1 == ~t9_pc~0); 1258637#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1258638#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1259430#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1258666#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1258667#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1258910#L715 assume !(1 == ~t10_pc~0); 1259321#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1259322#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1258629#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1258630#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1258481#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1258482#L734 assume !(1 == ~t11_pc~0); 1259420#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1259419#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1259418#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1259417#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1258738#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1258739#L1213 assume !(1 == ~M_E~0); 1259416#L1213-2 assume !(1 == ~T1_E~0); 1259415#L1218-1 assume !(1 == ~T2_E~0); 1259414#L1223-1 assume !(1 == ~T3_E~0); 1259413#L1228-1 assume !(1 == ~T4_E~0); 1259282#L1233-1 assume !(1 == ~T5_E~0); 1259283#L1238-1 assume !(1 == ~T6_E~0); 1259412#L1243-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1258861#L1248-1 assume !(1 == ~T8_E~0); 1258914#L1253-1 assume !(1 == ~T9_E~0); 1258915#L1258-1 assume !(1 == ~T10_E~0); 1258889#L1263-1 assume !(1 == ~T11_E~0); 1258890#L1268-1 assume !(1 == ~E_1~0); 1258686#L1273-1 assume !(1 == ~E_2~0); 1258687#L1278-1 assume !(1 == ~E_3~0); 1258237#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1258238#L1288-1 assume !(1 == ~E_5~0); 1259031#L1293-1 assume !(1 == ~E_6~0); 1258983#L1298-1 assume !(1 == ~E_7~0); 1258717#L1303-1 assume !(1 == ~E_8~0); 1258250#L1308-1 assume !(1 == ~E_9~0); 1258131#L1313-1 assume !(1 == ~E_10~0); 1258132#L1318-1 assume !(1 == ~E_11~0); 1258143#L1323-1 assume { :end_inline_reset_delta_events } true; 1258144#L1644-2 [2021-12-19 19:18:00,302 INFO L793 eck$LassoCheckResult]: Loop: 1258144#L1644-2 assume !false; 1258785#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1258786#L1065 assume !false; 1258881#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1259277#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1257758#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1259119#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1258255#L906 assume !(0 != eval_~tmp~0#1); 1258257#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1328794#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1328789#L1090-3 assume !(0 == ~M_E~0); 1328783#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1328778#L1095-3 assume !(0 == ~T2_E~0); 1328773#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1328768#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1328763#L1110-3 assume !(0 == ~T5_E~0); 1328757#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1328751#L1120-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1326812#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1326813#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1326795#L1135-3 assume !(0 == ~T10_E~0); 1326796#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1326779#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1326780#L1150-3 assume !(0 == ~E_2~0); 1326766#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1326767#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1326748#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1326749#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1326732#L1175-3 assume !(0 == ~E_7~0); 1326733#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1326715#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1326716#L1190-3 assume !(0 == ~E_10~0); 1326694#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1326695#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1326675#L525-36 assume !(1 == ~m_pc~0); 1326674#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1326648#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1326649#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1326604#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1326605#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1326107#L544-36 assume !(1 == ~t1_pc~0); 1326108#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1326103#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1326104#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1326097#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1326098#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1326090#L563-36 assume 1 == ~t2_pc~0; 1326092#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1326083#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1326084#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1326077#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1326078#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1324117#L582-36 assume !(1 == ~t3_pc~0); 1324118#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1324105#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1324106#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1324095#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1324096#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1324083#L601-36 assume !(1 == ~t4_pc~0); 1324084#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1324069#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1324070#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1324054#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1324055#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1324036#L620-36 assume !(1 == ~t5_pc~0); 1324035#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1324034#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1324033#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1324032#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1324031#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1324030#L639-36 assume !(1 == ~t6_pc~0); 1324028#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1324027#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1324026#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1324025#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1324024#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1324023#L658-36 assume !(1 == ~t7_pc~0); 1324021#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1324020#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1324019#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1324018#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1324017#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1324016#L677-36 assume !(1 == ~t8_pc~0); 1318801#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1324015#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1324014#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1324013#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1324012#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1324011#L696-36 assume 1 == ~t9_pc~0; 1324009#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1324007#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1324005#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1324003#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1324002#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1324001#L715-36 assume !(1 == ~t10_pc~0); 1296735#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1324000#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1323999#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1323998#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1323997#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1323996#L734-36 assume !(1 == ~t11_pc~0); 1323994#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1323993#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1323992#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1323991#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1323990#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1323989#L1213-3 assume !(1 == ~M_E~0); 1289441#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1323988#L1218-3 assume !(1 == ~T2_E~0); 1323987#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1323986#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1323985#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1323984#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1323982#L1243-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1323976#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1323970#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1323965#L1258-3 assume !(1 == ~T10_E~0); 1323960#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1323951#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1323945#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1323938#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1323933#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1323928#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1323921#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1323914#L1298-3 assume !(1 == ~E_7~0); 1323908#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1323903#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1323897#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1323890#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1323883#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1323844#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1323827#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1323560#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1291397#L1663 assume !(0 == start_simulation_~tmp~3#1); 1257888#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1258663#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1257831#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1258562#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1257778#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1257779#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1258118#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1259226#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1258144#L1644-2 [2021-12-19 19:18:00,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,302 INFO L85 PathProgramCache]: Analyzing trace with hash 948156820, now seen corresponding path program 1 times [2021-12-19 19:18:00,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125297818] [2021-12-19 19:18:00,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,303 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:00,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:00,324 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:00,324 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125297818] [2021-12-19 19:18:00,324 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125297818] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:00,324 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:00,324 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:00,324 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979576490] [2021-12-19 19:18:00,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:00,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:00,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:00,325 INFO L85 PathProgramCache]: Analyzing trace with hash -2062726725, now seen corresponding path program 1 times [2021-12-19 19:18:00,325 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:00,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878514262] [2021-12-19 19:18:00,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:00,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:00,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:00,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:00,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:00,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878514262] [2021-12-19 19:18:00,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878514262] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:00,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:00,346 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:00,346 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435291019] [2021-12-19 19:18:00,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:00,346 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:00,346 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:00,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:18:00,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:18:00,347 INFO L87 Difference]: Start difference. First operand 76605 states and 107880 transitions. cyclomatic complexity: 31277 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:01,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:01,102 INFO L93 Difference]: Finished difference Result 101491 states and 141986 transitions. [2021-12-19 19:18:01,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:18:01,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101491 states and 141986 transitions. [2021-12-19 19:18:01,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 101296 [2021-12-19 19:18:01,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101491 states to 101491 states and 141986 transitions. [2021-12-19 19:18:01,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101491 [2021-12-19 19:18:01,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101491 [2021-12-19 19:18:01,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101491 states and 141986 transitions. [2021-12-19 19:18:01,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:01,952 INFO L681 BuchiCegarLoop]: Abstraction has 101491 states and 141986 transitions. [2021-12-19 19:18:02,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101491 states and 141986 transitions. [2021-12-19 19:18:02,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101491 to 69459. [2021-12-19 19:18:02,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69459 states, 69459 states have (on average 1.4031011100073425) internal successors, (97458), 69458 states have internal predecessors, (97458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:02,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69459 states to 69459 states and 97458 transitions. [2021-12-19 19:18:02,957 INFO L704 BuchiCegarLoop]: Abstraction has 69459 states and 97458 transitions. [2021-12-19 19:18:02,958 INFO L587 BuchiCegarLoop]: Abstraction has 69459 states and 97458 transitions. [2021-12-19 19:18:02,958 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-12-19 19:18:02,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69459 states and 97458 transitions. [2021-12-19 19:18:03,152 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69280 [2021-12-19 19:18:03,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:03,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:03,158 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:03,158 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:03,159 INFO L791 eck$LassoCheckResult]: Stem: 1436902#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1436903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1436911#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1436912#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1436640#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1436641#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1436507#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1436414#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1436124#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1435760#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1435761#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1435810#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1435811#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1436780#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1436781#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1436826#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1436229#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1436230#L1090 assume !(0 == ~M_E~0); 1436273#L1090-2 assume !(0 == ~T1_E~0); 1436274#L1095-1 assume !(0 == ~T2_E~0); 1436983#L1100-1 assume !(0 == ~T3_E~0); 1436984#L1105-1 assume !(0 == ~T4_E~0); 1436038#L1110-1 assume !(0 == ~T5_E~0); 1436039#L1115-1 assume !(0 == ~T6_E~0); 1436453#L1120-1 assume !(0 == ~T7_E~0); 1436754#L1125-1 assume !(0 == ~T8_E~0); 1437389#L1130-1 assume !(0 == ~T9_E~0); 1437006#L1135-1 assume !(0 == ~T10_E~0); 1436233#L1140-1 assume !(0 == ~T11_E~0); 1436234#L1145-1 assume !(0 == ~E_1~0); 1436930#L1150-1 assume !(0 == ~E_2~0); 1436429#L1155-1 assume !(0 == ~E_3~0); 1436430#L1160-1 assume !(0 == ~E_4~0); 1436515#L1165-1 assume !(0 == ~E_5~0); 1436516#L1170-1 assume !(0 == ~E_6~0); 1437240#L1175-1 assume !(0 == ~E_7~0); 1436595#L1180-1 assume !(0 == ~E_8~0); 1436596#L1185-1 assume !(0 == ~E_9~0); 1436227#L1190-1 assume !(0 == ~E_10~0); 1436228#L1195-1 assume !(0 == ~E_11~0); 1436609#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1436443#L525 assume !(1 == ~m_pc~0); 1435847#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1435848#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1436612#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1436613#L1350 assume !(0 != activate_threads_~tmp~1#1); 1436216#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1436217#L544 assume !(1 == ~t1_pc~0); 1436451#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1436452#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1436927#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1436061#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1436062#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1436720#L563 assume !(1 == ~t2_pc~0); 1436913#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1435871#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1435872#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1436303#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1436304#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1436804#L582 assume !(1 == ~t3_pc~0); 1436928#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1437330#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1437331#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1437252#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1435942#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1435943#L601 assume !(1 == ~t4_pc~0); 1436949#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1436454#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1436455#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1436943#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1436944#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1437309#L620 assume !(1 == ~t5_pc~0); 1436770#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1436771#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1436750#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1436751#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1437343#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1437344#L639 assume !(1 == ~t6_pc~0); 1436753#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1436345#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1436346#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1437258#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1436461#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1436462#L658 assume !(1 == ~t7_pc~0); 1436663#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1436664#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1436789#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1436790#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1436223#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1436224#L677 assume !(1 == ~t8_pc~0); 1436249#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1436020#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1436021#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1436300#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1436301#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1437056#L696 assume !(1 == ~t9_pc~0); 1436731#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1436732#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1436838#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1436758#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1436759#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1436988#L715 assume !(1 == ~t10_pc~0); 1437271#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1436858#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1436723#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1436724#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1436587#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1436012#L734 assume !(1 == ~t11_pc~0); 1436013#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1436519#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1436600#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1435748#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1435749#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1436824#L1213 assume !(1 == ~M_E~0); 1436584#L1213-2 assume !(1 == ~T1_E~0); 1436585#L1218-1 assume !(1 == ~T2_E~0); 1435785#L1223-1 assume !(1 == ~T3_E~0); 1435786#L1228-1 assume !(1 == ~T4_E~0); 1436561#L1233-1 assume !(1 == ~T5_E~0); 1437345#L1238-1 assume !(1 == ~T6_E~0); 1436941#L1243-1 assume !(1 == ~T7_E~0); 1436942#L1248-1 assume !(1 == ~T8_E~0); 1436993#L1253-1 assume !(1 == ~T9_E~0); 1436994#L1258-1 assume !(1 == ~T10_E~0); 1436969#L1263-1 assume !(1 == ~T11_E~0); 1436970#L1268-1 assume !(1 == ~E_1~0); 1436778#L1273-1 assume !(1 == ~E_2~0); 1436779#L1278-1 assume !(1 == ~E_3~0); 1436343#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1436344#L1288-1 assume !(1 == ~E_5~0); 1437107#L1293-1 assume !(1 == ~E_6~0); 1437062#L1298-1 assume !(1 == ~E_7~0); 1436807#L1303-1 assume !(1 == ~E_8~0); 1436356#L1308-1 assume !(1 == ~E_9~0); 1436239#L1313-1 assume !(1 == ~E_10~0); 1436240#L1318-1 assume !(1 == ~E_11~0); 1436250#L1323-1 assume { :end_inline_reset_delta_events } true; 1436251#L1644-2 [2021-12-19 19:18:03,159 INFO L793 eck$LassoCheckResult]: Loop: 1436251#L1644-2 assume !false; 1490974#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1490969#L1065 assume !false; 1490968#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1490965#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1490955#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1490954#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1490952#L906 assume !(0 != eval_~tmp~0#1); 1490953#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1505125#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1505124#L1090-3 assume !(0 == ~M_E~0); 1505123#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1505122#L1095-3 assume !(0 == ~T2_E~0); 1505121#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1505120#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1505119#L1110-3 assume !(0 == ~T5_E~0); 1437244#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1437245#L1120-3 assume !(0 == ~T7_E~0); 1436938#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1436939#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1437268#L1135-3 assume !(0 == ~T10_E~0); 1436333#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1435821#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1435822#L1150-3 assume !(0 == ~E_2~0); 1435944#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1435945#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1436312#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1436313#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1436713#L1175-3 assume !(0 == ~E_7~0); 1436219#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1435974#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1435975#L1190-3 assume !(0 == ~E_10~0); 1437262#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1437263#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1436542#L525-36 assume !(1 == ~m_pc~0); 1436543#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1436073#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1436074#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1436371#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1436372#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1436278#L544-36 assume !(1 == ~t1_pc~0); 1436279#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1437104#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1504546#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1504545#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1504544#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1504543#L563-36 assume 1 == ~t2_pc~0; 1504542#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1504540#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1504539#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1504538#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1504536#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1504534#L582-36 assume !(1 == ~t3_pc~0); 1501781#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1504531#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1504529#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1504527#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1504525#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1504523#L601-36 assume !(1 == ~t4_pc~0); 1504520#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1504518#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1504516#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1504514#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1504512#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1504510#L620-36 assume !(1 == ~t5_pc~0); 1500014#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1504507#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1504505#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1504503#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1504501#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1504499#L639-36 assume !(1 == ~t6_pc~0); 1504496#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1504494#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1504492#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1504490#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1504488#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1504485#L658-36 assume !(1 == ~t7_pc~0); 1504482#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1504480#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1504478#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1504476#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1504474#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1504472#L677-36 assume !(1 == ~t8_pc~0); 1502853#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1504469#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1504467#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1504465#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1504463#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1504461#L696-36 assume !(1 == ~t9_pc~0); 1437378#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1437379#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1504706#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1437197#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1436714#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1436715#L715-36 assume !(1 == ~t10_pc~0); 1496099#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1495829#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1495821#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1495816#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1495810#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1495765#L734-36 assume !(1 == ~t11_pc~0); 1495720#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1495712#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1495705#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1495699#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1495693#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1495687#L1213-3 assume !(1 == ~M_E~0); 1459001#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1495675#L1218-3 assume !(1 == ~T2_E~0); 1495671#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1495664#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1495658#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1495651#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1495642#L1243-3 assume !(1 == ~T7_E~0); 1495631#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1495621#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1495611#L1258-3 assume !(1 == ~T10_E~0); 1495601#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1495593#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1495583#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495574#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1495566#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1495558#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1495549#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1495540#L1298-3 assume !(1 == ~E_7~0); 1495530#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1495520#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1495512#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1495505#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1495500#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1495302#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1495285#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1494988#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1459190#L1663 assume !(0 == start_simulation_~tmp~3#1); 1459191#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1491007#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1490999#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1490996#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1490991#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1490986#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1490982#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1490977#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1436251#L1644-2 [2021-12-19 19:18:03,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:03,160 INFO L85 PathProgramCache]: Analyzing trace with hash 1086953880, now seen corresponding path program 1 times [2021-12-19 19:18:03,160 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:03,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3457344] [2021-12-19 19:18:03,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:03,161 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:03,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:03,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:03,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:03,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3457344] [2021-12-19 19:18:03,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3457344] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:03,210 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:03,210 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:03,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743745878] [2021-12-19 19:18:03,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:03,210 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:03,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:03,211 INFO L85 PathProgramCache]: Analyzing trace with hash -1761398948, now seen corresponding path program 1 times [2021-12-19 19:18:03,211 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:03,211 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264293106] [2021-12-19 19:18:03,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:03,211 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:03,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:03,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:03,231 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:03,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264293106] [2021-12-19 19:18:03,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264293106] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:03,231 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:03,231 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:03,232 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735323099] [2021-12-19 19:18:03,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:03,232 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:03,232 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:03,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:18:03,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:18:03,233 INFO L87 Difference]: Start difference. First operand 69459 states and 97458 transitions. cyclomatic complexity: 28001 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:03,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:03,627 INFO L93 Difference]: Finished difference Result 109147 states and 151941 transitions. [2021-12-19 19:18:03,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:18:03,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109147 states and 151941 transitions. [2021-12-19 19:18:04,545 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 108752 [2021-12-19 19:18:04,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109147 states to 109147 states and 151941 transitions. [2021-12-19 19:18:04,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109147 [2021-12-19 19:18:04,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109147 [2021-12-19 19:18:04,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109147 states and 151941 transitions. [2021-12-19 19:18:04,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:04,951 INFO L681 BuchiCegarLoop]: Abstraction has 109147 states and 151941 transitions. [2021-12-19 19:18:05,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109147 states and 151941 transitions. [2021-12-19 19:18:05,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109147 to 76605. [2021-12-19 19:18:05,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76605 states, 76605 states have (on average 1.3977808237060243) internal successors, (107077), 76604 states have internal predecessors, (107077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:05,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76605 states to 76605 states and 107077 transitions. [2021-12-19 19:18:05,797 INFO L704 BuchiCegarLoop]: Abstraction has 76605 states and 107077 transitions. [2021-12-19 19:18:05,797 INFO L587 BuchiCegarLoop]: Abstraction has 76605 states and 107077 transitions. [2021-12-19 19:18:05,797 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-12-19 19:18:05,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76605 states and 107077 transitions. [2021-12-19 19:18:06,524 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 76320 [2021-12-19 19:18:06,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:06,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:06,530 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:06,530 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:06,532 INFO L791 eck$LassoCheckResult]: Stem: 1615515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1615516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1615529#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1615530#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1615247#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1615248#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1615116#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1615026#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1614741#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1614378#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1614379#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1614427#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1614428#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1615390#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1615391#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1615443#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1614843#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1614844#L1090 assume !(0 == ~M_E~0); 1614891#L1090-2 assume !(0 == ~T1_E~0); 1614892#L1095-1 assume !(0 == ~T2_E~0); 1615601#L1100-1 assume !(0 == ~T3_E~0); 1615602#L1105-1 assume !(0 == ~T4_E~0); 1614655#L1110-1 assume !(0 == ~T5_E~0); 1614656#L1115-1 assume !(0 == ~T6_E~0); 1615066#L1120-1 assume !(0 == ~T7_E~0); 1615361#L1125-1 assume !(0 == ~T8_E~0); 1616026#L1130-1 assume !(0 == ~T9_E~0); 1615624#L1135-1 assume !(0 == ~T10_E~0); 1614851#L1140-1 assume !(0 == ~T11_E~0); 1614852#L1145-1 assume !(0 == ~E_1~0); 1615546#L1150-1 assume !(0 == ~E_2~0); 1615041#L1155-1 assume !(0 == ~E_3~0); 1615042#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1615124#L1165-1 assume !(0 == ~E_5~0); 1615125#L1170-1 assume !(0 == ~E_6~0); 1615980#L1175-1 assume !(0 == ~E_7~0); 1615203#L1180-1 assume !(0 == ~E_8~0); 1615204#L1185-1 assume !(0 == ~E_9~0); 1615713#L1190-1 assume !(0 == ~E_10~0); 1616188#L1195-1 assume !(0 == ~E_11~0); 1616187#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1616186#L525 assume !(1 == ~m_pc~0); 1616184#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1616183#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1616182#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1616181#L1350 assume !(0 != activate_threads_~tmp~1#1); 1616180#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1615275#L544 assume !(1 == ~t1_pc~0); 1615062#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1615063#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1615543#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1616177#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1615327#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1615328#L563 assume !(1 == ~t2_pc~0); 1615531#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1615532#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1615322#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1615323#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1615413#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1615414#L582 assume !(1 == ~t3_pc~0); 1615544#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1616028#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1616169#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1616168#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1616167#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1616166#L601 assume !(1 == ~t4_pc~0); 1616164#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1616163#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1616162#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1616161#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1616160#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1616159#L620 assume !(1 == ~t5_pc~0); 1616158#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1616157#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1616156#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1616155#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1616154#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1616153#L639 assume !(1 == ~t6_pc~0); 1616151#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1616150#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1616149#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1616148#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1616147#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1616146#L658 assume !(1 == ~t7_pc~0); 1616144#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1616143#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1616142#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1616141#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1616140#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1616139#L677 assume !(1 == ~t8_pc~0); 1616138#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1616137#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1616136#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1616135#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1616134#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1616133#L696 assume !(1 == ~t9_pc~0); 1616132#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1616171#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1616170#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1616127#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1616126#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1616125#L715 assume !(1 == ~t10_pc~0); 1616124#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1616123#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1616122#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1616121#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1616120#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1616119#L734 assume !(1 == ~t11_pc~0); 1616117#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1616116#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1616115#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1616114#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1616113#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1616112#L1213 assume !(1 == ~M_E~0); 1616111#L1213-2 assume !(1 == ~T1_E~0); 1616110#L1218-1 assume !(1 == ~T2_E~0); 1616109#L1223-1 assume !(1 == ~T3_E~0); 1616108#L1228-1 assume !(1 == ~T4_E~0); 1616107#L1233-1 assume !(1 == ~T5_E~0); 1616106#L1238-1 assume !(1 == ~T6_E~0); 1616105#L1243-1 assume !(1 == ~T7_E~0); 1616104#L1248-1 assume !(1 == ~T8_E~0); 1616103#L1253-1 assume !(1 == ~T9_E~0); 1616102#L1258-1 assume !(1 == ~T10_E~0); 1616101#L1263-1 assume !(1 == ~T11_E~0); 1616100#L1268-1 assume !(1 == ~E_1~0); 1616099#L1273-1 assume !(1 == ~E_2~0); 1616098#L1278-1 assume !(1 == ~E_3~0); 1616097#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1614956#L1288-1 assume !(1 == ~E_5~0); 1615734#L1293-1 assume !(1 == ~E_6~0); 1615683#L1298-1 assume !(1 == ~E_7~0); 1615417#L1303-1 assume !(1 == ~E_8~0); 1614967#L1308-1 assume !(1 == ~E_9~0); 1614857#L1313-1 assume !(1 == ~E_10~0); 1614858#L1318-1 assume !(1 == ~E_11~0); 1614867#L1323-1 assume { :end_inline_reset_delta_events } true; 1614868#L1644-2 [2021-12-19 19:18:06,532 INFO L793 eck$LassoCheckResult]: Loop: 1614868#L1644-2 assume !false; 1674884#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1674874#L1065 assume !false; 1674871#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1674779#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1674765#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1674764#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1674762#L906 assume !(0 != eval_~tmp~0#1); 1674763#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1684822#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1684818#L1090-3 assume !(0 == ~M_E~0); 1684814#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1684808#L1095-3 assume !(0 == ~T2_E~0); 1684803#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1684798#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1684793#L1110-3 assume !(0 == ~T5_E~0); 1684787#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1684781#L1120-3 assume !(0 == ~T7_E~0); 1684775#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1684767#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1684760#L1135-3 assume !(0 == ~T10_E~0); 1684752#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1684745#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1684737#L1150-3 assume !(0 == ~E_2~0); 1684730#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1684722#L1160-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1682692#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1682693#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1682630#L1175-3 assume !(0 == ~E_7~0); 1682631#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1682569#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1682570#L1190-3 assume !(0 == ~E_10~0); 1682464#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1682465#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1682458#L525-36 assume !(1 == ~m_pc~0); 1682457#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1682440#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1682441#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1682422#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1682423#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1682404#L544-36 assume !(1 == ~t1_pc~0); 1682405#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1682389#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1682390#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1682371#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1682372#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1682354#L563-36 assume !(1 == ~t2_pc~0); 1682355#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1682334#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1682335#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1682298#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1682299#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1682263#L582-36 assume !(1 == ~t3_pc~0); 1682261#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1682259#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682257#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1682255#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1682253#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1682251#L601-36 assume 1 == ~t4_pc~0; 1682249#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1682245#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1682243#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1682241#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1682239#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1682237#L620-36 assume !(1 == ~t5_pc~0); 1677758#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1682235#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1682233#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1682231#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1682229#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1682227#L639-36 assume 1 == ~t6_pc~0; 1682225#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1682220#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1682218#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1682216#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1682203#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1682201#L658-36 assume !(1 == ~t7_pc~0); 1682199#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1682198#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1682197#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1682196#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1682195#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1658916#L677-36 assume !(1 == ~t8_pc~0); 1658911#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1658907#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1658903#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1658900#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1657054#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1643009#L696-36 assume !(1 == ~t9_pc~0); 1643002#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1642999#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1642996#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1642994#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1642990#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1642988#L715-36 assume !(1 == ~t10_pc~0); 1642987#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1642986#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1642985#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1642984#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1642983#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1642982#L734-36 assume 1 == ~t11_pc~0; 1642981#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1642979#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1642978#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1642977#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1642976#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642975#L1213-3 assume !(1 == ~M_E~0); 1640393#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1642974#L1218-3 assume !(1 == ~T2_E~0); 1642973#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1642972#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1642971#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1642970#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1642969#L1243-3 assume !(1 == ~T7_E~0); 1642968#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1642967#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1642966#L1258-3 assume !(1 == ~T10_E~0); 1642965#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1642964#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1642963#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1642962#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1642960#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1642958#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1642956#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1642954#L1298-3 assume !(1 == ~E_7~0); 1642951#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1642949#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1642947#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1642945#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1642943#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1642939#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1642925#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1642922#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1640705#L1663 assume !(0 == start_simulation_~tmp~3#1); 1640706#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1674909#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1674903#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1674901#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1674899#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1674897#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1674890#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1674887#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1614868#L1644-2 [2021-12-19 19:18:06,532 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:06,532 INFO L85 PathProgramCache]: Analyzing trace with hash 968512406, now seen corresponding path program 1 times [2021-12-19 19:18:06,533 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:06,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982702079] [2021-12-19 19:18:06,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:06,533 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:06,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:06,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:06,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:06,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982702079] [2021-12-19 19:18:06,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982702079] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:06,551 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:06,552 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:06,552 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888440491] [2021-12-19 19:18:06,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:06,552 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:06,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:06,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1690033502, now seen corresponding path program 1 times [2021-12-19 19:18:06,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:06,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021382552] [2021-12-19 19:18:06,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:06,553 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:06,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:06,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:06,576 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:06,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021382552] [2021-12-19 19:18:06,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021382552] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:06,577 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:06,577 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:06,577 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618068203] [2021-12-19 19:18:06,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:06,578 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:06,578 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:06,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:18:06,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:18:06,579 INFO L87 Difference]: Start difference. First operand 76605 states and 107077 transitions. cyclomatic complexity: 30474 Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:06,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:06,933 INFO L93 Difference]: Finished difference Result 100115 states and 138991 transitions. [2021-12-19 19:18:06,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:18:06,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100115 states and 138991 transitions. [2021-12-19 19:18:07,340 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 99904 [2021-12-19 19:18:07,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100115 states to 100115 states and 138991 transitions. [2021-12-19 19:18:07,601 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100115 [2021-12-19 19:18:07,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100115 [2021-12-19 19:18:07,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100115 states and 138991 transitions. [2021-12-19 19:18:07,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:07,730 INFO L681 BuchiCegarLoop]: Abstraction has 100115 states and 138991 transitions. [2021-12-19 19:18:07,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100115 states and 138991 transitions. [2021-12-19 19:18:08,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100115 to 69459. [2021-12-19 19:18:08,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69459 states, 69459 states have (on average 1.3915403331461726) internal successors, (96655), 69458 states have internal predecessors, (96655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:08,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69459 states to 69459 states and 96655 transitions. [2021-12-19 19:18:08,795 INFO L704 BuchiCegarLoop]: Abstraction has 69459 states and 96655 transitions. [2021-12-19 19:18:08,795 INFO L587 BuchiCegarLoop]: Abstraction has 69459 states and 96655 transitions. [2021-12-19 19:18:08,795 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-12-19 19:18:08,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69459 states and 96655 transitions. [2021-12-19 19:18:08,975 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69280 [2021-12-19 19:18:08,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:08,976 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:08,979 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:08,979 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:08,979 INFO L791 eck$LassoCheckResult]: Stem: 1792246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1792247#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1792256#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1792257#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1791988#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1791989#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1791855#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1791761#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1791473#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1791110#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1791111#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1791158#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1791159#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1792127#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1792128#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1792170#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1791577#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1791578#L1090 assume !(0 == ~M_E~0); 1791622#L1090-2 assume !(0 == ~T1_E~0); 1791623#L1095-1 assume !(0 == ~T2_E~0); 1792327#L1100-1 assume !(0 == ~T3_E~0); 1792328#L1105-1 assume !(0 == ~T4_E~0); 1791388#L1110-1 assume !(0 == ~T5_E~0); 1791389#L1115-1 assume !(0 == ~T6_E~0); 1791801#L1120-1 assume !(0 == ~T7_E~0); 1792102#L1125-1 assume !(0 == ~T8_E~0); 1792741#L1130-1 assume !(0 == ~T9_E~0); 1792353#L1135-1 assume !(0 == ~T10_E~0); 1791583#L1140-1 assume !(0 == ~T11_E~0); 1791584#L1145-1 assume !(0 == ~E_1~0); 1792275#L1150-1 assume !(0 == ~E_2~0); 1791776#L1155-1 assume !(0 == ~E_3~0); 1791777#L1160-1 assume !(0 == ~E_4~0); 1791863#L1165-1 assume !(0 == ~E_5~0); 1791864#L1170-1 assume !(0 == ~E_6~0); 1792583#L1175-1 assume !(0 == ~E_7~0); 1791944#L1180-1 assume !(0 == ~E_8~0); 1791945#L1185-1 assume !(0 == ~E_9~0); 1791579#L1190-1 assume !(0 == ~E_10~0); 1791580#L1195-1 assume !(0 == ~E_11~0); 1791959#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1791791#L525 assume !(1 == ~m_pc~0); 1791196#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1791197#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1791962#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1791963#L1350 assume !(0 != activate_threads_~tmp~1#1); 1791566#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1791567#L544 assume !(1 == ~t1_pc~0); 1791799#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1791800#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1792272#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1791410#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1791411#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1792070#L563 assume !(1 == ~t2_pc~0); 1792258#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1791220#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1791221#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1791652#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1791653#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1792151#L582 assume !(1 == ~t3_pc~0); 1792273#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1792672#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792673#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1792594#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1791291#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1791292#L601 assume !(1 == ~t4_pc~0); 1792293#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1791802#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1791803#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1792287#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1792288#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1792656#L620 assume !(1 == ~t5_pc~0); 1792117#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1792118#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1792098#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1792099#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1792691#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1792692#L639 assume !(1 == ~t6_pc~0); 1792100#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1791694#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1791695#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1792598#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1791810#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1791811#L658 assume !(1 == ~t7_pc~0); 1792012#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1792013#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1792136#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1792137#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1791573#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1791574#L677 assume !(1 == ~t8_pc~0); 1791599#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1791370#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1791371#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1791649#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1791650#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1792411#L696 assume !(1 == ~t9_pc~0); 1792081#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1792082#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1792182#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1792106#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1792107#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1792332#L715 assume !(1 == ~t10_pc~0); 1792618#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1792201#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1792073#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1792074#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1791936#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1791362#L734 assume !(1 == ~t11_pc~0); 1791363#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1791867#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1791949#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1791098#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1791099#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1792169#L1213 assume !(1 == ~M_E~0); 1791933#L1213-2 assume !(1 == ~T1_E~0); 1791934#L1218-1 assume !(1 == ~T2_E~0); 1791135#L1223-1 assume !(1 == ~T3_E~0); 1791136#L1228-1 assume !(1 == ~T4_E~0); 1791910#L1233-1 assume !(1 == ~T5_E~0); 1792693#L1238-1 assume !(1 == ~T6_E~0); 1792285#L1243-1 assume !(1 == ~T7_E~0); 1792286#L1248-1 assume !(1 == ~T8_E~0); 1792337#L1253-1 assume !(1 == ~T9_E~0); 1792338#L1258-1 assume !(1 == ~T10_E~0); 1792313#L1263-1 assume !(1 == ~T11_E~0); 1792314#L1268-1 assume !(1 == ~E_1~0); 1792125#L1273-1 assume !(1 == ~E_2~0); 1792126#L1278-1 assume !(1 == ~E_3~0); 1791692#L1283-1 assume !(1 == ~E_4~0); 1791693#L1288-1 assume !(1 == ~E_5~0); 1792461#L1293-1 assume !(1 == ~E_6~0); 1792416#L1298-1 assume !(1 == ~E_7~0); 1792154#L1303-1 assume !(1 == ~E_8~0); 1791704#L1308-1 assume !(1 == ~E_9~0); 1791589#L1313-1 assume !(1 == ~E_10~0); 1791590#L1318-1 assume !(1 == ~E_11~0); 1791600#L1323-1 assume { :end_inline_reset_delta_events } true; 1791601#L1644-2 [2021-12-19 19:18:08,980 INFO L793 eck$LassoCheckResult]: Loop: 1791601#L1644-2 assume !false; 1850730#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1850725#L1065 assume !false; 1850724#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1848696#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1848676#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1848667#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1848655#L906 assume !(0 != eval_~tmp~0#1); 1848656#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1858918#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1858916#L1090-3 assume !(0 == ~M_E~0); 1858914#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1858912#L1095-3 assume !(0 == ~T2_E~0); 1858910#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1858909#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1858907#L1110-3 assume !(0 == ~T5_E~0); 1858905#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1858903#L1120-3 assume !(0 == ~T7_E~0); 1858901#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1858899#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1858896#L1135-3 assume !(0 == ~T10_E~0); 1858894#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1858892#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1858890#L1150-3 assume !(0 == ~E_2~0); 1858888#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1858885#L1160-3 assume !(0 == ~E_4~0); 1858883#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1858881#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1858879#L1175-3 assume !(0 == ~E_7~0); 1858877#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1858875#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1858874#L1190-3 assume !(0 == ~E_10~0); 1858873#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1858872#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1858870#L525-36 assume !(1 == ~m_pc~0); 1858868#L525-38 is_master_triggered_~__retres1~0#1 := 0; 1858867#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1858866#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1858865#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 1858864#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1858863#L544-36 assume !(1 == ~t1_pc~0); 1858862#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 1858861#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1858860#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1858858#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1858856#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1858854#L563-36 assume 1 == ~t2_pc~0; 1858852#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1858850#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1858849#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1858848#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1858847#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1858846#L582-36 assume !(1 == ~t3_pc~0); 1858000#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1858842#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1858840#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1858838#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1858836#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1858830#L601-36 assume !(1 == ~t4_pc~0); 1858828#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1858826#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1858824#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1858822#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1858820#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1858817#L620-36 assume !(1 == ~t5_pc~0); 1858468#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1858814#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1858812#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1858810#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1858808#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1858807#L639-36 assume !(1 == ~t6_pc~0); 1858804#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1858802#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1858800#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1858798#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1858797#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1858796#L658-36 assume !(1 == ~t7_pc~0); 1858792#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1858790#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1858788#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1858786#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 1858784#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1858782#L677-36 assume !(1 == ~t8_pc~0); 1848629#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 1858151#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1858150#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1858149#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1858148#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1858147#L696-36 assume !(1 == ~t9_pc~0); 1858145#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1858143#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1858141#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1858140#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 1858138#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1858136#L715-36 assume !(1 == ~t10_pc~0); 1857641#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1858133#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1858131#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1858129#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1858126#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1858124#L734-36 assume !(1 == ~t11_pc~0); 1858121#L734-38 is_transmit11_triggered_~__retres1~11#1 := 0; 1858119#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1858117#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1858115#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1858114#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1858112#L1213-3 assume !(1 == ~M_E~0); 1820647#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1858109#L1218-3 assume !(1 == ~T2_E~0); 1858107#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1858106#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1858105#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1858104#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1858103#L1243-3 assume !(1 == ~T7_E~0); 1858102#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1858101#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1858100#L1258-3 assume !(1 == ~T10_E~0); 1858099#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1858098#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1858097#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1858096#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1858095#L1283-3 assume !(1 == ~E_4~0); 1858094#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1858093#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1858092#L1298-3 assume !(1 == ~E_7~0); 1858091#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1858090#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1858089#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1858088#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1858087#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1858086#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1791879#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1791880#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1792381#L1663 assume !(0 == start_simulation_~tmp~3#1); 1844178#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1850748#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1850742#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1850740#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1850738#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1850736#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1850734#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1850732#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1791601#L1644-2 [2021-12-19 19:18:08,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:08,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 1 times [2021-12-19 19:18:08,980 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:08,981 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425773211] [2021-12-19 19:18:08,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:08,981 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:08,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:08,987 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:08,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:09,036 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:09,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:09,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1234267488, now seen corresponding path program 1 times [2021-12-19 19:18:09,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:09,037 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135202179] [2021-12-19 19:18:09,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:09,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:09,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:09,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:09,058 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135202179] [2021-12-19 19:18:09,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135202179] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:09,058 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:09,058 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:18:09,058 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421723676] [2021-12-19 19:18:09,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:09,058 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:09,058 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:09,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:18:09,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:18:09,059 INFO L87 Difference]: Start difference. First operand 69459 states and 96655 transitions. cyclomatic complexity: 27198 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:09,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:09,411 INFO L93 Difference]: Finished difference Result 128915 states and 177487 transitions. [2021-12-19 19:18:09,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-19 19:18:09,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128915 states and 177487 transitions. [2021-12-19 19:18:10,467 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 128704 [2021-12-19 19:18:10,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128915 states to 128915 states and 177487 transitions. [2021-12-19 19:18:10,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128915 [2021-12-19 19:18:10,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128915 [2021-12-19 19:18:10,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128915 states and 177487 transitions. [2021-12-19 19:18:10,928 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:10,928 INFO L681 BuchiCegarLoop]: Abstraction has 128915 states and 177487 transitions. [2021-12-19 19:18:11,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128915 states and 177487 transitions. [2021-12-19 19:18:11,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128915 to 69651. [2021-12-19 19:18:11,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69651 states, 69651 states have (on average 1.3904610127636359) internal successors, (96847), 69650 states have internal predecessors, (96847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:11,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69651 states to 69651 states and 96847 transitions. [2021-12-19 19:18:11,718 INFO L704 BuchiCegarLoop]: Abstraction has 69651 states and 96847 transitions. [2021-12-19 19:18:11,718 INFO L587 BuchiCegarLoop]: Abstraction has 69651 states and 96847 transitions. [2021-12-19 19:18:11,718 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-12-19 19:18:11,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69651 states and 96847 transitions. [2021-12-19 19:18:12,370 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 69472 [2021-12-19 19:18:12,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:12,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:12,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:12,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:12,379 INFO L791 eck$LassoCheckResult]: Stem: 1990625#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1990626#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1990635#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1990636#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1990371#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 1990372#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1990240#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1990151#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1989863#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1989500#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1989501#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1989549#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1989550#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1990505#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1990506#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1990549#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1989966#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1989967#L1090 assume !(0 == ~M_E~0); 1990012#L1090-2 assume !(0 == ~T1_E~0); 1990013#L1095-1 assume !(0 == ~T2_E~0); 1990711#L1100-1 assume !(0 == ~T3_E~0); 1990712#L1105-1 assume !(0 == ~T4_E~0); 1989777#L1110-1 assume !(0 == ~T5_E~0); 1989778#L1115-1 assume !(0 == ~T6_E~0); 1990189#L1120-1 assume !(0 == ~T7_E~0); 1990478#L1125-1 assume !(0 == ~T8_E~0); 1991136#L1130-1 assume !(0 == ~T9_E~0); 1990732#L1135-1 assume !(0 == ~T10_E~0); 1989972#L1140-1 assume !(0 == ~T11_E~0); 1989973#L1145-1 assume !(0 == ~E_1~0); 1990654#L1150-1 assume !(0 == ~E_2~0); 1990164#L1155-1 assume !(0 == ~E_3~0); 1990165#L1160-1 assume !(0 == ~E_4~0); 1990248#L1165-1 assume !(0 == ~E_5~0); 1990249#L1170-1 assume !(0 == ~E_6~0); 1990959#L1175-1 assume !(0 == ~E_7~0); 1990328#L1180-1 assume !(0 == ~E_8~0); 1990329#L1185-1 assume !(0 == ~E_9~0); 1989968#L1190-1 assume !(0 == ~E_10~0); 1989969#L1195-1 assume !(0 == ~E_11~0); 1990342#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1990179#L525 assume !(1 == ~m_pc~0); 1989587#L525-2 is_master_triggered_~__retres1~0#1 := 0; 1989588#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1990345#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1990346#L1350 assume !(0 != activate_threads_~tmp~1#1); 1989955#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1989956#L544 assume !(1 == ~t1_pc~0); 1990187#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1990188#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1990651#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1989801#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 1989802#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1990446#L563 assume !(1 == ~t2_pc~0); 1990637#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1989611#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1989612#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1990041#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 1990042#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1990531#L582 assume !(1 == ~t3_pc~0); 1990652#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1991057#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1991058#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1990969#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 1989680#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1989681#L601 assume !(1 == ~t4_pc~0); 1990675#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1990190#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1990191#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1990667#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 1990668#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1991042#L620 assume !(1 == ~t5_pc~0); 1990495#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1990496#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1990476#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1990477#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 1991075#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1991076#L639 assume !(1 == ~t6_pc~0); 1990475#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1990083#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1990084#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1990975#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 1990197#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1990198#L658 assume !(1 == ~t7_pc~0); 1990394#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1990395#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1990517#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1990518#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 1989962#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1989963#L677 assume !(1 == ~t8_pc~0); 1989988#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1989759#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1989760#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1990038#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 1990039#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1990781#L696 assume !(1 == ~t9_pc~0); 1990457#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1990458#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1990561#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1990482#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 1990483#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1990716#L715 assume !(1 == ~t10_pc~0); 1991000#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1990579#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1990449#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1990450#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 1990320#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1989751#L734 assume !(1 == ~t11_pc~0); 1989752#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1990252#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1990333#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1989488#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 1989489#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1990548#L1213 assume !(1 == ~M_E~0); 1990317#L1213-2 assume !(1 == ~T1_E~0); 1990318#L1218-1 assume !(1 == ~T2_E~0); 1989525#L1223-1 assume !(1 == ~T3_E~0); 1989526#L1228-1 assume !(1 == ~T4_E~0); 1990294#L1233-1 assume !(1 == ~T5_E~0); 1991077#L1238-1 assume !(1 == ~T6_E~0); 1990665#L1243-1 assume !(1 == ~T7_E~0); 1990666#L1248-1 assume !(1 == ~T8_E~0); 1990718#L1253-1 assume !(1 == ~T9_E~0); 1990719#L1258-1 assume !(1 == ~T10_E~0); 1990696#L1263-1 assume !(1 == ~T11_E~0); 1990697#L1268-1 assume !(1 == ~E_1~0); 1990503#L1273-1 assume !(1 == ~E_2~0); 1990504#L1278-1 assume !(1 == ~E_3~0); 1990081#L1283-1 assume !(1 == ~E_4~0); 1990082#L1288-1 assume !(1 == ~E_5~0); 1990830#L1293-1 assume !(1 == ~E_6~0); 1990787#L1298-1 assume !(1 == ~E_7~0); 1990534#L1303-1 assume !(1 == ~E_8~0); 1990092#L1308-1 assume !(1 == ~E_9~0); 1989978#L1313-1 assume !(1 == ~E_10~0); 1989979#L1318-1 assume !(1 == ~E_11~0); 1989989#L1323-1 assume { :end_inline_reset_delta_events } true; 1989990#L1644-2 [2021-12-19 19:18:12,394 INFO L793 eck$LassoCheckResult]: Loop: 1989990#L1644-2 assume !false; 2048000#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2047995#L1065 assume !false; 2047956#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2046646#L829 assume !(0 == ~m_st~0); 2046647#L833 assume !(0 == ~t1_st~0); 2046636#L837 assume !(0 == ~t2_st~0); 2046637#L841 assume !(0 == ~t3_st~0); 2046640#L845 assume !(0 == ~t4_st~0); 2046642#L849 assume !(0 == ~t5_st~0); 2046644#L853 assume !(0 == ~t6_st~0); 2046645#L857 assume !(0 == ~t7_st~0); 2046648#L861 assume !(0 == ~t8_st~0); 2046638#L865 assume !(0 == ~t9_st~0); 2046639#L869 assume !(0 == ~t10_st~0); 2046641#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2046643#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2028152#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2028153#L906 assume !(0 != eval_~tmp~0#1); 2054827#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2054828#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2054817#L1090-3 assume !(0 == ~M_E~0); 2054818#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2054809#L1095-3 assume !(0 == ~T2_E~0); 2054810#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2054801#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2054802#L1110-3 assume !(0 == ~T5_E~0); 2054795#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2054796#L1120-3 assume !(0 == ~T7_E~0); 2054787#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2054788#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2054779#L1135-3 assume !(0 == ~T10_E~0); 2054780#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2054770#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2054771#L1150-3 assume !(0 == ~E_2~0); 2054762#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2054763#L1160-3 assume !(0 == ~E_4~0); 2054754#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2054755#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2054748#L1175-3 assume !(0 == ~E_7~0); 2054749#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2054737#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2054738#L1190-3 assume !(0 == ~E_10~0); 2054725#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2054726#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2054713#L525-36 assume !(1 == ~m_pc~0); 2054712#L525-38 is_master_triggered_~__retres1~0#1 := 0; 2054701#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2054702#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2054691#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 2054692#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054680#L544-36 assume !(1 == ~t1_pc~0); 2054681#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2054669#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2054670#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054615#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2054616#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2054592#L563-36 assume 1 == ~t2_pc~0; 2054594#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2053087#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2053088#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2051330#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2051331#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2049594#L582-36 assume !(1 == ~t3_pc~0); 2049595#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2049586#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2049587#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2049578#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2049579#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2049567#L601-36 assume !(1 == ~t4_pc~0); 2049568#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2049559#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2049560#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2048978#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2048979#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2048518#L620-36 assume !(1 == ~t5_pc~0); 2048519#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2048513#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2048514#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2048507#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2048508#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2048500#L639-36 assume !(1 == ~t6_pc~0); 2048502#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2048493#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2048494#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2048489#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2048490#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2048483#L658-36 assume !(1 == ~t7_pc~0); 2048482#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2048469#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2048470#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2048455#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 2048456#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2048442#L677-36 assume !(1 == ~t8_pc~0); 2048375#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2048429#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2048430#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2048417#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2048418#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2048404#L696-36 assume 1 == ~t9_pc~0; 2048406#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2048305#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2048306#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2048291#L1422-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2048292#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2048282#L715-36 assume !(1 == ~t10_pc~0); 2048281#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2048280#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2048279#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2048278#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2048277#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2048276#L734-36 assume 1 == ~t11_pc~0; 2048275#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2048273#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2048272#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2048271#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2048270#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2048269#L1213-3 assume !(1 == ~M_E~0); 2037410#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2048268#L1218-3 assume !(1 == ~T2_E~0); 2048267#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2048266#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2048265#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2048264#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2048263#L1243-3 assume !(1 == ~T7_E~0); 2048262#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2048261#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2048260#L1258-3 assume !(1 == ~T10_E~0); 2048259#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2048258#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2048257#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2048256#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2048255#L1283-3 assume !(1 == ~E_4~0); 2048254#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2048253#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2048252#L1298-3 assume !(1 == ~E_7~0); 2048251#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2048250#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2048249#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2048248#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2048247#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2048246#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2048232#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2048226#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2048222#L1663 assume !(0 == start_simulation_~tmp~3#1); 2048061#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2048053#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2048048#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2048046#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2048044#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2048043#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2048040#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2048038#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 1989990#L1644-2 [2021-12-19 19:18:12,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:12,394 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 2 times [2021-12-19 19:18:12,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:12,395 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044966823] [2021-12-19 19:18:12,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:12,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:12,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:12,411 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:12,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:12,482 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:12,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:12,483 INFO L85 PathProgramCache]: Analyzing trace with hash 481202418, now seen corresponding path program 1 times [2021-12-19 19:18:12,483 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:12,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309586597] [2021-12-19 19:18:12,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:12,483 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:12,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:12,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:12,503 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:12,503 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309586597] [2021-12-19 19:18:12,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309586597] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:12,504 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:12,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:12,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40142967] [2021-12-19 19:18:12,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:12,504 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:12,504 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:12,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:12,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:12,505 INFO L87 Difference]: Start difference. First operand 69651 states and 96847 transitions. cyclomatic complexity: 27198 Second operand has 3 states, 3 states have (on average 51.0) internal successors, (153), 3 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:12,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:12,828 INFO L93 Difference]: Finished difference Result 128691 states and 177359 transitions. [2021-12-19 19:18:12,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:12,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128691 states and 177359 transitions. [2021-12-19 19:18:13,387 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 128480 [2021-12-19 19:18:13,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128691 states to 128691 states and 177359 transitions. [2021-12-19 19:18:13,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128691 [2021-12-19 19:18:13,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128691 [2021-12-19 19:18:13,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128691 states and 177359 transitions. [2021-12-19 19:18:13,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:13,885 INFO L681 BuchiCegarLoop]: Abstraction has 128691 states and 177359 transitions. [2021-12-19 19:18:13,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128691 states and 177359 transitions. [2021-12-19 19:18:15,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128691 to 126083. [2021-12-19 19:18:15,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126083 states, 126083 states have (on average 1.379400870854913) internal successors, (173919), 126082 states have internal predecessors, (173919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:15,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126083 states to 126083 states and 173919 transitions. [2021-12-19 19:18:15,463 INFO L704 BuchiCegarLoop]: Abstraction has 126083 states and 173919 transitions. [2021-12-19 19:18:15,463 INFO L587 BuchiCegarLoop]: Abstraction has 126083 states and 173919 transitions. [2021-12-19 19:18:15,463 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-12-19 19:18:15,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126083 states and 173919 transitions. [2021-12-19 19:18:16,237 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 125872 [2021-12-19 19:18:16,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:16,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:16,259 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:16,260 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:16,260 INFO L791 eck$LassoCheckResult]: Stem: 2188979#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 2188980#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 2188990#L1607 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2188991#L754 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2188721#L761 assume 1 == ~m_i~0;~m_st~0 := 0; 2188722#L761-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2188585#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2188494#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2188210#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2187848#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2187849#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2187897#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2187898#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2188861#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2188862#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2188912#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 2188312#L816-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2188313#L1090 assume !(0 == ~M_E~0); 2188363#L1090-2 assume !(0 == ~T1_E~0); 2188364#L1095-1 assume !(0 == ~T2_E~0); 2189062#L1100-1 assume !(0 == ~T3_E~0); 2189063#L1105-1 assume !(0 == ~T4_E~0); 2188127#L1110-1 assume !(0 == ~T5_E~0); 2188128#L1115-1 assume !(0 == ~T6_E~0); 2188537#L1120-1 assume !(0 == ~T7_E~0); 2188832#L1125-1 assume !(0 == ~T8_E~0); 2189481#L1130-1 assume !(0 == ~T9_E~0); 2189082#L1135-1 assume !(0 == ~T10_E~0); 2188320#L1140-1 assume !(0 == ~T11_E~0); 2188321#L1145-1 assume !(0 == ~E_1~0); 2189007#L1150-1 assume !(0 == ~E_2~0); 2188510#L1155-1 assume !(0 == ~E_3~0); 2188511#L1160-1 assume !(0 == ~E_4~0); 2188593#L1165-1 assume !(0 == ~E_5~0); 2188594#L1170-1 assume !(0 == ~E_6~0); 2189305#L1175-1 assume !(0 == ~E_7~0); 2188675#L1180-1 assume !(0 == ~E_8~0); 2188676#L1185-1 assume !(0 == ~E_9~0); 2188314#L1190-1 assume !(0 == ~E_10~0); 2188315#L1195-1 assume !(0 == ~E_11~0); 2188689#L1200-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2188532#L525 assume !(1 == ~m_pc~0); 2187936#L525-2 is_master_triggered_~__retres1~0#1 := 0; 2187937#L536 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2188692#L537 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2188693#L1350 assume !(0 != activate_threads_~tmp~1#1); 2188302#L1350-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2188303#L544 assume !(1 == ~t1_pc~0); 2188533#L544-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2188534#L555 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2189004#L556 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2188149#L1358 assume !(0 != activate_threads_~tmp___0~0#1); 2188150#L1358-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2188800#L563 assume !(1 == ~t2_pc~0); 2188992#L563-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2187958#L574 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2187959#L575 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2188391#L1366 assume !(0 != activate_threads_~tmp___1~0#1); 2188392#L1366-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2188883#L582 assume !(1 == ~t3_pc~0); 2189005#L582-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2189408#L593 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2189409#L594 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2189318#L1374 assume !(0 != activate_threads_~tmp___2~0#1); 2188028#L1374-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2188029#L601 assume !(1 == ~t4_pc~0); 2189026#L601-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2188538#L612 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2188539#L613 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2189020#L1382 assume !(0 != activate_threads_~tmp___3~0#1); 2189021#L1382-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2189388#L620 assume !(1 == ~t5_pc~0); 2188852#L620-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2188853#L631 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2188828#L632 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2188829#L1390 assume !(0 != activate_threads_~tmp___4~0#1); 2189429#L1390-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2189430#L639 assume !(1 == ~t6_pc~0); 2188831#L639-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2188429#L650 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2188430#L651 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2189320#L1398 assume !(0 != activate_threads_~tmp___5~0#1); 2188543#L1398-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2188544#L658 assume !(1 == ~t7_pc~0); 2188748#L658-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2188749#L669 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2188869#L670 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2188870#L1406 assume !(0 != activate_threads_~tmp___6~0#1); 2188308#L1406-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2188309#L677 assume !(1 == ~t8_pc~0); 2188335#L677-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2188112#L688 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2188113#L689 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2188385#L1414 assume !(0 != activate_threads_~tmp___7~0#1); 2188386#L1414-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2189133#L696 assume !(1 == ~t9_pc~0); 2188816#L696-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2188817#L707 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2188920#L708 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2188840#L1422 assume !(0 != activate_threads_~tmp___8~0#1); 2188841#L1422-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2189067#L715 assume !(1 == ~t10_pc~0); 2189342#L715-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2188934#L726 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2188803#L727 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2188804#L1430 assume !(0 != activate_threads_~tmp___9~0#1); 2188666#L1430-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2188101#L734 assume !(1 == ~t11_pc~0); 2188102#L734-2 is_transmit11_triggered_~__retres1~11#1 := 0; 2188600#L745 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2188680#L746 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2187838#L1438 assume !(0 != activate_threads_~tmp___10~0#1); 2187839#L1438-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2188905#L1213 assume !(1 == ~M_E~0); 2188664#L1213-2 assume !(1 == ~T1_E~0); 2188665#L1218-1 assume !(1 == ~T2_E~0); 2187873#L1223-1 assume !(1 == ~T3_E~0); 2187874#L1228-1 assume !(1 == ~T4_E~0); 2188639#L1233-1 assume !(1 == ~T5_E~0); 2189431#L1238-1 assume !(1 == ~T6_E~0); 2189018#L1243-1 assume !(1 == ~T7_E~0); 2189019#L1248-1 assume !(1 == ~T8_E~0); 2189069#L1253-1 assume !(1 == ~T9_E~0); 2189070#L1258-1 assume !(1 == ~T10_E~0); 2189045#L1263-1 assume !(1 == ~T11_E~0); 2189046#L1268-1 assume !(1 == ~E_1~0); 2188857#L1273-1 assume !(1 == ~E_2~0); 2188858#L1278-1 assume !(1 == ~E_3~0); 2188427#L1283-1 assume !(1 == ~E_4~0); 2188428#L1288-1 assume !(1 == ~E_5~0); 2189188#L1293-1 assume !(1 == ~E_6~0); 2189141#L1298-1 assume !(1 == ~E_7~0); 2188886#L1303-1 assume !(1 == ~E_8~0); 2188438#L1308-1 assume !(1 == ~E_9~0); 2188326#L1313-1 assume !(1 == ~E_10~0); 2188327#L1318-1 assume !(1 == ~E_11~0); 2188336#L1323-1 assume { :end_inline_reset_delta_events } true; 2188337#L1644-2 [2021-12-19 19:18:16,261 INFO L793 eck$LassoCheckResult]: Loop: 2188337#L1644-2 assume !false; 2267694#L1645 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2267689#L1065 assume !false; 2267686#L902 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2267682#L829 assume !(0 == ~m_st~0); 2267683#L833 assume !(0 == ~t1_st~0); 2290217#L837 assume !(0 == ~t2_st~0); 2290218#L841 assume !(0 == ~t3_st~0); 2290223#L845 assume !(0 == ~t4_st~0); 2290226#L849 assume !(0 == ~t5_st~0); 2290221#L853 assume !(0 == ~t6_st~0); 2290222#L857 assume !(0 == ~t7_st~0); 2290225#L861 assume !(0 == ~t8_st~0); 2290219#L865 assume !(0 == ~t9_st~0); 2290220#L869 assume !(0 == ~t10_st~0); 2290224#L873 assume !(0 == ~t11_st~0);exists_runnable_thread_~__retres1~12#1 := 0; 2290227#L891 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2290211#L892 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2290212#L906 assume !(0 != eval_~tmp~0#1); 2312168#L1080 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2312167#L754-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2312166#L1090-3 assume !(0 == ~M_E~0); 2312165#L1090-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2312164#L1095-3 assume !(0 == ~T2_E~0); 2312163#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2312162#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2312161#L1110-3 assume !(0 == ~T5_E~0); 2312160#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2312159#L1120-3 assume !(0 == ~T7_E~0); 2312158#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2312157#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2312156#L1135-3 assume !(0 == ~T10_E~0); 2312155#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2312154#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2312153#L1150-3 assume !(0 == ~E_2~0); 2312152#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2312151#L1160-3 assume !(0 == ~E_4~0); 2312150#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2312149#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2312148#L1175-3 assume !(0 == ~E_7~0); 2312147#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2312146#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2312145#L1190-3 assume !(0 == ~E_10~0); 2312144#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2312143#L1200-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2188619#L525-36 assume !(1 == ~m_pc~0); 2188620#L525-38 is_master_triggered_~__retres1~0#1 := 0; 2311727#L536-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2311728#L537-12 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2311721#L1350-36 assume !(0 != activate_threads_~tmp~1#1); 2311722#L1350-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2311714#L544-36 assume !(1 == ~t1_pc~0); 2311715#L544-38 is_transmit1_triggered_~__retres1~1#1 := 0; 2311708#L555-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2311709#L556-12 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2311701#L1358-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2311702#L1358-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2311694#L563-36 assume !(1 == ~t2_pc~0); 2311695#L563-38 is_transmit2_triggered_~__retres1~2#1 := 0; 2311687#L574-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2311688#L575-12 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2311681#L1366-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2311682#L1366-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2311676#L582-36 assume !(1 == ~t3_pc~0); 2304246#L582-38 is_transmit3_triggered_~__retres1~3#1 := 0; 2311671#L593-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2311672#L594-12 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2311664#L1374-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2311665#L1374-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2311656#L601-36 assume !(1 == ~t4_pc~0); 2311657#L601-38 is_transmit4_triggered_~__retres1~4#1 := 0; 2311650#L612-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2311651#L613-12 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2312133#L1382-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2312131#L1382-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2312129#L620-36 assume !(1 == ~t5_pc~0); 2233565#L620-38 is_transmit5_triggered_~__retres1~5#1 := 0; 2312125#L631-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2312126#L632-12 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2312119#L1390-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2312120#L1390-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2312593#L639-36 assume !(1 == ~t6_pc~0); 2312591#L639-38 is_transmit6_triggered_~__retres1~6#1 := 0; 2312106#L650-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2312107#L651-12 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2312049#L1398-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2312050#L1398-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2189381#L658-36 assume !(1 == ~t7_pc~0); 2187963#L658-38 is_transmit7_triggered_~__retres1~7#1 := 0; 2187964#L669-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2189258#L670-12 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2187938#L1406-36 assume !(0 != activate_threads_~tmp___6~0#1); 2187939#L1406-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2188976#L677-36 assume !(1 == ~t8_pc~0); 2188753#L677-38 is_transmit8_triggered_~__retres1~8#1 := 0; 2188754#L688-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2188884#L689-12 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2189380#L1414-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2188779#L1414-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2188780#L696-36 assume !(1 == ~t9_pc~0); 2188657#L696-38 is_transmit9_triggered_~__retres1~9#1 := 0; 2189098#L707-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2189099#L708-12 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2189259#L1422-36 assume !(0 != activate_threads_~tmp___8~0#1); 2188794#L1422-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2188795#L715-36 assume !(1 == ~t10_pc~0); 2188763#L715-38 is_transmit10_triggered_~__retres1~10#1 := 0; 2187836#L726-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2187837#L727-12 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2187812#L1430-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2187813#L1430-38 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2188214#L734-36 assume 1 == ~t11_pc~0; 2188215#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2187916#L745-12 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2188236#L746-12 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2187830#L1438-36 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2187831#L1438-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2188863#L1213-3 assume !(1 == ~M_E~0); 2188504#L1213-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2188505#L1218-3 assume !(1 == ~T2_E~0); 2188264#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2188265#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2188460#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2188461#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2189442#L1243-3 assume !(1 == ~T7_E~0); 2300998#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2300989#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2300988#L1258-3 assume !(1 == ~T10_E~0); 2300987#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2300986#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2300985#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2300964#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2300963#L1283-3 assume !(1 == ~E_4~0); 2300961#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2300960#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2300958#L1298-3 assume !(1 == ~E_7~0); 2300956#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2300954#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2300952#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2300951#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2300950#L1323-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2300949#L829-1 assume !(0 == ~m_st~0); 2257032#L833-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2300938#L891-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2300935#L892-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 2300933#L1663 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 2189520#L1464 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2188253#L525-39 assume 1 == ~m_pc~0; 2187820#L526-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2187821#L536-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2257030#L537-13 activate_threads_#t~ret17#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2257014#L1350-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2257012#L1350-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2257009#L544-39 assume !(1 == ~t1_pc~0); 2257007#L544-41 is_transmit1_triggered_~__retres1~1#1 := 0; 2257005#L555-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2257003#L556-13 activate_threads_#t~ret18#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2257001#L1358-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2256999#L1358-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2256996#L563-39 assume !(1 == ~t2_pc~0); 2256994#L563-41 is_transmit2_triggered_~__retres1~2#1 := 0; 2256991#L574-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2256989#L575-13 activate_threads_#t~ret19#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2256987#L1366-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2256985#L1366-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2256984#L582-39 assume !(1 == ~t3_pc~0); 2224621#L582-41 is_transmit3_triggered_~__retres1~3#1 := 0; 2256981#L593-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2256979#L594-13 activate_threads_#t~ret20#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2256977#L1374-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2256976#L1374-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2256975#L601-39 assume !(1 == ~t4_pc~0); 2256971#L601-41 is_transmit4_triggered_~__retres1~4#1 := 0; 2256969#L612-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2256967#L613-13 activate_threads_#t~ret21#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2256965#L1382-39 assume !(0 != activate_threads_~tmp___3~0#1); 2256963#L1382-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2256961#L620-39 assume !(1 == ~t5_pc~0); 2228953#L620-41 is_transmit5_triggered_~__retres1~5#1 := 0; 2256785#L631-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2256782#L632-13 activate_threads_#t~ret22#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2256780#L1390-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2256778#L1390-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2256776#L639-39 assume !(1 == ~t6_pc~0); 2256774#L639-41 is_transmit6_triggered_~__retres1~6#1 := 0; 2256770#L650-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2256768#L651-13 activate_threads_#t~ret23#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2256766#L1398-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2256764#L1398-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2256762#L658-39 assume !(1 == ~t7_pc~0); 2256759#L658-41 is_transmit7_triggered_~__retres1~7#1 := 0; 2256757#L669-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2256754#L670-13 activate_threads_#t~ret24#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2256752#L1406-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2256750#L1406-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2256748#L677-39 assume !(1 == ~t8_pc~0); 2215790#L677-41 is_transmit8_triggered_~__retres1~8#1 := 0; 2256745#L688-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2256742#L689-13 activate_threads_#t~ret25#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2256740#L1414-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2256738#L1414-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2256737#L696-39 assume 1 == ~t9_pc~0; 2256736#L697-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2256734#L707-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2256732#L708-13 activate_threads_#t~ret26#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2256729#L1422-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2256728#L1422-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2228738#L715-39 assume !(1 == ~t10_pc~0); 2228736#L715-41 is_transmit10_triggered_~__retres1~10#1 := 0; 2228734#L726-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2228732#L727-13 activate_threads_#t~ret27#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2228729#L1430-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2228727#L1430-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2228725#L734-39 assume 1 == ~t11_pc~0; 2228722#L735-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 2228720#L745-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2228717#L746-13 activate_threads_#t~ret28#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2228715#L1438-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2228713#L1438-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 2228710#L1471 assume 1 == ~M_E~0;~M_E~0 := 2; 2228711#L1471-2 assume !(1 == ~T1_E~0); 2268957#L1476-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2268955#L1481-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2268952#L1486-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2268950#L1491-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2268948#L1496-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2268947#L1501-1 assume !(1 == ~T7_E~0); 2268945#L1506-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2268943#L1511-1 assume !(1 == ~T9_E~0); 2268941#L1516-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2268939#L1521-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2268937#L1526-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2268934#L1531-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2268932#L1536-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2268930#L1541-1 assume !(1 == ~E_4~0); 2268928#L1546-1 assume 1 == ~E_5~0;~E_5~0 := 2; 2268926#L1551-1 assume !(1 == ~E_6~0); 2268925#L1556-1 assume !(1 == ~E_7~0); 2268921#L1561-1 assume 1 == ~E_8~0;~E_8~0 := 2; 2268919#L1566-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2268917#L1571-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2268916#L1576-1 assume 1 == ~E_11~0;~E_11~0 := 2; 2268911#L1581-1 assume { :end_inline_reset_time_events } true; 2257027#L1663-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 2268812#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 2268805#L891-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 2268801#L892-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 2268796#L1618 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2268791#L1625 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2268790#L1626 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2268789#L1676 assume !(0 != start_simulation_~tmp___0~1#1); 2188337#L1644-2 [2021-12-19 19:18:16,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:16,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1767012250, now seen corresponding path program 3 times [2021-12-19 19:18:16,261 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:16,262 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239628367] [2021-12-19 19:18:16,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:16,262 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:16,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:16,268 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-19 19:18:16,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-19 19:18:16,301 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-19 19:18:16,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:16,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1926061987, now seen corresponding path program 1 times [2021-12-19 19:18:16,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:16,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275395609] [2021-12-19 19:18:16,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:16,302 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:16,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:16,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:16,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:16,327 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275395609] [2021-12-19 19:18:16,327 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275395609] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:16,327 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:16,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:16,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471145445] [2021-12-19 19:18:16,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:16,328 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:16,328 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:16,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:18:16,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:18:16,329 INFO L87 Difference]: Start difference. First operand 126083 states and 173919 transitions. cyclomatic complexity: 47838 Second operand has 3 states, 3 states have (on average 83.66666666666667) internal successors, (251), 3 states have internal predecessors, (251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:16,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:16,933 INFO L93 Difference]: Finished difference Result 238946 states and 328125 transitions. [2021-12-19 19:18:16,933 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:18:16,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 238946 states and 328125 transitions.