./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c3fed411 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.2-tmp.no-commuhash-c3fed41 [2021-12-19 19:17:33,818 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-19 19:17:33,820 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-19 19:17:33,850 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-19 19:17:33,850 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-19 19:17:33,852 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-19 19:17:33,853 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-19 19:17:33,855 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-19 19:17:33,857 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-19 19:17:33,860 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-19 19:17:33,860 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-19 19:17:33,861 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-19 19:17:33,861 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-19 19:17:33,864 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-19 19:17:33,865 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-19 19:17:33,869 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-19 19:17:33,870 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-19 19:17:33,870 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-19 19:17:33,872 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-19 19:17:33,876 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-19 19:17:33,877 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-19 19:17:33,877 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-19 19:17:33,878 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-19 19:17:33,879 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-19 19:17:33,884 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-19 19:17:33,884 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-19 19:17:33,884 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-19 19:17:33,886 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-19 19:17:33,886 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-19 19:17:33,886 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-19 19:17:33,887 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-19 19:17:33,888 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-19 19:17:33,889 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-19 19:17:33,890 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-19 19:17:33,891 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-19 19:17:33,891 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-19 19:17:33,892 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-19 19:17:33,892 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-19 19:17:33,892 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-19 19:17:33,892 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-19 19:17:33,893 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-19 19:17:33,894 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-19 19:17:33,923 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-19 19:17:33,923 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-19 19:17:33,923 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-19 19:17:33,923 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-19 19:17:33,924 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-19 19:17:33,924 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-19 19:17:33,925 INFO L138 SettingsManager]: * Use SBE=true [2021-12-19 19:17:33,925 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-19 19:17:33,925 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-19 19:17:33,925 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-19 19:17:33,926 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-19 19:17:33,926 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-19 19:17:33,926 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-19 19:17:33,926 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-19 19:17:33,926 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-19 19:17:33,926 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-19 19:17:33,927 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-19 19:17:33,928 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-19 19:17:33,929 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-19 19:17:33,929 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-19 19:17:33,929 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-19 19:17:33,929 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-19 19:17:33,929 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-19 19:17:33,929 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-19 19:17:33,930 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-19 19:17:33,930 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-19 19:17:33,930 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-19 19:17:33,931 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2021-12-19 19:17:34,118 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-19 19:17:34,133 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-19 19:17:34,134 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-19 19:17:34,135 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-19 19:17:34,136 INFO L275 PluginConnector]: CDTParser initialized [2021-12-19 19:17:34,137 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-12-19 19:17:34,171 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c9832dc51/293e3e18c7224c4e989bf108c3bc08fa/FLAG3963dd6ed [2021-12-19 19:17:34,556 INFO L306 CDTParser]: Found 1 translation units. [2021-12-19 19:17:34,556 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-12-19 19:17:34,566 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c9832dc51/293e3e18c7224c4e989bf108c3bc08fa/FLAG3963dd6ed [2021-12-19 19:17:34,578 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c9832dc51/293e3e18c7224c4e989bf108c3bc08fa [2021-12-19 19:17:34,580 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-19 19:17:34,581 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-19 19:17:34,582 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:34,582 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-19 19:17:34,584 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-19 19:17:34,584 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,585 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@38cd3e09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34, skipping insertion in model container [2021-12-19 19:17:34,585 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,589 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-19 19:17:34,615 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-19 19:17:34,724 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-12-19 19:17:34,822 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:34,832 INFO L203 MainTranslator]: Completed pre-run [2021-12-19 19:17:34,839 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-12-19 19:17:34,890 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-19 19:17:34,903 INFO L208 MainTranslator]: Completed translation [2021-12-19 19:17:34,904 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34 WrapperNode [2021-12-19 19:17:34,904 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-19 19:17:34,905 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:34,905 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-19 19:17:34,905 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-19 19:17:34,924 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:34,932 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,005 INFO L137 Inliner]: procedures = 52, calls = 66, calls flagged for inlining = 61, calls inlined = 254, statements flattened = 3910 [2021-12-19 19:17:35,006 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-19 19:17:35,007 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-19 19:17:35,007 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-19 19:17:35,007 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-19 19:17:35,013 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,013 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,030 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,036 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,074 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,099 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,104 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,115 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-19 19:17:35,116 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-19 19:17:35,116 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-19 19:17:35,116 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-19 19:17:35,117 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (1/1) ... [2021-12-19 19:17:35,123 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-19 19:17:35,132 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-19 19:17:35,143 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-19 19:17:35,151 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-19 19:17:35,174 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-19 19:17:35,174 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-19 19:17:35,175 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-19 19:17:35,175 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-19 19:17:35,250 INFO L236 CfgBuilder]: Building ICFG [2021-12-19 19:17:35,251 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-19 19:17:36,662 INFO L277 CfgBuilder]: Performing block encoding [2021-12-19 19:17:36,682 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-19 19:17:36,682 INFO L301 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-19 19:17:36,686 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:36 BoogieIcfgContainer [2021-12-19 19:17:36,686 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-19 19:17:36,687 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-19 19:17:36,687 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-19 19:17:36,690 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-19 19:17:36,690 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,691 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 19.12 07:17:34" (1/3) ... [2021-12-19 19:17:36,691 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9095cbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:36, skipping insertion in model container [2021-12-19 19:17:36,691 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,692 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 19.12 07:17:34" (2/3) ... [2021-12-19 19:17:36,692 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9095cbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 19.12 07:17:36, skipping insertion in model container [2021-12-19 19:17:36,692 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-19 19:17:36,692 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 19.12 07:17:36" (3/3) ... [2021-12-19 19:17:36,693 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2021-12-19 19:17:36,740 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-19 19:17:36,740 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-19 19:17:36,740 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-19 19:17:36,741 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-19 19:17:36,741 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-19 19:17:36,741 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-19 19:17:36,741 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-19 19:17:36,741 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-19 19:17:36,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-12-19 19:17:36,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,859 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,860 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,860 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-19 19:17:36,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:36,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-12-19 19:17:36,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:36,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:36,884 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,884 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:36,897 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1609#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1450#L1731true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 696#L814true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 529#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 598#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1031#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1624#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 945#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 451#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 481#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 700#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 693#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244#L1174true assume !(0 == ~M_E~0); 1354#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 167#L1179-1true assume !(0 == ~T2_E~0); 119#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 188#L1194-1true assume !(0 == ~T5_E~0); 819#L1199-1true assume !(0 == ~T6_E~0); 979#L1204-1true assume !(0 == ~T7_E~0); 742#L1209-1true assume !(0 == ~T8_E~0); 1244#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1637#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 307#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 491#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1336#L1249-1true assume !(0 == ~E_4~0); 468#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 51#L1259-1true assume !(0 == ~E_6~0); 31#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1612#L1274-1true assume !(0 == ~E_9~0); 1325#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1466#L1289-1true assume !(0 == ~E_12~0); 508#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341#L566true assume 1 == ~m_pc~0; 39#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 972#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767#L578true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1189#L1455true assume !(0 != activate_threads_~tmp~1#1); 256#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1616#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714#L597true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1535#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1404#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397#L604true assume !(1 == ~t2_pc~0); 783#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1363#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413#L616true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1198#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 986#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465#L623true assume 1 == ~t3_pc~0; 359#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454#L635true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1025#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1242#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38#L642true assume !(1 == ~t4_pc~0); 663#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 265#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521#L654true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 796#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1123#L661true assume 1 == ~t5_pc~0; 149#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 708#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130#L673true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1100#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 827#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1490#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562#L692true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1115#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1401#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393#L699true assume 1 == ~t7_pc~0; 674#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 894#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144#L711true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 589#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 804#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L718true assume !(1 == ~t8_pc~0); 1250#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#L730true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 226#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 857#L737true assume 1 == ~t9_pc~0; 1502#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1284#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 735#L749true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1638#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 404#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1094#L756true assume 1 == ~t10_pc~0; 887#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 814#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5#L768true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 536#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 290#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 754#L775true assume !(1 == ~t11_pc~0); 445#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1262#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 223#L787true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 849#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L794true assume 1 == ~t12_pc~0; 117#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1101#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 975#L806true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 690#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L1307true assume !(1 == ~M_E~0); 541#L1307-2true assume !(1 == ~T1_E~0); 1445#L1312-1true assume !(1 == ~T2_E~0); 479#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 640#L1322-1true assume !(1 == ~T4_E~0); 295#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1414#L1337-1true assume !(1 == ~T7_E~0); 636#L1342-1true assume !(1 == ~T8_E~0); 1322#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 895#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1136#L1367-1true assume !(1 == ~E_1~0); 189#L1372-1true assume !(1 == ~E_2~0); 488#L1377-1true assume !(1 == ~E_3~0); 351#L1382-1true assume !(1 == ~E_4~0); 784#L1387-1true assume !(1 == ~E_5~0); 1258#L1392-1true assume !(1 == ~E_6~0); 363#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1389#L1402-1true assume !(1 == ~E_8~0); 195#L1407-1true assume !(1 == ~E_9~0); 1520#L1412-1true assume !(1 == ~E_10~0); 974#L1417-1true assume !(1 == ~E_11~0); 1696#L1422-1true assume !(1 == ~E_12~0); 1385#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2021-12-19 19:17:36,904 INFO L793 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 522#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 844#L1149true assume false; 1434#L1164true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419#L814-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999#L1174-3true assume !(0 == ~M_E~0); 992#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 717#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 896#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 577#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume !(0 == ~T8_E~0); 14#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 412#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 100#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1249-3true assume !(0 == ~E_4~0); 1446#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1237#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 765#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1504#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1321#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 411#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1379#L1289-3true assume !(0 == ~E_12~0); 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218#L566-39true assume !(1 == ~m_pc~0); 654#L566-41true is_master_triggered_~__retres1~0#1 := 0; 606#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396#L578-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 836#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298#L585-39true assume 1 == ~t1_pc~0; 968#L586-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L597-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1225#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 871#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L604-39true assume !(1 == ~t2_pc~0); 1222#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 339#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134#L616-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L623-39true assume !(1 == ~t3_pc~0); 650#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 853#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486#L635-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 803#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304#L642-39true assume 1 == ~t4_pc~0; 448#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 753#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#L654-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1184#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204#L661-39true assume !(1 == ~t5_pc~0); 25#L661-41true is_transmit5_triggered_~__retres1~5#1 := 0; 1627#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961#L673-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 977#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1145#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785#L692-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 289#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1491#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1248#L699-39true assume 1 == ~t7_pc~0; 579#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 381#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982#L711-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1269#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 511#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1388#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461#L730-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1153#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 707#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume 1 == ~t9_pc~0; 276#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 452#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1323#L749-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1449#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027#L756-39true assume 1 == ~t10_pc~0; 1376#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1515#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352#L768-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 460#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 431#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1694#L787-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1546#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 759#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467#L794-39true assume 1 == ~t12_pc~0; 277#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 914#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1347#L806-13true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 810#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1307#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1199#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610#L1312-3true assume !(1 == ~T2_E~0); 1604#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 828#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1672#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 533#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 957#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 632#L1352-3true assume !(1 == ~T10_E~0); 1112#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1508#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 20#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 343#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 927#L1392-3true assume !(1 == ~E_6~0); 1595#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1373#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 605#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 156#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1149#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 547#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1105#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1651#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 739#L962-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1433#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1215#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 647#L962-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1318#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 331#L1750true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1590#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2021-12-19 19:17:36,908 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:36,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2021-12-19 19:17:36,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:36,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952628413] [2021-12-19 19:17:36,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:36,924 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,095 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,096 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952628413] [2021-12-19 19:17:37,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952628413] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,104 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,106 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1002938399] [2021-12-19 19:17:37,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,110 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1819192778, now seen corresponding path program 1 times [2021-12-19 19:17:37,111 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,111 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659227433] [2021-12-19 19:17:37,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,181 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,181 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1659227433] [2021-12-19 19:17:37,181 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1659227433] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,181 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,181 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:37,181 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560906377] [2021-12-19 19:17:37,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,182 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,183 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-19 19:17:37,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-19 19:17:37,237 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,309 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2021-12-19 19:17:37,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-19 19:17:37,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2021-12-19 19:17:37,330 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2021-12-19 19:17:37,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:37,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:37,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2021-12-19 19:17:37,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,357 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-19 19:17:37,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2021-12-19 19:17:37,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:37,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2021-12-19 19:17:37,419 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-19 19:17:37,419 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-19 19:17:37,419 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-19 19:17:37,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2021-12-19 19:17:37,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,428 INFO L791 eck$LassoCheckResult]: Stem: 4201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5055#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4547#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4354#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4355#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4440#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4741#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4863#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4864#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3652#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3653#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4801#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4247#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4248#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4154#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4155#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4543#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3896#L1174 assume !(0 == ~M_E~0); 3897#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3748#L1179-1 assume !(0 == ~T2_E~0); 3650#L1184-1 assume !(0 == ~T3_E~0); 3651#L1189-1 assume !(0 == ~T4_E~0); 3689#L1194-1 assume !(0 == ~T5_E~0); 3789#L1199-1 assume !(0 == ~T6_E~0); 4684#L1204-1 assume !(0 == ~T7_E~0); 4603#L1209-1 assume !(0 == ~T8_E~0); 4604#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4992#L1219-1 assume !(0 == ~T10_E~0); 5077#L1224-1 assume !(0 == ~T11_E~0); 4014#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3609#L1244-1 assume !(0 == ~E_3~0); 3610#L1249-1 assume !(0 == ~E_4~0); 4271#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3460#L1264-1 assume !(0 == ~E_7~0); 3461#L1269-1 assume !(0 == ~E_8~0); 5082#L1274-1 assume !(0 == ~E_9~0); 5017#L1279-1 assume !(0 == ~E_10~0); 3693#L1284-1 assume !(0 == ~E_11~0); 3694#L1289-1 assume !(0 == ~E_12~0); 4323#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324#L566 assume 1 == ~m_pc~0; 3477#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4632#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4633#L1455 assume !(0 != activate_threads_~tmp~1#1); 3923#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3924#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4573#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4574#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5042#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5040#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4186#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4187#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4824#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4825#L623 assume 1 == ~t3_pc~0; 4101#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3441#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4252#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4859#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3474#L642 assume !(1 == ~t4_pc~0); 3475#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3940#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3941#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3546#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3547#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4664#L661 assume 1 == ~t5_pc~0; 3711#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3712#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3673#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4693#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4694#L680 assume !(1 == ~t6_pc~0); 4134#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4396#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4397#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5038#L699 assume 1 == ~t7_pc~0; 4524#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4525#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3701#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3702#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4426#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325#L718 assume !(1 == ~t8_pc~0); 4326#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3687#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3688#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3729#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3730#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3863#L737 assume 1 == ~t9_pc~0; 4728#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3998#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4599#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4600#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4172#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4173#L756 assume 1 == ~t10_pc~0; 4752#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4418#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3404#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3405#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3980#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3981#L775 assume !(1 == ~t11_pc~0); 4235#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4236#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3857#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3621#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3622#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3808#L794 assume 1 == ~t12_pc~0; 3648#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3626#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4819#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3774#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3775#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L1307 assume !(1 == ~M_E~0); 4255#L1307-2 assume !(1 == ~T1_E~0); 4366#L1312-1 assume !(1 == ~T2_E~0); 4285#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4286#L1322-1 assume !(1 == ~T4_E~0); 3989#L1327-1 assume !(1 == ~T5_E~0); 3990#L1332-1 assume !(1 == ~T6_E~0); 4528#L1337-1 assume !(1 == ~T7_E~0); 4490#L1342-1 assume !(1 == ~T8_E~0); 4491#L1347-1 assume !(1 == ~T9_E~0); 4888#L1352-1 assume !(1 == ~T10_E~0); 4761#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4152#L1362-1 assume !(1 == ~T12_E~0); 4153#L1367-1 assume !(1 == ~E_1~0); 3790#L1372-1 assume !(1 == ~E_2~0); 3791#L1377-1 assume !(1 == ~E_3~0); 4084#L1382-1 assume !(1 == ~E_4~0); 4085#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4104#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4105#L1402-1 assume !(1 == ~E_8~0); 3801#L1407-1 assume !(1 == ~E_9~0); 3802#L1412-1 assume !(1 == ~E_10~0); 4817#L1417-1 assume !(1 == ~E_11~0); 4818#L1422-1 assume !(1 == ~E_12~0); 5036#L1427-1 assume { :end_inline_reset_delta_events } true; 3605#L1768-2 [2021-12-19 19:17:37,429 INFO L793 eck$LassoCheckResult]: Loop: 3605#L1768-2 assume !false; 3606#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4344#L1149 assume !false; 4716#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4869#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3995#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3901#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3902#L976 assume !(0 != eval_~tmp~0#1); 5035#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4836#L1174-3 assume !(0 == ~M_E~0); 4829#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4578#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4579#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4762#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4413#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3764#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4005#L1209-3 assume !(0 == ~T8_E~0); 3425#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3426#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4184#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4185#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4203#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3613#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3614#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4057#L1249-3 assume !(0 == ~E_4~0); 4516#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4630#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3619#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3620#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5015#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4182#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4183#L1289-3 assume !(0 == ~E_12~0); 4171#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3847#L566-39 assume 1 == ~m_pc~0; 3848#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4450#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4162#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4163#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4705#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4706#L585-39 assume 1 == ~t1_pc~0; 4816#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3856#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3931#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3932#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4738#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4431#L604-39 assume 1 == ~t2_pc~0; 4432#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4063#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4064#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4481#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4482#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4046#L623-39 assume 1 == ~t3_pc~0; 3442#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3444#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4722#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3898#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3899#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4670#L642-39 assume 1 == ~t4_pc~0; 4241#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4242#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3770#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3771#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4868#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3819#L661-39 assume !(1 == ~t5_pc~0); 3450#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3451#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4811#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4812#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4725#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4726#L680-39 assume 1 == ~t6_pc~0; 3512#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3513#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4655#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3978#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3979#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4993#L699-39 assume !(1 == ~t7_pc~0); 4416#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4137#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4821#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4942#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4940#L718-39 assume 1 == ~t8_pc~0; 4329#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4330#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4262#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4263#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4565#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4534#L737-39 assume 1 == ~t9_pc~0; 3959#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3960#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4249#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5016#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4917#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4860#L756-39 assume !(1 == ~t10_pc~0); 4341#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4342#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4086#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4087#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4219#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4212#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4213#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5075#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L794-39 assume !(1 == ~t12_pc~0); 3955#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3956#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4776#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4677#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4970#L1312-3 assume !(1 == ~T2_E~0); 5081#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4695#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4696#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3640#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3611#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3612#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4358#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4483#L1352-3 assume !(1 == ~T10_E~0); 4484#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4923#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5074#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4070#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4071#L1392-3 assume !(1 == ~E_6~0); 4786#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4449#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3725#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3726#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4374#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4375#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3735#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4602#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4454#L1787 assume !(0 == start_simulation_~tmp~3#1); 4455#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4978#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3706#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4501#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4502#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4053#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4054#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4055#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3605#L1768-2 [2021-12-19 19:17:37,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2021-12-19 19:17:37,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,430 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538240890] [2021-12-19 19:17:37,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,488 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538240890] [2021-12-19 19:17:37,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538240890] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,489 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596566294] [2021-12-19 19:17:37,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,489 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1764555615, now seen corresponding path program 1 times [2021-12-19 19:17:37,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,490 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247799473] [2021-12-19 19:17:37,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,491 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,578 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,578 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247799473] [2021-12-19 19:17:37,579 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247799473] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,579 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,579 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753038814] [2021-12-19 19:17:37,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,580 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,580 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:37,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:37,581 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,623 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2021-12-19 19:17:37,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:37,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2021-12-19 19:17:37,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-12-19 19:17:37,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:37,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:37,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2021-12-19 19:17:37,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,645 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-19 19:17:37,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2021-12-19 19:17:37,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:37,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-12-19 19:17:37,668 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-19 19:17:37,668 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-19 19:17:37,668 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-19 19:17:37,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2021-12-19 19:17:37,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,691 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,691 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,693 INFO L791 eck$LassoCheckResult]: Stem: 7584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8438#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7930#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7737#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7738#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7823#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8124#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8246#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8247#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7035#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7036#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8184#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7630#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7631#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7537#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7538#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7926#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7279#L1174 assume !(0 == ~M_E~0); 7280#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7131#L1179-1 assume !(0 == ~T2_E~0); 7033#L1184-1 assume !(0 == ~T3_E~0); 7034#L1189-1 assume !(0 == ~T4_E~0); 7072#L1194-1 assume !(0 == ~T5_E~0); 7172#L1199-1 assume !(0 == ~T6_E~0); 8067#L1204-1 assume !(0 == ~T7_E~0); 7986#L1209-1 assume !(0 == ~T8_E~0); 7987#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8375#L1219-1 assume !(0 == ~T10_E~0); 8460#L1224-1 assume !(0 == ~T11_E~0); 7397#L1229-1 assume !(0 == ~T12_E~0); 6958#L1234-1 assume !(0 == ~E_1~0); 6959#L1239-1 assume !(0 == ~E_2~0); 6992#L1244-1 assume !(0 == ~E_3~0); 6993#L1249-1 assume !(0 == ~E_4~0); 7654#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6888#L1259-1 assume !(0 == ~E_6~0); 6843#L1264-1 assume !(0 == ~E_7~0); 6844#L1269-1 assume !(0 == ~E_8~0); 8465#L1274-1 assume !(0 == ~E_9~0); 8400#L1279-1 assume !(0 == ~E_10~0); 7076#L1284-1 assume !(0 == ~E_11~0); 7077#L1289-1 assume !(0 == ~E_12~0); 7706#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7707#L566 assume 1 == ~m_pc~0; 6860#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6861#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8015#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8016#L1455 assume !(0 != activate_threads_~tmp~1#1); 7306#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7307#L585 assume 1 == ~t1_pc~0; 6955#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6956#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7956#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7957#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8425#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L604 assume !(1 == ~t2_pc~0); 8035#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8036#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7569#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7570#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8207#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8208#L623 assume 1 == ~t3_pc~0; 7484#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6824#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7634#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8242#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6857#L642 assume !(1 == ~t4_pc~0); 6858#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7323#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7324#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6929#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6930#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8047#L661 assume 1 == ~t5_pc~0; 7094#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7095#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7056#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7057#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8076#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8077#L680 assume !(1 == ~t6_pc~0); 7517#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7518#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7779#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7780#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8308#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8421#L699 assume 1 == ~t7_pc~0; 7907#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7908#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7084#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7085#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7809#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7708#L718 assume !(1 == ~t8_pc~0); 7709#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7070#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7071#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7112#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7113#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7246#L737 assume 1 == ~t9_pc~0; 8111#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7381#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7982#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7983#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L756 assume 1 == ~t10_pc~0; 8135#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7801#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6787#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6788#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7363#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7364#L775 assume !(1 == ~t11_pc~0); 7618#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7619#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7240#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7004#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7005#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7191#L794 assume 1 == ~t12_pc~0; 7031#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7009#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8202#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7157#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7158#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7637#L1307 assume !(1 == ~M_E~0); 7638#L1307-2 assume !(1 == ~T1_E~0); 7749#L1312-1 assume !(1 == ~T2_E~0); 7668#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7669#L1322-1 assume !(1 == ~T4_E~0); 7372#L1327-1 assume !(1 == ~T5_E~0); 7373#L1332-1 assume !(1 == ~T6_E~0); 7911#L1337-1 assume !(1 == ~T7_E~0); 7873#L1342-1 assume !(1 == ~T8_E~0); 7874#L1347-1 assume !(1 == ~T9_E~0); 8271#L1352-1 assume !(1 == ~T10_E~0); 8144#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7535#L1362-1 assume !(1 == ~T12_E~0); 7536#L1367-1 assume !(1 == ~E_1~0); 7173#L1372-1 assume !(1 == ~E_2~0); 7174#L1377-1 assume !(1 == ~E_3~0); 7467#L1382-1 assume !(1 == ~E_4~0); 7468#L1387-1 assume !(1 == ~E_5~0); 8037#L1392-1 assume !(1 == ~E_6~0); 7487#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7488#L1402-1 assume !(1 == ~E_8~0); 7184#L1407-1 assume !(1 == ~E_9~0); 7185#L1412-1 assume !(1 == ~E_10~0); 8200#L1417-1 assume !(1 == ~E_11~0); 8201#L1422-1 assume !(1 == ~E_12~0); 8419#L1427-1 assume { :end_inline_reset_delta_events } true; 6988#L1768-2 [2021-12-19 19:17:37,694 INFO L793 eck$LassoCheckResult]: Loop: 6988#L1768-2 assume !false; 6989#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7727#L1149 assume !false; 8099#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8252#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7378#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7284#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7285#L976 assume !(0 != eval_~tmp~0#1); 8418#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8428#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8219#L1174-3 assume !(0 == ~M_E~0); 8212#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8145#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7796#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7146#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7147#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7388#L1209-3 assume !(0 == ~T8_E~0); 6808#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6809#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7567#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7586#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6996#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6997#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7440#L1249-3 assume !(0 == ~E_4~0); 7899#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8371#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8013#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7002#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7003#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8398#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7565#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7566#L1289-3 assume !(0 == ~E_12~0); 7554#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7230#L566-39 assume !(1 == ~m_pc~0); 7232#L566-41 is_master_triggered_~__retres1~0#1 := 0; 7833#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7545#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7546#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8088#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8089#L585-39 assume !(1 == ~t1_pc~0); 7238#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7239#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7314#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7315#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8121#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7814#L604-39 assume 1 == ~t2_pc~0; 7815#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7446#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7447#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7864#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7865#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7429#L623-39 assume 1 == ~t3_pc~0; 6825#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6827#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8105#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7281#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7282#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8053#L642-39 assume 1 == ~t4_pc~0; 7624#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7625#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7153#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7154#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8251#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7202#L661-39 assume !(1 == ~t5_pc~0); 6833#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6834#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8194#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8195#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8108#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8109#L680-39 assume !(1 == ~t6_pc~0); 6897#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6896#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8038#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7361#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7362#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8376#L699-39 assume 1 == ~t7_pc~0; 7798#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7520#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7521#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8204#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8325#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8323#L718-39 assume 1 == ~t8_pc~0; 7712#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7713#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7645#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7646#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 7948#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7917#L737-39 assume !(1 == ~t9_pc~0); 7344#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 7343#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7632#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8399#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8300#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8243#L756-39 assume 1 == ~t10_pc~0; 8244#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7725#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7469#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7470#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7602#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6942#L775-39 assume !(1 == ~t11_pc~0); 6944#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 7595#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7596#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8458#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8006#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7653#L794-39 assume 1 == ~t12_pc~0; 7345#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7339#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8159#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8060#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8352#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8353#L1312-3 assume !(1 == ~T2_E~0); 8464#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8078#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8079#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7023#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6994#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6995#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7741#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7866#L1352-3 assume !(1 == ~T10_E~0); 7867#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8306#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8457#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8448#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6821#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6822#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7453#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7454#L1392-3 assume !(1 == ~E_6~0); 8169#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8415#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7108#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7109#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7757#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7758#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7118#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7119#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7985#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7837#L1787 assume !(0 == start_simulation_~tmp~3#1); 7838#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8361#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7089#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7884#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 7885#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7436#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7437#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1768-2 [2021-12-19 19:17:37,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2021-12-19 19:17:37,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621644203] [2021-12-19 19:17:37,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,700 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,758 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621644203] [2021-12-19 19:17:37,759 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621644203] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,759 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,759 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,759 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282150918] [2021-12-19 19:17:37,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,759 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,760 INFO L85 PathProgramCache]: Analyzing trace with hash 1578992735, now seen corresponding path program 1 times [2021-12-19 19:17:37,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843318512] [2021-12-19 19:17:37,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,761 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843318512] [2021-12-19 19:17:37,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843318512] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290511346] [2021-12-19 19:17:37,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,819 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,819 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:37,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:37,819 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:37,843 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2021-12-19 19:17:37,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:37,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2021-12-19 19:17:37,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-12-19 19:17:37,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:37,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:37,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2021-12-19 19:17:37,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:37,864 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-19 19:17:37,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2021-12-19 19:17:37,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:37,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:37,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-12-19 19:17:37,888 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-19 19:17:37,888 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-19 19:17:37,888 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-19 19:17:37,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2021-12-19 19:17:37,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:37,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:37,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:37,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:37,896 INFO L791 eck$LassoCheckResult]: Stem: 10967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11821#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11313#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11120#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11121#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11206#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11507#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11629#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11630#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10418#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10419#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11567#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11013#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11014#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10920#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10921#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11309#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10662#L1174 assume !(0 == ~M_E~0); 10663#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10514#L1179-1 assume !(0 == ~T2_E~0); 10416#L1184-1 assume !(0 == ~T3_E~0); 10417#L1189-1 assume !(0 == ~T4_E~0); 10455#L1194-1 assume !(0 == ~T5_E~0); 10555#L1199-1 assume !(0 == ~T6_E~0); 11450#L1204-1 assume !(0 == ~T7_E~0); 11369#L1209-1 assume !(0 == ~T8_E~0); 11370#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11758#L1219-1 assume !(0 == ~T10_E~0); 11843#L1224-1 assume !(0 == ~T11_E~0); 10780#L1229-1 assume !(0 == ~T12_E~0); 10341#L1234-1 assume !(0 == ~E_1~0); 10342#L1239-1 assume !(0 == ~E_2~0); 10375#L1244-1 assume !(0 == ~E_3~0); 10376#L1249-1 assume !(0 == ~E_4~0); 11037#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10271#L1259-1 assume !(0 == ~E_6~0); 10226#L1264-1 assume !(0 == ~E_7~0); 10227#L1269-1 assume !(0 == ~E_8~0); 11848#L1274-1 assume !(0 == ~E_9~0); 11783#L1279-1 assume !(0 == ~E_10~0); 10459#L1284-1 assume !(0 == ~E_11~0); 10460#L1289-1 assume !(0 == ~E_12~0); 11089#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11090#L566 assume 1 == ~m_pc~0; 10243#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10244#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11398#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11399#L1455 assume !(0 != activate_threads_~tmp~1#1); 10689#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10690#L585 assume 1 == ~t1_pc~0; 10338#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10339#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11339#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11340#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11806#L604 assume !(1 == ~t2_pc~0); 11418#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11419#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10952#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10953#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11590#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11591#L623 assume 1 == ~t3_pc~0; 10867#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10207#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11017#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11018#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11625#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10240#L642 assume !(1 == ~t4_pc~0); 10241#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10706#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10707#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10312#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10313#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11430#L661 assume 1 == ~t5_pc~0; 10477#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10478#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10439#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10440#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11459#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11460#L680 assume !(1 == ~t6_pc~0); 10900#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10901#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11162#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11163#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11691#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11804#L699 assume 1 == ~t7_pc~0; 11290#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11291#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10467#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10468#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11192#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11091#L718 assume !(1 == ~t8_pc~0); 11092#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10453#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10454#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10495#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10496#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10629#L737 assume 1 == ~t9_pc~0; 11494#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10764#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11365#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11366#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10938#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10939#L756 assume 1 == ~t10_pc~0; 11518#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11184#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10170#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10171#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10746#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10747#L775 assume !(1 == ~t11_pc~0); 11001#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11002#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10623#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10387#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10388#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10574#L794 assume 1 == ~t12_pc~0; 10414#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10392#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11585#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10540#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10541#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11020#L1307 assume !(1 == ~M_E~0); 11021#L1307-2 assume !(1 == ~T1_E~0); 11132#L1312-1 assume !(1 == ~T2_E~0); 11051#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11052#L1322-1 assume !(1 == ~T4_E~0); 10755#L1327-1 assume !(1 == ~T5_E~0); 10756#L1332-1 assume !(1 == ~T6_E~0); 11294#L1337-1 assume !(1 == ~T7_E~0); 11256#L1342-1 assume !(1 == ~T8_E~0); 11257#L1347-1 assume !(1 == ~T9_E~0); 11654#L1352-1 assume !(1 == ~T10_E~0); 11527#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10918#L1362-1 assume !(1 == ~T12_E~0); 10919#L1367-1 assume !(1 == ~E_1~0); 10556#L1372-1 assume !(1 == ~E_2~0); 10557#L1377-1 assume !(1 == ~E_3~0); 10850#L1382-1 assume !(1 == ~E_4~0); 10851#L1387-1 assume !(1 == ~E_5~0); 11420#L1392-1 assume !(1 == ~E_6~0); 10870#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10871#L1402-1 assume !(1 == ~E_8~0); 10567#L1407-1 assume !(1 == ~E_9~0); 10568#L1412-1 assume !(1 == ~E_10~0); 11583#L1417-1 assume !(1 == ~E_11~0); 11584#L1422-1 assume !(1 == ~E_12~0); 11802#L1427-1 assume { :end_inline_reset_delta_events } true; 10371#L1768-2 [2021-12-19 19:17:37,896 INFO L793 eck$LassoCheckResult]: Loop: 10371#L1768-2 assume !false; 10372#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11110#L1149 assume !false; 11482#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11635#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10761#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10667#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10668#L976 assume !(0 != eval_~tmp~0#1); 11801#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11811#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11602#L1174-3 assume !(0 == ~M_E~0); 11595#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11344#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11345#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11528#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11179#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10529#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10530#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10771#L1209-3 assume !(0 == ~T8_E~0); 10191#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10192#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10950#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10951#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10969#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10379#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10380#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10823#L1249-3 assume !(0 == ~E_4~0); 11282#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11754#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11396#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10385#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10386#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11781#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10948#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10949#L1289-3 assume !(0 == ~E_12~0); 10937#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10613#L566-39 assume 1 == ~m_pc~0; 10614#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11216#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10928#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10929#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11471#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11472#L585-39 assume !(1 == ~t1_pc~0); 10621#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10622#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10697#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10698#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11504#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11197#L604-39 assume 1 == ~t2_pc~0; 11198#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10829#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10830#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11247#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11248#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10812#L623-39 assume 1 == ~t3_pc~0; 10208#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10210#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11488#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10664#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10665#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11436#L642-39 assume !(1 == ~t4_pc~0); 11009#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 11008#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10536#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10537#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11634#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10585#L661-39 assume !(1 == ~t5_pc~0); 10216#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10217#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11578#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11491#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11492#L680-39 assume 1 == ~t6_pc~0; 10278#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11421#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10744#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10745#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11759#L699-39 assume 1 == ~t7_pc~0; 11181#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10903#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10904#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11587#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11708#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11706#L718-39 assume 1 == ~t8_pc~0; 11095#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11096#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11028#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11029#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11331#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11300#L737-39 assume 1 == ~t9_pc~0; 10725#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10726#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11015#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11782#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11683#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11626#L756-39 assume !(1 == ~t10_pc~0); 11107#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11108#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10852#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10853#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10985#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10325#L775-39 assume 1 == ~t11_pc~0; 10326#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10978#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10979#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11841#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11389#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11036#L794-39 assume !(1 == ~t12_pc~0); 10721#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10722#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11542#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11443#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10267#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10268#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11735#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11736#L1312-3 assume !(1 == ~T2_E~0); 11847#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11461#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11462#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10406#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10377#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10378#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11124#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11249#L1352-3 assume !(1 == ~T10_E~0); 11250#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11689#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11840#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11831#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10204#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10205#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10836#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10837#L1392-3 assume !(1 == ~E_6~0); 11552#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11798#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11215#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10491#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10492#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11140#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11141#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10501#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10502#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11368#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 11220#L1787 assume !(0 == start_simulation_~tmp~3#1); 11221#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11744#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10472#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11267#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 11268#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10819#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10820#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10821#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10371#L1768-2 [2021-12-19 19:17:37,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2021-12-19 19:17:37,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124920222] [2021-12-19 19:17:37,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,935 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124920222] [2021-12-19 19:17:37,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124920222] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,939 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491197984] [2021-12-19 19:17:37,939 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,939 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:37,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:37,940 INFO L85 PathProgramCache]: Analyzing trace with hash -601300672, now seen corresponding path program 1 times [2021-12-19 19:17:37,940 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:37,943 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879387626] [2021-12-19 19:17:37,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:37,944 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:37,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:37,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:37,985 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:37,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879387626] [2021-12-19 19:17:37,985 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879387626] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:37,986 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:37,986 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:37,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2114640249] [2021-12-19 19:17:37,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:37,986 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:37,986 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:37,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:37,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:37,987 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,034 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2021-12-19 19:17:38,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2021-12-19 19:17:38,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-12-19 19:17:38,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,048 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2021-12-19 19:17:38,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,050 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-19 19:17:38,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2021-12-19 19:17:38,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-12-19 19:17:38,070 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-19 19:17:38,070 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-19 19:17:38,070 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-19 19:17:38,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2021-12-19 19:17:38,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,077 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,077 INFO L791 eck$LassoCheckResult]: Stem: 14351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 14352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15204#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14698#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14503#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14504#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14589#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14891#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15012#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15013#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13801#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13802#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14950#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14396#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14397#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14303#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14304#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14693#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14045#L1174 assume !(0 == ~M_E~0); 14046#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13897#L1179-1 assume !(0 == ~T2_E~0); 13799#L1184-1 assume !(0 == ~T3_E~0); 13800#L1189-1 assume !(0 == ~T4_E~0); 13838#L1194-1 assume !(0 == ~T5_E~0); 13938#L1199-1 assume !(0 == ~T6_E~0); 14833#L1204-1 assume !(0 == ~T7_E~0); 14752#L1209-1 assume !(0 == ~T8_E~0); 14753#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15141#L1219-1 assume !(0 == ~T10_E~0); 15226#L1224-1 assume !(0 == ~T11_E~0); 14164#L1229-1 assume !(0 == ~T12_E~0); 13726#L1234-1 assume !(0 == ~E_1~0); 13727#L1239-1 assume !(0 == ~E_2~0); 13760#L1244-1 assume !(0 == ~E_3~0); 13761#L1249-1 assume !(0 == ~E_4~0); 14420#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13654#L1259-1 assume !(0 == ~E_6~0); 13609#L1264-1 assume !(0 == ~E_7~0); 13610#L1269-1 assume !(0 == ~E_8~0); 15231#L1274-1 assume !(0 == ~E_9~0); 15166#L1279-1 assume !(0 == ~E_10~0); 13842#L1284-1 assume !(0 == ~E_11~0); 13843#L1289-1 assume !(0 == ~E_12~0); 14472#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14473#L566 assume 1 == ~m_pc~0; 13626#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13627#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14781#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14782#L1455 assume !(0 != activate_threads_~tmp~1#1); 14072#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14073#L585 assume 1 == ~t1_pc~0; 13721#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13722#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14722#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14723#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15191#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15189#L604 assume !(1 == ~t2_pc~0); 14801#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14802#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14335#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14336#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14975#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14976#L623 assume 1 == ~t3_pc~0; 14250#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13590#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14400#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14401#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15008#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13623#L642 assume !(1 == ~t4_pc~0); 13624#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14089#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14090#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13697#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13698#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14813#L661 assume 1 == ~t5_pc~0; 13860#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13861#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13823#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14844#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14845#L680 assume !(1 == ~t6_pc~0); 14283#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14284#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14545#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14546#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15074#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15187#L699 assume 1 == ~t7_pc~0; 14673#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14674#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13850#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13851#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14575#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14474#L718 assume !(1 == ~t8_pc~0); 14475#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13836#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13837#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13878#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13879#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14012#L737 assume 1 == ~t9_pc~0; 14878#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14148#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14748#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14749#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14321#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14322#L756 assume 1 == ~t10_pc~0; 14901#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14567#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13553#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13554#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14129#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14130#L775 assume !(1 == ~t11_pc~0); 14384#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14385#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14009#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13770#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13771#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13957#L794 assume 1 == ~t12_pc~0; 13798#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13775#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14968#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13925#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 13926#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14403#L1307 assume !(1 == ~M_E~0); 14404#L1307-2 assume !(1 == ~T1_E~0); 14515#L1312-1 assume !(1 == ~T2_E~0); 14434#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14435#L1322-1 assume !(1 == ~T4_E~0); 14138#L1327-1 assume !(1 == ~T5_E~0); 14139#L1332-1 assume !(1 == ~T6_E~0); 14677#L1337-1 assume !(1 == ~T7_E~0); 14639#L1342-1 assume !(1 == ~T8_E~0); 14640#L1347-1 assume !(1 == ~T9_E~0); 15037#L1352-1 assume !(1 == ~T10_E~0); 14910#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14301#L1362-1 assume !(1 == ~T12_E~0); 14302#L1367-1 assume !(1 == ~E_1~0); 13939#L1372-1 assume !(1 == ~E_2~0); 13940#L1377-1 assume !(1 == ~E_3~0); 14233#L1382-1 assume !(1 == ~E_4~0); 14234#L1387-1 assume !(1 == ~E_5~0); 14803#L1392-1 assume !(1 == ~E_6~0); 14255#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14256#L1402-1 assume !(1 == ~E_8~0); 13955#L1407-1 assume !(1 == ~E_9~0); 13956#L1412-1 assume !(1 == ~E_10~0); 14966#L1417-1 assume !(1 == ~E_11~0); 14967#L1422-1 assume !(1 == ~E_12~0); 15185#L1427-1 assume { :end_inline_reset_delta_events } true; 13754#L1768-2 [2021-12-19 19:17:38,077 INFO L793 eck$LassoCheckResult]: Loop: 13754#L1768-2 assume !false; 13755#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14495#L1149 assume !false; 14866#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15018#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14144#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14056#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14057#L976 assume !(0 != eval_~tmp~0#1); 15184#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15194#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14985#L1174-3 assume !(0 == ~M_E~0); 14978#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14727#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14728#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14912#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14562#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13915#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13916#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14154#L1209-3 assume !(0 == ~T8_E~0); 13574#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13575#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14333#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14334#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14353#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13762#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13763#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14209#L1249-3 assume !(0 == ~E_4~0); 14665#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15137#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14779#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13768#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13769#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15164#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14331#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14332#L1289-3 assume !(0 == ~E_12~0); 14320#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13993#L566-39 assume 1 == ~m_pc~0; 13994#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14599#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14311#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14312#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14854#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14855#L585-39 assume !(1 == ~t1_pc~0); 14004#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14005#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14080#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14081#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14580#L604-39 assume 1 == ~t2_pc~0; 14581#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14212#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14213#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14630#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14631#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14195#L623-39 assume 1 == ~t3_pc~0; 13591#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13593#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14871#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14047#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14048#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14819#L642-39 assume 1 == ~t4_pc~0; 14390#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14391#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13919#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13968#L661-39 assume 1 == ~t5_pc~0; 13969#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13600#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14960#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14961#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14874#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14875#L680-39 assume 1 == ~t6_pc~0; 13661#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13662#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14804#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14127#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14128#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15142#L699-39 assume 1 == ~t7_pc~0; 14564#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14286#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14287#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14970#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15091#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15089#L718-39 assume !(1 == ~t8_pc~0); 14480#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 14479#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14411#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14412#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 14713#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14683#L737-39 assume 1 == ~t9_pc~0; 14108#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14109#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14398#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15165#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15066#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15009#L756-39 assume 1 == ~t10_pc~0; 15010#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14491#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14235#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14236#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14368#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13708#L775-39 assume 1 == ~t11_pc~0; 13709#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14361#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14362#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15224#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14772#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14419#L794-39 assume !(1 == ~t12_pc~0); 14104#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14105#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14925#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14826#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13650#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13651#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15118#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15119#L1312-3 assume !(1 == ~T2_E~0); 15230#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14843#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13789#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13758#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13759#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14507#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14632#L1352-3 assume !(1 == ~T10_E~0); 14633#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15072#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15223#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15214#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13584#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13585#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14219#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14220#L1392-3 assume !(1 == ~E_6~0); 14935#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15181#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14598#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13874#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13875#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14523#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14524#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13884#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13885#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14751#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14602#L1787 assume !(0 == start_simulation_~tmp~3#1); 14603#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15127#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13855#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14650#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 14651#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14202#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14203#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14204#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13754#L1768-2 [2021-12-19 19:17:38,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,078 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2021-12-19 19:17:38,078 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818579692] [2021-12-19 19:17:38,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818579692] [2021-12-19 19:17:38,099 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818579692] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,099 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,099 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [819368147] [2021-12-19 19:17:38,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,099 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371202, now seen corresponding path program 1 times [2021-12-19 19:17:38,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999286006] [2021-12-19 19:17:38,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,100 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,127 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999286006] [2021-12-19 19:17:38,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999286006] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,127 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119382853] [2021-12-19 19:17:38,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,128 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,128 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,129 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,151 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2021-12-19 19:17:38,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2021-12-19 19:17:38,159 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-12-19 19:17:38,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2021-12-19 19:17:38,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,167 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-19 19:17:38,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2021-12-19 19:17:38,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-12-19 19:17:38,187 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-19 19:17:38,187 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-19 19:17:38,187 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-19 19:17:38,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2021-12-19 19:17:38,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,193 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,193 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,193 INFO L791 eck$LassoCheckResult]: Stem: 17733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18587#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18081#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17886#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17887#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17972#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18273#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18395#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18396#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17184#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17185#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18333#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17779#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17780#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17686#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17687#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17428#L1174 assume !(0 == ~M_E~0); 17429#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17280#L1179-1 assume !(0 == ~T2_E~0); 17182#L1184-1 assume !(0 == ~T3_E~0); 17183#L1189-1 assume !(0 == ~T4_E~0); 17221#L1194-1 assume !(0 == ~T5_E~0); 17321#L1199-1 assume !(0 == ~T6_E~0); 18216#L1204-1 assume !(0 == ~T7_E~0); 18135#L1209-1 assume !(0 == ~T8_E~0); 18136#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18524#L1219-1 assume !(0 == ~T10_E~0); 18609#L1224-1 assume !(0 == ~T11_E~0); 17546#L1229-1 assume !(0 == ~T12_E~0); 17107#L1234-1 assume !(0 == ~E_1~0); 17108#L1239-1 assume !(0 == ~E_2~0); 17143#L1244-1 assume !(0 == ~E_3~0); 17144#L1249-1 assume !(0 == ~E_4~0); 17803#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17037#L1259-1 assume !(0 == ~E_6~0); 16992#L1264-1 assume !(0 == ~E_7~0); 16993#L1269-1 assume !(0 == ~E_8~0); 18614#L1274-1 assume !(0 == ~E_9~0); 18549#L1279-1 assume !(0 == ~E_10~0); 17225#L1284-1 assume !(0 == ~E_11~0); 17226#L1289-1 assume !(0 == ~E_12~0); 17855#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17856#L566 assume 1 == ~m_pc~0; 17009#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17010#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18164#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18165#L1455 assume !(0 != activate_threads_~tmp~1#1); 17455#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17456#L585 assume 1 == ~t1_pc~0; 17104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18105#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18106#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18574#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18572#L604 assume !(1 == ~t2_pc~0); 18184#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18185#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17718#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17719#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18358#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18359#L623 assume 1 == ~t3_pc~0; 17633#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16973#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17783#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17784#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18391#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17006#L642 assume !(1 == ~t4_pc~0); 17007#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17472#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17473#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17078#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17079#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18196#L661 assume 1 == ~t5_pc~0; 17243#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17244#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17205#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17206#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18227#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18228#L680 assume !(1 == ~t6_pc~0); 17666#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17667#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17928#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17929#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18457#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18570#L699 assume 1 == ~t7_pc~0; 18056#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18057#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17233#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17234#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17958#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17857#L718 assume !(1 == ~t8_pc~0); 17858#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17219#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17220#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17261#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17262#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17395#L737 assume 1 == ~t9_pc~0; 18261#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17530#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18131#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18132#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17704#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17705#L756 assume 1 == ~t10_pc~0; 18284#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17950#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16936#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16937#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17512#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17513#L775 assume !(1 == ~t11_pc~0); 17767#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17768#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17389#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17153#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17154#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17340#L794 assume 1 == ~t12_pc~0; 17181#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17158#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18351#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17308#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17309#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17786#L1307 assume !(1 == ~M_E~0); 17787#L1307-2 assume !(1 == ~T1_E~0); 17898#L1312-1 assume !(1 == ~T2_E~0); 17817#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17818#L1322-1 assume !(1 == ~T4_E~0); 17521#L1327-1 assume !(1 == ~T5_E~0); 17522#L1332-1 assume !(1 == ~T6_E~0); 18060#L1337-1 assume !(1 == ~T7_E~0); 18022#L1342-1 assume !(1 == ~T8_E~0); 18023#L1347-1 assume !(1 == ~T9_E~0); 18420#L1352-1 assume !(1 == ~T10_E~0); 18293#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17684#L1362-1 assume !(1 == ~T12_E~0); 17685#L1367-1 assume !(1 == ~E_1~0); 17322#L1372-1 assume !(1 == ~E_2~0); 17323#L1377-1 assume !(1 == ~E_3~0); 17616#L1382-1 assume !(1 == ~E_4~0); 17617#L1387-1 assume !(1 == ~E_5~0); 18186#L1392-1 assume !(1 == ~E_6~0); 17638#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17639#L1402-1 assume !(1 == ~E_8~0); 17335#L1407-1 assume !(1 == ~E_9~0); 17336#L1412-1 assume !(1 == ~E_10~0); 18349#L1417-1 assume !(1 == ~E_11~0); 18350#L1422-1 assume !(1 == ~E_12~0); 18568#L1427-1 assume { :end_inline_reset_delta_events } true; 17137#L1768-2 [2021-12-19 19:17:38,193 INFO L793 eck$LassoCheckResult]: Loop: 17137#L1768-2 assume !false; 17138#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17876#L1149 assume !false; 18248#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18401#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17527#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17433#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17434#L976 assume !(0 != eval_~tmp~0#1); 18567#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18577#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18368#L1174-3 assume !(0 == ~M_E~0); 18361#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18110#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18111#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18295#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17945#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17298#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17299#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17537#L1209-3 assume !(0 == ~T8_E~0); 16957#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16958#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17716#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17717#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17735#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17145#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17146#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17589#L1249-3 assume !(0 == ~E_4~0); 18048#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18520#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18162#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17151#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17152#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18547#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17714#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17715#L1289-3 assume !(0 == ~E_12~0); 17703#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17379#L566-39 assume 1 == ~m_pc~0; 17380#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17982#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17694#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17695#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18237#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18238#L585-39 assume !(1 == ~t1_pc~0); 17387#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17388#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17463#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17464#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18270#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17963#L604-39 assume 1 == ~t2_pc~0; 17964#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17595#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17596#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18015#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18016#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17578#L623-39 assume 1 == ~t3_pc~0; 16976#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16978#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18254#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17430#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18202#L642-39 assume !(1 == ~t4_pc~0); 17777#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 17776#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17302#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17303#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18400#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17353#L661-39 assume !(1 == ~t5_pc~0); 16982#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16983#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18343#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18344#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18258#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18259#L680-39 assume 1 == ~t6_pc~0; 17046#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17047#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18187#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17510#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17511#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18525#L699-39 assume 1 == ~t7_pc~0; 17947#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17669#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17670#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18353#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18473#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18471#L718-39 assume 1 == ~t8_pc~0; 17861#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17862#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17794#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17795#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18096#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18066#L737-39 assume 1 == ~t9_pc~0; 17491#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17492#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18548#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18449#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18392#L756-39 assume !(1 == ~t10_pc~0); 17873#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17874#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17618#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17619#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17751#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17091#L775-39 assume 1 == ~t11_pc~0; 17092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17744#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17745#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18607#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18155#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17802#L794-39 assume 1 == ~t12_pc~0; 17494#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17488#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18308#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18209#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17033#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17034#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18501#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18502#L1312-3 assume !(1 == ~T2_E~0); 18613#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18225#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18226#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17170#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17141#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17142#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17890#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18013#L1352-3 assume !(1 == ~T10_E~0); 18014#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18454#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18606#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18597#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16967#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16968#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17602#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17603#L1392-3 assume !(1 == ~E_6~0); 18318#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18564#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17981#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17257#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17258#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17904#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17905#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17267#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17268#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18134#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17985#L1787 assume !(0 == start_simulation_~tmp~3#1); 17986#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18510#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17238#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18033#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 18034#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17585#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17586#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17587#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17137#L1768-2 [2021-12-19 19:17:38,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,194 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2021-12-19 19:17:38,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228584201] [2021-12-19 19:17:38,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,195 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228584201] [2021-12-19 19:17:38,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228584201] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,223 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078773250] [2021-12-19 19:17:38,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,223 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,224 INFO L85 PathProgramCache]: Analyzing trace with hash 673802017, now seen corresponding path program 1 times [2021-12-19 19:17:38,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105974586] [2021-12-19 19:17:38,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,224 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105974586] [2021-12-19 19:17:38,253 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105974586] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,253 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523187563] [2021-12-19 19:17:38,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,254 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,254 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,276 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2021-12-19 19:17:38,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2021-12-19 19:17:38,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,287 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-12-19 19:17:38,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2021-12-19 19:17:38,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,290 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-19 19:17:38,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2021-12-19 19:17:38,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-12-19 19:17:38,311 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-19 19:17:38,311 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-19 19:17:38,311 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-19 19:17:38,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2021-12-19 19:17:38,318 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,320 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,321 INFO L791 eck$LassoCheckResult]: Stem: 21116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 21117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21970#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21462#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21269#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21270#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21355#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21656#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21778#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21779#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20567#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20568#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21716#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21162#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21163#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21069#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21070#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21458#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20811#L1174 assume !(0 == ~M_E~0); 20812#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20663#L1179-1 assume !(0 == ~T2_E~0); 20565#L1184-1 assume !(0 == ~T3_E~0); 20566#L1189-1 assume !(0 == ~T4_E~0); 20604#L1194-1 assume !(0 == ~T5_E~0); 20704#L1199-1 assume !(0 == ~T6_E~0); 21599#L1204-1 assume !(0 == ~T7_E~0); 21518#L1209-1 assume !(0 == ~T8_E~0); 21519#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21907#L1219-1 assume !(0 == ~T10_E~0); 21992#L1224-1 assume !(0 == ~T11_E~0); 20929#L1229-1 assume !(0 == ~T12_E~0); 20490#L1234-1 assume !(0 == ~E_1~0); 20491#L1239-1 assume !(0 == ~E_2~0); 20524#L1244-1 assume !(0 == ~E_3~0); 20525#L1249-1 assume !(0 == ~E_4~0); 21186#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20420#L1259-1 assume !(0 == ~E_6~0); 20375#L1264-1 assume !(0 == ~E_7~0); 20376#L1269-1 assume !(0 == ~E_8~0); 21997#L1274-1 assume !(0 == ~E_9~0); 21932#L1279-1 assume !(0 == ~E_10~0); 20608#L1284-1 assume !(0 == ~E_11~0); 20609#L1289-1 assume !(0 == ~E_12~0); 21238#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21239#L566 assume 1 == ~m_pc~0; 20392#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20393#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21547#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21548#L1455 assume !(0 != activate_threads_~tmp~1#1); 20838#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20839#L585 assume 1 == ~t1_pc~0; 20487#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20488#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21488#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21489#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 21957#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21955#L604 assume !(1 == ~t2_pc~0); 21567#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21568#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21101#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21102#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21739#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21740#L623 assume 1 == ~t3_pc~0; 21016#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20356#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21166#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21167#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21774#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20389#L642 assume !(1 == ~t4_pc~0); 20390#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20855#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20856#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20461#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20462#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21579#L661 assume 1 == ~t5_pc~0; 20626#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20627#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20588#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20589#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21608#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21609#L680 assume !(1 == ~t6_pc~0); 21049#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21050#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21311#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21312#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 21840#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21953#L699 assume 1 == ~t7_pc~0; 21439#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21440#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20616#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20617#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21240#L718 assume !(1 == ~t8_pc~0); 21241#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20602#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20603#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20644#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20645#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20778#L737 assume 1 == ~t9_pc~0; 21643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20913#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21514#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21515#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21087#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21088#L756 assume 1 == ~t10_pc~0; 21667#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21333#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20319#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20320#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 20895#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20896#L775 assume !(1 == ~t11_pc~0); 21150#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21151#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20772#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20536#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20537#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20723#L794 assume 1 == ~t12_pc~0; 20563#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20541#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21734#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20689#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20690#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21169#L1307 assume !(1 == ~M_E~0); 21170#L1307-2 assume !(1 == ~T1_E~0); 21281#L1312-1 assume !(1 == ~T2_E~0); 21200#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21201#L1322-1 assume !(1 == ~T4_E~0); 20904#L1327-1 assume !(1 == ~T5_E~0); 20905#L1332-1 assume !(1 == ~T6_E~0); 21443#L1337-1 assume !(1 == ~T7_E~0); 21405#L1342-1 assume !(1 == ~T8_E~0); 21406#L1347-1 assume !(1 == ~T9_E~0); 21803#L1352-1 assume !(1 == ~T10_E~0); 21676#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21067#L1362-1 assume !(1 == ~T12_E~0); 21068#L1367-1 assume !(1 == ~E_1~0); 20705#L1372-1 assume !(1 == ~E_2~0); 20706#L1377-1 assume !(1 == ~E_3~0); 20999#L1382-1 assume !(1 == ~E_4~0); 21000#L1387-1 assume !(1 == ~E_5~0); 21569#L1392-1 assume !(1 == ~E_6~0); 21019#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21020#L1402-1 assume !(1 == ~E_8~0); 20716#L1407-1 assume !(1 == ~E_9~0); 20717#L1412-1 assume !(1 == ~E_10~0); 21732#L1417-1 assume !(1 == ~E_11~0); 21733#L1422-1 assume !(1 == ~E_12~0); 21951#L1427-1 assume { :end_inline_reset_delta_events } true; 20520#L1768-2 [2021-12-19 19:17:38,321 INFO L793 eck$LassoCheckResult]: Loop: 20520#L1768-2 assume !false; 20521#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21259#L1149 assume !false; 21631#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21784#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20910#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20816#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20817#L976 assume !(0 != eval_~tmp~0#1); 21950#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21960#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21751#L1174-3 assume !(0 == ~M_E~0); 21744#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21493#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21494#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21677#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21328#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20678#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20679#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20920#L1209-3 assume !(0 == ~T8_E~0); 20340#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20341#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21099#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21100#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21118#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20528#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20529#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20972#L1249-3 assume !(0 == ~E_4~0); 21431#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21903#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21545#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20534#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20535#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21930#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21097#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21098#L1289-3 assume !(0 == ~E_12~0); 21086#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20762#L566-39 assume 1 == ~m_pc~0; 20763#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21365#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21077#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21078#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21621#L585-39 assume !(1 == ~t1_pc~0); 20770#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20771#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20846#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20847#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21653#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21346#L604-39 assume 1 == ~t2_pc~0; 21347#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20978#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20979#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21396#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21397#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20961#L623-39 assume 1 == ~t3_pc~0; 20357#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20359#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21637#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20813#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20814#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21585#L642-39 assume 1 == ~t4_pc~0; 21156#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21157#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20685#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20686#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21783#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20734#L661-39 assume !(1 == ~t5_pc~0); 20365#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 20366#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21726#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21727#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21641#L680-39 assume 1 == ~t6_pc~0; 20427#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20428#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21570#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20893#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20894#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21908#L699-39 assume 1 == ~t7_pc~0; 21330#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21052#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21053#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21736#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21857#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21855#L718-39 assume 1 == ~t8_pc~0; 21244#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21245#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21177#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21178#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 21480#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21449#L737-39 assume 1 == ~t9_pc~0; 20874#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20875#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21164#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21931#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21832#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21775#L756-39 assume 1 == ~t10_pc~0; 21776#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21257#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21001#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21002#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21134#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20474#L775-39 assume 1 == ~t11_pc~0; 20475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21127#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21128#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21990#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21185#L794-39 assume !(1 == ~t12_pc~0); 20870#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 20871#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21691#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21592#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20416#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20417#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21884#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21885#L1312-3 assume !(1 == ~T2_E~0); 21996#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21610#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21611#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20555#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20526#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20527#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21273#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21398#L1352-3 assume !(1 == ~T10_E~0); 21399#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21838#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21989#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21980#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20353#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20354#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20985#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20986#L1392-3 assume !(1 == ~E_6~0); 21701#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21947#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21364#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20640#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20641#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21289#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21290#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20650#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20651#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21517#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 21369#L1787 assume !(0 == start_simulation_~tmp~3#1); 21370#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21893#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20621#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21416#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 21417#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20968#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20969#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20970#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20520#L1768-2 [2021-12-19 19:17:38,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,322 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2021-12-19 19:17:38,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,322 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968930970] [2021-12-19 19:17:38,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,345 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968930970] [2021-12-19 19:17:38,345 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968930970] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,345 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,345 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,345 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633805759] [2021-12-19 19:17:38,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,346 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1017478530, now seen corresponding path program 1 times [2021-12-19 19:17:38,346 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491509172] [2021-12-19 19:17:38,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491509172] [2021-12-19 19:17:38,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [491509172] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,375 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,375 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766630729] [2021-12-19 19:17:38,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,376 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,377 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,398 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2021-12-19 19:17:38,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2021-12-19 19:17:38,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-12-19 19:17:38,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2021-12-19 19:17:38,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,415 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-19 19:17:38,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2021-12-19 19:17:38,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-12-19 19:17:38,450 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-19 19:17:38,451 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-19 19:17:38,451 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-19 19:17:38,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2021-12-19 19:17:38,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,456 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,457 INFO L791 eck$LassoCheckResult]: Stem: 24499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25353#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24845#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24652#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24653#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24738#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25039#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25161#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25162#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23951#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25099#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24545#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24546#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24452#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24453#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24841#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24194#L1174 assume !(0 == ~M_E~0); 24195#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24046#L1179-1 assume !(0 == ~T2_E~0); 23948#L1184-1 assume !(0 == ~T3_E~0); 23949#L1189-1 assume !(0 == ~T4_E~0); 23987#L1194-1 assume !(0 == ~T5_E~0); 24087#L1199-1 assume !(0 == ~T6_E~0); 24982#L1204-1 assume !(0 == ~T7_E~0); 24901#L1209-1 assume !(0 == ~T8_E~0); 24902#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25290#L1219-1 assume !(0 == ~T10_E~0); 25375#L1224-1 assume !(0 == ~T11_E~0); 24312#L1229-1 assume !(0 == ~T12_E~0); 23873#L1234-1 assume !(0 == ~E_1~0); 23874#L1239-1 assume !(0 == ~E_2~0); 23907#L1244-1 assume !(0 == ~E_3~0); 23908#L1249-1 assume !(0 == ~E_4~0); 24569#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23803#L1259-1 assume !(0 == ~E_6~0); 23758#L1264-1 assume !(0 == ~E_7~0); 23759#L1269-1 assume !(0 == ~E_8~0); 25380#L1274-1 assume !(0 == ~E_9~0); 25315#L1279-1 assume !(0 == ~E_10~0); 23991#L1284-1 assume !(0 == ~E_11~0); 23992#L1289-1 assume !(0 == ~E_12~0); 24621#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L566 assume 1 == ~m_pc~0; 23775#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23776#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24930#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24931#L1455 assume !(0 != activate_threads_~tmp~1#1); 24221#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24222#L585 assume 1 == ~t1_pc~0; 23870#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23871#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24872#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25340#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25338#L604 assume !(1 == ~t2_pc~0); 24950#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24951#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24484#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24485#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25122#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25123#L623 assume 1 == ~t3_pc~0; 24399#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23739#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24549#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24550#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23772#L642 assume !(1 == ~t4_pc~0); 23773#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24238#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24239#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23844#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23845#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24962#L661 assume 1 == ~t5_pc~0; 24009#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24010#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23971#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23972#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24991#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24992#L680 assume !(1 == ~t6_pc~0); 24432#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24433#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24694#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24695#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25223#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25336#L699 assume 1 == ~t7_pc~0; 24822#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24823#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23999#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24000#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24724#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24623#L718 assume !(1 == ~t8_pc~0); 24624#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23985#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23986#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24027#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24028#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24161#L737 assume 1 == ~t9_pc~0; 25026#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24296#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24897#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24898#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24470#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24471#L756 assume 1 == ~t10_pc~0; 25050#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24716#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23702#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23703#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24278#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24279#L775 assume !(1 == ~t11_pc~0); 24533#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24534#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24155#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23919#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23920#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24106#L794 assume 1 == ~t12_pc~0; 23946#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23924#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25117#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24072#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24073#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24552#L1307 assume !(1 == ~M_E~0); 24553#L1307-2 assume !(1 == ~T1_E~0); 24664#L1312-1 assume !(1 == ~T2_E~0); 24583#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24584#L1322-1 assume !(1 == ~T4_E~0); 24287#L1327-1 assume !(1 == ~T5_E~0); 24288#L1332-1 assume !(1 == ~T6_E~0); 24826#L1337-1 assume !(1 == ~T7_E~0); 24788#L1342-1 assume !(1 == ~T8_E~0); 24789#L1347-1 assume !(1 == ~T9_E~0); 25186#L1352-1 assume !(1 == ~T10_E~0); 25059#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24450#L1362-1 assume !(1 == ~T12_E~0); 24451#L1367-1 assume !(1 == ~E_1~0); 24088#L1372-1 assume !(1 == ~E_2~0); 24089#L1377-1 assume !(1 == ~E_3~0); 24382#L1382-1 assume !(1 == ~E_4~0); 24383#L1387-1 assume !(1 == ~E_5~0); 24952#L1392-1 assume !(1 == ~E_6~0); 24402#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24403#L1402-1 assume !(1 == ~E_8~0); 24099#L1407-1 assume !(1 == ~E_9~0); 24100#L1412-1 assume !(1 == ~E_10~0); 25115#L1417-1 assume !(1 == ~E_11~0); 25116#L1422-1 assume !(1 == ~E_12~0); 25334#L1427-1 assume { :end_inline_reset_delta_events } true; 23903#L1768-2 [2021-12-19 19:17:38,457 INFO L793 eck$LassoCheckResult]: Loop: 23903#L1768-2 assume !false; 23904#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24642#L1149 assume !false; 25014#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25167#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24293#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24199#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24200#L976 assume !(0 != eval_~tmp~0#1); 25333#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25343#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25134#L1174-3 assume !(0 == ~M_E~0); 25127#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24876#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24877#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25060#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24711#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24061#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24062#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24303#L1209-3 assume !(0 == ~T8_E~0); 23723#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23724#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24482#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24483#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24501#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23911#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23912#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24355#L1249-3 assume !(0 == ~E_4~0); 24814#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25286#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24928#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23917#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23918#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25313#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24480#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24481#L1289-3 assume !(0 == ~E_12~0); 24469#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24145#L566-39 assume 1 == ~m_pc~0; 24146#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24748#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24460#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24461#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25003#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25004#L585-39 assume !(1 == ~t1_pc~0); 24153#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24154#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24229#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24230#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25036#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24729#L604-39 assume 1 == ~t2_pc~0; 24730#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24361#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24362#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24779#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24780#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24344#L623-39 assume 1 == ~t3_pc~0; 23740#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23742#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25020#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24196#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24197#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24968#L642-39 assume 1 == ~t4_pc~0; 24539#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24540#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24068#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24069#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25166#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24117#L661-39 assume !(1 == ~t5_pc~0); 23748#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23749#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25109#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25110#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25023#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25024#L680-39 assume 1 == ~t6_pc~0; 23810#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23811#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24953#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24276#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24277#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25291#L699-39 assume 1 == ~t7_pc~0; 24713#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24435#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24436#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25119#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25240#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25238#L718-39 assume 1 == ~t8_pc~0; 24627#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24628#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24560#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24561#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24863#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24832#L737-39 assume 1 == ~t9_pc~0; 24257#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24258#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25314#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25215#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25158#L756-39 assume 1 == ~t10_pc~0; 25159#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24640#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24384#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24385#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24517#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23857#L775-39 assume 1 == ~t11_pc~0; 23858#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24510#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24511#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25373#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24921#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24568#L794-39 assume 1 == ~t12_pc~0; 24260#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24254#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25074#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24975#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23799#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23800#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25268#L1312-3 assume !(1 == ~T2_E~0); 25379#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24993#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24994#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23938#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23909#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23910#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24656#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24781#L1352-3 assume !(1 == ~T10_E~0); 24782#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25221#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25372#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25363#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23736#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23737#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24368#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24369#L1392-3 assume !(1 == ~E_6~0); 25084#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25330#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24747#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24023#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24024#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24672#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24673#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24033#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24034#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24900#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24752#L1787 assume !(0 == start_simulation_~tmp~3#1); 24753#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25276#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24799#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 24800#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24351#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24352#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 24353#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23903#L1768-2 [2021-12-19 19:17:38,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2021-12-19 19:17:38,458 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,458 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25133699] [2021-12-19 19:17:38,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,459 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,487 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,487 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25133699] [2021-12-19 19:17:38,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25133699] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,488 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679723992] [2021-12-19 19:17:38,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,489 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,489 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 1 times [2021-12-19 19:17:38,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,491 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972062949] [2021-12-19 19:17:38,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,492 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,536 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972062949] [2021-12-19 19:17:38,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972062949] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,539 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,540 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530341989] [2021-12-19 19:17:38,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,540 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,540 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,541 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,562 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2021-12-19 19:17:38,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2021-12-19 19:17:38,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-12-19 19:17:38,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2021-12-19 19:17:38,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,578 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-19 19:17:38,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2021-12-19 19:17:38,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-12-19 19:17:38,599 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-19 19:17:38,599 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-19 19:17:38,599 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-19 19:17:38,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2021-12-19 19:17:38,603 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,605 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,605 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,605 INFO L791 eck$LassoCheckResult]: Stem: 27882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28736#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28228#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28035#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28036#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28121#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28422#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28544#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28545#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27333#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27334#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28482#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27928#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27929#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27835#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27836#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28224#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27577#L1174 assume !(0 == ~M_E~0); 27578#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27429#L1179-1 assume !(0 == ~T2_E~0); 27331#L1184-1 assume !(0 == ~T3_E~0); 27332#L1189-1 assume !(0 == ~T4_E~0); 27370#L1194-1 assume !(0 == ~T5_E~0); 27470#L1199-1 assume !(0 == ~T6_E~0); 28365#L1204-1 assume !(0 == ~T7_E~0); 28284#L1209-1 assume !(0 == ~T8_E~0); 28285#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28673#L1219-1 assume !(0 == ~T10_E~0); 28758#L1224-1 assume !(0 == ~T11_E~0); 27695#L1229-1 assume !(0 == ~T12_E~0); 27256#L1234-1 assume !(0 == ~E_1~0); 27257#L1239-1 assume !(0 == ~E_2~0); 27290#L1244-1 assume !(0 == ~E_3~0); 27291#L1249-1 assume !(0 == ~E_4~0); 27952#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27186#L1259-1 assume !(0 == ~E_6~0); 27141#L1264-1 assume !(0 == ~E_7~0); 27142#L1269-1 assume !(0 == ~E_8~0); 28763#L1274-1 assume !(0 == ~E_9~0); 28698#L1279-1 assume !(0 == ~E_10~0); 27374#L1284-1 assume !(0 == ~E_11~0); 27375#L1289-1 assume !(0 == ~E_12~0); 28004#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28005#L566 assume 1 == ~m_pc~0; 27158#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27159#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28313#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28314#L1455 assume !(0 != activate_threads_~tmp~1#1); 27604#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27605#L585 assume 1 == ~t1_pc~0; 27253#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27254#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28254#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28255#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28723#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28721#L604 assume !(1 == ~t2_pc~0); 28333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27867#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27868#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28505#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28506#L623 assume 1 == ~t3_pc~0; 27782#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27122#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27932#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27933#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28540#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27155#L642 assume !(1 == ~t4_pc~0); 27156#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27621#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27622#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27227#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27228#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28345#L661 assume 1 == ~t5_pc~0; 27392#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27393#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27354#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27355#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28375#L680 assume !(1 == ~t6_pc~0); 27815#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27816#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28077#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28078#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28606#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28719#L699 assume 1 == ~t7_pc~0; 28205#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28206#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27382#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27383#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28107#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28006#L718 assume !(1 == ~t8_pc~0); 28007#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27368#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27369#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27410#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27411#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27544#L737 assume 1 == ~t9_pc~0; 28409#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27679#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28280#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28281#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 27853#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27854#L756 assume 1 == ~t10_pc~0; 28433#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28099#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27085#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27086#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27661#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27662#L775 assume !(1 == ~t11_pc~0); 27916#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27917#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27538#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27302#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27303#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27489#L794 assume 1 == ~t12_pc~0; 27329#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27307#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28500#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27455#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27456#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27935#L1307 assume !(1 == ~M_E~0); 27936#L1307-2 assume !(1 == ~T1_E~0); 28047#L1312-1 assume !(1 == ~T2_E~0); 27966#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27967#L1322-1 assume !(1 == ~T4_E~0); 27670#L1327-1 assume !(1 == ~T5_E~0); 27671#L1332-1 assume !(1 == ~T6_E~0); 28209#L1337-1 assume !(1 == ~T7_E~0); 28171#L1342-1 assume !(1 == ~T8_E~0); 28172#L1347-1 assume !(1 == ~T9_E~0); 28569#L1352-1 assume !(1 == ~T10_E~0); 28442#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27833#L1362-1 assume !(1 == ~T12_E~0); 27834#L1367-1 assume !(1 == ~E_1~0); 27471#L1372-1 assume !(1 == ~E_2~0); 27472#L1377-1 assume !(1 == ~E_3~0); 27765#L1382-1 assume !(1 == ~E_4~0); 27766#L1387-1 assume !(1 == ~E_5~0); 28335#L1392-1 assume !(1 == ~E_6~0); 27785#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27786#L1402-1 assume !(1 == ~E_8~0); 27482#L1407-1 assume !(1 == ~E_9~0); 27483#L1412-1 assume !(1 == ~E_10~0); 28498#L1417-1 assume !(1 == ~E_11~0); 28499#L1422-1 assume !(1 == ~E_12~0); 28717#L1427-1 assume { :end_inline_reset_delta_events } true; 27286#L1768-2 [2021-12-19 19:17:38,606 INFO L793 eck$LassoCheckResult]: Loop: 27286#L1768-2 assume !false; 27287#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28025#L1149 assume !false; 28397#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28550#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27676#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27582#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27583#L976 assume !(0 != eval_~tmp~0#1); 28716#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28726#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28517#L1174-3 assume !(0 == ~M_E~0); 28510#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28259#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28260#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28443#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28094#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27444#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27445#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27686#L1209-3 assume !(0 == ~T8_E~0); 27106#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27107#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27865#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27866#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27884#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27294#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27295#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27738#L1249-3 assume !(0 == ~E_4~0); 28197#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28669#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28311#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27300#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27301#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28696#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27863#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27864#L1289-3 assume !(0 == ~E_12~0); 27852#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27528#L566-39 assume 1 == ~m_pc~0; 27529#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28131#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27843#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27844#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28386#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28387#L585-39 assume !(1 == ~t1_pc~0); 27536#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 27537#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27612#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27613#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28419#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28112#L604-39 assume 1 == ~t2_pc~0; 28113#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27744#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27745#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28162#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28163#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27727#L623-39 assume 1 == ~t3_pc~0; 27123#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27125#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28403#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27579#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27580#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28351#L642-39 assume 1 == ~t4_pc~0; 27922#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27923#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27451#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27452#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28549#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27500#L661-39 assume !(1 == ~t5_pc~0); 27131#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 27132#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28492#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28493#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28406#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28407#L680-39 assume 1 == ~t6_pc~0; 27193#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27194#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28336#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27659#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27660#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28674#L699-39 assume 1 == ~t7_pc~0; 28096#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27818#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27819#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28502#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28623#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28621#L718-39 assume 1 == ~t8_pc~0; 28010#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28011#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27943#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27944#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 28246#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28215#L737-39 assume 1 == ~t9_pc~0; 27640#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27641#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27930#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28697#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28598#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28541#L756-39 assume !(1 == ~t10_pc~0); 28022#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28023#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27768#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27900#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27240#L775-39 assume 1 == ~t11_pc~0; 27241#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27893#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27894#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28756#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28304#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27951#L794-39 assume !(1 == ~t12_pc~0); 27636#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27637#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28457#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28358#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27182#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27183#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28650#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28651#L1312-3 assume !(1 == ~T2_E~0); 28762#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28376#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28377#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27321#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27292#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27293#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28039#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28164#L1352-3 assume !(1 == ~T10_E~0); 28165#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28604#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28755#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28746#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27119#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27120#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27751#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27752#L1392-3 assume !(1 == ~E_6~0); 28467#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28713#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28130#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27406#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27407#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28055#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28056#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27416#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27417#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28283#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28135#L1787 assume !(0 == start_simulation_~tmp~3#1); 28136#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28659#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27387#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28182#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28183#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27734#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27735#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 27736#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27286#L1768-2 [2021-12-19 19:17:38,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2021-12-19 19:17:38,606 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,607 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259470528] [2021-12-19 19:17:38,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,607 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259470528] [2021-12-19 19:17:38,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259470528] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,628 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520944378] [2021-12-19 19:17:38,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,629 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 1 times [2021-12-19 19:17:38,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,630 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757195636] [2021-12-19 19:17:38,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,656 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,656 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757195636] [2021-12-19 19:17:38,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757195636] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,656 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,656 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,656 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068485743] [2021-12-19 19:17:38,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,657 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,657 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,658 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,675 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2021-12-19 19:17:38,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2021-12-19 19:17:38,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-12-19 19:17:38,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,692 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,692 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2021-12-19 19:17:38,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,694 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-19 19:17:38,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2021-12-19 19:17:38,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-12-19 19:17:38,725 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-19 19:17:38,725 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-19 19:17:38,725 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-19 19:17:38,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2021-12-19 19:17:38,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,729 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,731 INFO L791 eck$LassoCheckResult]: Stem: 31265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 31266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32119#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31611#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31418#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31419#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31504#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31805#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31927#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31928#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30716#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30717#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31865#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31311#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31312#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31218#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31219#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31607#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30960#L1174 assume !(0 == ~M_E~0); 30961#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30812#L1179-1 assume !(0 == ~T2_E~0); 30714#L1184-1 assume !(0 == ~T3_E~0); 30715#L1189-1 assume !(0 == ~T4_E~0); 30753#L1194-1 assume !(0 == ~T5_E~0); 30853#L1199-1 assume !(0 == ~T6_E~0); 31748#L1204-1 assume !(0 == ~T7_E~0); 31667#L1209-1 assume !(0 == ~T8_E~0); 31668#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32056#L1219-1 assume !(0 == ~T10_E~0); 32141#L1224-1 assume !(0 == ~T11_E~0); 31078#L1229-1 assume !(0 == ~T12_E~0); 30639#L1234-1 assume !(0 == ~E_1~0); 30640#L1239-1 assume !(0 == ~E_2~0); 30673#L1244-1 assume !(0 == ~E_3~0); 30674#L1249-1 assume !(0 == ~E_4~0); 31335#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30569#L1259-1 assume !(0 == ~E_6~0); 30524#L1264-1 assume !(0 == ~E_7~0); 30525#L1269-1 assume !(0 == ~E_8~0); 32146#L1274-1 assume !(0 == ~E_9~0); 32081#L1279-1 assume !(0 == ~E_10~0); 30757#L1284-1 assume !(0 == ~E_11~0); 30758#L1289-1 assume !(0 == ~E_12~0); 31387#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31388#L566 assume 1 == ~m_pc~0; 30541#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30542#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31696#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31697#L1455 assume !(0 != activate_threads_~tmp~1#1); 30987#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30988#L585 assume 1 == ~t1_pc~0; 30636#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30637#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31637#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31638#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32106#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32104#L604 assume !(1 == ~t2_pc~0); 31716#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31717#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31250#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31251#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31888#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31889#L623 assume 1 == ~t3_pc~0; 31165#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30505#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31315#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31316#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31923#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30538#L642 assume !(1 == ~t4_pc~0); 30539#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31004#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31005#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30610#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30611#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31728#L661 assume 1 == ~t5_pc~0; 30775#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30776#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30737#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30738#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31757#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31758#L680 assume !(1 == ~t6_pc~0); 31198#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31199#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31460#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31461#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31989#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32102#L699 assume 1 == ~t7_pc~0; 31588#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31589#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30765#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30766#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31490#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31389#L718 assume !(1 == ~t8_pc~0); 31390#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30751#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30752#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30793#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30794#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30927#L737 assume 1 == ~t9_pc~0; 31792#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31062#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31663#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31664#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31236#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31237#L756 assume 1 == ~t10_pc~0; 31816#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31482#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30468#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30469#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31044#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31045#L775 assume !(1 == ~t11_pc~0); 31299#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31300#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30921#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30685#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30686#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30872#L794 assume 1 == ~t12_pc~0; 30712#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30690#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31883#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30838#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30839#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31318#L1307 assume !(1 == ~M_E~0); 31319#L1307-2 assume !(1 == ~T1_E~0); 31430#L1312-1 assume !(1 == ~T2_E~0); 31349#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31350#L1322-1 assume !(1 == ~T4_E~0); 31053#L1327-1 assume !(1 == ~T5_E~0); 31054#L1332-1 assume !(1 == ~T6_E~0); 31592#L1337-1 assume !(1 == ~T7_E~0); 31554#L1342-1 assume !(1 == ~T8_E~0); 31555#L1347-1 assume !(1 == ~T9_E~0); 31952#L1352-1 assume !(1 == ~T10_E~0); 31825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31216#L1362-1 assume !(1 == ~T12_E~0); 31217#L1367-1 assume !(1 == ~E_1~0); 30854#L1372-1 assume !(1 == ~E_2~0); 30855#L1377-1 assume !(1 == ~E_3~0); 31148#L1382-1 assume !(1 == ~E_4~0); 31149#L1387-1 assume !(1 == ~E_5~0); 31718#L1392-1 assume !(1 == ~E_6~0); 31168#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31169#L1402-1 assume !(1 == ~E_8~0); 30865#L1407-1 assume !(1 == ~E_9~0); 30866#L1412-1 assume !(1 == ~E_10~0); 31881#L1417-1 assume !(1 == ~E_11~0); 31882#L1422-1 assume !(1 == ~E_12~0); 32100#L1427-1 assume { :end_inline_reset_delta_events } true; 30669#L1768-2 [2021-12-19 19:17:38,731 INFO L793 eck$LassoCheckResult]: Loop: 30669#L1768-2 assume !false; 30670#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31408#L1149 assume !false; 31780#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31933#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31059#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30965#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30966#L976 assume !(0 != eval_~tmp~0#1); 32099#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32109#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31900#L1174-3 assume !(0 == ~M_E~0); 31893#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31642#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31643#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31477#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30827#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30828#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31069#L1209-3 assume !(0 == ~T8_E~0); 30489#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30490#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31248#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31249#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31267#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30677#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30678#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31121#L1249-3 assume !(0 == ~E_4~0); 31580#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32052#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31694#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30683#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30684#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32079#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31247#L1289-3 assume !(0 == ~E_12~0); 31235#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30911#L566-39 assume 1 == ~m_pc~0; 30912#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31514#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31226#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31227#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31769#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31770#L585-39 assume !(1 == ~t1_pc~0); 30919#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30920#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30995#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30996#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31802#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31495#L604-39 assume 1 == ~t2_pc~0; 31496#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31127#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31128#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31545#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31546#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31110#L623-39 assume 1 == ~t3_pc~0; 30506#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30508#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31786#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30962#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30963#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31734#L642-39 assume 1 == ~t4_pc~0; 31305#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31306#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30834#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30835#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31932#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30883#L661-39 assume !(1 == ~t5_pc~0); 30514#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 30515#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31875#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31876#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31789#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31790#L680-39 assume 1 == ~t6_pc~0; 30576#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30577#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31719#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31042#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31043#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32057#L699-39 assume 1 == ~t7_pc~0; 31479#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31201#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31202#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31885#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32006#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32004#L718-39 assume 1 == ~t8_pc~0; 31393#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31394#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31326#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31327#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31629#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31598#L737-39 assume !(1 == ~t9_pc~0); 31025#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31024#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31313#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32080#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31981#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31924#L756-39 assume 1 == ~t10_pc~0; 31925#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31406#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31150#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31151#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31283#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30623#L775-39 assume 1 == ~t11_pc~0; 30624#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31276#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31277#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32139#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31687#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L794-39 assume 1 == ~t12_pc~0; 31026#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31020#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31840#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31741#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30565#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30566#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32033#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32034#L1312-3 assume !(1 == ~T2_E~0); 32145#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31759#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31760#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30704#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30675#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30676#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31422#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31547#L1352-3 assume !(1 == ~T10_E~0); 31548#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31987#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32138#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32129#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30502#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30503#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31134#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31135#L1392-3 assume !(1 == ~E_6~0); 31850#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32096#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31513#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30789#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30790#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31438#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31439#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30799#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30800#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31666#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31518#L1787 assume !(0 == start_simulation_~tmp~3#1); 31519#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32042#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30770#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31565#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31566#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31117#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31118#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 31119#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30669#L1768-2 [2021-12-19 19:17:38,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2021-12-19 19:17:38,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340030157] [2021-12-19 19:17:38,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,732 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,755 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340030157] [2021-12-19 19:17:38,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340030157] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,755 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,756 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243197305] [2021-12-19 19:17:38,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,757 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,757 INFO L85 PathProgramCache]: Analyzing trace with hash -182660158, now seen corresponding path program 1 times [2021-12-19 19:17:38,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362055295] [2021-12-19 19:17:38,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,786 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,786 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362055295] [2021-12-19 19:17:38,786 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362055295] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,786 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,787 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62423631] [2021-12-19 19:17:38,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,787 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,787 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,788 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,804 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2021-12-19 19:17:38,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2021-12-19 19:17:38,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-12-19 19:17:38,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2021-12-19 19:17:38,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,821 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-19 19:17:38,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2021-12-19 19:17:38,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-12-19 19:17:38,838 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-19 19:17:38,838 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-19 19:17:38,838 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-19 19:17:38,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2021-12-19 19:17:38,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,845 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,846 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,846 INFO L791 eck$LassoCheckResult]: Stem: 34648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35502#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34996#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34801#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 34802#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34887#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35189#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35310#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35311#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34099#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34100#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35248#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34694#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34695#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34601#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34602#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34991#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34343#L1174 assume !(0 == ~M_E~0); 34344#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34195#L1179-1 assume !(0 == ~T2_E~0); 34097#L1184-1 assume !(0 == ~T3_E~0); 34098#L1189-1 assume !(0 == ~T4_E~0); 34136#L1194-1 assume !(0 == ~T5_E~0); 34236#L1199-1 assume !(0 == ~T6_E~0); 35131#L1204-1 assume !(0 == ~T7_E~0); 35050#L1209-1 assume !(0 == ~T8_E~0); 35051#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35439#L1219-1 assume !(0 == ~T10_E~0); 35524#L1224-1 assume !(0 == ~T11_E~0); 34462#L1229-1 assume !(0 == ~T12_E~0); 34024#L1234-1 assume !(0 == ~E_1~0); 34025#L1239-1 assume !(0 == ~E_2~0); 34058#L1244-1 assume !(0 == ~E_3~0); 34059#L1249-1 assume !(0 == ~E_4~0); 34718#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33952#L1259-1 assume !(0 == ~E_6~0); 33907#L1264-1 assume !(0 == ~E_7~0); 33908#L1269-1 assume !(0 == ~E_8~0); 35529#L1274-1 assume !(0 == ~E_9~0); 35464#L1279-1 assume !(0 == ~E_10~0); 34140#L1284-1 assume !(0 == ~E_11~0); 34141#L1289-1 assume !(0 == ~E_12~0); 34770#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34771#L566 assume 1 == ~m_pc~0; 33924#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33925#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35079#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35080#L1455 assume !(0 != activate_threads_~tmp~1#1); 34370#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34371#L585 assume 1 == ~t1_pc~0; 34019#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34020#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35020#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35021#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35489#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35487#L604 assume !(1 == ~t2_pc~0); 35099#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35100#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34633#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34634#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35273#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35274#L623 assume 1 == ~t3_pc~0; 34548#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33888#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34698#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34699#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35306#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33921#L642 assume !(1 == ~t4_pc~0); 33922#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34387#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34388#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33995#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 33996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35111#L661 assume 1 == ~t5_pc~0; 34158#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34159#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34120#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34121#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35142#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35143#L680 assume !(1 == ~t6_pc~0); 34581#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34582#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34844#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35372#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35485#L699 assume 1 == ~t7_pc~0; 34971#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34972#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34148#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34149#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 34873#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34772#L718 assume !(1 == ~t8_pc~0); 34773#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34134#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34135#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34176#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34177#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34310#L737 assume 1 == ~t9_pc~0; 35176#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34445#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35046#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35047#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34619#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34620#L756 assume 1 == ~t10_pc~0; 35199#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34865#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33851#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33852#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34427#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34428#L775 assume !(1 == ~t11_pc~0); 34682#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34683#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34304#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34068#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34069#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34255#L794 assume 1 == ~t12_pc~0; 34096#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34073#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35266#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34223#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34224#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34701#L1307 assume !(1 == ~M_E~0); 34702#L1307-2 assume !(1 == ~T1_E~0); 34813#L1312-1 assume !(1 == ~T2_E~0); 34732#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34733#L1322-1 assume !(1 == ~T4_E~0); 34436#L1327-1 assume !(1 == ~T5_E~0); 34437#L1332-1 assume !(1 == ~T6_E~0); 34975#L1337-1 assume !(1 == ~T7_E~0); 34937#L1342-1 assume !(1 == ~T8_E~0); 34938#L1347-1 assume !(1 == ~T9_E~0); 35335#L1352-1 assume !(1 == ~T10_E~0); 35208#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34599#L1362-1 assume !(1 == ~T12_E~0); 34600#L1367-1 assume !(1 == ~E_1~0); 34237#L1372-1 assume !(1 == ~E_2~0); 34238#L1377-1 assume !(1 == ~E_3~0); 34531#L1382-1 assume !(1 == ~E_4~0); 34532#L1387-1 assume !(1 == ~E_5~0); 35101#L1392-1 assume !(1 == ~E_6~0); 34553#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34554#L1402-1 assume !(1 == ~E_8~0); 34250#L1407-1 assume !(1 == ~E_9~0); 34251#L1412-1 assume !(1 == ~E_10~0); 35264#L1417-1 assume !(1 == ~E_11~0); 35265#L1422-1 assume !(1 == ~E_12~0); 35483#L1427-1 assume { :end_inline_reset_delta_events } true; 34052#L1768-2 [2021-12-19 19:17:38,846 INFO L793 eck$LassoCheckResult]: Loop: 34052#L1768-2 assume !false; 34053#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34793#L1149 assume !false; 35164#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35316#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34442#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34354#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34355#L976 assume !(0 != eval_~tmp~0#1); 35482#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35492#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35283#L1174-3 assume !(0 == ~M_E~0); 35276#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35025#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35026#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35210#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34860#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34213#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34214#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34452#L1209-3 assume !(0 == ~T8_E~0); 33872#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33873#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34631#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34632#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34650#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34060#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34061#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34504#L1249-3 assume !(0 == ~E_4~0); 34963#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35435#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35077#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34066#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34067#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35462#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34629#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34630#L1289-3 assume !(0 == ~E_12~0); 34618#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34294#L566-39 assume 1 == ~m_pc~0; 34295#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34897#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34609#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34610#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35152#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35153#L585-39 assume !(1 == ~t1_pc~0); 34301#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34302#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34378#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34379#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35185#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34877#L604-39 assume 1 == ~t2_pc~0; 34878#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34510#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34511#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34928#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34929#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34493#L623-39 assume 1 == ~t3_pc~0; 33889#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33891#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35169#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34345#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34346#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35117#L642-39 assume 1 == ~t4_pc~0; 34688#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34689#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34217#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34218#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35315#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34264#L661-39 assume !(1 == ~t5_pc~0); 33897#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 33898#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35258#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35259#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35172#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35173#L680-39 assume 1 == ~t6_pc~0; 33959#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33960#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35102#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34425#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34426#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35440#L699-39 assume 1 == ~t7_pc~0; 34862#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34584#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34585#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35268#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35389#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35387#L718-39 assume 1 == ~t8_pc~0; 34776#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34777#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34709#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34710#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 35011#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34981#L737-39 assume 1 == ~t9_pc~0; 34406#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34407#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34696#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35463#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35364#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35307#L756-39 assume !(1 == ~t10_pc~0); 34788#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 34789#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34533#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34534#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34666#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34006#L775-39 assume 1 == ~t11_pc~0; 34007#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34659#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34660#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35522#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35070#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34717#L794-39 assume !(1 == ~t12_pc~0); 34402#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 34403#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35223#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35124#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33948#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35416#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35417#L1312-3 assume !(1 == ~T2_E~0); 35528#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35140#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35141#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34087#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34056#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34057#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34805#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34930#L1352-3 assume !(1 == ~T10_E~0); 34931#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35370#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35521#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35512#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33882#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33883#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34517#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34518#L1392-3 assume !(1 == ~E_6~0); 35233#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35479#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34896#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34172#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34173#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 34819#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34820#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34182#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34183#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35049#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34900#L1787 assume !(0 == start_simulation_~tmp~3#1); 34901#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35425#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34153#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34948#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34949#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34500#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34501#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 34502#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34052#L1768-2 [2021-12-19 19:17:38,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,847 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2021-12-19 19:17:38,847 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267567465] [2021-12-19 19:17:38,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,848 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,873 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267567465] [2021-12-19 19:17:38,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267567465] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,873 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,874 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,874 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720081647] [2021-12-19 19:17:38,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,874 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,874 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 2 times [2021-12-19 19:17:38,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,875 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504270276] [2021-12-19 19:17:38,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,875 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,901 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,901 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504270276] [2021-12-19 19:17:38,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504270276] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,902 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,902 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [750642168] [2021-12-19 19:17:38,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,902 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,902 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,903 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:38,917 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2021-12-19 19:17:38,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:38,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2021-12-19 19:17:38,922 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-12-19 19:17:38,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:38,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:38,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2021-12-19 19:17:38,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:38,929 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-19 19:17:38,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2021-12-19 19:17:38,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:38,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:38,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-12-19 19:17:38,946 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-19 19:17:38,946 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-19 19:17:38,946 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-19 19:17:38,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2021-12-19 19:17:38,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:38,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:38,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:38,951 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,951 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:38,952 INFO L791 eck$LassoCheckResult]: Stem: 38031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 38032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38885#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38379#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38184#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38185#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38270#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38571#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38693#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38694#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37482#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37483#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38631#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38077#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38078#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37984#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37985#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38374#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37726#L1174 assume !(0 == ~M_E~0); 37727#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37578#L1179-1 assume !(0 == ~T2_E~0); 37480#L1184-1 assume !(0 == ~T3_E~0); 37481#L1189-1 assume !(0 == ~T4_E~0); 37519#L1194-1 assume !(0 == ~T5_E~0); 37619#L1199-1 assume !(0 == ~T6_E~0); 38514#L1204-1 assume !(0 == ~T7_E~0); 38433#L1209-1 assume !(0 == ~T8_E~0); 38434#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38822#L1219-1 assume !(0 == ~T10_E~0); 38907#L1224-1 assume !(0 == ~T11_E~0); 37844#L1229-1 assume !(0 == ~T12_E~0); 37405#L1234-1 assume !(0 == ~E_1~0); 37406#L1239-1 assume !(0 == ~E_2~0); 37441#L1244-1 assume !(0 == ~E_3~0); 37442#L1249-1 assume !(0 == ~E_4~0); 38101#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37335#L1259-1 assume !(0 == ~E_6~0); 37290#L1264-1 assume !(0 == ~E_7~0); 37291#L1269-1 assume !(0 == ~E_8~0); 38912#L1274-1 assume !(0 == ~E_9~0); 38847#L1279-1 assume !(0 == ~E_10~0); 37523#L1284-1 assume !(0 == ~E_11~0); 37524#L1289-1 assume !(0 == ~E_12~0); 38153#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38154#L566 assume 1 == ~m_pc~0; 37307#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37308#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38462#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38463#L1455 assume !(0 != activate_threads_~tmp~1#1); 37753#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37754#L585 assume 1 == ~t1_pc~0; 37402#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37403#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38403#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38404#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38872#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38870#L604 assume !(1 == ~t2_pc~0); 38482#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38483#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38016#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38017#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38654#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38655#L623 assume 1 == ~t3_pc~0; 37931#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37271#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38081#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38082#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38689#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37304#L642 assume !(1 == ~t4_pc~0); 37305#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37770#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37771#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37377#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38494#L661 assume 1 == ~t5_pc~0; 37541#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37542#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37503#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37504#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38525#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38526#L680 assume !(1 == ~t6_pc~0); 37964#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37965#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38226#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38227#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38755#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38868#L699 assume 1 == ~t7_pc~0; 38354#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38355#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37531#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37532#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38256#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38155#L718 assume !(1 == ~t8_pc~0); 38156#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37517#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37518#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37559#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37560#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37693#L737 assume 1 == ~t9_pc~0; 38558#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37828#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38429#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38430#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38002#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38003#L756 assume 1 == ~t10_pc~0; 38582#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37234#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37235#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37810#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37811#L775 assume !(1 == ~t11_pc~0); 38065#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38066#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37687#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37451#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37452#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37638#L794 assume 1 == ~t12_pc~0; 37479#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37456#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38649#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37604#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37605#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38084#L1307 assume !(1 == ~M_E~0); 38085#L1307-2 assume !(1 == ~T1_E~0); 38196#L1312-1 assume !(1 == ~T2_E~0); 38115#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38116#L1322-1 assume !(1 == ~T4_E~0); 37819#L1327-1 assume !(1 == ~T5_E~0); 37820#L1332-1 assume !(1 == ~T6_E~0); 38358#L1337-1 assume !(1 == ~T7_E~0); 38320#L1342-1 assume !(1 == ~T8_E~0); 38321#L1347-1 assume !(1 == ~T9_E~0); 38718#L1352-1 assume !(1 == ~T10_E~0); 38591#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37982#L1362-1 assume !(1 == ~T12_E~0); 37983#L1367-1 assume !(1 == ~E_1~0); 37620#L1372-1 assume !(1 == ~E_2~0); 37621#L1377-1 assume !(1 == ~E_3~0); 37914#L1382-1 assume !(1 == ~E_4~0); 37915#L1387-1 assume !(1 == ~E_5~0); 38484#L1392-1 assume !(1 == ~E_6~0); 37934#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37935#L1402-1 assume !(1 == ~E_8~0); 37631#L1407-1 assume !(1 == ~E_9~0); 37632#L1412-1 assume !(1 == ~E_10~0); 38647#L1417-1 assume !(1 == ~E_11~0); 38648#L1422-1 assume !(1 == ~E_12~0); 38866#L1427-1 assume { :end_inline_reset_delta_events } true; 37435#L1768-2 [2021-12-19 19:17:38,952 INFO L793 eck$LassoCheckResult]: Loop: 37435#L1768-2 assume !false; 37436#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38174#L1149 assume !false; 38546#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38699#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37825#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37731#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37732#L976 assume !(0 != eval_~tmp~0#1); 38865#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38875#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38666#L1174-3 assume !(0 == ~M_E~0); 38659#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38408#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38409#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38593#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37596#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37597#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37835#L1209-3 assume !(0 == ~T8_E~0); 37255#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37256#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38014#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38015#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38033#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37443#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37444#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37887#L1249-3 assume !(0 == ~E_4~0); 38346#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38818#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38460#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37449#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37450#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38845#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38012#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38013#L1289-3 assume !(0 == ~E_12~0); 38001#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37677#L566-39 assume 1 == ~m_pc~0; 37678#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38280#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37992#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37993#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38535#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38536#L585-39 assume !(1 == ~t1_pc~0); 37685#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37686#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37761#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37762#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38261#L604-39 assume 1 == ~t2_pc~0; 38262#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37893#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37894#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38313#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38314#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37876#L623-39 assume 1 == ~t3_pc~0; 37274#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37276#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38552#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37729#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38500#L642-39 assume 1 == ~t4_pc~0; 38073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37600#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37601#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38698#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37651#L661-39 assume !(1 == ~t5_pc~0); 37280#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37281#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38641#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38642#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38555#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38556#L680-39 assume 1 == ~t6_pc~0; 37344#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37345#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38485#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37808#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37809#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38823#L699-39 assume 1 == ~t7_pc~0; 38245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37967#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37968#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38651#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38772#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38770#L718-39 assume 1 == ~t8_pc~0; 38160#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38161#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38093#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38394#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38363#L737-39 assume 1 == ~t9_pc~0; 37789#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37790#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38079#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38846#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38747#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38690#L756-39 assume 1 == ~t10_pc~0; 38691#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38169#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37916#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37917#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38049#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37389#L775-39 assume 1 == ~t11_pc~0; 37390#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38042#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38043#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38905#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38453#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38100#L794-39 assume 1 == ~t12_pc~0; 37792#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37786#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38606#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38507#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37331#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37332#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38799#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38800#L1312-3 assume !(1 == ~T2_E~0); 38911#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38523#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38524#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37468#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37439#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37440#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38188#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38311#L1352-3 assume !(1 == ~T10_E~0); 38312#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38752#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38904#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38895#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37265#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37266#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37900#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37901#L1392-3 assume !(1 == ~E_6~0); 38616#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38862#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38279#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37555#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37556#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38202#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38203#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37565#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37566#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38432#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 38283#L1787 assume !(0 == start_simulation_~tmp~3#1); 38284#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38808#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37536#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38331#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 38332#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37883#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37884#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 37885#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37435#L1768-2 [2021-12-19 19:17:38,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2021-12-19 19:17:38,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717062387] [2021-12-19 19:17:38,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717062387] [2021-12-19 19:17:38,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717062387] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,973 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,973 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315413900] [2021-12-19 19:17:38,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,973 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:38,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:38,974 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 2 times [2021-12-19 19:17:38,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:38,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273635240] [2021-12-19 19:17:38,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:38,974 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:38,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:38,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:38,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:38,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273635240] [2021-12-19 19:17:38,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273635240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:38,998 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:38,998 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:38,998 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [183827179] [2021-12-19 19:17:38,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:38,998 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:38,998 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:38,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:38,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:38,999 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,013 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2021-12-19 19:17:39,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:39,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2021-12-19 19:17:39,019 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:39,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-12-19 19:17:39,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-19 19:17:39,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-19 19:17:39,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2021-12-19 19:17:39,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,047 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-19 19:17:39,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2021-12-19 19:17:39,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-19 19:17:39,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-12-19 19:17:39,065 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-19 19:17:39,065 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-19 19:17:39,065 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-19 19:17:39,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2021-12-19 19:17:39,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-19 19:17:39,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,070 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,070 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,070 INFO L791 eck$LassoCheckResult]: Stem: 41414#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 42268#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41760#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41567#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41568#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41653#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41954#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42076#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42077#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40865#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40866#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42014#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41460#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41461#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41367#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41368#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 41756#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41109#L1174 assume !(0 == ~M_E~0); 41110#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40961#L1179-1 assume !(0 == ~T2_E~0); 40863#L1184-1 assume !(0 == ~T3_E~0); 40864#L1189-1 assume !(0 == ~T4_E~0); 40902#L1194-1 assume !(0 == ~T5_E~0); 41002#L1199-1 assume !(0 == ~T6_E~0); 41897#L1204-1 assume !(0 == ~T7_E~0); 41816#L1209-1 assume !(0 == ~T8_E~0); 41817#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42205#L1219-1 assume !(0 == ~T10_E~0); 42290#L1224-1 assume !(0 == ~T11_E~0); 41227#L1229-1 assume !(0 == ~T12_E~0); 40788#L1234-1 assume !(0 == ~E_1~0); 40789#L1239-1 assume !(0 == ~E_2~0); 40822#L1244-1 assume !(0 == ~E_3~0); 40823#L1249-1 assume !(0 == ~E_4~0); 41484#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40718#L1259-1 assume !(0 == ~E_6~0); 40673#L1264-1 assume !(0 == ~E_7~0); 40674#L1269-1 assume !(0 == ~E_8~0); 42295#L1274-1 assume !(0 == ~E_9~0); 42230#L1279-1 assume !(0 == ~E_10~0); 40906#L1284-1 assume !(0 == ~E_11~0); 40907#L1289-1 assume !(0 == ~E_12~0); 41536#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41537#L566 assume 1 == ~m_pc~0; 40690#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 40691#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41845#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41846#L1455 assume !(0 != activate_threads_~tmp~1#1); 41136#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41137#L585 assume 1 == ~t1_pc~0; 40785#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40786#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41786#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41787#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42255#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42253#L604 assume !(1 == ~t2_pc~0); 41865#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41866#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41399#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41400#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42037#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42038#L623 assume 1 == ~t3_pc~0; 41314#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40654#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41464#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41465#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42072#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40687#L642 assume !(1 == ~t4_pc~0); 40688#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41153#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41154#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40759#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 40760#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41877#L661 assume 1 == ~t5_pc~0; 40924#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40925#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40886#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40887#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 41906#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41907#L680 assume !(1 == ~t6_pc~0); 41347#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41348#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41609#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41610#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42138#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42251#L699 assume 1 == ~t7_pc~0; 41737#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41738#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40914#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40915#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41639#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41538#L718 assume !(1 == ~t8_pc~0); 41539#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40900#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40901#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40942#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 40943#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41076#L737 assume 1 == ~t9_pc~0; 41941#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41211#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41812#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41813#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41385#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41386#L756 assume 1 == ~t10_pc~0; 41965#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41631#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40617#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40618#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41193#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41194#L775 assume !(1 == ~t11_pc~0); 41448#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41449#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41070#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40834#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40835#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41021#L794 assume 1 == ~t12_pc~0; 40861#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40839#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42032#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40987#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 40988#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41467#L1307 assume !(1 == ~M_E~0); 41468#L1307-2 assume !(1 == ~T1_E~0); 41579#L1312-1 assume !(1 == ~T2_E~0); 41498#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41499#L1322-1 assume !(1 == ~T4_E~0); 41202#L1327-1 assume !(1 == ~T5_E~0); 41203#L1332-1 assume !(1 == ~T6_E~0); 41741#L1337-1 assume !(1 == ~T7_E~0); 41703#L1342-1 assume !(1 == ~T8_E~0); 41704#L1347-1 assume !(1 == ~T9_E~0); 42101#L1352-1 assume !(1 == ~T10_E~0); 41974#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41365#L1362-1 assume !(1 == ~T12_E~0); 41366#L1367-1 assume !(1 == ~E_1~0); 41003#L1372-1 assume !(1 == ~E_2~0); 41004#L1377-1 assume !(1 == ~E_3~0); 41297#L1382-1 assume !(1 == ~E_4~0); 41298#L1387-1 assume !(1 == ~E_5~0); 41867#L1392-1 assume !(1 == ~E_6~0); 41317#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41318#L1402-1 assume !(1 == ~E_8~0); 41014#L1407-1 assume !(1 == ~E_9~0); 41015#L1412-1 assume !(1 == ~E_10~0); 42030#L1417-1 assume !(1 == ~E_11~0); 42031#L1422-1 assume !(1 == ~E_12~0); 42249#L1427-1 assume { :end_inline_reset_delta_events } true; 40818#L1768-2 [2021-12-19 19:17:39,071 INFO L793 eck$LassoCheckResult]: Loop: 40818#L1768-2 assume !false; 40819#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41557#L1149 assume !false; 41929#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42082#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41208#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41114#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41115#L976 assume !(0 != eval_~tmp~0#1); 42248#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42258#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42049#L1174-3 assume !(0 == ~M_E~0); 42042#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41791#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41792#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41975#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41626#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40976#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40977#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41218#L1209-3 assume !(0 == ~T8_E~0); 40638#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40639#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41397#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41398#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41416#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40826#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40827#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41270#L1249-3 assume !(0 == ~E_4~0); 41729#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42201#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41843#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40832#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40833#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42228#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41395#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41396#L1289-3 assume !(0 == ~E_12~0); 41384#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41060#L566-39 assume 1 == ~m_pc~0; 41061#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41663#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41375#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41376#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41918#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41919#L585-39 assume !(1 == ~t1_pc~0); 41068#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 41069#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41144#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41145#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41951#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41644#L604-39 assume 1 == ~t2_pc~0; 41645#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41276#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41277#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41694#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41695#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41259#L623-39 assume !(1 == ~t3_pc~0); 40656#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 40657#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41935#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41111#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41112#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41883#L642-39 assume !(1 == ~t4_pc~0); 41456#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41455#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40983#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40984#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42081#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41032#L661-39 assume !(1 == ~t5_pc~0); 40663#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 40664#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42024#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42025#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41938#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41939#L680-39 assume 1 == ~t6_pc~0; 40725#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40726#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41868#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41191#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41192#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42206#L699-39 assume 1 == ~t7_pc~0; 41628#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41350#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41351#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42034#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42155#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42153#L718-39 assume 1 == ~t8_pc~0; 41542#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41543#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41475#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41476#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 41778#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41747#L737-39 assume 1 == ~t9_pc~0; 41172#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41173#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41462#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42229#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42130#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42073#L756-39 assume !(1 == ~t10_pc~0); 41554#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41555#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41299#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41300#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41432#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40772#L775-39 assume 1 == ~t11_pc~0; 40773#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41425#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41426#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42288#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41836#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41483#L794-39 assume !(1 == ~t12_pc~0); 41168#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 41169#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41989#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41890#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40714#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42182#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42183#L1312-3 assume !(1 == ~T2_E~0); 42294#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41908#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41909#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40853#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40824#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40825#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41571#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41696#L1352-3 assume !(1 == ~T10_E~0); 41697#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42136#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42287#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42278#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40651#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40652#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41283#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41284#L1392-3 assume !(1 == ~E_6~0); 41999#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42245#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41662#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40938#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40939#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41587#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41588#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40948#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40949#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41815#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41667#L1787 assume !(0 == start_simulation_~tmp~3#1); 41668#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42191#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40919#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41714#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 41715#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41266#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41267#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 41268#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 40818#L1768-2 [2021-12-19 19:17:39,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,071 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2021-12-19 19:17:39,071 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,072 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209016732] [2021-12-19 19:17:39,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209016732] [2021-12-19 19:17:39,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209016732] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,098 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,098 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,098 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762139198] [2021-12-19 19:17:39,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,099 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,099 INFO L85 PathProgramCache]: Analyzing trace with hash 1824468511, now seen corresponding path program 1 times [2021-12-19 19:17:39,099 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,100 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720932274] [2021-12-19 19:17:39,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,100 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,123 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,123 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720932274] [2021-12-19 19:17:39,123 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720932274] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,123 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,123 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,123 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422849374] [2021-12-19 19:17:39,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,124 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,124 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:39,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:39,125 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,237 INFO L93 Difference]: Finished difference Result 3122 states and 4596 transitions. [2021-12-19 19:17:39,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3122 states and 4596 transitions. [2021-12-19 19:17:39,247 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2936 [2021-12-19 19:17:39,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3122 states to 3122 states and 4596 transitions. [2021-12-19 19:17:39,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3122 [2021-12-19 19:17:39,256 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3122 [2021-12-19 19:17:39,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3122 states and 4596 transitions. [2021-12-19 19:17:39,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,259 INFO L681 BuchiCegarLoop]: Abstraction has 3122 states and 4596 transitions. [2021-12-19 19:17:39,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3122 states and 4596 transitions. [2021-12-19 19:17:39,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3122 to 3122. [2021-12-19 19:17:39,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3122 states, 3122 states have (on average 1.4721332479180014) internal successors, (4596), 3121 states have internal predecessors, (4596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3122 states to 3122 states and 4596 transitions. [2021-12-19 19:17:39,297 INFO L704 BuchiCegarLoop]: Abstraction has 3122 states and 4596 transitions. [2021-12-19 19:17:39,297 INFO L587 BuchiCegarLoop]: Abstraction has 3122 states and 4596 transitions. [2021-12-19 19:17:39,297 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-19 19:17:39,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3122 states and 4596 transitions. [2021-12-19 19:17:39,303 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2936 [2021-12-19 19:17:39,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,305 INFO L791 eck$LassoCheckResult]: Stem: 46236#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 46237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 47231#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46595#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46396#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 46397#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46484#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46793#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46933#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46934#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45685#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45686#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46855#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46284#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46285#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46189#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46190#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 46591#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45929#L1174 assume !(0 == ~M_E~0); 45930#L1174-2 assume !(0 == ~T1_E~0); 45781#L1179-1 assume !(0 == ~T2_E~0); 45683#L1184-1 assume !(0 == ~T3_E~0); 45684#L1189-1 assume !(0 == ~T4_E~0); 45722#L1194-1 assume !(0 == ~T5_E~0); 45822#L1199-1 assume !(0 == ~T6_E~0); 46735#L1204-1 assume !(0 == ~T7_E~0); 46653#L1209-1 assume !(0 == ~T8_E~0); 46654#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47121#L1219-1 assume !(0 == ~T10_E~0); 47260#L1224-1 assume !(0 == ~T11_E~0); 46049#L1229-1 assume !(0 == ~T12_E~0); 45608#L1234-1 assume !(0 == ~E_1~0); 45609#L1239-1 assume !(0 == ~E_2~0); 45642#L1244-1 assume !(0 == ~E_3~0); 45643#L1249-1 assume !(0 == ~E_4~0); 46309#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 45538#L1259-1 assume !(0 == ~E_6~0); 45493#L1264-1 assume !(0 == ~E_7~0); 45494#L1269-1 assume !(0 == ~E_8~0); 47276#L1274-1 assume !(0 == ~E_9~0); 47159#L1279-1 assume !(0 == ~E_10~0); 45726#L1284-1 assume !(0 == ~E_11~0); 45727#L1289-1 assume !(0 == ~E_12~0); 46364#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46365#L566 assume 1 == ~m_pc~0; 45510#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45511#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46682#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46683#L1455 assume !(0 != activate_threads_~tmp~1#1); 45957#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45958#L585 assume 1 == ~t1_pc~0; 45605#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45606#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46621#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46622#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 47203#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47198#L604 assume !(1 == ~t2_pc~0); 46702#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46703#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46221#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46222#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46883#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46884#L623 assume 1 == ~t3_pc~0; 46136#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45474#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46288#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46289#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 46927#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45507#L642 assume !(1 == ~t4_pc~0); 45508#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 45974#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45975#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45579#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 45580#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46715#L661 assume 1 == ~t5_pc~0; 45744#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45745#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45706#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45707#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 46745#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46746#L680 assume !(1 == ~t6_pc~0); 46169#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46170#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46440#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46441#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 47014#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47194#L699 assume 1 == ~t7_pc~0; 46572#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46573#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45734#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45735#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 46470#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46366#L718 assume !(1 == ~t8_pc~0); 46367#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 45720#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45721#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45762#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 45763#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45896#L737 assume 1 == ~t9_pc~0; 46780#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46033#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46649#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46650#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 46207#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46208#L756 assume 1 == ~t10_pc~0; 46804#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46462#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45437#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45438#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 46015#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46016#L775 assume !(1 == ~t11_pc~0); 46272#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 46273#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45890#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45654#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45655#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45841#L794 assume 1 == ~t12_pc~0; 45681#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45659#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46878#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45807#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 45808#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46291#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 46292#L1307-2 assume !(1 == ~T1_E~0); 46408#L1312-1 assume !(1 == ~T2_E~0); 47469#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47468#L1322-1 assume !(1 == ~T4_E~0); 47467#L1327-1 assume !(1 == ~T5_E~0); 47466#L1332-1 assume !(1 == ~T6_E~0); 47210#L1337-1 assume !(1 == ~T7_E~0); 46534#L1342-1 assume !(1 == ~T8_E~0); 46535#L1347-1 assume !(1 == ~T9_E~0); 46964#L1352-1 assume !(1 == ~T10_E~0); 46813#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46187#L1362-1 assume !(1 == ~T12_E~0); 46188#L1367-1 assume !(1 == ~E_1~0); 45823#L1372-1 assume !(1 == ~E_2~0); 45824#L1377-1 assume !(1 == ~E_3~0); 46119#L1382-1 assume !(1 == ~E_4~0); 46120#L1387-1 assume !(1 == ~E_5~0); 46704#L1392-1 assume !(1 == ~E_6~0); 46139#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46140#L1402-1 assume !(1 == ~E_8~0); 45834#L1407-1 assume !(1 == ~E_9~0); 45835#L1412-1 assume !(1 == ~E_10~0); 46876#L1417-1 assume !(1 == ~E_11~0); 46877#L1422-1 assume !(1 == ~E_12~0); 47290#L1427-1 assume { :end_inline_reset_delta_events } true; 47313#L1768-2 [2021-12-19 19:17:39,306 INFO L793 eck$LassoCheckResult]: Loop: 47313#L1768-2 assume !false; 47309#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47306#L1149 assume !false; 46939#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 46940#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47293#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47292#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 47188#L976 assume !(0 != eval_~tmp~0#1); 47189#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47212#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47213#L1174-3 assume !(0 == ~M_E~0); 46892#L1174-5 assume !(0 == ~T1_E~0); 46627#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46628#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46814#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46457#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45796#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45797#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46040#L1209-3 assume !(0 == ~T8_E~0); 45458#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45459#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46219#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46220#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46238#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45646#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45647#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46092#L1249-3 assume !(0 == ~E_4~0); 46563#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47117#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46680#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45652#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45653#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47155#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 46217#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46218#L1289-3 assume !(0 == ~E_12~0); 46206#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45880#L566-39 assume 1 == ~m_pc~0; 45881#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46494#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46197#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46198#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46757#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46758#L585-39 assume !(1 == ~t1_pc~0); 45888#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 45889#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45965#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45966#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46790#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46475#L604-39 assume 1 == ~t2_pc~0; 46476#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46098#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46099#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46525#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46526#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46081#L623-39 assume 1 == ~t3_pc~0; 45475#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45477#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46774#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45931#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45932#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46721#L642-39 assume 1 == ~t4_pc~0; 46278#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46279#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45803#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45804#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46938#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45852#L661-39 assume !(1 == ~t5_pc~0); 45483#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 45484#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46870#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46871#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46777#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46778#L680-39 assume 1 == ~t6_pc~0; 45545#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45546#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46705#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46706#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48361#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48360#L699-39 assume !(1 == ~t7_pc~0); 48358#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 48357#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48356#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48355#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48354#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48353#L718-39 assume !(1 == ~t8_pc~0); 48352#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 48350#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48349#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48348#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 48347#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48345#L737-39 assume 1 == ~t9_pc~0; 48342#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48340#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47156#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47157#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47230#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46929#L756-39 assume !(1 == ~t10_pc~0); 46930#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 48333#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46121#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46122#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48314#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48313#L775-39 assume 1 == ~t11_pc~0; 48311#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48310#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48309#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48308#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48307#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48306#L794-39 assume !(1 == ~t12_pc~0); 48304#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 48303#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48302#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48301#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48300#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48299#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47147#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47084#L1312-3 assume !(1 == ~T2_E~0); 48211#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48210#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48209#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48208#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48207#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48206#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46865#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46527#L1352-3 assume !(1 == ~T10_E~0); 46528#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47012#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47424#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47423#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47422#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47421#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47420#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47419#L1392-3 assume !(1 == ~E_6~0); 47416#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47183#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46493#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 45758#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45759#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47409#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47406#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47402#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47389#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47387#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 47384#L1787 assume !(0 == start_simulation_~tmp~3#1); 46921#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47100#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 45739#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47338#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 47337#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47336#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47328#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 47318#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 47313#L1768-2 [2021-12-19 19:17:39,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1916493015, now seen corresponding path program 1 times [2021-12-19 19:17:39,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149822824] [2021-12-19 19:17:39,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,329 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149822824] [2021-12-19 19:17:39,329 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149822824] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,329 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,329 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260118821] [2021-12-19 19:17:39,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,330 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,330 INFO L85 PathProgramCache]: Analyzing trace with hash 79213857, now seen corresponding path program 1 times [2021-12-19 19:17:39,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,330 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943666448] [2021-12-19 19:17:39,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,338 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,365 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943666448] [2021-12-19 19:17:39,366 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943666448] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,366 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,366 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,366 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942807967] [2021-12-19 19:17:39,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,366 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,367 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:39,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:39,368 INFO L87 Difference]: Start difference. First operand 3122 states and 4596 transitions. cyclomatic complexity: 1476 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,491 INFO L93 Difference]: Finished difference Result 5980 states and 8783 transitions. [2021-12-19 19:17:39,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5980 states and 8783 transitions. [2021-12-19 19:17:39,511 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5754 [2021-12-19 19:17:39,531 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5980 states to 5980 states and 8783 transitions. [2021-12-19 19:17:39,531 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5980 [2021-12-19 19:17:39,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5980 [2021-12-19 19:17:39,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5980 states and 8783 transitions. [2021-12-19 19:17:39,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,543 INFO L681 BuchiCegarLoop]: Abstraction has 5980 states and 8783 transitions. [2021-12-19 19:17:39,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5980 states and 8783 transitions. [2021-12-19 19:17:39,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5980 to 5980. [2021-12-19 19:17:39,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5980 states, 5980 states have (on average 1.4687290969899665) internal successors, (8783), 5979 states have internal predecessors, (8783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5980 states to 5980 states and 8783 transitions. [2021-12-19 19:17:39,624 INFO L704 BuchiCegarLoop]: Abstraction has 5980 states and 8783 transitions. [2021-12-19 19:17:39,625 INFO L587 BuchiCegarLoop]: Abstraction has 5980 states and 8783 transitions. [2021-12-19 19:17:39,625 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-19 19:17:39,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5980 states and 8783 transitions. [2021-12-19 19:17:39,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5754 [2021-12-19 19:17:39,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:39,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:39,643 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,643 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:39,644 INFO L791 eck$LassoCheckResult]: Stem: 55352#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 55353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 56275#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55708#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55510#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 55511#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55597#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55909#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56044#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56045#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54798#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54799#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55974#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55399#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55400#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55305#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 55306#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 55703#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55044#L1174 assume !(0 == ~M_E~0); 55045#L1174-2 assume !(0 == ~T1_E~0); 54896#L1179-1 assume !(0 == ~T2_E~0); 54796#L1184-1 assume !(0 == ~T3_E~0); 54797#L1189-1 assume !(0 == ~T4_E~0); 54835#L1194-1 assume !(0 == ~T5_E~0); 54937#L1199-1 assume !(0 == ~T6_E~0); 55846#L1204-1 assume !(0 == ~T7_E~0); 55763#L1209-1 assume !(0 == ~T8_E~0); 55764#L1214-1 assume !(0 == ~T9_E~0); 56183#L1219-1 assume !(0 == ~T10_E~0); 56301#L1224-1 assume !(0 == ~T11_E~0); 55163#L1229-1 assume !(0 == ~T12_E~0); 54723#L1234-1 assume !(0 == ~E_1~0); 54724#L1239-1 assume !(0 == ~E_2~0); 54757#L1244-1 assume !(0 == ~E_3~0); 54758#L1249-1 assume !(0 == ~E_4~0); 55426#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 54651#L1259-1 assume !(0 == ~E_6~0); 54606#L1264-1 assume !(0 == ~E_7~0); 54607#L1269-1 assume !(0 == ~E_8~0); 56311#L1274-1 assume !(0 == ~E_9~0); 56219#L1279-1 assume !(0 == ~E_10~0); 54839#L1284-1 assume !(0 == ~E_11~0); 54840#L1289-1 assume !(0 == ~E_12~0); 55479#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55480#L566 assume 1 == ~m_pc~0; 54623#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 54624#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55793#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55794#L1455 assume !(0 != activate_threads_~tmp~1#1); 55071#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55072#L585 assume 1 == ~t1_pc~0; 54718#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54719#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55732#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55733#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 56253#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56248#L604 assume !(1 == ~t2_pc~0); 55813#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 55814#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55335#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55336#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56001#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56002#L623 assume 1 == ~t3_pc~0; 55250#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54586#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55405#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55406#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 56036#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54620#L642 assume !(1 == ~t4_pc~0); 54621#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 55088#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55089#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54694#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 54695#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55826#L661 assume 1 == ~t5_pc~0; 54857#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54858#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54819#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54820#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 55857#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55858#L680 assume !(1 == ~t6_pc~0); 55283#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55284#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55552#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55553#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 56109#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56246#L699 assume 1 == ~t7_pc~0; 55682#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55683#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54847#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54848#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 55583#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55481#L718 assume !(1 == ~t8_pc~0); 55482#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 54833#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54834#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54879#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 54880#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55011#L737 assume 1 == ~t9_pc~0; 55892#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55147#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55758#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55759#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 55321#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55322#L756 assume 1 == ~t10_pc~0; 55918#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55575#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54549#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54550#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 55128#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55129#L775 assume !(1 == ~t11_pc~0); 55387#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 55388#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55008#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54767#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54768#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54956#L794 assume 1 == ~t12_pc~0; 54795#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54772#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55994#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54924#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 54925#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55408#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 55409#L1307-2 assume !(1 == ~T1_E~0); 55522#L1312-1 assume !(1 == ~T2_E~0); 59076#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59074#L1322-1 assume !(1 == ~T4_E~0); 59072#L1327-1 assume !(1 == ~T5_E~0); 59069#L1332-1 assume !(1 == ~T6_E~0); 59067#L1337-1 assume !(1 == ~T7_E~0); 59065#L1342-1 assume !(1 == ~T8_E~0); 59063#L1347-1 assume !(1 == ~T9_E~0); 56217#L1352-1 assume !(1 == ~T10_E~0); 59061#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59060#L1362-1 assume !(1 == ~T12_E~0); 59059#L1367-1 assume !(1 == ~E_1~0); 59057#L1372-1 assume !(1 == ~E_2~0); 59054#L1377-1 assume !(1 == ~E_3~0); 59052#L1382-1 assume !(1 == ~E_4~0); 59050#L1387-1 assume !(1 == ~E_5~0); 56392#L1392-1 assume !(1 == ~E_6~0); 56387#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 56386#L1402-1 assume !(1 == ~E_8~0); 56384#L1407-1 assume !(1 == ~E_9~0); 56382#L1412-1 assume !(1 == ~E_10~0); 56378#L1417-1 assume !(1 == ~E_11~0); 56370#L1422-1 assume !(1 == ~E_12~0); 56361#L1427-1 assume { :end_inline_reset_delta_events } true; 56354#L1768-2 [2021-12-19 19:17:39,644 INFO L793 eck$LassoCheckResult]: Loop: 56354#L1768-2 assume !false; 56348#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56344#L1149 assume !false; 56343#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 56335#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 56329#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56328#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56326#L976 assume !(0 != eval_~tmp~0#1); 56325#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56324#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56322#L1174-3 assume !(0 == ~M_E~0); 56323#L1174-5 assume !(0 == ~T1_E~0); 60486#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60485#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60484#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60483#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60482#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60481#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60480#L1209-3 assume !(0 == ~T8_E~0); 60479#L1214-3 assume !(0 == ~T9_E~0); 60478#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 60477#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60476#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60475#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60474#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60473#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60472#L1249-3 assume !(0 == ~E_4~0); 60471#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60470#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 60469#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60468#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60467#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 60466#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 60465#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60464#L1289-3 assume !(0 == ~E_12~0); 60463#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60462#L566-39 assume 1 == ~m_pc~0; 60460#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 60459#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60458#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60457#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60456#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60455#L585-39 assume 1 == ~t1_pc~0; 60453#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60452#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60451#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60450#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60449#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60448#L604-39 assume 1 == ~t2_pc~0; 59915#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59913#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59911#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59909#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59908#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59907#L623-39 assume !(1 == ~t3_pc~0); 59904#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 59901#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59899#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59897#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59895#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59893#L642-39 assume 1 == ~t4_pc~0; 59890#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59887#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59885#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59884#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59883#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59881#L661-39 assume !(1 == ~t5_pc~0); 59878#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 59876#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59873#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59872#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59871#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59870#L680-39 assume 1 == ~t6_pc~0; 59868#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59867#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59866#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59865#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59864#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56849#L699-39 assume !(1 == ~t7_pc~0); 56843#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 56837#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56833#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56829#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56825#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56822#L718-39 assume !(1 == ~t8_pc~0); 56816#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 56810#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56806#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56802#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 56798#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56794#L737-39 assume 1 == ~t9_pc~0; 56787#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56782#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56778#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 56774#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56770#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56767#L756-39 assume !(1 == ~t10_pc~0); 56759#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 56755#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56751#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56747#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56743#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56739#L775-39 assume 1 == ~t11_pc~0; 56731#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 56727#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56723#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56719#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56715#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56711#L794-39 assume 1 == ~t12_pc~0; 56704#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56699#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56695#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56691#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 56687#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56208#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56209#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56160#L1312-3 assume !(1 == ~T2_E~0); 56675#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56672#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56669#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56666#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56662#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56659#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56656#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56652#L1352-3 assume !(1 == ~T10_E~0); 56650#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56648#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56645#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56643#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56641#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56639#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56637#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56635#L1392-3 assume !(1 == ~E_6~0); 56632#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56630#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56628#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56626#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56624#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56622#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56619#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 56616#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 56603#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56601#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 56599#L1787 assume !(0 == start_simulation_~tmp~3#1); 56030#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 56589#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 56581#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 56579#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 56385#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56383#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56371#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 56362#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 56354#L1768-2 [2021-12-19 19:17:39,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,645 INFO L85 PathProgramCache]: Analyzing trace with hash -1890427175, now seen corresponding path program 1 times [2021-12-19 19:17:39,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,645 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714316659] [2021-12-19 19:17:39,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,670 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,670 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [714316659] [2021-12-19 19:17:39,670 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [714316659] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,670 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,671 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,671 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292170575] [2021-12-19 19:17:39,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,671 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:39,671 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:39,672 INFO L85 PathProgramCache]: Analyzing trace with hash -313352060, now seen corresponding path program 1 times [2021-12-19 19:17:39,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:39,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813627685] [2021-12-19 19:17:39,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:39,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:39,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:39,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:39,700 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:39,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813627685] [2021-12-19 19:17:39,700 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813627685] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:39,701 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:39,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:39,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564809997] [2021-12-19 19:17:39,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:39,701 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:39,701 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:39,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:39,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:39,702 INFO L87 Difference]: Start difference. First operand 5980 states and 8783 transitions. cyclomatic complexity: 2807 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:39,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:39,885 INFO L93 Difference]: Finished difference Result 11288 states and 16550 transitions. [2021-12-19 19:17:39,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:39,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11288 states and 16550 transitions. [2021-12-19 19:17:39,925 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11018 [2021-12-19 19:17:39,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11288 states to 11288 states and 16550 transitions. [2021-12-19 19:17:39,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11288 [2021-12-19 19:17:39,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11288 [2021-12-19 19:17:39,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11288 states and 16550 transitions. [2021-12-19 19:17:39,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:39,982 INFO L681 BuchiCegarLoop]: Abstraction has 11288 states and 16550 transitions. [2021-12-19 19:17:39,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11288 states and 16550 transitions. [2021-12-19 19:17:40,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11288 to 11284. [2021-12-19 19:17:40,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11284 states, 11284 states have (on average 1.466323998582063) internal successors, (16546), 11283 states have internal predecessors, (16546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11284 states to 11284 states and 16546 transitions. [2021-12-19 19:17:40,141 INFO L704 BuchiCegarLoop]: Abstraction has 11284 states and 16546 transitions. [2021-12-19 19:17:40,141 INFO L587 BuchiCegarLoop]: Abstraction has 11284 states and 16546 transitions. [2021-12-19 19:17:40,141 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-19 19:17:40,141 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11284 states and 16546 transitions. [2021-12-19 19:17:40,169 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11018 [2021-12-19 19:17:40,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:40,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:40,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,171 INFO L791 eck$LassoCheckResult]: Stem: 72628#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 72629#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 73532#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72983#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72783#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 72784#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72870#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73181#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73311#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73312#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 72076#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72077#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73244#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 72674#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 72675#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 72581#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 72582#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 72978#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72322#L1174 assume !(0 == ~M_E~0); 72323#L1174-2 assume !(0 == ~T1_E~0); 72172#L1179-1 assume !(0 == ~T2_E~0); 72074#L1184-1 assume !(0 == ~T3_E~0); 72075#L1189-1 assume !(0 == ~T4_E~0); 72113#L1194-1 assume !(0 == ~T5_E~0); 72213#L1199-1 assume !(0 == ~T6_E~0); 73121#L1204-1 assume !(0 == ~T7_E~0); 73037#L1209-1 assume !(0 == ~T8_E~0); 73038#L1214-1 assume !(0 == ~T9_E~0); 73453#L1219-1 assume !(0 == ~T10_E~0); 73560#L1224-1 assume !(0 == ~T11_E~0); 72441#L1229-1 assume !(0 == ~T12_E~0); 72001#L1234-1 assume !(0 == ~E_1~0); 72002#L1239-1 assume !(0 == ~E_2~0); 72035#L1244-1 assume !(0 == ~E_3~0); 72036#L1249-1 assume !(0 == ~E_4~0); 72699#L1254-1 assume !(0 == ~E_5~0); 71929#L1259-1 assume !(0 == ~E_6~0); 71884#L1264-1 assume !(0 == ~E_7~0); 71885#L1269-1 assume !(0 == ~E_8~0); 73573#L1274-1 assume !(0 == ~E_9~0); 73486#L1279-1 assume !(0 == ~E_10~0); 72117#L1284-1 assume !(0 == ~E_11~0); 72118#L1289-1 assume !(0 == ~E_12~0); 72752#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72753#L566 assume 1 == ~m_pc~0; 71901#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 71902#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73066#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73067#L1455 assume !(0 != activate_threads_~tmp~1#1); 72349#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72350#L585 assume 1 == ~t1_pc~0; 71996#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 71997#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73007#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73008#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 73514#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73512#L604 assume !(1 == ~t2_pc~0); 73086#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73087#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72613#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72614#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 73271#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73272#L623 assume 1 == ~t3_pc~0; 72528#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71864#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72678#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72679#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 73307#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71898#L642 assume !(1 == ~t4_pc~0); 71899#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 72366#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72367#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71970#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 71971#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73100#L661 assume 1 == ~t5_pc~0; 72135#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72136#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72097#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72098#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 73132#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73133#L680 assume !(1 == ~t6_pc~0); 72561#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72562#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72826#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72827#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 73377#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73510#L699 assume 1 == ~t7_pc~0; 72957#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72958#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72125#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 72126#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 72856#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72754#L718 assume !(1 == ~t8_pc~0); 72755#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 72111#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72112#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72153#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 72154#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 72289#L737 assume 1 == ~t9_pc~0; 73168#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72424#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73033#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73034#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 72599#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72600#L756 assume 1 == ~t10_pc~0; 73191#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 72848#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71827#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71828#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 72406#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 72407#L775 assume !(1 == ~t11_pc~0); 72662#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 72663#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72283#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72045#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 72046#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 72232#L794 assume 1 == ~t12_pc~0; 72073#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 72050#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73263#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 72200#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 72201#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72681#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 72682#L1307-2 assume !(1 == ~T1_E~0); 72795#L1312-1 assume !(1 == ~T2_E~0); 73530#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72926#L1322-1 assume !(1 == ~T4_E~0); 72927#L1327-1 assume !(1 == ~T5_E~0); 72961#L1332-1 assume !(1 == ~T6_E~0); 72962#L1337-1 assume !(1 == ~T7_E~0); 72921#L1342-1 assume !(1 == ~T8_E~0); 72922#L1347-1 assume !(1 == ~T9_E~0); 73892#L1352-1 assume !(1 == ~T10_E~0); 73889#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73886#L1362-1 assume !(1 == ~T12_E~0); 73883#L1367-1 assume !(1 == ~E_1~0); 73880#L1372-1 assume !(1 == ~E_2~0); 73876#L1377-1 assume !(1 == ~E_3~0); 73873#L1382-1 assume !(1 == ~E_4~0); 73870#L1387-1 assume !(1 == ~E_5~0); 73866#L1392-1 assume !(1 == ~E_6~0); 73666#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 73663#L1402-1 assume !(1 == ~E_8~0); 73661#L1407-1 assume !(1 == ~E_9~0); 73659#L1412-1 assume !(1 == ~E_10~0); 73642#L1417-1 assume !(1 == ~E_11~0); 73629#L1422-1 assume !(1 == ~E_12~0); 73620#L1427-1 assume { :end_inline_reset_delta_events } true; 73613#L1768-2 [2021-12-19 19:17:40,172 INFO L793 eck$LassoCheckResult]: Loop: 73613#L1768-2 assume !false; 73607#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73603#L1149 assume !false; 73602#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 73594#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 73588#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 73587#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 73585#L976 assume !(0 != eval_~tmp~0#1); 73584#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73583#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73582#L1174-3 assume !(0 == ~M_E~0); 73274#L1174-5 assume !(0 == ~T1_E~0); 73012#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73013#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73202#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72843#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 72190#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72191#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72431#L1209-3 assume !(0 == ~T8_E~0); 71848#L1214-3 assume !(0 == ~T9_E~0); 71849#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 72909#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 79810#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 79808#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 79806#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 79804#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79802#L1249-3 assume !(0 == ~E_4~0); 79800#L1254-3 assume !(0 == ~E_5~0); 79797#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79795#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 79793#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 79791#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79789#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 79787#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 79784#L1289-3 assume !(0 == ~E_12~0); 79782#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79780#L566-39 assume 1 == ~m_pc~0; 79777#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 79775#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79773#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79770#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76201#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76198#L585-39 assume 1 == ~t1_pc~0; 76195#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76193#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76191#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76189#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76187#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76186#L604-39 assume !(1 == ~t2_pc~0); 76183#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 76180#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76178#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76176#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 76174#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76172#L623-39 assume 1 == ~t3_pc~0; 76167#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76164#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76162#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76159#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76157#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76155#L642-39 assume !(1 == ~t4_pc~0); 75497#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 75029#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75028#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73316#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73317#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74617#L661-39 assume 1 == ~t5_pc~0; 74608#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74600#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74591#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74584#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74576#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74569#L680-39 assume !(1 == ~t6_pc~0); 74560#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 74552#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74543#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74536#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74528#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74522#L699-39 assume !(1 == ~t7_pc~0); 74501#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 74493#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74485#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74477#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 74470#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74465#L718-39 assume 1 == ~t8_pc~0; 74449#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 74440#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74433#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74425#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 74417#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74411#L737-39 assume 1 == ~t9_pc~0; 74403#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74363#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73484#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73485#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 73367#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73308#L756-39 assume !(1 == ~t10_pc~0); 72770#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 72771#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 72513#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72514#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 72646#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71983#L775-39 assume !(1 == ~t11_pc~0); 71985#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 72639#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72640#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73558#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73057#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 72698#L794-39 assume 1 == ~t12_pc~0; 72388#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 72382#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73217#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73113#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 71925#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71926#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 73477#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73428#L1312-3 assume !(1 == ~T2_E~0); 74035#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74030#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74025#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 74020#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74014#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74009#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 74004#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 73998#L1352-3 assume !(1 == ~T10_E~0); 73995#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73992#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73988#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73985#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73982#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73979#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73976#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73972#L1392-3 assume !(1 == ~E_6~0); 73969#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73967#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 73965#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 73963#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 73961#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 73959#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 73956#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 73953#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 73940#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 73938#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 73936#L1787 assume !(0 == start_simulation_~tmp~3#1); 73301#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 73926#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 73918#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 73916#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 73667#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73643#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73630#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 73621#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 73613#L1768-2 [2021-12-19 19:17:40,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,172 INFO L85 PathProgramCache]: Analyzing trace with hash -163282213, now seen corresponding path program 1 times [2021-12-19 19:17:40,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343040238] [2021-12-19 19:17:40,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,173 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,203 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,203 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343040238] [2021-12-19 19:17:40,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343040238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,203 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:40,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122156298] [2021-12-19 19:17:40,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:40,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1193108635, now seen corresponding path program 1 times [2021-12-19 19:17:40,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,204 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249243546] [2021-12-19 19:17:40,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249243546] [2021-12-19 19:17:40,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249243546] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:40,238 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296675012] [2021-12-19 19:17:40,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:40,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:40,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:40,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:40,239 INFO L87 Difference]: Start difference. First operand 11284 states and 16546 transitions. cyclomatic complexity: 5270 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:40,379 INFO L93 Difference]: Finished difference Result 22192 states and 32319 transitions. [2021-12-19 19:17:40,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:40,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22192 states and 32319 transitions. [2021-12-19 19:17:40,518 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21911 [2021-12-19 19:17:40,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22192 states to 22192 states and 32319 transitions. [2021-12-19 19:17:40,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22192 [2021-12-19 19:17:40,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22192 [2021-12-19 19:17:40,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22192 states and 32319 transitions. [2021-12-19 19:17:40,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:40,612 INFO L681 BuchiCegarLoop]: Abstraction has 22192 states and 32319 transitions. [2021-12-19 19:17:40,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22192 states and 32319 transitions. [2021-12-19 19:17:40,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22192 to 21456. [2021-12-19 19:17:40,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21456 states, 21456 states have (on average 1.4581935123042506) internal successors, (31287), 21455 states have internal predecessors, (31287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:40,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21456 states to 21456 states and 31287 transitions. [2021-12-19 19:17:40,899 INFO L704 BuchiCegarLoop]: Abstraction has 21456 states and 31287 transitions. [2021-12-19 19:17:40,899 INFO L587 BuchiCegarLoop]: Abstraction has 21456 states and 31287 transitions. [2021-12-19 19:17:40,899 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-19 19:17:40,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21456 states and 31287 transitions. [2021-12-19 19:17:40,956 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21175 [2021-12-19 19:17:40,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:40,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:40,958 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:40,959 INFO L791 eck$LassoCheckResult]: Stem: 106118#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 106119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 107162#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106500#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106288#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 106289#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106380#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106716#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106861#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106862#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105556#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105557#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 106791#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 106168#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106169#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 106071#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 106072#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 106495#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105800#L1174 assume !(0 == ~M_E~0); 105801#L1174-2 assume !(0 == ~T1_E~0); 105654#L1179-1 assume !(0 == ~T2_E~0); 105554#L1184-1 assume !(0 == ~T3_E~0); 105555#L1189-1 assume !(0 == ~T4_E~0); 105593#L1194-1 assume !(0 == ~T5_E~0); 105695#L1199-1 assume !(0 == ~T6_E~0); 106654#L1204-1 assume !(0 == ~T7_E~0); 106560#L1209-1 assume !(0 == ~T8_E~0); 106561#L1214-1 assume !(0 == ~T9_E~0); 107033#L1219-1 assume !(0 == ~T10_E~0); 107207#L1224-1 assume !(0 == ~T11_E~0); 105921#L1229-1 assume !(0 == ~T12_E~0); 105480#L1234-1 assume !(0 == ~E_1~0); 105481#L1239-1 assume !(0 == ~E_2~0); 105514#L1244-1 assume !(0 == ~E_3~0); 105515#L1249-1 assume !(0 == ~E_4~0); 106198#L1254-1 assume !(0 == ~E_5~0); 105408#L1259-1 assume !(0 == ~E_6~0); 105366#L1264-1 assume !(0 == ~E_7~0); 105367#L1269-1 assume !(0 == ~E_8~0); 107243#L1274-1 assume !(0 == ~E_9~0); 107085#L1279-1 assume !(0 == ~E_10~0); 105597#L1284-1 assume !(0 == ~E_11~0); 105598#L1289-1 assume !(0 == ~E_12~0); 106253#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106254#L566 assume !(1 == ~m_pc~0); 106713#L566-2 is_master_triggered_~__retres1~0#1 := 0; 106714#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106596#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106597#L1455 assume !(0 != activate_threads_~tmp~1#1); 105827#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105828#L585 assume 1 == ~t1_pc~0; 105475#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105476#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106527#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106528#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 107128#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107121#L604 assume !(1 == ~t2_pc~0); 106617#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 106618#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106103#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 106104#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 106821#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106822#L623 assume 1 == ~t3_pc~0; 106013#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 105347#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106175#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106176#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 106856#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105380#L642 assume !(1 == ~t4_pc~0); 105381#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 105844#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105845#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 105449#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 105450#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106632#L661 assume 1 == ~t5_pc~0; 105617#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 105618#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105577#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105578#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 106665#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106666#L680 assume !(1 == ~t6_pc~0); 106048#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 106049#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106333#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106334#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 106937#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107118#L699 assume 1 == ~t7_pc~0; 106471#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 106472#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 105605#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105606#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 106365#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106255#L718 assume !(1 == ~t8_pc~0); 106256#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 105591#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 105592#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 105635#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 105636#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 105767#L737 assume 1 == ~t9_pc~0; 106700#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 105905#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106556#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106557#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 106089#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 106090#L756 assume 1 == ~t10_pc~0; 106728#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 106357#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 105310#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105311#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 105886#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105887#L775 assume !(1 == ~t11_pc~0); 106155#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 106156#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 105761#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 105524#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 105525#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 105714#L794 assume 1 == ~t12_pc~0; 105553#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 105529#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 106813#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 105682#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 105683#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106178#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 106179#L1307-2 assume !(1 == ~T1_E~0); 106300#L1312-1 assume !(1 == ~T2_E~0); 121657#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 121652#L1322-1 assume !(1 == ~T4_E~0); 121648#L1327-1 assume !(1 == ~T5_E~0); 121644#L1332-1 assume !(1 == ~T6_E~0); 121640#L1337-1 assume !(1 == ~T7_E~0); 106431#L1342-1 assume !(1 == ~T8_E~0); 106432#L1347-1 assume !(1 == ~T9_E~0); 107083#L1352-1 assume !(1 == ~T10_E~0); 123376#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123374#L1362-1 assume !(1 == ~T12_E~0); 123372#L1367-1 assume !(1 == ~E_1~0); 123370#L1372-1 assume !(1 == ~E_2~0); 123368#L1377-1 assume !(1 == ~E_3~0); 123366#L1382-1 assume !(1 == ~E_4~0); 106619#L1387-1 assume !(1 == ~E_5~0); 106620#L1392-1 assume !(1 == ~E_6~0); 124725#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 124724#L1402-1 assume !(1 == ~E_8~0); 124723#L1407-1 assume !(1 == ~E_9~0); 124722#L1412-1 assume !(1 == ~E_10~0); 124721#L1417-1 assume !(1 == ~E_11~0); 123315#L1422-1 assume !(1 == ~E_12~0); 123311#L1427-1 assume { :end_inline_reset_delta_events } true; 123312#L1768-2 [2021-12-19 19:17:40,959 INFO L793 eck$LassoCheckResult]: Loop: 123312#L1768-2 assume !false; 124696#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124692#L1149 assume !false; 124691#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 107052#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 105902#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 105811#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105812#L976 assume !(0 != eval_~tmp~0#1); 107149#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107139#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107140#L1174-3 assume !(0 == ~M_E~0); 124676#L1174-5 assume !(0 == ~T1_E~0); 125406#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 125404#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 125402#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 125400#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 125397#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 125395#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 125393#L1209-3 assume !(0 == ~T8_E~0); 125391#L1214-3 assume !(0 == ~T9_E~0); 125389#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 125387#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 125384#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 125382#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 125380#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 125378#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 125376#L1249-3 assume !(0 == ~E_4~0); 125374#L1254-3 assume !(0 == ~E_5~0); 125371#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 125369#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 125367#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 125365#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 125363#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 125361#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 125358#L1289-3 assume !(0 == ~E_12~0); 125356#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125354#L566-39 assume !(1 == ~m_pc~0); 125352#L566-41 is_master_triggered_~__retres1~0#1 := 0; 125350#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125348#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 125345#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 125343#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125341#L585-39 assume !(1 == ~t1_pc~0); 125339#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 125336#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125334#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125331#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 125329#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 125327#L604-39 assume !(1 == ~t2_pc~0); 125325#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 125322#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125320#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 125319#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 125316#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125314#L623-39 assume 1 == ~t3_pc~0; 125312#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 125309#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125307#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125305#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 125304#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125301#L642-39 assume !(1 == ~t4_pc~0); 125299#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 125296#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125294#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125292#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 125288#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125286#L661-39 assume !(1 == ~t5_pc~0); 125277#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 125275#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125273#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 125270#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 125268#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125191#L680-39 assume !(1 == ~t6_pc~0); 125185#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 125176#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125172#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 125168#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 125167#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125166#L699-39 assume 1 == ~t7_pc~0; 125165#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125163#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125162#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125161#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125160#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125159#L718-39 assume 1 == ~t8_pc~0; 125157#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 125156#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125155#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125154#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 125153#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 125152#L737-39 assume !(1 == ~t9_pc~0); 125151#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 125149#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125148#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 125147#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 125146#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125145#L756-39 assume !(1 == ~t10_pc~0); 125143#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 125142#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 125141#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125140#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 125139#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105462#L775-39 assume 1 == ~t11_pc~0; 105463#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 106129#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 106130#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 107204#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 106585#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 106195#L794-39 assume 1 == ~t12_pc~0; 106197#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 124943#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 124941#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 124939#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 124937#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124935#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 107072#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106999#L1312-3 assume !(1 == ~T2_E~0); 124930#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 124928#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 124926#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124924#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 124922#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 124919#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 124917#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123634#L1352-3 assume !(1 == ~T10_E~0); 124914#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 124912#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 124910#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 124907#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 124905#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 124903#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 124901#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123381#L1392-3 assume !(1 == ~E_6~0); 124898#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107102#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 106390#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 105631#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 105632#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 106307#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 106308#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 105639#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 105640#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 106559#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 106394#L1787 assume !(0 == start_simulation_~tmp~3#1); 106395#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 107014#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 105610#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 106840#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 123323#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123320#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123316#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 123313#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 123312#L1768-2 [2021-12-19 19:17:40,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1400935302, now seen corresponding path program 1 times [2021-12-19 19:17:40,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388251020] [2021-12-19 19:17:40,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,960 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:40,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:40,983 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:40,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388251020] [2021-12-19 19:17:40,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388251020] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:40,983 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:40,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-19 19:17:40,984 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413038549] [2021-12-19 19:17:40,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:40,984 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:40,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:40,984 INFO L85 PathProgramCache]: Analyzing trace with hash -46213149, now seen corresponding path program 1 times [2021-12-19 19:17:40,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:40,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53780726] [2021-12-19 19:17:40,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:40,985 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:40,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:41,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:41,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:41,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [53780726] [2021-12-19 19:17:41,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [53780726] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:41,008 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:41,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:41,008 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389221344] [2021-12-19 19:17:41,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:41,009 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:41,009 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:41,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-19 19:17:41,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-19 19:17:41,010 INFO L87 Difference]: Start difference. First operand 21456 states and 31287 transitions. cyclomatic complexity: 9847 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:41,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:41,242 INFO L93 Difference]: Finished difference Result 40956 states and 59437 transitions. [2021-12-19 19:17:41,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-19 19:17:41,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40956 states and 59437 transitions. [2021-12-19 19:17:41,557 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40644 [2021-12-19 19:17:41,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40956 states to 40956 states and 59437 transitions. [2021-12-19 19:17:41,730 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40956 [2021-12-19 19:17:41,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40956 [2021-12-19 19:17:41,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40956 states and 59437 transitions. [2021-12-19 19:17:41,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:41,807 INFO L681 BuchiCegarLoop]: Abstraction has 40956 states and 59437 transitions. [2021-12-19 19:17:41,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40956 states and 59437 transitions. [2021-12-19 19:17:42,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40956 to 40924. [2021-12-19 19:17:42,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40924 states, 40924 states have (on average 1.451593197145929) internal successors, (59405), 40923 states have internal predecessors, (59405), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:42,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40924 states to 40924 states and 59405 transitions. [2021-12-19 19:17:42,502 INFO L704 BuchiCegarLoop]: Abstraction has 40924 states and 59405 transitions. [2021-12-19 19:17:42,502 INFO L587 BuchiCegarLoop]: Abstraction has 40924 states and 59405 transitions. [2021-12-19 19:17:42,502 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-19 19:17:42,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40924 states and 59405 transitions. [2021-12-19 19:17:42,591 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40612 [2021-12-19 19:17:42,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:42,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:42,593 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,593 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:42,594 INFO L791 eck$LassoCheckResult]: Stem: 168544#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 168545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 169599#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168922#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 168707#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 168708#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168803#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 169147#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169298#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169299#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 167970#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 167971#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 169218#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168594#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168595#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 168495#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 168496#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 168917#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168221#L1174 assume !(0 == ~M_E~0); 168222#L1174-2 assume !(0 == ~T1_E~0); 168070#L1179-1 assume !(0 == ~T2_E~0); 167968#L1184-1 assume !(0 == ~T3_E~0); 167969#L1189-1 assume !(0 == ~T4_E~0); 168008#L1194-1 assume !(0 == ~T5_E~0); 168111#L1199-1 assume !(0 == ~T6_E~0); 169075#L1204-1 assume !(0 == ~T7_E~0); 168987#L1209-1 assume !(0 == ~T8_E~0); 168988#L1214-1 assume !(0 == ~T9_E~0); 169467#L1219-1 assume !(0 == ~T10_E~0); 169650#L1224-1 assume !(0 == ~T11_E~0); 168347#L1229-1 assume !(0 == ~T12_E~0); 167895#L1234-1 assume !(0 == ~E_1~0); 167896#L1239-1 assume !(0 == ~E_2~0); 167929#L1244-1 assume !(0 == ~E_3~0); 167930#L1249-1 assume !(0 == ~E_4~0); 168618#L1254-1 assume !(0 == ~E_5~0); 167826#L1259-1 assume !(0 == ~E_6~0); 167784#L1264-1 assume !(0 == ~E_7~0); 167785#L1269-1 assume !(0 == ~E_8~0); 169680#L1274-1 assume !(0 == ~E_9~0); 169526#L1279-1 assume !(0 == ~E_10~0); 168011#L1284-1 assume !(0 == ~E_11~0); 168012#L1289-1 assume !(0 == ~E_12~0); 168674#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168675#L566 assume !(1 == ~m_pc~0); 169141#L566-2 is_master_triggered_~__retres1~0#1 := 0; 169142#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169018#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169019#L1455 assume !(0 != activate_threads_~tmp~1#1); 168248#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168249#L585 assume !(1 == ~t1_pc~0); 168436#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 168437#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168951#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 168952#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 169573#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169567#L604 assume !(1 == ~t2_pc~0); 169039#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 169040#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 168525#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168526#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169252#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169253#L623 assume 1 == ~t3_pc~0; 168435#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 167765#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168598#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 168599#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 169293#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 167798#L642 assume !(1 == ~t4_pc~0); 167799#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 168267#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168268#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 167869#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 167870#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169052#L661 assume 1 == ~t5_pc~0; 168031#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 168032#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 167991#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 167992#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 169086#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169087#L680 assume !(1 == ~t6_pc~0); 168471#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 168472#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168753#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 168754#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 169379#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169562#L699 assume 1 == ~t7_pc~0; 168893#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 168894#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 168019#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168020#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 168785#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168676#L718 assume !(1 == ~t8_pc~0); 168677#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 168006#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 168007#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 168053#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 168054#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168188#L737 assume 1 == ~t9_pc~0; 169127#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 168332#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 168980#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168981#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 168511#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 168512#L756 assume 1 == ~t10_pc~0; 169157#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 168776#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 167729#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 167730#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 168312#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 168313#L775 assume !(1 == ~t11_pc~0); 168581#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 168582#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 168185#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 167939#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 167940#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168131#L794 assume 1 == ~t12_pc~0; 167967#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 167944#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 169244#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 168098#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 168099#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168601#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 168602#L1307-2 assume !(1 == ~T1_E~0); 168719#L1312-1 assume !(1 == ~T2_E~0); 168634#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168635#L1322-1 assume !(1 == ~T4_E~0); 168322#L1327-1 assume !(1 == ~T5_E~0); 168323#L1332-1 assume !(1 == ~T6_E~0); 168897#L1337-1 assume !(1 == ~T7_E~0); 168854#L1342-1 assume !(1 == ~T8_E~0); 168855#L1347-1 assume !(1 == ~T9_E~0); 169522#L1352-1 assume !(1 == ~T10_E~0); 184939#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 184938#L1362-1 assume !(1 == ~T12_E~0); 184937#L1367-1 assume !(1 == ~E_1~0); 184936#L1372-1 assume !(1 == ~E_2~0); 184935#L1377-1 assume !(1 == ~E_3~0); 182702#L1382-1 assume !(1 == ~E_4~0); 182701#L1387-1 assume !(1 == ~E_5~0); 181060#L1392-1 assume !(1 == ~E_6~0); 182700#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 182699#L1402-1 assume !(1 == ~E_8~0); 182698#L1407-1 assume !(1 == ~E_9~0); 182684#L1412-1 assume !(1 == ~E_10~0); 182682#L1417-1 assume !(1 == ~E_11~0); 182680#L1422-1 assume !(1 == ~E_12~0); 182674#L1427-1 assume { :end_inline_reset_delta_events } true; 182672#L1768-2 [2021-12-19 19:17:42,594 INFO L793 eck$LassoCheckResult]: Loop: 182672#L1768-2 assume !false; 182669#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 182665#L1149 assume !false; 182663#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 181973#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 181660#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 181105#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 181103#L976 assume !(0 != eval_~tmp~0#1); 181104#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 182987#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 182984#L1174-3 assume !(0 == ~M_E~0); 182982#L1174-5 assume !(0 == ~T1_E~0); 182980#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 182978#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 182976#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 182974#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 182971#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 182969#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 182967#L1209-3 assume !(0 == ~T8_E~0); 182965#L1214-3 assume !(0 == ~T9_E~0); 182963#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 182961#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 182958#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 182956#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 182954#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 182952#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 182950#L1249-3 assume !(0 == ~E_4~0); 182948#L1254-3 assume !(0 == ~E_5~0); 182945#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 182943#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 182941#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 182939#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 182937#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 182935#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 182932#L1289-3 assume !(0 == ~E_12~0); 182930#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 182928#L566-39 assume !(1 == ~m_pc~0); 182926#L566-41 is_master_triggered_~__retres1~0#1 := 0; 182924#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182922#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 182919#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 182917#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 182915#L585-39 assume !(1 == ~t1_pc~0); 182913#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 182911#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 182910#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 182909#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 182908#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182907#L604-39 assume !(1 == ~t2_pc~0); 182906#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 182904#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 182903#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 182902#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 182901#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 182900#L623-39 assume 1 == ~t3_pc~0; 182898#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 182895#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 182893#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 182891#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 182888#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 182886#L642-39 assume 1 == ~t4_pc~0; 182883#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 182881#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 182879#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 182877#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 182874#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 182872#L661-39 assume 1 == ~t5_pc~0; 182870#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 182867#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 182865#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 182863#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 182860#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 182858#L680-39 assume 1 == ~t6_pc~0; 182855#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 182853#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 182851#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 182849#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 182846#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 182844#L699-39 assume 1 == ~t7_pc~0; 182842#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 182839#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 182837#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 182835#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 182834#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 182833#L718-39 assume !(1 == ~t8_pc~0); 182832#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 182830#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 182829#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 182828#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 182827#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 182826#L737-39 assume 1 == ~t9_pc~0; 182822#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 182820#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 182818#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 182816#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 182814#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 182812#L756-39 assume !(1 == ~t10_pc~0); 182808#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 182806#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 182804#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 182802#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 182800#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 182798#L775-39 assume 1 == ~t11_pc~0; 182794#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 182792#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 182790#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 182788#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 182786#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 182784#L794-39 assume !(1 == ~t12_pc~0); 182780#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 182778#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 182776#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 182774#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 182772#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182770#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 181739#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 182762#L1312-3 assume !(1 == ~T2_E~0); 182760#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 182758#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 182756#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 182754#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 182752#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 182750#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 182749#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 182743#L1352-3 assume !(1 == ~T10_E~0); 182741#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 182739#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 182738#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 182733#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182728#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 182727#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 182726#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 181702#L1392-3 assume !(1 == ~E_6~0); 182725#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 182724#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 182723#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 182722#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 182721#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 182720#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 182719#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182717#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182705#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182704#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 182703#L1787 assume !(0 == start_simulation_~tmp~3#1); 169285#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182691#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182683#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182681#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 182679#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182678#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182677#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 182675#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 182672#L1768-2 [2021-12-19 19:17:42,594 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1024833881, now seen corresponding path program 1 times [2021-12-19 19:17:42,595 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,595 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498624818] [2021-12-19 19:17:42,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,595 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,622 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498624818] [2021-12-19 19:17:42,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498624818] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,622 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-19 19:17:42,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883031523] [2021-12-19 19:17:42,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,623 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:42,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:42,623 INFO L85 PathProgramCache]: Analyzing trace with hash -1615547227, now seen corresponding path program 1 times [2021-12-19 19:17:42,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:42,623 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093948328] [2021-12-19 19:17:42,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:42,624 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:42,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:42,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:42,644 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:42,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093948328] [2021-12-19 19:17:42,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093948328] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:42,645 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:42,645 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:42,645 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804173790] [2021-12-19 19:17:42,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:42,645 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:42,645 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:42,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-19 19:17:42,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-19 19:17:42,646 INFO L87 Difference]: Start difference. First operand 40924 states and 59405 transitions. cyclomatic complexity: 18513 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:43,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:43,276 INFO L93 Difference]: Finished difference Result 114435 states and 166070 transitions. [2021-12-19 19:17:43,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-19 19:17:43,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114435 states and 166070 transitions. [2021-12-19 19:17:43,726 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 113620 [2021-12-19 19:17:44,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114435 states to 114435 states and 166070 transitions. [2021-12-19 19:17:44,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114435 [2021-12-19 19:17:44,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114435 [2021-12-19 19:17:44,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114435 states and 166070 transitions. [2021-12-19 19:17:44,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:44,274 INFO L681 BuchiCegarLoop]: Abstraction has 114435 states and 166070 transitions. [2021-12-19 19:17:44,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114435 states and 166070 transitions. [2021-12-19 19:17:44,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114435 to 42043. [2021-12-19 19:17:44,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42043 states, 42043 states have (on average 1.4395737697119615) internal successors, (60524), 42042 states have internal predecessors, (60524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:45,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42043 states to 42043 states and 60524 transitions. [2021-12-19 19:17:45,007 INFO L704 BuchiCegarLoop]: Abstraction has 42043 states and 60524 transitions. [2021-12-19 19:17:45,007 INFO L587 BuchiCegarLoop]: Abstraction has 42043 states and 60524 transitions. [2021-12-19 19:17:45,007 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-19 19:17:45,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42043 states and 60524 transitions. [2021-12-19 19:17:45,220 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41728 [2021-12-19 19:17:45,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:45,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:45,222 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,222 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:45,222 INFO L791 eck$LassoCheckResult]: Stem: 323910#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 323911#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 324959#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 324288#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 324068#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 324069#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 324160#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 324508#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 324661#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 324662#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 323342#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 323343#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 324581#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 323955#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 323956#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 323861#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 323862#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 324283#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 323592#L1174 assume !(0 == ~M_E~0); 323593#L1174-2 assume !(0 == ~T1_E~0); 323441#L1179-1 assume !(0 == ~T2_E~0); 323340#L1184-1 assume !(0 == ~T3_E~0); 323341#L1189-1 assume !(0 == ~T4_E~0); 323380#L1194-1 assume !(0 == ~T5_E~0); 323484#L1199-1 assume !(0 == ~T6_E~0); 324437#L1204-1 assume !(0 == ~T7_E~0); 324348#L1209-1 assume !(0 == ~T8_E~0); 324349#L1214-1 assume !(0 == ~T9_E~0); 324833#L1219-1 assume !(0 == ~T10_E~0); 325004#L1224-1 assume !(0 == ~T11_E~0); 323716#L1229-1 assume !(0 == ~T12_E~0); 323268#L1234-1 assume !(0 == ~E_1~0); 323269#L1239-1 assume !(0 == ~E_2~0); 323302#L1244-1 assume !(0 == ~E_3~0); 323303#L1249-1 assume !(0 == ~E_4~0); 323983#L1254-1 assume !(0 == ~E_5~0); 323199#L1259-1 assume !(0 == ~E_6~0); 323157#L1264-1 assume !(0 == ~E_7~0); 323158#L1269-1 assume !(0 == ~E_8~0); 325032#L1274-1 assume !(0 == ~E_9~0); 324878#L1279-1 assume !(0 == ~E_10~0); 323384#L1284-1 assume !(0 == ~E_11~0); 323385#L1289-1 assume !(0 == ~E_12~0); 324037#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 324038#L566 assume !(1 == ~m_pc~0); 324502#L566-2 is_master_triggered_~__retres1~0#1 := 0; 324503#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 324378#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 324379#L1455 assume !(0 != activate_threads_~tmp~1#1); 323619#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323620#L585 assume !(1 == ~t1_pc~0); 323805#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 323806#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 324312#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 324313#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 324920#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 324917#L604 assume !(1 == ~t2_pc~0); 324400#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 324401#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 324894#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 324798#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 324616#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324617#L623 assume 1 == ~t3_pc~0; 323804#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 323137#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323959#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 323960#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 324653#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323171#L642 assume !(1 == ~t4_pc~0); 323172#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 323636#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323637#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 323242#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 323243#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 324413#L661 assume 1 == ~t5_pc~0; 323404#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 323405#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323363#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 323364#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 324449#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 324450#L680 assume !(1 == ~t6_pc~0); 323839#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 323840#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324114#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 324115#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 324738#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 324915#L699 assume 1 == ~t7_pc~0; 324254#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 324255#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323392#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 323393#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 324145#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 324039#L718 assume !(1 == ~t8_pc~0); 324040#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 323378#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 323379#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 323424#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 323425#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 323559#L737 assume 1 == ~t9_pc~0; 324488#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 323701#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 324341#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 324342#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 323878#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 323879#L756 assume 1 == ~t10_pc~0; 324519#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 324136#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 323101#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 323102#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 323679#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 323680#L775 assume !(1 == ~t11_pc~0); 323942#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 323943#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 323556#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 323312#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 323313#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 323504#L794 assume 1 == ~t12_pc~0; 323339#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 323317#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 324608#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 323469#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 323470#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323962#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 323963#L1307-2 assume !(1 == ~T1_E~0); 324080#L1312-1 assume !(1 == ~T2_E~0); 323997#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 323998#L1322-1 assume !(1 == ~T4_E~0); 324220#L1327-1 assume !(1 == ~T5_E~0); 324259#L1332-1 assume !(1 == ~T6_E~0); 324260#L1337-1 assume !(1 == ~T7_E~0); 324933#L1342-1 assume !(1 == ~T8_E~0); 330188#L1347-1 assume !(1 == ~T9_E~0); 330186#L1352-1 assume !(1 == ~T10_E~0); 330184#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 330182#L1362-1 assume !(1 == ~T12_E~0); 330180#L1367-1 assume !(1 == ~E_1~0); 330178#L1372-1 assume !(1 == ~E_2~0); 330175#L1377-1 assume !(1 == ~E_3~0); 330173#L1382-1 assume !(1 == ~E_4~0); 329996#L1387-1 assume !(1 == ~E_5~0); 329867#L1392-1 assume !(1 == ~E_6~0); 329623#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 329621#L1402-1 assume !(1 == ~E_8~0); 329618#L1407-1 assume !(1 == ~E_9~0); 329476#L1412-1 assume !(1 == ~E_10~0); 329384#L1417-1 assume !(1 == ~E_11~0); 329382#L1422-1 assume !(1 == ~E_12~0); 329342#L1427-1 assume { :end_inline_reset_delta_events } true; 329331#L1768-2 [2021-12-19 19:17:45,222 INFO L793 eck$LassoCheckResult]: Loop: 329331#L1768-2 assume !false; 329323#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 329318#L1149 assume !false; 329316#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 329278#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 329271#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 329269#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 329266#L976 assume !(0 != eval_~tmp~0#1); 329267#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 332149#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 332147#L1174-3 assume !(0 == ~M_E~0); 332145#L1174-5 assume !(0 == ~T1_E~0); 332143#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 332141#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 332139#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 332136#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 332134#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 332132#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 332130#L1209-3 assume !(0 == ~T8_E~0); 332128#L1214-3 assume !(0 == ~T9_E~0); 332127#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 332123#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 332121#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 332119#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 332118#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 332113#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 332108#L1249-3 assume !(0 == ~E_4~0); 332107#L1254-3 assume !(0 == ~E_5~0); 332106#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 332105#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 332104#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 332103#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 332102#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 332101#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 332100#L1289-3 assume !(0 == ~E_12~0); 332099#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332098#L566-39 assume !(1 == ~m_pc~0); 332097#L566-41 is_master_triggered_~__retres1~0#1 := 0; 332096#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 332095#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 332094#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 332093#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332092#L585-39 assume !(1 == ~t1_pc~0); 332091#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 332090#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 332089#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 332088#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 332087#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 332086#L604-39 assume !(1 == ~t2_pc~0); 332085#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 332083#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 332081#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 332079#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 332077#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 332076#L623-39 assume 1 == ~t3_pc~0; 332075#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 332073#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 332072#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 332071#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 332070#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 332056#L642-39 assume 1 == ~t4_pc~0; 332053#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 332051#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 332049#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 332047#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 332045#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332043#L661-39 assume 1 == ~t5_pc~0; 332041#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 332039#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 332033#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 332031#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 332029#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 332028#L680-39 assume !(1 == ~t6_pc~0); 332027#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 331734#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 331457#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 331454#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 331452#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 331450#L699-39 assume !(1 == ~t7_pc~0); 331447#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 331445#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 331443#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 331440#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 331438#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 331436#L718-39 assume !(1 == ~t8_pc~0); 331265#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 331262#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 331260#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 331259#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 331222#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 331219#L737-39 assume !(1 == ~t9_pc~0); 331159#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 331156#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 331154#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 331152#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 331150#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 331147#L756-39 assume 1 == ~t10_pc~0; 331145#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 331142#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 331140#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 331138#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 331136#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 331135#L775-39 assume !(1 == ~t11_pc~0); 330963#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 330959#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 330957#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 330955#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 330898#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 330895#L794-39 assume 1 == ~t12_pc~0; 330893#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 330890#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 330888#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 330886#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 330884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 330882#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 328072#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 328068#L1312-3 assume !(1 == ~T2_E~0); 330877#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 330764#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 330648#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 330646#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 330556#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 330480#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 330477#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 330268#L1352-3 assume !(1 == ~T10_E~0); 330267#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 330145#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 330143#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 330142#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 330005#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 330003#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 329887#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 329882#L1392-3 assume !(1 == ~E_6~0); 329768#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 329765#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 329629#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 329627#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 329626#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 329624#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 329524#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 329425#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 329412#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 329410#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 329408#L1787 assume !(0 == start_simulation_~tmp~3#1); 324647#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 329361#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 329353#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 329351#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 329349#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 329347#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329345#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 329343#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 329331#L1768-2 [2021-12-19 19:17:45,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,223 INFO L85 PathProgramCache]: Analyzing trace with hash 30140183, now seen corresponding path program 1 times [2021-12-19 19:17:45,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828396544] [2021-12-19 19:17:45,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,224 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:45,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:45,246 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:45,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828396544] [2021-12-19 19:17:45,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828396544] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:45,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:45,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:45,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351613281] [2021-12-19 19:17:45,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:45,247 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:45,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:45,247 INFO L85 PathProgramCache]: Analyzing trace with hash 27770721, now seen corresponding path program 1 times [2021-12-19 19:17:45,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:45,247 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487003750] [2021-12-19 19:17:45,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:45,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:45,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:45,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:45,267 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:45,267 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487003750] [2021-12-19 19:17:45,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487003750] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:45,267 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:45,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:45,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860200056] [2021-12-19 19:17:45,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:45,268 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:45,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:45,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:45,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:45,268 INFO L87 Difference]: Start difference. First operand 42043 states and 60524 transitions. cyclomatic complexity: 18513 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:45,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:45,754 INFO L93 Difference]: Finished difference Result 100959 states and 144474 transitions. [2021-12-19 19:17:45,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:45,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100959 states and 144474 transitions. [2021-12-19 19:17:46,231 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 100469 [2021-12-19 19:17:46,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100959 states to 100959 states and 144474 transitions. [2021-12-19 19:17:46,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100959 [2021-12-19 19:17:46,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100959 [2021-12-19 19:17:46,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100959 states and 144474 transitions. [2021-12-19 19:17:46,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:46,814 INFO L681 BuchiCegarLoop]: Abstraction has 100959 states and 144474 transitions. [2021-12-19 19:17:46,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100959 states and 144474 transitions. [2021-12-19 19:17:47,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100959 to 80342. [2021-12-19 19:17:47,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80342 states, 80342 states have (on average 1.4341813746234846) internal successors, (115225), 80341 states have internal predecessors, (115225), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:47,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80342 states to 80342 states and 115225 transitions. [2021-12-19 19:17:47,819 INFO L704 BuchiCegarLoop]: Abstraction has 80342 states and 115225 transitions. [2021-12-19 19:17:47,819 INFO L587 BuchiCegarLoop]: Abstraction has 80342 states and 115225 transitions. [2021-12-19 19:17:47,819 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-19 19:17:47,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80342 states and 115225 transitions. [2021-12-19 19:17:47,999 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79980 [2021-12-19 19:17:47,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:47,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:48,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:48,001 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:48,002 INFO L791 eck$LassoCheckResult]: Stem: 466921#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 466922#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 467924#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 467298#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 467085#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 467086#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 467180#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 467509#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 467662#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 467663#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 466352#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 466353#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 467581#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 466969#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 466970#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 466872#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 466873#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 467294#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 466602#L1174 assume !(0 == ~M_E~0); 466603#L1174-2 assume !(0 == ~T1_E~0); 466450#L1179-1 assume !(0 == ~T2_E~0); 466350#L1184-1 assume !(0 == ~T3_E~0); 466351#L1189-1 assume !(0 == ~T4_E~0); 466388#L1194-1 assume !(0 == ~T5_E~0); 466493#L1199-1 assume !(0 == ~T6_E~0); 467446#L1204-1 assume !(0 == ~T7_E~0); 467359#L1209-1 assume !(0 == ~T8_E~0); 467360#L1214-1 assume !(0 == ~T9_E~0); 467816#L1219-1 assume !(0 == ~T10_E~0); 467962#L1224-1 assume !(0 == ~T11_E~0); 466726#L1229-1 assume !(0 == ~T12_E~0); 466275#L1234-1 assume !(0 == ~E_1~0); 466276#L1239-1 assume !(0 == ~E_2~0); 466309#L1244-1 assume !(0 == ~E_3~0); 466310#L1249-1 assume !(0 == ~E_4~0); 466997#L1254-1 assume !(0 == ~E_5~0); 466208#L1259-1 assume !(0 == ~E_6~0); 466167#L1264-1 assume !(0 == ~E_7~0); 466168#L1269-1 assume !(0 == ~E_8~0); 467988#L1274-1 assume !(0 == ~E_9~0); 467849#L1279-1 assume !(0 == ~E_10~0); 466392#L1284-1 assume !(0 == ~E_11~0); 466393#L1289-1 assume !(0 == ~E_12~0); 467052#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 467053#L566 assume !(1 == ~m_pc~0); 467506#L566-2 is_master_triggered_~__retres1~0#1 := 0; 467507#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 467388#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 467389#L1455 assume !(0 != activate_threads_~tmp~1#1); 466629#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 466630#L585 assume !(1 == ~t1_pc~0); 466818#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 466819#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 467324#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 467325#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 467892#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 467886#L604 assume !(1 == ~t2_pc~0); 467410#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 467411#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 466904#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 466905#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 467615#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 467616#L623 assume !(1 == ~t3_pc~0); 466147#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 466148#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 466973#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 466974#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 467658#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 466181#L642 assume !(1 == ~t4_pc~0); 466182#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 466649#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 466650#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 466249#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 466250#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 467424#L661 assume 1 == ~t5_pc~0; 466412#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 466413#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 466373#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 466374#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 467457#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 467458#L680 assume !(1 == ~t6_pc~0); 466852#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 466853#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 467133#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 467134#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 467729#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 467883#L699 assume 1 == ~t7_pc~0; 467274#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 467275#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 466400#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 466401#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 467165#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 467054#L718 assume !(1 == ~t8_pc~0); 467055#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 466386#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 466387#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 466430#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 466431#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 466567#L737 assume 1 == ~t9_pc~0; 467493#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 466711#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 467351#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 467352#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 466890#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 466891#L756 assume 1 == ~t10_pc~0; 467522#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 467157#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 466113#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 466114#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 466691#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 466692#L775 assume !(1 == ~t11_pc~0); 466956#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 466957#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 466561#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 466321#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 466322#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 466511#L794 assume 1 == ~t12_pc~0; 466348#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 466326#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 467606#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 466477#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 466478#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 466977#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 466978#L1307-2 assume !(1 == ~T1_E~0); 467099#L1312-1 assume !(1 == ~T2_E~0); 467012#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 467013#L1322-1 assume !(1 == ~T4_E~0); 466701#L1327-1 assume !(1 == ~T5_E~0); 466702#L1332-1 assume !(1 == ~T6_E~0); 467898#L1337-1 assume !(1 == ~T7_E~0); 467899#L1342-1 assume !(1 == ~T8_E~0); 467846#L1347-1 assume !(1 == ~T9_E~0); 467847#L1352-1 assume !(1 == ~T10_E~0); 500043#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 500042#L1362-1 assume !(1 == ~T12_E~0); 500041#L1367-1 assume !(1 == ~E_1~0); 500040#L1372-1 assume !(1 == ~E_2~0); 500039#L1377-1 assume !(1 == ~E_3~0); 500038#L1382-1 assume !(1 == ~E_4~0); 500037#L1387-1 assume !(1 == ~E_5~0); 497114#L1392-1 assume !(1 == ~E_6~0); 500036#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 500035#L1402-1 assume !(1 == ~E_8~0); 500034#L1407-1 assume !(1 == ~E_9~0); 500033#L1412-1 assume !(1 == ~E_10~0); 500032#L1417-1 assume !(1 == ~E_11~0); 500031#L1422-1 assume !(1 == ~E_12~0); 500029#L1427-1 assume { :end_inline_reset_delta_events } true; 500027#L1768-2 [2021-12-19 19:17:48,002 INFO L793 eck$LassoCheckResult]: Loop: 500027#L1768-2 assume !false; 497009#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 497005#L1149 assume !false; 496507#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 496217#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 496202#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 496197#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 496189#L976 assume !(0 != eval_~tmp~0#1); 496190#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 500589#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 500587#L1174-3 assume !(0 == ~M_E~0); 500585#L1174-5 assume !(0 == ~T1_E~0); 500582#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 500580#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 500578#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 500577#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 500575#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 500573#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 500571#L1209-3 assume !(0 == ~T8_E~0); 500569#L1214-3 assume !(0 == ~T9_E~0); 500567#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 500564#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 500562#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 500560#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 500558#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 500556#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 500554#L1249-3 assume !(0 == ~E_4~0); 500551#L1254-3 assume !(0 == ~E_5~0); 500549#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 500547#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 500545#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 500543#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 500541#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 500538#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 500536#L1289-3 assume !(0 == ~E_12~0); 500534#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 500532#L566-39 assume !(1 == ~m_pc~0); 500530#L566-41 is_master_triggered_~__retres1~0#1 := 0; 500528#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 500525#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 500523#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 500521#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 500519#L585-39 assume !(1 == ~t1_pc~0); 500517#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 500515#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 500512#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500510#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 500508#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 500506#L604-39 assume !(1 == ~t2_pc~0); 500502#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 500500#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 500497#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 500495#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 500492#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 500490#L623-39 assume !(1 == ~t3_pc~0); 476058#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 500487#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 500484#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500482#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 500480#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 500478#L642-39 assume !(1 == ~t4_pc~0); 500476#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 500473#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 500470#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 500468#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 500466#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 500464#L661-39 assume 1 == ~t5_pc~0; 500462#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 500459#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 500456#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 500454#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 500452#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 500450#L680-39 assume !(1 == ~t6_pc~0); 500448#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 500445#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 500444#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 500443#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 500442#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 500440#L699-39 assume 1 == ~t7_pc~0; 500438#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 500436#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 500435#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 500434#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 500432#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 500431#L718-39 assume !(1 == ~t8_pc~0); 500430#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 500428#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 500427#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 500426#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 500425#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 500423#L737-39 assume !(1 == ~t9_pc~0); 500421#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 500418#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 500416#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 500414#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 500412#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 500410#L756-39 assume !(1 == ~t10_pc~0); 500407#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 500405#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 500403#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 500401#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 500399#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 500398#L775-39 assume !(1 == ~t11_pc~0); 500394#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 500391#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 500389#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 500387#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 500384#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 500382#L794-39 assume 1 == ~t12_pc~0; 500380#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 500378#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 500376#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 500374#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 500372#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 500370#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 497338#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 500362#L1312-3 assume !(1 == ~T2_E~0); 500360#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 500358#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 500356#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 500354#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 500352#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 500349#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 500347#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 500343#L1352-3 assume !(1 == ~T10_E~0); 500341#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 500339#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 500337#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 500334#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 500332#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 500330#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 500328#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 497293#L1392-3 assume !(1 == ~E_6~0); 500325#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 500322#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 500320#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 500318#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 500316#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 500314#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 500312#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 500306#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 500293#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 500291#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 500289#L1787 assume !(0 == start_simulation_~tmp~3#1); 500285#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 500268#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 500260#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 500258#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 500255#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 500253#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 500046#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 500030#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 500027#L1768-2 [2021-12-19 19:17:48,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:48,003 INFO L85 PathProgramCache]: Analyzing trace with hash 952060534, now seen corresponding path program 1 times [2021-12-19 19:17:48,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:48,003 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301734992] [2021-12-19 19:17:48,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:48,003 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:48,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:48,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:48,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:48,026 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301734992] [2021-12-19 19:17:48,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301734992] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:48,026 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:48,026 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:48,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949222498] [2021-12-19 19:17:48,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:48,027 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:48,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:48,027 INFO L85 PathProgramCache]: Analyzing trace with hash -832358881, now seen corresponding path program 1 times [2021-12-19 19:17:48,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:48,028 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875487453] [2021-12-19 19:17:48,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:48,028 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:48,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:48,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:48,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:48,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875487453] [2021-12-19 19:17:48,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875487453] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:48,048 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:48,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:48,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653883133] [2021-12-19 19:17:48,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:48,049 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:48,049 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:48,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:48,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:48,050 INFO L87 Difference]: Start difference. First operand 80342 states and 115225 transitions. cyclomatic complexity: 34915 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:48,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:48,759 INFO L93 Difference]: Finished difference Result 192177 states and 274126 transitions. [2021-12-19 19:17:48,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:48,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192177 states and 274126 transitions. [2021-12-19 19:17:49,743 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 191464 [2021-12-19 19:17:50,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192177 states to 192177 states and 274126 transitions. [2021-12-19 19:17:50,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192177 [2021-12-19 19:17:50,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192177 [2021-12-19 19:17:50,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192177 states and 274126 transitions. [2021-12-19 19:17:50,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:50,261 INFO L681 BuchiCegarLoop]: Abstraction has 192177 states and 274126 transitions. [2021-12-19 19:17:50,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192177 states and 274126 transitions. [2021-12-19 19:17:51,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192177 to 153529. [2021-12-19 19:17:51,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153529 states, 153529 states have (on average 1.4293716496557654) internal successors, (219450), 153528 states have internal predecessors, (219450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:52,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153529 states to 153529 states and 219450 transitions. [2021-12-19 19:17:52,056 INFO L704 BuchiCegarLoop]: Abstraction has 153529 states and 219450 transitions. [2021-12-19 19:17:52,056 INFO L587 BuchiCegarLoop]: Abstraction has 153529 states and 219450 transitions. [2021-12-19 19:17:52,056 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-19 19:17:52,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 153529 states and 219450 transitions. [2021-12-19 19:17:52,764 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 153072 [2021-12-19 19:17:52,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:17:52,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:17:52,768 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:52,768 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:17:52,768 INFO L791 eck$LassoCheckResult]: Stem: 739447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 739448#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 740497#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 739827#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 739615#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 739616#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 739707#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 740047#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 740200#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 740201#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 738880#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 738881#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 740118#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 739496#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 739497#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 739395#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 739396#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 739823#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 739129#L1174 assume !(0 == ~M_E~0); 739130#L1174-2 assume !(0 == ~T1_E~0); 738975#L1179-1 assume !(0 == ~T2_E~0); 738878#L1184-1 assume !(0 == ~T3_E~0); 738879#L1189-1 assume !(0 == ~T4_E~0); 738918#L1194-1 assume !(0 == ~T5_E~0); 739019#L1199-1 assume !(0 == ~T6_E~0); 739982#L1204-1 assume !(0 == ~T7_E~0); 739892#L1209-1 assume !(0 == ~T8_E~0); 739893#L1214-1 assume !(0 == ~T9_E~0); 740376#L1219-1 assume !(0 == ~T10_E~0); 740528#L1224-1 assume !(0 == ~T11_E~0); 739251#L1229-1 assume !(0 == ~T12_E~0); 738804#L1234-1 assume !(0 == ~E_1~0); 738805#L1239-1 assume !(0 == ~E_2~0); 738838#L1244-1 assume !(0 == ~E_3~0); 738839#L1249-1 assume !(0 == ~E_4~0); 739526#L1254-1 assume !(0 == ~E_5~0); 738737#L1259-1 assume !(0 == ~E_6~0); 738696#L1264-1 assume !(0 == ~E_7~0); 738697#L1269-1 assume !(0 == ~E_8~0); 740554#L1274-1 assume !(0 == ~E_9~0); 740421#L1279-1 assume !(0 == ~E_10~0); 738921#L1284-1 assume !(0 == ~E_11~0); 738922#L1289-1 assume !(0 == ~E_12~0); 739581#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 739582#L566 assume !(1 == ~m_pc~0); 740044#L566-2 is_master_triggered_~__retres1~0#1 := 0; 740045#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 739923#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 739924#L1455 assume !(0 != activate_threads_~tmp~1#1); 739156#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 739157#L585 assume !(1 == ~t1_pc~0); 739341#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 739342#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 739856#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 739857#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 740466#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 740463#L604 assume !(1 == ~t2_pc~0); 739942#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 739943#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 739431#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 739432#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 740152#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 740153#L623 assume !(1 == ~t3_pc~0); 738676#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 738677#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 739500#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 739501#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 740193#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 738710#L642 assume !(1 == ~t4_pc~0); 738711#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 739175#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 739176#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 738778#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 738779#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 739957#L661 assume !(1 == ~t5_pc~0); 740122#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 739846#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 738901#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 738902#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 739991#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 739992#L680 assume !(1 == ~t6_pc~0); 739376#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 739377#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 739659#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 739660#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 740279#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 740461#L699 assume 1 == ~t7_pc~0; 739800#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 739801#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 738929#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 738930#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 739693#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 739583#L718 assume !(1 == ~t8_pc~0); 739584#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 738916#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 738917#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 738956#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 738957#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 739095#L737 assume 1 == ~t9_pc~0; 740031#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 739236#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 739884#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 739885#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 739416#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 739417#L756 assume 1 == ~t10_pc~0; 740058#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 739683#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 738642#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 738643#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 739218#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 739219#L775 assume !(1 == ~t11_pc~0); 739484#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 739485#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 739089#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 738850#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 738851#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 739037#L794 assume 1 == ~t12_pc~0; 738876#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 738855#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 740147#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 739003#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 739004#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 739503#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 739504#L1307-2 assume !(1 == ~T1_E~0); 739628#L1312-1 assume !(1 == ~T2_E~0); 739540#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 739541#L1322-1 assume !(1 == ~T4_E~0); 739227#L1327-1 assume !(1 == ~T5_E~0); 739228#L1332-1 assume !(1 == ~T6_E~0); 739805#L1337-1 assume !(1 == ~T7_E~0); 739760#L1342-1 assume !(1 == ~T8_E~0); 739761#L1347-1 assume !(1 == ~T9_E~0); 766157#L1352-1 assume !(1 == ~T10_E~0); 766155#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 766153#L1362-1 assume !(1 == ~T12_E~0); 766150#L1367-1 assume !(1 == ~E_1~0); 766148#L1372-1 assume !(1 == ~E_2~0); 766146#L1377-1 assume !(1 == ~E_3~0); 766144#L1382-1 assume !(1 == ~E_4~0); 766142#L1387-1 assume !(1 == ~E_5~0); 764224#L1392-1 assume !(1 == ~E_6~0); 766138#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 766136#L1402-1 assume !(1 == ~E_8~0); 766134#L1407-1 assume !(1 == ~E_9~0); 766133#L1412-1 assume !(1 == ~E_10~0); 766128#L1417-1 assume !(1 == ~E_11~0); 766123#L1422-1 assume !(1 == ~E_12~0); 764559#L1427-1 assume { :end_inline_reset_delta_events } true; 764557#L1768-2 [2021-12-19 19:17:52,769 INFO L793 eck$LassoCheckResult]: Loop: 764557#L1768-2 assume !false; 764393#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 764388#L1149 assume !false; 764386#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 764192#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 764185#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 764183#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 763852#L976 assume !(0 != eval_~tmp~0#1); 763853#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 775721#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 775716#L1174-3 assume !(0 == ~M_E~0); 775712#L1174-5 assume !(0 == ~T1_E~0); 775708#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 775703#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 775697#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 775691#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 775685#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 775679#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 775673#L1209-3 assume !(0 == ~T8_E~0); 775667#L1214-3 assume !(0 == ~T9_E~0); 775663#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 775657#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 775651#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 775646#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 775641#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 775637#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 775631#L1249-3 assume !(0 == ~E_4~0); 775626#L1254-3 assume !(0 == ~E_5~0); 775619#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 775613#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 775608#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 775603#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 775596#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 775592#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 775589#L1289-3 assume !(0 == ~E_12~0); 775585#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 775579#L566-39 assume !(1 == ~m_pc~0); 775572#L566-41 is_master_triggered_~__retres1~0#1 := 0; 775562#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 775554#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 775545#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 775538#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 775531#L585-39 assume !(1 == ~t1_pc~0); 775524#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 775516#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 775507#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 775497#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 775489#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 775483#L604-39 assume 1 == ~t2_pc~0; 775475#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 775466#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 775458#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 775399#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 775391#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 764814#L623-39 assume !(1 == ~t3_pc~0); 764812#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 764810#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 764808#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 764806#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 764804#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 764802#L642-39 assume !(1 == ~t4_pc~0); 764799#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 764796#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 764794#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 764792#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 764790#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 764788#L661-39 assume !(1 == ~t5_pc~0); 746536#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 764786#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 764784#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 764782#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 764780#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 764778#L680-39 assume !(1 == ~t6_pc~0); 764775#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 764772#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 764770#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 764768#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 764766#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 764764#L699-39 assume 1 == ~t7_pc~0; 764761#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 764758#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 764756#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 764754#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 764752#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 764750#L718-39 assume !(1 == ~t8_pc~0); 764747#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 764744#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 764742#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 764740#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 764738#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 764736#L737-39 assume !(1 == ~t9_pc~0); 764733#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 764730#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 764728#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 764726#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 764724#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 764722#L756-39 assume 1 == ~t10_pc~0; 764719#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 764716#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 764714#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 764712#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 764710#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 764708#L775-39 assume !(1 == ~t11_pc~0); 764705#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 764702#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 764700#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 764698#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 764696#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 764694#L794-39 assume 1 == ~t12_pc~0; 764691#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 764688#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 764686#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 764684#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 764682#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 764680#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 762143#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 764672#L1312-3 assume !(1 == ~T2_E~0); 764670#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 764668#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 764666#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 764664#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 764662#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 764660#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 764659#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 764656#L1352-3 assume !(1 == ~T10_E~0); 764655#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 764654#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 764653#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 764652#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 764638#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 764636#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 764634#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 764359#L1392-3 assume !(1 == ~E_6~0); 764630#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 764628#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 764626#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 764624#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 764622#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 764620#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 764618#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 764613#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 764600#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 764598#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 764596#L1787 assume !(0 == start_simulation_~tmp~3#1); 764593#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 764578#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 764570#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 764568#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 764566#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 764564#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 764562#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 764560#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 764557#L1768-2 [2021-12-19 19:17:52,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:52,769 INFO L85 PathProgramCache]: Analyzing trace with hash -1675787179, now seen corresponding path program 1 times [2021-12-19 19:17:52,770 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:52,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385032004] [2021-12-19 19:17:52,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:52,770 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:52,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:52,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:52,801 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:52,801 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385032004] [2021-12-19 19:17:52,801 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385032004] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:52,801 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:52,801 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:52,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494993033] [2021-12-19 19:17:52,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:52,802 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:17:52,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:17:52,802 INFO L85 PathProgramCache]: Analyzing trace with hash -578032766, now seen corresponding path program 1 times [2021-12-19 19:17:52,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:17:52,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618357786] [2021-12-19 19:17:52,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:17:52,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:17:52,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:17:52,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:17:52,827 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:17:52,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618357786] [2021-12-19 19:17:52,827 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618357786] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:17:52,827 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:17:52,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:17:52,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856269042] [2021-12-19 19:17:52,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:17:52,828 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:17:52,828 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:17:52,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:17:52,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:17:52,829 INFO L87 Difference]: Start difference. First operand 153529 states and 219450 transitions. cyclomatic complexity: 65953 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:17:54,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:17:54,313 INFO L93 Difference]: Finished difference Result 365300 states and 519539 transitions. [2021-12-19 19:17:54,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:17:54,316 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 365300 states and 519539 transitions. [2021-12-19 19:17:55,895 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 364140 [2021-12-19 19:17:56,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 365300 states to 365300 states and 519539 transitions. [2021-12-19 19:17:56,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 365300 [2021-12-19 19:17:57,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 365300 [2021-12-19 19:17:57,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 365300 states and 519539 transitions. [2021-12-19 19:17:57,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:17:57,110 INFO L681 BuchiCegarLoop]: Abstraction has 365300 states and 519539 transitions. [2021-12-19 19:17:57,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365300 states and 519539 transitions. [2021-12-19 19:17:59,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365300 to 293144. [2021-12-19 19:17:59,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 293144 states, 293144 states have (on average 1.4250163742051687) internal successors, (417735), 293143 states have internal predecessors, (417735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:00,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 293144 states to 293144 states and 417735 transitions. [2021-12-19 19:18:00,446 INFO L704 BuchiCegarLoop]: Abstraction has 293144 states and 417735 transitions. [2021-12-19 19:18:00,446 INFO L587 BuchiCegarLoop]: Abstraction has 293144 states and 417735 transitions. [2021-12-19 19:18:00,446 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-19 19:18:00,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 293144 states and 417735 transitions. [2021-12-19 19:18:01,716 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 292496 [2021-12-19 19:18:01,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-19 19:18:01,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-19 19:18:01,718 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,718 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-19 19:18:01,719 INFO L791 eck$LassoCheckResult]: Stem: 1258296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1258297#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1259315#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258674#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1258455#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1258456#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1258549#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1258901#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1259052#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1259053#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1257719#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1257720#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1258972#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1258341#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1258342#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1258245#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1258246#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1258669#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1257965#L1174 assume !(0 == ~M_E~0); 1257966#L1174-2 assume !(0 == ~T1_E~0); 1257814#L1179-1 assume !(0 == ~T2_E~0); 1257717#L1184-1 assume !(0 == ~T3_E~0); 1257718#L1189-1 assume !(0 == ~T4_E~0); 1257757#L1194-1 assume !(0 == ~T5_E~0); 1257855#L1199-1 assume !(0 == ~T6_E~0); 1258827#L1204-1 assume !(0 == ~T7_E~0); 1258739#L1209-1 assume !(0 == ~T8_E~0); 1258740#L1214-1 assume !(0 == ~T9_E~0); 1259216#L1219-1 assume !(0 == ~T10_E~0); 1259349#L1224-1 assume !(0 == ~T11_E~0); 1258092#L1229-1 assume !(0 == ~T12_E~0); 1257645#L1234-1 assume !(0 == ~E_1~0); 1257646#L1239-1 assume !(0 == ~E_2~0); 1257679#L1244-1 assume !(0 == ~E_3~0); 1257680#L1249-1 assume !(0 == ~E_4~0); 1258367#L1254-1 assume !(0 == ~E_5~0); 1257576#L1259-1 assume !(0 == ~E_6~0); 1257535#L1264-1 assume !(0 == ~E_7~0); 1257536#L1269-1 assume !(0 == ~E_8~0); 1259369#L1274-1 assume !(0 == ~E_9~0); 1259252#L1279-1 assume !(0 == ~E_10~0); 1257760#L1284-1 assume !(0 == ~E_11~0); 1257761#L1289-1 assume !(0 == ~E_12~0); 1258423#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1258424#L566 assume !(1 == ~m_pc~0); 1258895#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1258896#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1258769#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1258770#L1455 assume !(0 != activate_threads_~tmp~1#1); 1257992#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1257993#L585 assume !(1 == ~t1_pc~0); 1258185#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1258186#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1258701#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1258702#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1259288#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1259285#L604 assume !(1 == ~t2_pc~0); 1258790#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1258791#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1258278#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1258279#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1259004#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1259005#L623 assume !(1 == ~t3_pc~0); 1257515#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1257516#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1258345#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1258346#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1259048#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1257549#L642 assume !(1 == ~t4_pc~0); 1257550#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1258012#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1258013#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1257619#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1257620#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1258804#L661 assume !(1 == ~t5_pc~0); 1258977#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1258691#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1257740#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1257741#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1258838#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1258839#L680 assume !(1 == ~t6_pc~0); 1258223#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1258224#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1258501#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1258502#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1259130#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1259282#L699 assume !(1 == ~t7_pc~0); 1259283#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1258918#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1257768#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1257769#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1258535#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1258425#L718 assume !(1 == ~t8_pc~0); 1258426#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1257755#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1257756#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1257797#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1257798#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1257931#L737 assume 1 == ~t9_pc~0; 1258881#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1258076#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1258730#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1258731#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1258264#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1258265#L756 assume 1 == ~t10_pc~0; 1258908#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1258526#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1257481#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1257482#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1258057#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1258058#L775 assume !(1 == ~t11_pc~0); 1258329#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1258330#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1257928#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1257689#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1257690#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1257874#L794 assume 1 == ~t12_pc~0; 1257716#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1257694#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1258998#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1257842#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1257843#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1258348#L1307 assume 1 == ~M_E~0;~M_E~0 := 2; 1258349#L1307-2 assume !(1 == ~T1_E~0); 1258468#L1312-1 assume !(1 == ~T2_E~0); 1258382#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1258383#L1322-1 assume !(1 == ~T4_E~0); 1258066#L1327-1 assume !(1 == ~T5_E~0); 1258067#L1332-1 assume !(1 == ~T6_E~0); 1259295#L1337-1 assume !(1 == ~T7_E~0); 1259296#L1342-1 assume !(1 == ~T8_E~0); 1259250#L1347-1 assume !(1 == ~T9_E~0); 1259084#L1352-1 assume !(1 == ~T10_E~0); 1258919#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1258241#L1362-1 assume !(1 == ~T12_E~0); 1258242#L1367-1 assume !(1 == ~E_1~0); 1259146#L1372-1 assume !(1 == ~E_2~0); 1258393#L1377-1 assume !(1 == ~E_3~0); 1258394#L1382-1 assume !(1 == ~E_4~0); 1258792#L1387-1 assume !(1 == ~E_5~0); 1258793#L1392-1 assume !(1 == ~E_6~0); 1258191#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1258192#L1402-1 assume !(1 == ~E_8~0); 1257872#L1407-1 assume !(1 == ~E_9~0); 1257873#L1412-1 assume !(1 == ~E_10~0); 1259338#L1417-1 assume !(1 == ~E_11~0); 1259393#L1422-1 assume !(1 == ~E_12~0); 1259394#L1427-1 assume { :end_inline_reset_delta_events } true; 1315087#L1768-2 [2021-12-19 19:18:01,719 INFO L793 eck$LassoCheckResult]: Loop: 1315087#L1768-2 assume !false; 1315079#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1315073#L1149 assume !false; 1315071#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1315010#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1314997#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1314991#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1314983#L976 assume !(0 != eval_~tmp~0#1); 1314984#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1326199#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1326198#L1174-3 assume !(0 == ~M_E~0); 1326197#L1174-5 assume !(0 == ~T1_E~0); 1326196#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1326195#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1326194#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1326193#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1326192#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1326191#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1326190#L1209-3 assume !(0 == ~T8_E~0); 1326189#L1214-3 assume !(0 == ~T9_E~0); 1326188#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1326187#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1326186#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1326185#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1326184#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1326183#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1326182#L1249-3 assume !(0 == ~E_4~0); 1326181#L1254-3 assume !(0 == ~E_5~0); 1326180#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1326179#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1326178#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1326177#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1326176#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1326175#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1326174#L1289-3 assume !(0 == ~E_12~0); 1326172#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1326173#L566-39 assume !(1 == ~m_pc~0); 1410866#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1410862#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1410859#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1410855#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1410853#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1410851#L585-39 assume !(1 == ~t1_pc~0); 1326163#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1326162#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1326161#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1326160#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1326159#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1326158#L604-39 assume 1 == ~t2_pc~0; 1326156#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1326154#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1326152#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1326150#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1326149#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1326148#L623-39 assume !(1 == ~t3_pc~0); 1323845#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1326147#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1326146#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1326145#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1326144#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1326143#L642-39 assume 1 == ~t4_pc~0; 1326141#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1326140#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1326139#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1326109#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1325853#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1316615#L661-39 assume !(1 == ~t5_pc~0); 1316611#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1316607#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1316602#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1316598#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1316592#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1316588#L680-39 assume 1 == ~t6_pc~0; 1316583#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1316579#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1316574#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1316570#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1316568#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316564#L699-39 assume !(1 == ~t7_pc~0); 1280301#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1316555#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1316549#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316544#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1316537#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1316532#L718-39 assume 1 == ~t8_pc~0; 1316526#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1316520#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1316514#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1316509#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1316502#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1316497#L737-39 assume 1 == ~t9_pc~0; 1316490#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1316485#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1316478#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1316472#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1316464#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1316458#L756-39 assume 1 == ~t10_pc~0; 1316452#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1316443#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1316438#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1316434#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1316428#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1316423#L775-39 assume 1 == ~t11_pc~0; 1316416#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1316410#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1316404#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1316398#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1316391#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1316386#L794-39 assume 1 == ~t12_pc~0; 1316380#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1316371#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1316365#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1316359#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1316354#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316348#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1294592#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1315648#L1312-3 assume !(1 == ~T2_E~0); 1315638#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1315625#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1315614#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1315602#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1315592#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1315584#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1315575#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1302855#L1352-3 assume !(1 == ~T10_E~0); 1315559#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1315551#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1315543#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1315535#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1315526#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1315516#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1315507#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1311642#L1392-3 assume !(1 == ~E_6~0); 1315439#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1315435#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1315432#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1315428#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1315422#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1315417#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1315414#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1315318#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1315300#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1315296#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1315291#L1787 assume !(0 == start_simulation_~tmp~3#1); 1315289#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1315162#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1315147#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1315131#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1315127#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1315109#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1315100#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1315095#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1315087#L1768-2 [2021-12-19 19:18:01,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:01,720 INFO L85 PathProgramCache]: Analyzing trace with hash 143938740, now seen corresponding path program 1 times [2021-12-19 19:18:01,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:01,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799441807] [2021-12-19 19:18:01,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:01,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:01,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:01,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:01,753 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:01,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799441807] [2021-12-19 19:18:01,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799441807] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:01,755 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:01,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:01,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167187955] [2021-12-19 19:18:01,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:01,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-19 19:18:01,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-19 19:18:01,756 INFO L85 PathProgramCache]: Analyzing trace with hash -228513210, now seen corresponding path program 1 times [2021-12-19 19:18:01,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-19 19:18:01,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818951934] [2021-12-19 19:18:01,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-19 19:18:01,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-19 19:18:01,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-19 19:18:01,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-19 19:18:01,777 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-19 19:18:01,777 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818951934] [2021-12-19 19:18:01,778 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818951934] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-19 19:18:01,778 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-19 19:18:01,778 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-19 19:18:01,778 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349394253] [2021-12-19 19:18:01,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-19 19:18:01,778 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-19 19:18:01,778 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-19 19:18:01,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-19 19:18:01,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-19 19:18:01,779 INFO L87 Difference]: Start difference. First operand 293144 states and 417735 transitions. cyclomatic complexity: 124623 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-19 19:18:04,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-19 19:18:04,103 INFO L93 Difference]: Finished difference Result 693079 states and 983060 transitions. [2021-12-19 19:18:04,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-19 19:18:04,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693079 states and 983060 transitions. [2021-12-19 19:18:07,665 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 691024 [2021-12-19 19:18:09,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693079 states to 693079 states and 983060 transitions. [2021-12-19 19:18:09,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693079 [2021-12-19 19:18:09,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693079 [2021-12-19 19:18:09,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693079 states and 983060 transitions. [2021-12-19 19:18:10,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-19 19:18:10,069 INFO L681 BuchiCegarLoop]: Abstraction has 693079 states and 983060 transitions. [2021-12-19 19:18:10,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693079 states and 983060 transitions.