./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version ff03de63 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-ff03de6 [2021-12-21 22:38:17,049 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-21 22:38:17,050 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-21 22:38:17,083 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-21 22:38:17,084 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-21 22:38:17,090 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-21 22:38:17,091 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-21 22:38:17,097 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-21 22:38:17,099 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-21 22:38:17,102 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-21 22:38:17,102 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-21 22:38:17,103 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-21 22:38:17,104 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-21 22:38:17,106 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-21 22:38:17,107 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-21 22:38:17,109 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-21 22:38:17,110 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-21 22:38:17,110 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-21 22:38:17,112 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-21 22:38:17,116 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-21 22:38:17,117 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-21 22:38:17,118 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-21 22:38:17,119 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-21 22:38:17,119 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-21 22:38:17,124 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-21 22:38:17,124 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-21 22:38:17,124 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-21 22:38:17,125 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-21 22:38:17,126 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-21 22:38:17,126 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-21 22:38:17,126 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-21 22:38:17,127 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-21 22:38:17,128 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-21 22:38:17,129 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-21 22:38:17,130 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-21 22:38:17,130 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-21 22:38:17,131 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-21 22:38:17,131 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-21 22:38:17,131 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-21 22:38:17,131 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-21 22:38:17,132 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-21 22:38:17,134 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-21 22:38:17,161 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-21 22:38:17,161 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-21 22:38:17,162 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-21 22:38:17,162 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-21 22:38:17,163 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-21 22:38:17,163 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-21 22:38:17,163 INFO L138 SettingsManager]: * Use SBE=true [2021-12-21 22:38:17,163 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-21 22:38:17,163 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-21 22:38:17,163 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-21 22:38:17,164 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-21 22:38:17,164 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-21 22:38:17,164 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-21 22:38:17,164 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-21 22:38:17,165 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-21 22:38:17,166 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-21 22:38:17,166 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-21 22:38:17,167 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-21 22:38:17,167 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-21 22:38:17,167 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-21 22:38:17,168 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-21 22:38:17,168 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2021-12-21 22:38:17,382 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-21 22:38:17,406 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-21 22:38:17,408 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-21 22:38:17,409 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-21 22:38:17,409 INFO L275 PluginConnector]: CDTParser initialized [2021-12-21 22:38:17,410 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-12-21 22:38:17,461 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2132dc691/176980fe6b0f477ba166b3c6a1fd80b4/FLAG813d85c05 [2021-12-21 22:38:17,848 INFO L306 CDTParser]: Found 1 translation units. [2021-12-21 22:38:17,848 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-12-21 22:38:17,869 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2132dc691/176980fe6b0f477ba166b3c6a1fd80b4/FLAG813d85c05 [2021-12-21 22:38:18,220 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2132dc691/176980fe6b0f477ba166b3c6a1fd80b4 [2021-12-21 22:38:18,223 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-21 22:38:18,225 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-21 22:38:18,228 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-21 22:38:18,228 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-21 22:38:18,230 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-21 22:38:18,231 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,232 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@354d50a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18, skipping insertion in model container [2021-12-21 22:38:18,233 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,238 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-21 22:38:18,260 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-21 22:38:18,380 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2021-12-21 22:38:18,435 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-21 22:38:18,440 INFO L203 MainTranslator]: Completed pre-run [2021-12-21 22:38:18,450 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2021-12-21 22:38:18,469 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-21 22:38:18,480 INFO L208 MainTranslator]: Completed translation [2021-12-21 22:38:18,480 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18 WrapperNode [2021-12-21 22:38:18,480 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-21 22:38:18,481 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-21 22:38:18,481 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-21 22:38:18,481 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-21 22:38:18,485 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,490 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,513 INFO L137 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 62, statements flattened = 813 [2021-12-21 22:38:18,514 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-21 22:38:18,514 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-21 22:38:18,514 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-21 22:38:18,514 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-21 22:38:18,519 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,520 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,523 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,523 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,530 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,537 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,543 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,547 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-21 22:38:18,547 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-21 22:38:18,547 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-21 22:38:18,547 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-21 22:38:18,548 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (1/1) ... [2021-12-21 22:38:18,553 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-21 22:38:18,562 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-21 22:38:18,572 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-21 22:38:18,622 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-21 22:38:18,638 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-21 22:38:18,638 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-21 22:38:18,638 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-21 22:38:18,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-21 22:38:18,692 INFO L234 CfgBuilder]: Building ICFG [2021-12-21 22:38:18,693 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-21 22:38:19,094 INFO L275 CfgBuilder]: Performing block encoding [2021-12-21 22:38:19,102 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-21 22:38:19,102 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2021-12-21 22:38:19,104 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.12 10:38:19 BoogieIcfgContainer [2021-12-21 22:38:19,104 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-21 22:38:19,104 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-21 22:38:19,105 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-21 22:38:19,107 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-21 22:38:19,108 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:19,108 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.12 10:38:18" (1/3) ... [2021-12-21 22:38:19,109 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@168f37e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.12 10:38:19, skipping insertion in model container [2021-12-21 22:38:19,109 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:19,109 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:18" (2/3) ... [2021-12-21 22:38:19,109 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@168f37e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.12 10:38:19, skipping insertion in model container [2021-12-21 22:38:19,110 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:19,110 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.12 10:38:19" (3/3) ... [2021-12-21 22:38:19,111 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2021-12-21 22:38:19,166 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-21 22:38:19,166 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-21 22:38:19,166 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-21 22:38:19,166 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-21 22:38:19,166 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-21 22:38:19,166 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-21 22:38:19,167 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-21 22:38:19,167 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-21 22:38:19,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2021-12-21 22:38:19,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:19,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:19,242 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,243 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,243 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-21 22:38:19,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2021-12-21 22:38:19,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:19,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:19,256 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,256 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,262 INFO L791 eck$LassoCheckResult]: Stem: 314#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 215#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 221#L641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 308#L285true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 204#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 194#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 254#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 144#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L439-1true assume !(0 == ~T3_E~0); 169#L444-1true assume !(0 == ~E_M~0); 277#L449-1true assume !(0 == ~E_1~0); 59#L454-1true assume !(0 == ~E_2~0); 301#L459-1true assume !(0 == ~E_3~0); 38#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294#L208true assume 1 == ~m_pc~0; 299#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 324#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L220true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 48#L531true assume !(0 != activate_threads_~tmp~1#1); 133#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117#L227true assume !(1 == ~t1_pc~0); 47#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 195#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197#L239true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58#L539true assume !(0 != activate_threads_~tmp___0~0#1); 139#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77#L246true assume 1 == ~t2_pc~0; 130#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 149#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#L258true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 208#L547true assume !(0 != activate_threads_~tmp___1~0#1); 232#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83#L265true assume !(1 == ~t3_pc~0); 309#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 4#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L277true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320#L555true assume !(0 != activate_threads_~tmp___2~0#1); 64#L555-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199#L477true assume !(1 == ~M_E~0); 261#L477-2true assume !(1 == ~T1_E~0); 216#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 167#L487-1true assume !(1 == ~T3_E~0); 250#L492-1true assume !(1 == ~E_M~0); 41#L497-1true assume !(1 == ~E_1~0); 138#L502-1true assume !(1 == ~E_2~0); 29#L507-1true assume !(1 == ~E_3~0); 115#L512-1true assume { :end_inline_reset_delta_events } true; 191#L678-2true [2021-12-21 22:38:19,268 INFO L793 eck$LassoCheckResult]: Loop: 191#L678-2true assume !false; 282#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140#L404true assume false; 5#L419true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63#L285-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 263#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 326#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 189#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 71#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 95#L454-3true assume 0 == ~E_2~0;~E_2~0 := 1; 234#L459-3true assume !(0 == ~E_3~0); 60#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246#L208-15true assume 1 == ~m_pc~0; 279#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 243#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52#L220-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 153#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286#L227-15true assume !(1 == ~t1_pc~0); 271#L227-17true is_transmit1_triggered_~__retres1~1#1 := 0; 235#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19#L239-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170#L246-15true assume !(1 == ~t2_pc~0); 14#L246-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 288#L258-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 311#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L265-15true assume !(1 == ~t3_pc~0); 265#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 126#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90#L277-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 212#L555-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L477-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 260#L482-3true assume !(1 == ~T2_E~0); 96#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 51#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 285#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 137#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 182#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 54#L343-1true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 207#L697true assume !(0 == start_simulation_~tmp~3#1); 3#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 251#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 81#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 70#L343-2true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 323#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 196#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 275#L660true start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 82#L710true assume !(0 != start_simulation_~tmp___0~1#1); 191#L678-2true [2021-12-21 22:38:19,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,274 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2021-12-21 22:38:19,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742333059] [2021-12-21 22:38:19,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,288 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,432 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742333059] [2021-12-21 22:38:19,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742333059] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,434 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,434 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105799019] [2021-12-21 22:38:19,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:19,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,440 INFO L85 PathProgramCache]: Analyzing trace with hash -203279494, now seen corresponding path program 1 times [2021-12-21 22:38:19,441 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298146583] [2021-12-21 22:38:19,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,441 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,470 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298146583] [2021-12-21 22:38:19,471 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298146583] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,471 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,471 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:19,471 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486962048] [2021-12-21 22:38:19,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,472 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:19,473 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:19,494 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:19,494 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:19,496 INFO L87 Difference]: Start difference. First operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:19,545 INFO L93 Difference]: Finished difference Result 323 states and 481 transitions. [2021-12-21 22:38:19,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:19,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 481 transitions. [2021-12-21 22:38:19,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 318 states and 476 transitions. [2021-12-21 22:38:19,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-21 22:38:19,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-21 22:38:19,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 476 transitions. [2021-12-21 22:38:19,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:19,564 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-21 22:38:19,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 476 transitions. [2021-12-21 22:38:19,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-21 22:38:19,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 476 transitions. [2021-12-21 22:38:19,606 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-21 22:38:19,606 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2021-12-21 22:38:19,607 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-21 22:38:19,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 476 transitions. [2021-12-21 22:38:19,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:19,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:19,612 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,612 INFO L791 eck$LassoCheckResult]: Stem: 973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 943#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 947#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 847#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 848#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 934#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 919#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 920#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 927#L429 assume !(0 == ~M_E~0); 756#L429-2 assume !(0 == ~T1_E~0); 757#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 878#L439-1 assume !(0 == ~T3_E~0); 900#L444-1 assume !(0 == ~E_M~0); 901#L449-1 assume !(0 == ~E_1~0); 762#L454-1 assume !(0 == ~E_2~0); 763#L459-1 assume !(0 == ~E_3~0); 723#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 724#L208 assume 1 == ~m_pc~0; 969#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 971#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 743#L531 assume !(0 != activate_threads_~tmp~1#1); 744#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 853#L227 assume !(1 == ~t1_pc~0); 741#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 742#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 928#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 760#L539 assume !(0 != activate_threads_~tmp___0~0#1); 761#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793#L246 assume 1 == ~t2_pc~0; 794#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 866#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 933#L547 assume !(0 != activate_threads_~tmp___1~0#1); 938#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 803#L265 assume !(1 == ~t3_pc~0); 685#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 658#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 659#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 883#L555 assume !(0 != activate_threads_~tmp___2~0#1); 775#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 776#L477 assume !(1 == ~M_E~0); 932#L477-2 assume !(1 == ~T1_E~0); 944#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 895#L487-1 assume !(1 == ~T3_E~0); 896#L492-1 assume !(1 == ~E_M~0); 731#L497-1 assume !(1 == ~E_1~0); 732#L502-1 assume !(1 == ~E_2~0); 710#L507-1 assume !(1 == ~E_3~0); 711#L512-1 assume { :end_inline_reset_delta_events } true; 800#L678-2 [2021-12-21 22:38:19,613 INFO L793 eck$LassoCheckResult]: Loop: 800#L678-2 assume !false; 925#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L404 assume !false; 852#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 833#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 695#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 727#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 780#L357 assume !(0 != eval_~tmp~0#1); 660#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 661#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 771#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 962#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 921#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 922#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 769#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 770#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 787#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 819#L459-3 assume !(0 == ~E_3~0); 764#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 765#L208-15 assume !(1 == ~m_pc~0); 906#L208-17 is_master_triggered_~__retres1~0#1 := 0; 907#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 751#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 752#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 788#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 789#L227-15 assume !(1 == ~t1_pc~0); 965#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 952#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 687#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 917#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L246-15 assume 1 == ~t2_pc~0; 666#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 667#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 958#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 966#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 753#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 754#L265-15 assume 1 == ~t3_pc~0; 828#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 830#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 811#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 806#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 807#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 908#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 909#L482-3 assume !(1 == ~T2_E~0); 818#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 747#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 748#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 872#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 873#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 842#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 714#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 675#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 676#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 755#L697 assume !(0 == start_simulation_~tmp~3#1); 656#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 657#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 798#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 783#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 784#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 929#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 930#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 799#L710 assume !(0 != start_simulation_~tmp___0~1#1); 800#L678-2 [2021-12-21 22:38:19,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,613 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2021-12-21 22:38:19,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134548684] [2021-12-21 22:38:19,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,662 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134548684] [2021-12-21 22:38:19,662 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134548684] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,662 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,662 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,663 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217173900] [2021-12-21 22:38:19,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:19,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,664 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 1 times [2021-12-21 22:38:19,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720688690] [2021-12-21 22:38:19,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,699 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,699 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720688690] [2021-12-21 22:38:19,699 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720688690] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,699 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,699 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,700 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [114102038] [2021-12-21 22:38:19,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,700 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:19,700 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:19,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:19,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:19,701 INFO L87 Difference]: Start difference. First operand 318 states and 476 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:19,707 INFO L93 Difference]: Finished difference Result 318 states and 475 transitions. [2021-12-21 22:38:19,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:19,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 475 transitions. [2021-12-21 22:38:19,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 475 transitions. [2021-12-21 22:38:19,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-21 22:38:19,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-21 22:38:19,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 475 transitions. [2021-12-21 22:38:19,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:19,712 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-21 22:38:19,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 475 transitions. [2021-12-21 22:38:19,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-21 22:38:19,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 475 transitions. [2021-12-21 22:38:19,738 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-21 22:38:19,738 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2021-12-21 22:38:19,738 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-21 22:38:19,738 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 475 transitions. [2021-12-21 22:38:19,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:19,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:19,740 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,740 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,740 INFO L791 eck$LassoCheckResult]: Stem: 1616#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1587#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1590#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1493#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 1494#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1577#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1562#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1563#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1570#L429 assume !(0 == ~M_E~0); 1399#L429-2 assume !(0 == ~T1_E~0); 1400#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1521#L439-1 assume !(0 == ~T3_E~0); 1543#L444-1 assume !(0 == ~E_M~0); 1544#L449-1 assume !(0 == ~E_1~0); 1407#L454-1 assume !(0 == ~E_2~0); 1408#L459-1 assume !(0 == ~E_3~0); 1366#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1367#L208 assume 1 == ~m_pc~0; 1612#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1614#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1435#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1386#L531 assume !(0 != activate_threads_~tmp~1#1); 1387#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1497#L227 assume !(1 == ~t1_pc~0); 1384#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1385#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1571#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1403#L539 assume !(0 != activate_threads_~tmp___0~0#1); 1404#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1436#L246 assume 1 == ~t2_pc~0; 1437#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1509#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1524#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1576#L547 assume !(0 != activate_threads_~tmp___1~0#1); 1581#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1446#L265 assume !(1 == ~t3_pc~0); 1328#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1301#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1302#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1526#L555 assume !(0 != activate_threads_~tmp___2~0#1); 1415#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1416#L477 assume !(1 == ~M_E~0); 1575#L477-2 assume !(1 == ~T1_E~0); 1585#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1538#L487-1 assume !(1 == ~T3_E~0); 1539#L492-1 assume !(1 == ~E_M~0); 1371#L497-1 assume !(1 == ~E_1~0); 1372#L502-1 assume !(1 == ~E_2~0); 1353#L507-1 assume !(1 == ~E_3~0); 1354#L512-1 assume { :end_inline_reset_delta_events } true; 1443#L678-2 [2021-12-21 22:38:19,741 INFO L793 eck$LassoCheckResult]: Loop: 1443#L678-2 assume !false; 1566#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1332#L404 assume !false; 1495#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1471#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1338#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1370#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1422#L357 assume !(0 != eval_~tmp~0#1); 1303#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1304#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1414#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1564#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1565#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1412#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1413#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1428#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1461#L459-3 assume !(0 == ~E_3~0); 1405#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1406#L208-15 assume 1 == ~m_pc~0; 1600#L209-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1550#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1394#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1395#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1429#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1430#L227-15 assume !(1 == ~t1_pc~0); 1607#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 1595#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1329#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1330#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1560#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1545#L246-15 assume 1 == ~t2_pc~0; 1313#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1314#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1601#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1610#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1396#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1397#L265-15 assume 1 == ~t3_pc~0; 1472#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1474#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1455#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1450#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1451#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1583#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1551#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1552#L482-3 assume !(1 == ~T2_E~0); 1462#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1392#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1393#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1515#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1516#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1485#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1357#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1320#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1321#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1398#L697 assume !(0 == start_simulation_~tmp~3#1); 1299#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1300#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1441#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1426#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 1427#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1572#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1573#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1442#L710 assume !(0 != start_simulation_~tmp___0~1#1); 1443#L678-2 [2021-12-21 22:38:19,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2021-12-21 22:38:19,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,742 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737747445] [2021-12-21 22:38:19,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,742 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,779 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737747445] [2021-12-21 22:38:19,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737747445] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,779 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,780 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441645767] [2021-12-21 22:38:19,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,781 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:19,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,782 INFO L85 PathProgramCache]: Analyzing trace with hash 378529221, now seen corresponding path program 1 times [2021-12-21 22:38:19,782 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,782 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827703916] [2021-12-21 22:38:19,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,783 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,817 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827703916] [2021-12-21 22:38:19,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827703916] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437004343] [2021-12-21 22:38:19,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,819 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:19,819 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:19,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:19,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:19,819 INFO L87 Difference]: Start difference. First operand 318 states and 475 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:19,826 INFO L93 Difference]: Finished difference Result 318 states and 474 transitions. [2021-12-21 22:38:19,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:19,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 474 transitions. [2021-12-21 22:38:19,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 474 transitions. [2021-12-21 22:38:19,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2021-12-21 22:38:19,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2021-12-21 22:38:19,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 474 transitions. [2021-12-21 22:38:19,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:19,833 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-21 22:38:19,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 474 transitions. [2021-12-21 22:38:19,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2021-12-21 22:38:19,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:19,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 474 transitions. [2021-12-21 22:38:19,837 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-21 22:38:19,837 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2021-12-21 22:38:19,837 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-21 22:38:19,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 474 transitions. [2021-12-21 22:38:19,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2021-12-21 22:38:19,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:19,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:19,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,839 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:19,841 INFO L791 eck$LassoCheckResult]: Stem: 2259#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2228#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2229#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2233#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2131#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2132#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2220#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2204#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2205#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2213#L429 assume !(0 == ~M_E~0); 2042#L429-2 assume !(0 == ~T1_E~0); 2043#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2163#L439-1 assume !(0 == ~T3_E~0); 2186#L444-1 assume !(0 == ~E_M~0); 2187#L449-1 assume !(0 == ~E_1~0); 2048#L454-1 assume !(0 == ~E_2~0); 2049#L459-1 assume !(0 == ~E_3~0); 2009#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2010#L208 assume 1 == ~m_pc~0; 2255#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2257#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2077#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2029#L531 assume !(0 != activate_threads_~tmp~1#1); 2030#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2139#L227 assume !(1 == ~t1_pc~0); 2027#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2028#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2214#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2046#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2047#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2078#L246 assume 1 == ~t2_pc~0; 2079#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2152#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2167#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2219#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2223#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2087#L265 assume !(1 == ~t3_pc~0); 1971#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1944#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1945#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2169#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2058#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2059#L477 assume !(1 == ~M_E~0); 2218#L477-2 assume !(1 == ~T1_E~0); 2230#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2181#L487-1 assume !(1 == ~T3_E~0); 2182#L492-1 assume !(1 == ~E_M~0); 2014#L497-1 assume !(1 == ~E_1~0); 2015#L502-1 assume !(1 == ~E_2~0); 1996#L507-1 assume !(1 == ~E_3~0); 1997#L512-1 assume { :end_inline_reset_delta_events } true; 2086#L678-2 [2021-12-21 22:38:19,841 INFO L793 eck$LassoCheckResult]: Loop: 2086#L678-2 assume !false; 2209#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1975#L404 assume !false; 2138#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2114#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1981#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2013#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2065#L357 assume !(0 != eval_~tmp~0#1); 1946#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1947#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2057#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2248#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2207#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2208#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2055#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2056#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2071#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2104#L459-3 assume !(0 == ~E_3~0); 2050#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2051#L208-15 assume !(1 == ~m_pc~0); 2192#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2193#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2037#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2038#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2072#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2073#L227-15 assume !(1 == ~t1_pc~0); 2250#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2238#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1972#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1973#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2203#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2188#L246-15 assume 1 == ~t2_pc~0; 1956#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1957#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2244#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2253#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2039#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2040#L265-15 assume 1 == ~t3_pc~0; 2115#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2117#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2098#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2093#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2094#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2226#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2194#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2195#L482-3 assume !(1 == ~T2_E~0); 2105#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2035#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2036#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2158#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2159#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2129#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2000#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1963#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1964#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2041#L697 assume !(0 == start_simulation_~tmp~3#1); 1942#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1943#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2084#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2069#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2070#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2215#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2216#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2085#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2086#L678-2 [2021-12-21 22:38:19,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,841 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2021-12-21 22:38:19,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868164113] [2021-12-21 22:38:19,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868164113] [2021-12-21 22:38:19,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868164113] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,888 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,889 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,891 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1076811895] [2021-12-21 22:38:19,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,892 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:19,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:19,892 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 2 times [2021-12-21 22:38:19,893 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:19,894 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967106459] [2021-12-21 22:38:19,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:19,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:19,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:19,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:19,949 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:19,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967106459] [2021-12-21 22:38:19,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967106459] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:19,949 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:19,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:19,949 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854966451] [2021-12-21 22:38:19,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:19,949 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:19,949 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:19,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:19,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:19,950 INFO L87 Difference]: Start difference. First operand 318 states and 474 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,003 INFO L93 Difference]: Finished difference Result 551 states and 816 transitions. [2021-12-21 22:38:20,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:20,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 816 transitions. [2021-12-21 22:38:20,007 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-21 22:38:20,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 816 transitions. [2021-12-21 22:38:20,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2021-12-21 22:38:20,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2021-12-21 22:38:20,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 816 transitions. [2021-12-21 22:38:20,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,010 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-21 22:38:20,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 816 transitions. [2021-12-21 22:38:20,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2021-12-21 22:38:20,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 816 transitions. [2021-12-21 22:38:20,017 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-21 22:38:20,017 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2021-12-21 22:38:20,017 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-21 22:38:20,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 816 transitions. [2021-12-21 22:38:20,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2021-12-21 22:38:20,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:20,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:20,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,020 INFO L791 eck$LassoCheckResult]: Stem: 3168#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3124#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3129#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3013#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3014#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3115#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3096#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3097#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3106#L429 assume !(0 == ~M_E~0); 2922#L429-2 assume !(0 == ~T1_E~0); 2923#L434-1 assume !(0 == ~T2_E~0); 3051#L439-1 assume !(0 == ~T3_E~0); 3075#L444-1 assume !(0 == ~E_M~0); 3076#L449-1 assume !(0 == ~E_1~0); 2928#L454-1 assume !(0 == ~E_2~0); 2929#L459-1 assume !(0 == ~E_3~0); 2888#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2889#L208 assume 1 == ~m_pc~0; 3162#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3164#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2958#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2909#L531 assume !(0 != activate_threads_~tmp~1#1); 2910#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3023#L227 assume !(1 == ~t1_pc~0); 2907#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2908#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3107#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2926#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2927#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2959#L246 assume 1 == ~t2_pc~0; 2960#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3038#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3055#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3114#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3118#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2968#L265 assume !(1 == ~t3_pc~0); 2850#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2823#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3057#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2938#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2939#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 3111#L477-2 assume !(1 == ~T1_E~0); 3230#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3126#L487-1 assume !(1 == ~T3_E~0); 3228#L492-1 assume !(1 == ~E_M~0); 3227#L497-1 assume !(1 == ~E_1~0); 3225#L502-1 assume !(1 == ~E_2~0); 3223#L507-1 assume !(1 == ~E_3~0); 3020#L512-1 assume { :end_inline_reset_delta_events } true; 2967#L678-2 [2021-12-21 22:38:20,021 INFO L793 eck$LassoCheckResult]: Loop: 2967#L678-2 assume !false; 3101#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2854#L404 assume !false; 3021#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3022#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2892#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2893#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3156#L357 assume !(0 != eval_~tmp~0#1); 2825#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2826#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2937#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3169#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3099#L434-3 assume !(0 == ~T2_E~0); 3100#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2935#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2936#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2952#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2985#L459-3 assume !(0 == ~E_3~0); 2930#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2931#L208-15 assume 1 == ~m_pc~0; 3142#L209-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3084#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2917#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2918#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2953#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2954#L227-15 assume !(1 == ~t1_pc~0); 3154#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3136#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2851#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2852#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3095#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3077#L246-15 assume 1 == ~t2_pc~0; 2835#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2836#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3143#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3160#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2919#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2920#L265-15 assume 1 == ~t3_pc~0; 2996#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2998#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2979#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2974#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2975#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3121#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3085#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3086#L482-3 assume !(1 == ~T2_E~0); 2986#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2915#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2916#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3044#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3045#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3011#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2879#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2842#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2843#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2921#L697 assume !(0 == start_simulation_~tmp~3#1); 2821#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2822#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3245#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3243#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 3241#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3239#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3237#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2966#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2967#L678-2 [2021-12-21 22:38:20,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2021-12-21 22:38:20,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457071992] [2021-12-21 22:38:20,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,022 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457071992] [2021-12-21 22:38:20,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457071992] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,038 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:20,039 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84599412] [2021-12-21 22:38:20,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,039 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:20,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,040 INFO L85 PathProgramCache]: Analyzing trace with hash 1916869251, now seen corresponding path program 1 times [2021-12-21 22:38:20,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386228573] [2021-12-21 22:38:20,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,040 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,081 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,081 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386228573] [2021-12-21 22:38:20,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386228573] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,081 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:20,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1319162684] [2021-12-21 22:38:20,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:20,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:20,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:20,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:20,083 INFO L87 Difference]: Start difference. First operand 551 states and 816 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,112 INFO L93 Difference]: Finished difference Result 1021 states and 1489 transitions. [2021-12-21 22:38:20,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:20,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1021 states and 1489 transitions. [2021-12-21 22:38:20,118 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 957 [2021-12-21 22:38:20,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1021 states to 1021 states and 1489 transitions. [2021-12-21 22:38:20,122 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1021 [2021-12-21 22:38:20,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1021 [2021-12-21 22:38:20,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1021 states and 1489 transitions. [2021-12-21 22:38:20,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,123 INFO L681 BuchiCegarLoop]: Abstraction has 1021 states and 1489 transitions. [2021-12-21 22:38:20,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1021 states and 1489 transitions. [2021-12-21 22:38:20,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1021 to 967. [2021-12-21 22:38:20,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 967 states to 967 states and 1415 transitions. [2021-12-21 22:38:20,135 INFO L704 BuchiCegarLoop]: Abstraction has 967 states and 1415 transitions. [2021-12-21 22:38:20,135 INFO L587 BuchiCegarLoop]: Abstraction has 967 states and 1415 transitions. [2021-12-21 22:38:20,145 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-21 22:38:20,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 967 states and 1415 transitions. [2021-12-21 22:38:20,149 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 903 [2021-12-21 22:38:20,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:20,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:20,150 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,150 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,150 INFO L791 eck$LassoCheckResult]: Stem: 4767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4710#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4715#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4596#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4597#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4699#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4677#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4678#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4685#L429 assume !(0 == ~M_E~0); 4502#L429-2 assume !(0 == ~T1_E~0); 4503#L434-1 assume !(0 == ~T2_E~0); 4629#L439-1 assume !(0 == ~T3_E~0); 4653#L444-1 assume !(0 == ~E_M~0); 4654#L449-1 assume !(0 == ~E_1~0); 4508#L454-1 assume !(0 == ~E_2~0); 4509#L459-1 assume !(0 == ~E_3~0); 4469#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4470#L208 assume !(1 == ~m_pc~0); 4759#L208-2 is_master_triggered_~__retres1~0#1 := 0; 4760#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4540#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4489#L531 assume !(0 != activate_threads_~tmp~1#1); 4490#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4601#L227 assume !(1 == ~t1_pc~0); 4487#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4488#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4686#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4506#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4507#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4541#L246 assume 1 == ~t2_pc~0; 4542#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4617#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4632#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4695#L547 assume !(0 != activate_threads_~tmp___1~0#1); 4704#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4551#L265 assume !(1 == ~t3_pc~0); 4431#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4404#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4405#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4636#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4520#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4521#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 4693#L477-2 assume !(1 == ~T1_E~0); 5048#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4712#L487-1 assume !(1 == ~T3_E~0); 5045#L492-1 assume !(1 == ~E_M~0); 5043#L497-1 assume !(1 == ~E_1~0); 5041#L502-1 assume !(1 == ~E_2~0); 5040#L507-1 assume !(1 == ~E_3~0); 4890#L512-1 assume { :end_inline_reset_delta_events } true; 4888#L678-2 [2021-12-21 22:38:20,151 INFO L793 eck$LassoCheckResult]: Loop: 4888#L678-2 assume !false; 4884#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4879#L404 assume !false; 4878#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4876#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4869#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4867#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4864#L357 assume !(0 != eval_~tmp~0#1); 4862#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4860#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4858#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4772#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4773#L434-3 assume !(0 == ~T2_E~0); 4719#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4720#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4535#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4536#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4722#L459-3 assume !(0 == ~E_3~0); 4723#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4733#L208-15 assume !(1 == ~m_pc~0); 4734#L208-17 is_master_triggered_~__retres1~0#1 := 0; 4730#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4731#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4634#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4635#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5343#L227-15 assume 1 == ~t1_pc~0; 4768#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4746#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4432#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4433#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4674#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4675#L246-15 assume 1 == ~t2_pc~0; 4412#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4413#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4753#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4754#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4766#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4690#L265-15 assume !(1 == ~t3_pc~0); 4691#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 5313#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5314#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4553#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4554#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5341#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4664#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L482-3 assume !(1 == ~T2_E~0); 4566#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4493#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4494#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4623#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4624#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4591#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4460#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4423#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4424#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4501#L697 assume !(0 == start_simulation_~tmp~3#1); 4538#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4905#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4902#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4900#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 4898#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4896#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4893#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4891#L710 assume !(0 != start_simulation_~tmp___0~1#1); 4888#L678-2 [2021-12-21 22:38:20,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,151 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2021-12-21 22:38:20,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113657665] [2021-12-21 22:38:20,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113657665] [2021-12-21 22:38:20,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113657665] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,190 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:20,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685021645] [2021-12-21 22:38:20,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,190 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:20,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,191 INFO L85 PathProgramCache]: Analyzing trace with hash 327802308, now seen corresponding path program 1 times [2021-12-21 22:38:20,191 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,191 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135019754] [2021-12-21 22:38:20,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,227 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135019754] [2021-12-21 22:38:20,232 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135019754] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,232 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,232 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:20,232 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485347218] [2021-12-21 22:38:20,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,233 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:20,233 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:20,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:20,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:20,234 INFO L87 Difference]: Start difference. First operand 967 states and 1415 transitions. cyclomatic complexity: 452 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,324 INFO L93 Difference]: Finished difference Result 2187 states and 3150 transitions. [2021-12-21 22:38:20,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:20,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2187 states and 3150 transitions. [2021-12-21 22:38:20,336 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2054 [2021-12-21 22:38:20,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2187 states to 2187 states and 3150 transitions. [2021-12-21 22:38:20,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2187 [2021-12-21 22:38:20,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2187 [2021-12-21 22:38:20,346 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2187 states and 3150 transitions. [2021-12-21 22:38:20,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,348 INFO L681 BuchiCegarLoop]: Abstraction has 2187 states and 3150 transitions. [2021-12-21 22:38:20,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2187 states and 3150 transitions. [2021-12-21 22:38:20,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2187 to 1725. [2021-12-21 22:38:20,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 1725 states and 2507 transitions. [2021-12-21 22:38:20,374 INFO L704 BuchiCegarLoop]: Abstraction has 1725 states and 2507 transitions. [2021-12-21 22:38:20,374 INFO L587 BuchiCegarLoop]: Abstraction has 1725 states and 2507 transitions. [2021-12-21 22:38:20,374 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-21 22:38:20,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1725 states and 2507 transitions. [2021-12-21 22:38:20,380 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1660 [2021-12-21 22:38:20,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:20,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:20,382 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,382 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,382 INFO L791 eck$LassoCheckResult]: Stem: 7946#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7880#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7886#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7757#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 7758#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7869#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7848#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7849#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7858#L429 assume !(0 == ~M_E~0); 7667#L429-2 assume !(0 == ~T1_E~0); 7668#L434-1 assume !(0 == ~T2_E~0); 7797#L439-1 assume !(0 == ~T3_E~0); 7825#L444-1 assume !(0 == ~E_M~0); 7826#L449-1 assume !(0 == ~E_1~0); 7673#L454-1 assume !(0 == ~E_2~0); 7674#L459-1 assume !(0 == ~E_3~0); 7634#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7635#L208 assume !(1 == ~m_pc~0); 7935#L208-2 is_master_triggered_~__retres1~0#1 := 0; 7936#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7705#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7654#L531 assume !(0 != activate_threads_~tmp~1#1); 7655#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7766#L227 assume !(1 == ~t1_pc~0); 7652#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7653#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7859#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7671#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7672#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7706#L246 assume !(1 == ~t2_pc~0); 7707#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7802#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7803#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7867#L547 assume !(0 != activate_threads_~tmp___1~0#1); 7873#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7714#L265 assume !(1 == ~t3_pc~0); 7597#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7570#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7571#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7806#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7683#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7684#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 7863#L477-2 assume !(1 == ~T1_E~0); 7913#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7820#L487-1 assume !(1 == ~T3_E~0); 7821#L492-1 assume !(1 == ~E_M~0); 7639#L497-1 assume !(1 == ~E_1~0); 7640#L502-1 assume !(1 == ~E_2~0); 7622#L507-1 assume !(1 == ~E_3~0); 7623#L512-1 assume { :end_inline_reset_delta_events } true; 8643#L678-2 [2021-12-21 22:38:20,382 INFO L793 eck$LassoCheckResult]: Loop: 8643#L678-2 assume !false; 8641#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8637#L404 assume !false; 8636#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8619#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8615#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8613#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8610#L357 assume !(0 != eval_~tmp~0#1); 8611#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8808#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8806#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8804#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8802#L434-3 assume !(0 == ~T2_E~0); 8800#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8798#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8795#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8793#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8791#L459-3 assume !(0 == ~E_3~0); 8789#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8787#L208-15 assume !(1 == ~m_pc~0); 8786#L208-17 is_master_triggered_~__retres1~0#1 := 0; 8785#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8784#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8783#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8782#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8780#L227-15 assume 1 == ~t1_pc~0; 8777#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8775#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8773#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8771#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8769#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8767#L246-15 assume !(1 == ~t2_pc~0); 8415#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8763#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8761#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8759#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8757#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8755#L265-15 assume !(1 == ~t3_pc~0); 8753#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 8751#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8749#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8747#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8745#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8743#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8723#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8720#L482-3 assume !(1 == ~T2_E~0); 8717#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8715#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8713#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8711#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8709#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8707#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8704#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8701#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8699#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8667#L697 assume !(0 == start_simulation_~tmp~3#1); 8665#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8661#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8657#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8655#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 8653#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8651#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8649#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8645#L710 assume !(0 != start_simulation_~tmp___0~1#1); 8643#L678-2 [2021-12-21 22:38:20,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2021-12-21 22:38:20,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32483138] [2021-12-21 22:38:20,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,383 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32483138] [2021-12-21 22:38:20,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32483138] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:20,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289359559] [2021-12-21 22:38:20,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,437 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:20,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1248755451, now seen corresponding path program 1 times [2021-12-21 22:38:20,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797373810] [2021-12-21 22:38:20,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,483 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797373810] [2021-12-21 22:38:20,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797373810] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,483 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:20,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [835949322] [2021-12-21 22:38:20,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:20,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:20,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:20,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:20,484 INFO L87 Difference]: Start difference. First operand 1725 states and 2507 transitions. cyclomatic complexity: 786 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,509 INFO L93 Difference]: Finished difference Result 2513 states and 3650 transitions. [2021-12-21 22:38:20,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:20,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2513 states and 3650 transitions. [2021-12-21 22:38:20,520 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2448 [2021-12-21 22:38:20,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2513 states to 2513 states and 3650 transitions. [2021-12-21 22:38:20,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2513 [2021-12-21 22:38:20,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2513 [2021-12-21 22:38:20,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2513 states and 3650 transitions. [2021-12-21 22:38:20,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,534 INFO L681 BuchiCegarLoop]: Abstraction has 2513 states and 3650 transitions. [2021-12-21 22:38:20,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2513 states and 3650 transitions. [2021-12-21 22:38:20,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2513 to 1749. [2021-12-21 22:38:20,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 1749 states and 2547 transitions. [2021-12-21 22:38:20,565 INFO L704 BuchiCegarLoop]: Abstraction has 1749 states and 2547 transitions. [2021-12-21 22:38:20,565 INFO L587 BuchiCegarLoop]: Abstraction has 1749 states and 2547 transitions. [2021-12-21 22:38:20,565 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-21 22:38:20,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1749 states and 2547 transitions. [2021-12-21 22:38:20,585 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1692 [2021-12-21 22:38:20,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:20,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:20,586 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,586 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,586 INFO L791 eck$LassoCheckResult]: Stem: 12170#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12118#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12119#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12123#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12007#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 12008#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12108#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12091#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12092#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12100#L429 assume !(0 == ~M_E~0); 11915#L429-2 assume !(0 == ~T1_E~0); 11916#L434-1 assume !(0 == ~T2_E~0); 12044#L439-1 assume !(0 == ~T3_E~0); 12069#L444-1 assume !(0 == ~E_M~0); 12070#L449-1 assume !(0 == ~E_1~0); 11921#L454-1 assume !(0 == ~E_2~0); 11922#L459-1 assume !(0 == ~E_3~0); 11881#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11882#L208 assume !(1 == ~m_pc~0); 12162#L208-2 is_master_triggered_~__retres1~0#1 := 0; 12163#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11953#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11901#L531 assume !(0 != activate_threads_~tmp~1#1); 11902#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12017#L227 assume !(1 == ~t1_pc~0); 11899#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11900#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12101#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11919#L539 assume !(0 != activate_threads_~tmp___0~0#1); 11920#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11954#L246 assume !(1 == ~t2_pc~0); 11955#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12048#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12049#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12106#L547 assume !(0 != activate_threads_~tmp___1~0#1); 12112#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11962#L265 assume !(1 == ~t3_pc~0); 11844#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11817#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11818#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12051#L555 assume !(0 != activate_threads_~tmp___2~0#1); 11931#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11932#L477 assume !(1 == ~M_E~0); 12105#L477-2 assume !(1 == ~T1_E~0); 12120#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12064#L487-1 assume !(1 == ~T3_E~0); 12065#L492-1 assume !(1 == ~E_M~0); 11886#L497-1 assume !(1 == ~E_1~0); 11887#L502-1 assume !(1 == ~E_2~0); 11869#L507-1 assume !(1 == ~E_3~0); 11870#L512-1 assume { :end_inline_reset_delta_events } true; 12015#L678-2 [2021-12-21 22:38:20,586 INFO L793 eck$LassoCheckResult]: Loop: 12015#L678-2 assume !false; 13300#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13295#L404 assume !false; 13293#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13289#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13246#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13245#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13243#L357 assume !(0 != eval_~tmp~0#1); 13244#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13535#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13534#L429-3 assume !(0 == ~M_E~0); 13533#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12094#L434-3 assume !(0 == ~T2_E~0); 12095#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11928#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11929#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13507#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13506#L459-3 assume !(0 == ~E_3~0); 13505#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13504#L208-15 assume !(1 == ~m_pc~0); 13503#L208-17 is_master_triggered_~__retres1~0#1 := 0; 13501#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13499#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13497#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13495#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13493#L227-15 assume 1 == ~t1_pc~0; 13476#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13472#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13468#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13464#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13461#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12071#L246-15 assume !(1 == ~t2_pc~0); 12072#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 12141#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12142#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12156#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11911#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11912#L265-15 assume 1 == ~t3_pc~0; 11991#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11993#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11974#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11969#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11970#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12116#L477-3 assume !(1 == ~M_E~0); 12079#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12080#L482-3 assume !(1 == ~T2_E~0); 11981#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11907#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11908#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12037#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12038#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12005#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11873#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11836#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11837#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 12110#L697 assume !(0 == start_simulation_~tmp~3#1); 11815#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11816#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11965#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13312#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 13310#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13308#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13306#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 13304#L710 assume !(0 != start_simulation_~tmp___0~1#1); 12015#L678-2 [2021-12-21 22:38:20,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,587 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2021-12-21 22:38:20,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598921414] [2021-12-21 22:38:20,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,587 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,613 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598921414] [2021-12-21 22:38:20,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598921414] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,613 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,613 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:20,613 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16390889] [2021-12-21 22:38:20,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,614 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:20,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483012, now seen corresponding path program 1 times [2021-12-21 22:38:20,614 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310163401] [2021-12-21 22:38:20,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,615 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,634 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1310163401] [2021-12-21 22:38:20,635 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1310163401] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,635 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,635 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:20,635 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1046465546] [2021-12-21 22:38:20,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:20,636 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:20,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:20,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:20,636 INFO L87 Difference]: Start difference. First operand 1749 states and 2547 transitions. cyclomatic complexity: 800 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,667 INFO L93 Difference]: Finished difference Result 2507 states and 3618 transitions. [2021-12-21 22:38:20,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:20,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2507 states and 3618 transitions. [2021-12-21 22:38:20,677 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2448 [2021-12-21 22:38:20,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2507 states to 2507 states and 3618 transitions. [2021-12-21 22:38:20,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2507 [2021-12-21 22:38:20,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2507 [2021-12-21 22:38:20,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2507 states and 3618 transitions. [2021-12-21 22:38:20,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,689 INFO L681 BuchiCegarLoop]: Abstraction has 2507 states and 3618 transitions. [2021-12-21 22:38:20,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2507 states and 3618 transitions. [2021-12-21 22:38:20,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2507 to 1749. [2021-12-21 22:38:20,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 1749 states and 2530 transitions. [2021-12-21 22:38:20,709 INFO L704 BuchiCegarLoop]: Abstraction has 1749 states and 2530 transitions. [2021-12-21 22:38:20,709 INFO L587 BuchiCegarLoop]: Abstraction has 1749 states and 2530 transitions. [2021-12-21 22:38:20,709 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-21 22:38:20,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1749 states and 2530 transitions. [2021-12-21 22:38:20,713 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1692 [2021-12-21 22:38:20,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:20,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:20,716 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,716 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:20,716 INFO L791 eck$LassoCheckResult]: Stem: 16431#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16383#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16388#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16274#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 16275#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16371#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16354#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16355#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16363#L429 assume !(0 == ~M_E~0); 16184#L429-2 assume !(0 == ~T1_E~0); 16185#L434-1 assume !(0 == ~T2_E~0); 16308#L439-1 assume !(0 == ~T3_E~0); 16333#L444-1 assume !(0 == ~E_M~0); 16334#L449-1 assume !(0 == ~E_1~0); 16190#L454-1 assume !(0 == ~E_2~0); 16191#L459-1 assume !(0 == ~E_3~0); 16151#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16152#L208 assume !(1 == ~m_pc~0); 16422#L208-2 is_master_triggered_~__retres1~0#1 := 0; 16423#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16222#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16171#L531 assume !(0 != activate_threads_~tmp~1#1); 16172#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16283#L227 assume !(1 == ~t1_pc~0); 16169#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16170#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16364#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16188#L539 assume !(0 != activate_threads_~tmp___0~0#1); 16189#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16223#L246 assume !(1 == ~t2_pc~0); 16224#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16313#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16314#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16369#L547 assume !(0 != activate_threads_~tmp___1~0#1); 16375#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16231#L265 assume !(1 == ~t3_pc~0); 16114#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16085#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16086#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16316#L555 assume !(0 != activate_threads_~tmp___2~0#1); 16200#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16201#L477 assume !(1 == ~M_E~0); 16368#L477-2 assume !(1 == ~T1_E~0); 16384#L482-1 assume !(1 == ~T2_E~0); 16328#L487-1 assume !(1 == ~T3_E~0); 16329#L492-1 assume !(1 == ~E_M~0); 16156#L497-1 assume !(1 == ~E_1~0); 16157#L502-1 assume !(1 == ~E_2~0); 16139#L507-1 assume !(1 == ~E_3~0); 16140#L512-1 assume { :end_inline_reset_delta_events } true; 16281#L678-2 [2021-12-21 22:38:20,716 INFO L793 eck$LassoCheckResult]: Loop: 16281#L678-2 assume !false; 17400#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17395#L404 assume !false; 17393#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17389#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17385#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17382#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17380#L357 assume !(0 != eval_~tmp~0#1); 16087#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16088#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16199#L429-3 assume !(0 == ~M_E~0); 16407#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16357#L434-3 assume !(0 == ~T2_E~0); 16358#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16197#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16198#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17799#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16393#L459-3 assume !(0 == ~E_3~0); 16192#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16193#L208-15 assume !(1 == ~m_pc~0); 16340#L208-17 is_master_triggered_~__retres1~0#1 := 0; 16341#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17746#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17745#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17744#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17742#L227-15 assume 1 == ~t1_pc~0; 17739#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17737#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17735#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17733#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17730#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16335#L246-15 assume !(1 == ~t2_pc~0); 16106#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16107#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16402#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16420#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16181#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16182#L265-15 assume 1 == ~t3_pc~0; 16258#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16260#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16241#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16236#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16237#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16380#L477-3 assume !(1 == ~M_E~0); 16342#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16343#L482-3 assume !(1 == ~T2_E~0); 16248#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16177#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16178#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16303#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16304#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16272#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16143#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16104#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16105#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16183#L697 assume !(0 == start_simulation_~tmp~3#1); 16373#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17415#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17413#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17412#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 17410#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17408#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17406#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17404#L710 assume !(0 != start_simulation_~tmp___0~1#1); 16281#L678-2 [2021-12-21 22:38:20,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,717 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2021-12-21 22:38:20,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,717 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300146346] [2021-12-21 22:38:20,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,717 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:20,724 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:20,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:20,761 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:20,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:20,762 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483012, now seen corresponding path program 2 times [2021-12-21 22:38:20,762 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:20,762 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294662003] [2021-12-21 22:38:20,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:20,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:20,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:20,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:20,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:20,784 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294662003] [2021-12-21 22:38:20,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294662003] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:20,784 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:20,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:20,785 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108687114] [2021-12-21 22:38:20,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:20,785 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:20,785 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:20,786 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-21 22:38:20,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-21 22:38:20,786 INFO L87 Difference]: Start difference. First operand 1749 states and 2530 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:20,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:20,891 INFO L93 Difference]: Finished difference Result 3053 states and 4338 transitions. [2021-12-21 22:38:20,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-21 22:38:20,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3053 states and 4338 transitions. [2021-12-21 22:38:20,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2992 [2021-12-21 22:38:20,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3053 states to 3053 states and 4338 transitions. [2021-12-21 22:38:20,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3053 [2021-12-21 22:38:20,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3053 [2021-12-21 22:38:20,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3053 states and 4338 transitions. [2021-12-21 22:38:20,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:20,946 INFO L681 BuchiCegarLoop]: Abstraction has 3053 states and 4338 transitions. [2021-12-21 22:38:20,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3053 states and 4338 transitions. [2021-12-21 22:38:21,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3053 to 1773. [2021-12-21 22:38:21,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 2554 transitions. [2021-12-21 22:38:21,010 INFO L704 BuchiCegarLoop]: Abstraction has 1773 states and 2554 transitions. [2021-12-21 22:38:21,010 INFO L587 BuchiCegarLoop]: Abstraction has 1773 states and 2554 transitions. [2021-12-21 22:38:21,010 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-21 22:38:21,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1773 states and 2554 transitions. [2021-12-21 22:38:21,013 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1716 [2021-12-21 22:38:21,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:21,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:21,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,014 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,014 INFO L791 eck$LassoCheckResult]: Stem: 21284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 21216#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21217#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21221#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21097#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 21098#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21206#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21187#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21188#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21195#L429 assume !(0 == ~M_E~0); 21003#L429-2 assume !(0 == ~T1_E~0); 21004#L434-1 assume !(0 == ~T2_E~0); 21137#L439-1 assume !(0 == ~T3_E~0); 21164#L444-1 assume !(0 == ~E_M~0); 21165#L449-1 assume !(0 == ~E_1~0); 21011#L454-1 assume !(0 == ~E_2~0); 21012#L459-1 assume !(0 == ~E_3~0); 20969#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20970#L208 assume !(1 == ~m_pc~0); 21272#L208-2 is_master_triggered_~__retres1~0#1 := 0; 21273#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21041#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20990#L531 assume !(0 != activate_threads_~tmp~1#1); 20991#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21106#L227 assume !(1 == ~t1_pc~0); 20988#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20989#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21196#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21007#L539 assume !(0 != activate_threads_~tmp___0~0#1); 21008#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21042#L246 assume !(1 == ~t2_pc~0); 21043#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21142#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21143#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21204#L547 assume !(0 != activate_threads_~tmp___1~0#1); 21209#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21050#L265 assume !(1 == ~t3_pc~0); 20932#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20903#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20904#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21148#L555 assume !(0 != activate_threads_~tmp___2~0#1); 21023#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21024#L477 assume !(1 == ~M_E~0); 21203#L477-2 assume !(1 == ~T1_E~0); 21218#L482-1 assume !(1 == ~T2_E~0); 21159#L487-1 assume !(1 == ~T3_E~0); 21160#L492-1 assume !(1 == ~E_M~0); 20975#L497-1 assume !(1 == ~E_1~0); 20976#L502-1 assume !(1 == ~E_2~0); 20959#L507-1 assume !(1 == ~E_3~0); 20960#L512-1 assume { :end_inline_reset_delta_events } true; 21049#L678-2 [2021-12-21 22:38:21,014 INFO L793 eck$LassoCheckResult]: Loop: 21049#L678-2 assume !false; 21191#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20936#L404 assume !false; 21104#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21081#L320 assume !(0 == ~m_st~0); 20943#L324 assume !(0 == ~t1_st~0); 20944#L328 assume !(0 == ~t2_st~0); 21199#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 21200#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22122#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22123#L357 assume !(0 != eval_~tmp~0#1); 22538#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21018#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21019#L429-3 assume !(0 == ~M_E~0); 21250#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21286#L434-3 assume !(0 == ~T2_E~0); 21225#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21226#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21034#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21035#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21229#L459-3 assume !(0 == ~E_3~0); 21230#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21239#L208-15 assume !(1 == ~m_pc~0); 21240#L208-17 is_master_triggered_~__retres1~0#1 := 0; 21236#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21237#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21145#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21146#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21265#L227-15 assume !(1 == ~t1_pc~0); 21266#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 21231#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21232#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21205#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21184#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21185#L246-15 assume !(1 == ~t2_pc~0); 20924#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 20925#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21268#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21269#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21001#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21002#L265-15 assume !(1 == ~t3_pc~0); 21201#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 21113#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21114#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21055#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21056#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21246#L477-3 assume !(1 == ~M_E~0); 21173#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21174#L482-3 assume !(1 == ~T2_E~0); 21069#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20996#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20997#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21128#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21129#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21093#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21094#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22662#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22660#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 22639#L697 assume !(0 == start_simulation_~tmp~3#1); 22629#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 21245#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21047#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21032#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 21033#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21197#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21198#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 21048#L710 assume !(0 != start_simulation_~tmp___0~1#1); 21049#L678-2 [2021-12-21 22:38:21,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2021-12-21 22:38:21,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,015 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236785690] [2021-12-21 22:38:21,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,015 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,033 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,051 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,053 INFO L85 PathProgramCache]: Analyzing trace with hash 763456204, now seen corresponding path program 1 times [2021-12-21 22:38:21,053 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558791963] [2021-12-21 22:38:21,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,053 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:21,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:21,126 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:21,127 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558791963] [2021-12-21 22:38:21,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558791963] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:21,127 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:21,127 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:21,127 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1433454255] [2021-12-21 22:38:21,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:21,127 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:21,127 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:21,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-21 22:38:21,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-21 22:38:21,128 INFO L87 Difference]: Start difference. First operand 1773 states and 2554 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:21,254 INFO L93 Difference]: Finished difference Result 3467 states and 4955 transitions. [2021-12-21 22:38:21,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-21 22:38:21,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3467 states and 4955 transitions. [2021-12-21 22:38:21,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3410 [2021-12-21 22:38:21,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3467 states to 3467 states and 4955 transitions. [2021-12-21 22:38:21,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3467 [2021-12-21 22:38:21,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3467 [2021-12-21 22:38:21,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3467 states and 4955 transitions. [2021-12-21 22:38:21,278 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:21,278 INFO L681 BuchiCegarLoop]: Abstraction has 3467 states and 4955 transitions. [2021-12-21 22:38:21,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3467 states and 4955 transitions. [2021-12-21 22:38:21,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3467 to 1833. [2021-12-21 22:38:21,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1833 states to 1833 states and 2597 transitions. [2021-12-21 22:38:21,302 INFO L704 BuchiCegarLoop]: Abstraction has 1833 states and 2597 transitions. [2021-12-21 22:38:21,303 INFO L587 BuchiCegarLoop]: Abstraction has 1833 states and 2597 transitions. [2021-12-21 22:38:21,303 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-21 22:38:21,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1833 states and 2597 transitions. [2021-12-21 22:38:21,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1776 [2021-12-21 22:38:21,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:21,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:21,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,307 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,308 INFO L791 eck$LassoCheckResult]: Stem: 26531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26472#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26476#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26354#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 26355#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26458#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26439#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26440#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26448#L429 assume !(0 == ~M_E~0); 26257#L429-2 assume !(0 == ~T1_E~0); 26258#L434-1 assume !(0 == ~T2_E~0); 26388#L439-1 assume !(0 == ~T3_E~0); 26416#L444-1 assume !(0 == ~E_M~0); 26417#L449-1 assume !(0 == ~E_1~0); 26265#L454-1 assume !(0 == ~E_2~0); 26266#L459-1 assume !(0 == ~E_3~0); 26224#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26225#L208 assume !(1 == ~m_pc~0); 26524#L208-2 is_master_triggered_~__retres1~0#1 := 0; 26525#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26295#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 26244#L531 assume !(0 != activate_threads_~tmp~1#1); 26245#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26359#L227 assume !(1 == ~t1_pc~0); 26242#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26243#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26449#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 26261#L539 assume !(0 != activate_threads_~tmp___0~0#1); 26262#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26296#L246 assume !(1 == ~t2_pc~0); 26297#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26393#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26394#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 26457#L547 assume !(0 != activate_threads_~tmp___1~0#1); 26463#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26306#L265 assume !(1 == ~t3_pc~0); 26185#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26156#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26157#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26398#L555 assume !(0 != activate_threads_~tmp___2~0#1); 26278#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26279#L477 assume !(1 == ~M_E~0); 26454#L477-2 assume !(1 == ~T1_E~0); 26473#L482-1 assume !(1 == ~T2_E~0); 26414#L487-1 assume !(1 == ~T3_E~0); 26415#L492-1 assume !(1 == ~E_M~0); 26229#L497-1 assume !(1 == ~E_1~0); 26230#L502-1 assume !(1 == ~E_2~0); 26212#L507-1 assume !(1 == ~E_3~0); 26213#L512-1 assume { :end_inline_reset_delta_events } true; 26356#L678-2 [2021-12-21 22:38:21,308 INFO L793 eck$LassoCheckResult]: Loop: 26356#L678-2 assume !false; 27231#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27227#L404 assume !false; 27226#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27224#L320 assume !(0 == ~m_st~0); 27225#L324 assume !(0 == ~t1_st~0); 27221#L328 assume !(0 == ~t2_st~0); 27222#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 27223#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27075#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27076#L357 assume !(0 != eval_~tmp~0#1); 27318#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27317#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27316#L429-3 assume !(0 == ~M_E~0); 27315#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27314#L434-3 assume !(0 == ~T2_E~0); 27313#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27312#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27311#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27310#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27309#L459-3 assume !(0 == ~E_3~0); 26263#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26264#L208-15 assume !(1 == ~m_pc~0); 26491#L208-17 is_master_triggered_~__retres1~0#1 := 0; 27358#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27357#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27356#L531-15 assume !(0 != activate_threads_~tmp~1#1); 27355#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27354#L227-15 assume 1 == ~t1_pc~0; 27352#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27351#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27350#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27349#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27348#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27347#L246-15 assume !(1 == ~t2_pc~0); 26878#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 27346#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27345#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27344#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27343#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27342#L265-15 assume !(1 == ~t3_pc~0); 27340#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 27339#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27338#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27337#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27336#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27335#L477-3 assume !(1 == ~M_E~0); 27159#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27334#L482-3 assume !(1 == ~T2_E~0); 27333#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27332#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27331#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27330#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27329#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27328#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27325#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27323#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27322#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 26460#L697 assume !(0 == start_simulation_~tmp~3#1); 26461#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 27249#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27245#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27243#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 27241#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27239#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27237#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 27234#L710 assume !(0 != start_simulation_~tmp___0~1#1); 26356#L678-2 [2021-12-21 22:38:21,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2021-12-21 22:38:21,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048969930] [2021-12-21 22:38:21,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,313 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,320 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,320 INFO L85 PathProgramCache]: Analyzing trace with hash 2144031309, now seen corresponding path program 1 times [2021-12-21 22:38:21,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037810912] [2021-12-21 22:38:21,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,321 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:21,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:21,334 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:21,335 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037810912] [2021-12-21 22:38:21,335 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037810912] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:21,335 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:21,335 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:21,335 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496958465] [2021-12-21 22:38:21,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:21,335 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:21,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:21,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:21,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:21,336 INFO L87 Difference]: Start difference. First operand 1833 states and 2597 transitions. cyclomatic complexity: 766 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:21,376 INFO L93 Difference]: Finished difference Result 2824 states and 3942 transitions. [2021-12-21 22:38:21,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:21,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2824 states and 3942 transitions. [2021-12-21 22:38:21,384 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2767 [2021-12-21 22:38:21,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2824 states to 2824 states and 3942 transitions. [2021-12-21 22:38:21,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2824 [2021-12-21 22:38:21,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2824 [2021-12-21 22:38:21,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2824 states and 3942 transitions. [2021-12-21 22:38:21,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:21,395 INFO L681 BuchiCegarLoop]: Abstraction has 2824 states and 3942 transitions. [2021-12-21 22:38:21,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2824 states and 3942 transitions. [2021-12-21 22:38:21,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2824 to 2734. [2021-12-21 22:38:21,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2734 states to 2734 states and 3820 transitions. [2021-12-21 22:38:21,422 INFO L704 BuchiCegarLoop]: Abstraction has 2734 states and 3820 transitions. [2021-12-21 22:38:21,422 INFO L587 BuchiCegarLoop]: Abstraction has 2734 states and 3820 transitions. [2021-12-21 22:38:21,422 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-21 22:38:21,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2734 states and 3820 transitions. [2021-12-21 22:38:21,427 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2677 [2021-12-21 22:38:21,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:21,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:21,427 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,427 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,427 INFO L791 eck$LassoCheckResult]: Stem: 31177#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 31117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 31118#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31123#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31010#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 31011#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31107#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31089#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31090#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31097#L429 assume !(0 == ~M_E~0); 30917#L429-2 assume !(0 == ~T1_E~0); 30918#L434-1 assume !(0 == ~T2_E~0); 31040#L439-1 assume !(0 == ~T3_E~0); 31065#L444-1 assume !(0 == ~E_M~0); 31066#L449-1 assume !(0 == ~E_1~0); 30925#L454-1 assume !(0 == ~E_2~0); 30926#L459-1 assume !(0 == ~E_3~0); 30883#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30884#L208 assume !(1 == ~m_pc~0); 31167#L208-2 is_master_triggered_~__retres1~0#1 := 0; 31168#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30954#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30904#L531 assume !(0 != activate_threads_~tmp~1#1); 30905#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31014#L227 assume !(1 == ~t1_pc~0); 30902#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30903#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31098#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30921#L539 assume !(0 != activate_threads_~tmp___0~0#1); 30922#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30955#L246 assume !(1 == ~t2_pc~0); 30956#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31043#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31044#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31106#L547 assume !(0 != activate_threads_~tmp___1~0#1); 31112#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30964#L265 assume !(1 == ~t3_pc~0); 30846#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30819#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30820#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31047#L555 assume !(0 != activate_threads_~tmp___2~0#1); 30938#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30939#L477 assume !(1 == ~M_E~0); 31102#L477-2 assume !(1 == ~T1_E~0); 31119#L482-1 assume !(1 == ~T2_E~0); 31063#L487-1 assume !(1 == ~T3_E~0); 31064#L492-1 assume !(1 == ~E_M~0); 30892#L497-1 assume !(1 == ~E_1~0); 30893#L502-1 assume !(1 == ~E_2~0); 30873#L507-1 assume !(1 == ~E_3~0); 30874#L512-1 assume { :end_inline_reset_delta_events } true; 31012#L678-2 assume !false; 33000#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32996#L404 [2021-12-21 22:38:21,427 INFO L793 eck$LassoCheckResult]: Loop: 32996#L404 assume !false; 32991#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32990#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32985#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32984#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 32983#L357 assume 0 != eval_~tmp~0#1; 32982#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 30929#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 30930#L362 assume !(0 == ~t1_st~0); 32902#L376 assume !(0 == ~t2_st~0); 32895#L390 assume !(0 == ~t3_st~0); 32996#L404 [2021-12-21 22:38:21,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2021-12-21 22:38:21,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470404788] [2021-12-21 22:38:21,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,432 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,439 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,440 INFO L85 PathProgramCache]: Analyzing trace with hash 257277008, now seen corresponding path program 1 times [2021-12-21 22:38:21,440 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535529380] [2021-12-21 22:38:21,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,440 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,442 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,444 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,444 INFO L85 PathProgramCache]: Analyzing trace with hash 1138955338, now seen corresponding path program 1 times [2021-12-21 22:38:21,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740428673] [2021-12-21 22:38:21,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:21,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:21,459 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:21,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740428673] [2021-12-21 22:38:21,459 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740428673] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:21,459 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:21,459 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:21,459 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1349802520] [2021-12-21 22:38:21,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:21,528 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:21,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:21,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:21,528 INFO L87 Difference]: Start difference. First operand 2734 states and 3820 transitions. cyclomatic complexity: 1089 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:21,563 INFO L93 Difference]: Finished difference Result 4892 states and 6761 transitions. [2021-12-21 22:38:21,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:21,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4892 states and 6761 transitions. [2021-12-21 22:38:21,578 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4784 [2021-12-21 22:38:21,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4892 states to 4892 states and 6761 transitions. [2021-12-21 22:38:21,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4892 [2021-12-21 22:38:21,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4892 [2021-12-21 22:38:21,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4892 states and 6761 transitions. [2021-12-21 22:38:21,604 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:21,604 INFO L681 BuchiCegarLoop]: Abstraction has 4892 states and 6761 transitions. [2021-12-21 22:38:21,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4892 states and 6761 transitions. [2021-12-21 22:38:21,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4892 to 4647. [2021-12-21 22:38:21,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4647 states to 4647 states and 6446 transitions. [2021-12-21 22:38:21,692 INFO L704 BuchiCegarLoop]: Abstraction has 4647 states and 6446 transitions. [2021-12-21 22:38:21,692 INFO L587 BuchiCegarLoop]: Abstraction has 4647 states and 6446 transitions. [2021-12-21 22:38:21,692 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-21 22:38:21,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4647 states and 6446 transitions. [2021-12-21 22:38:21,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2021-12-21 22:38:21,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:21,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:21,702 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,702 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,702 INFO L791 eck$LassoCheckResult]: Stem: 38875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 38799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 38800#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38805#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38654#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 38655#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 38786#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38763#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38764#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38772#L429 assume !(0 == ~M_E~0); 38554#L429-2 assume !(0 == ~T1_E~0); 38555#L434-1 assume !(0 == ~T2_E~0); 38702#L439-1 assume !(0 == ~T3_E~0); 38737#L444-1 assume !(0 == ~E_M~0); 38738#L449-1 assume !(0 == ~E_1~0); 39875#L454-1 assume !(0 == ~E_2~0); 39873#L459-1 assume !(0 == ~E_3~0); 39872#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39871#L208 assume !(1 == ~m_pc~0); 39870#L208-2 is_master_triggered_~__retres1~0#1 := 0; 39869#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39868#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38541#L531 assume !(0 != activate_threads_~tmp~1#1); 38542#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38664#L227 assume !(1 == ~t1_pc~0); 38665#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38773#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38774#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38558#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38559#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38696#L246 assume !(1 == ~t2_pc~0); 38754#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38755#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38783#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38784#L547 assume !(0 != activate_threads_~tmp___1~0#1); 38811#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38812#L265 assume !(1 == ~t3_pc~0); 38481#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38480#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38711#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38712#L555 assume !(0 != activate_threads_~tmp___2~0#1); 38571#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38572#L477 assume !(1 == ~M_E~0); 38835#L477-2 assume !(1 == ~T1_E~0); 38836#L482-1 assume !(1 == ~T2_E~0); 38732#L487-1 assume !(1 == ~T3_E~0); 38733#L492-1 assume !(1 == ~E_M~0); 38526#L497-1 assume !(1 == ~E_1~0); 38527#L502-1 assume !(1 == ~E_2~0); 38505#L507-1 assume !(1 == ~E_3~0); 38506#L512-1 assume { :end_inline_reset_delta_events } true; 38662#L678-2 assume !false; 40200#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40195#L404 [2021-12-21 22:38:21,702 INFO L793 eck$LassoCheckResult]: Loop: 40195#L404 assume !false; 40193#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40190#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40188#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40185#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40169#L357 assume 0 != eval_~tmp~0#1; 40170#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40179#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 40177#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39820#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 40172#L376 assume !(0 == ~t2_st~0); 40165#L390 assume !(0 == ~t3_st~0); 40195#L404 [2021-12-21 22:38:21,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,702 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2021-12-21 22:38:21,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,703 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992050207] [2021-12-21 22:38:21,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,703 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:21,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:21,718 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:21,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992050207] [2021-12-21 22:38:21,718 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992050207] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:21,718 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:21,718 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:21,718 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414870198] [2021-12-21 22:38:21,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:21,720 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:21,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,720 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 1 times [2021-12-21 22:38:21,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23395896] [2021-12-21 22:38:21,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,722 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,725 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,728 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,798 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:21,799 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:21,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:21,799 INFO L87 Difference]: Start difference. First operand 4647 states and 6446 transitions. cyclomatic complexity: 1802 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:21,814 INFO L93 Difference]: Finished difference Result 4598 states and 6377 transitions. [2021-12-21 22:38:21,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:21,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4598 states and 6377 transitions. [2021-12-21 22:38:21,826 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2021-12-21 22:38:21,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4598 states to 4598 states and 6377 transitions. [2021-12-21 22:38:21,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4598 [2021-12-21 22:38:21,848 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4598 [2021-12-21 22:38:21,848 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4598 states and 6377 transitions. [2021-12-21 22:38:21,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:21,852 INFO L681 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2021-12-21 22:38:21,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4598 states and 6377 transitions. [2021-12-21 22:38:21,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4598 to 4598. [2021-12-21 22:38:21,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:21,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4598 states to 4598 states and 6377 transitions. [2021-12-21 22:38:21,913 INFO L704 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2021-12-21 22:38:21,913 INFO L587 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2021-12-21 22:38:21,913 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-21 22:38:21,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4598 states and 6377 transitions. [2021-12-21 22:38:21,921 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2021-12-21 22:38:21,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:21,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:21,922 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,922 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:21,922 INFO L791 eck$LassoCheckResult]: Stem: 48081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 48022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 48023#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48027#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47899#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 47900#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48011#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47990#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47991#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48000#L429 assume !(0 == ~M_E~0); 47806#L429-2 assume !(0 == ~T1_E~0); 47807#L434-1 assume !(0 == ~T2_E~0); 47939#L439-1 assume !(0 == ~T3_E~0); 47967#L444-1 assume !(0 == ~E_M~0); 47968#L449-1 assume !(0 == ~E_1~0); 47812#L454-1 assume !(0 == ~E_2~0); 47813#L459-1 assume !(0 == ~E_3~0); 47770#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47771#L208 assume !(1 == ~m_pc~0); 48073#L208-2 is_master_triggered_~__retres1~0#1 := 0; 48074#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47843#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 47792#L531 assume !(0 != activate_threads_~tmp~1#1); 47793#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47909#L227 assume !(1 == ~t1_pc~0); 47790#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47791#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48001#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 47810#L539 assume !(0 != activate_threads_~tmp___0~0#1); 47811#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47844#L246 assume !(1 == ~t2_pc~0); 47845#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47943#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47944#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48009#L547 assume !(0 != activate_threads_~tmp___1~0#1); 48016#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47852#L265 assume !(1 == ~t3_pc~0); 47733#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47704#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47705#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47946#L555 assume !(0 != activate_threads_~tmp___2~0#1); 47822#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47823#L477 assume !(1 == ~M_E~0); 48007#L477-2 assume !(1 == ~T1_E~0); 48024#L482-1 assume !(1 == ~T2_E~0); 47962#L487-1 assume !(1 == ~T3_E~0); 47963#L492-1 assume !(1 == ~E_M~0); 47776#L497-1 assume !(1 == ~E_1~0); 47777#L502-1 assume !(1 == ~E_2~0); 47757#L507-1 assume !(1 == ~E_3~0); 47758#L512-1 assume { :end_inline_reset_delta_events } true; 47907#L678-2 assume !false; 49559#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49552#L404 [2021-12-21 22:38:21,922 INFO L793 eck$LassoCheckResult]: Loop: 49552#L404 assume !false; 49550#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 49547#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 49545#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 49544#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49542#L357 assume 0 != eval_~tmp~0#1; 49534#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 49529#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 49524#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 49071#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 49517#L376 assume !(0 == ~t2_st~0); 49558#L390 assume !(0 == ~t3_st~0); 49552#L404 [2021-12-21 22:38:21,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2021-12-21 22:38:21,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220098978] [2021-12-21 22:38:21,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,923 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,930 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,940 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,941 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 2 times [2021-12-21 22:38:21,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156730565] [2021-12-21 22:38:21,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,944 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:21,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:21,947 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:21,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:21,947 INFO L85 PathProgramCache]: Analyzing trace with hash 943838511, now seen corresponding path program 1 times [2021-12-21 22:38:21,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:21,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189520123] [2021-12-21 22:38:21,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:21,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:21,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:21,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:21,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:21,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189520123] [2021-12-21 22:38:21,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189520123] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:21,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:21,972 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:21,972 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139666551] [2021-12-21 22:38:21,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:22,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:22,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:22,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:22,047 INFO L87 Difference]: Start difference. First operand 4598 states and 6377 transitions. cyclomatic complexity: 1782 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:22,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:22,123 INFO L93 Difference]: Finished difference Result 8299 states and 11428 transitions. [2021-12-21 22:38:22,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:22,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8299 states and 11428 transitions. [2021-12-21 22:38:22,143 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8236 [2021-12-21 22:38:22,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8299 states to 8299 states and 11428 transitions. [2021-12-21 22:38:22,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8299 [2021-12-21 22:38:22,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8299 [2021-12-21 22:38:22,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8299 states and 11428 transitions. [2021-12-21 22:38:22,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:22,166 INFO L681 BuchiCegarLoop]: Abstraction has 8299 states and 11428 transitions. [2021-12-21 22:38:22,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8299 states and 11428 transitions. [2021-12-21 22:38:22,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8299 to 8145. [2021-12-21 22:38:22,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:22,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8145 states to 8145 states and 11232 transitions. [2021-12-21 22:38:22,252 INFO L704 BuchiCegarLoop]: Abstraction has 8145 states and 11232 transitions. [2021-12-21 22:38:22,252 INFO L587 BuchiCegarLoop]: Abstraction has 8145 states and 11232 transitions. [2021-12-21 22:38:22,252 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-21 22:38:22,252 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8145 states and 11232 transitions. [2021-12-21 22:38:22,271 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8082 [2021-12-21 22:38:22,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:22,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:22,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:22,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:22,271 INFO L791 eck$LassoCheckResult]: Stem: 60990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 60928#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 60929#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60934#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60804#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 60805#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60914#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60895#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60896#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60904#L429 assume !(0 == ~M_E~0); 60708#L429-2 assume !(0 == ~T1_E~0); 60709#L434-1 assume !(0 == ~T2_E~0); 60841#L439-1 assume !(0 == ~T3_E~0); 60870#L444-1 assume !(0 == ~E_M~0); 60871#L449-1 assume !(0 == ~E_1~0); 60714#L454-1 assume !(0 == ~E_2~0); 60715#L459-1 assume !(0 == ~E_3~0); 60673#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60674#L208 assume !(1 == ~m_pc~0); 60978#L208-2 is_master_triggered_~__retres1~0#1 := 0; 60979#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60745#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 60695#L531 assume !(0 != activate_threads_~tmp~1#1); 60696#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60814#L227 assume !(1 == ~t1_pc~0); 60693#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60694#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60905#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60712#L539 assume !(0 != activate_threads_~tmp___0~0#1); 60713#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60746#L246 assume !(1 == ~t2_pc~0); 60747#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60846#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60847#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60912#L547 assume !(0 != activate_threads_~tmp___1~0#1); 60922#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60754#L265 assume !(1 == ~t3_pc~0); 60636#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60609#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60610#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60850#L555 assume !(0 != activate_threads_~tmp___2~0#1); 60724#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60725#L477 assume !(1 == ~M_E~0); 60911#L477-2 assume !(1 == ~T1_E~0); 60930#L482-1 assume !(1 == ~T2_E~0); 60865#L487-1 assume !(1 == ~T3_E~0); 60866#L492-1 assume !(1 == ~E_M~0); 60679#L497-1 assume !(1 == ~E_1~0); 60680#L502-1 assume !(1 == ~E_2~0); 60660#L507-1 assume !(1 == ~E_3~0); 60661#L512-1 assume { :end_inline_reset_delta_events } true; 60812#L678-2 assume !false; 63423#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63382#L404 [2021-12-21 22:38:22,271 INFO L793 eck$LassoCheckResult]: Loop: 63382#L404 assume !false; 63373#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 63366#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 63357#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 63349#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 63343#L357 assume 0 != eval_~tmp~0#1; 63200#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 63196#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 63166#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 63167#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 63014#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 62889#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 62891#L390 assume !(0 == ~t3_st~0); 63382#L404 [2021-12-21 22:38:22,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:22,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2021-12-21 22:38:22,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:22,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851737582] [2021-12-21 22:38:22,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:22,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:22,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:22,276 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:22,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:22,282 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:22,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:22,282 INFO L85 PathProgramCache]: Analyzing trace with hash -1990224393, now seen corresponding path program 1 times [2021-12-21 22:38:22,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:22,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955823525] [2021-12-21 22:38:22,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:22,282 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:22,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:22,284 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:22,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:22,286 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:22,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:22,286 INFO L85 PathProgramCache]: Analyzing trace with hash -805906575, now seen corresponding path program 1 times [2021-12-21 22:38:22,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:22,287 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443138741] [2021-12-21 22:38:22,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:22,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:22,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:22,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:22,300 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:22,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443138741] [2021-12-21 22:38:22,300 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443138741] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:22,300 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:22,300 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:22,300 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983690483] [2021-12-21 22:38:22,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:22,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:22,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:22,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:22,378 INFO L87 Difference]: Start difference. First operand 8145 states and 11232 transitions. cyclomatic complexity: 3090 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:22,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:22,505 INFO L93 Difference]: Finished difference Result 13631 states and 18694 transitions. [2021-12-21 22:38:22,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:22,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13631 states and 18694 transitions. [2021-12-21 22:38:22,621 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13560 [2021-12-21 22:38:22,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13631 states to 13631 states and 18694 transitions. [2021-12-21 22:38:22,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13631 [2021-12-21 22:38:22,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13631 [2021-12-21 22:38:22,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13631 states and 18694 transitions. [2021-12-21 22:38:22,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:22,725 INFO L681 BuchiCegarLoop]: Abstraction has 13631 states and 18694 transitions. [2021-12-21 22:38:22,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13631 states and 18694 transitions. [2021-12-21 22:38:22,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13631 to 13407. [2021-12-21 22:38:23,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:23,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13407 states to 13407 states and 18470 transitions. [2021-12-21 22:38:23,050 INFO L704 BuchiCegarLoop]: Abstraction has 13407 states and 18470 transitions. [2021-12-21 22:38:23,050 INFO L587 BuchiCegarLoop]: Abstraction has 13407 states and 18470 transitions. [2021-12-21 22:38:23,050 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-21 22:38:23,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13407 states and 18470 transitions. [2021-12-21 22:38:23,137 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13336 [2021-12-21 22:38:23,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:23,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:23,138 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:23,138 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:23,138 INFO L791 eck$LassoCheckResult]: Stem: 82772#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 82716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 82717#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82721#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82589#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 82590#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82703#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82685#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82686#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82694#L429 assume !(0 == ~M_E~0); 82492#L429-2 assume !(0 == ~T1_E~0); 82493#L434-1 assume !(0 == ~T2_E~0); 82628#L439-1 assume !(0 == ~T3_E~0); 82658#L444-1 assume !(0 == ~E_M~0); 82659#L449-1 assume !(0 == ~E_1~0); 82498#L454-1 assume !(0 == ~E_2~0); 82499#L459-1 assume !(0 == ~E_3~0); 82458#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82459#L208 assume !(1 == ~m_pc~0); 82761#L208-2 is_master_triggered_~__retres1~0#1 := 0; 82762#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82529#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 82479#L531 assume !(0 != activate_threads_~tmp~1#1); 82480#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82600#L227 assume !(1 == ~t1_pc~0); 82477#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82478#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82695#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 82496#L539 assume !(0 != activate_threads_~tmp___0~0#1); 82497#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82530#L246 assume !(1 == ~t2_pc~0); 82531#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82634#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82635#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82701#L547 assume !(0 != activate_threads_~tmp___1~0#1); 82708#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82538#L265 assume !(1 == ~t3_pc~0); 82420#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82393#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82394#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82639#L555 assume !(0 != activate_threads_~tmp___2~0#1); 82508#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82509#L477 assume !(1 == ~M_E~0); 82700#L477-2 assume !(1 == ~T1_E~0); 82718#L482-1 assume !(1 == ~T2_E~0); 82653#L487-1 assume !(1 == ~T3_E~0); 82654#L492-1 assume !(1 == ~E_M~0); 82463#L497-1 assume !(1 == ~E_1~0); 82464#L502-1 assume !(1 == ~E_2~0); 82444#L507-1 assume !(1 == ~E_3~0); 82445#L512-1 assume { :end_inline_reset_delta_events } true; 82597#L678-2 assume !false; 86323#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86320#L404 [2021-12-21 22:38:23,138 INFO L793 eck$LassoCheckResult]: Loop: 86320#L404 assume !false; 86318#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 86315#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 86314#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 86292#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86291#L357 assume 0 != eval_~tmp~0#1; 86287#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 86282#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 86283#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 86728#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 86360#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 86340#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 86341#L390 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 86321#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 86320#L404 [2021-12-21 22:38:23,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:23,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2021-12-21 22:38:23,138 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:23,139 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545753903] [2021-12-21 22:38:23,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:23,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:23,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,143 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:23,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,203 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:23,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:23,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1567417278, now seen corresponding path program 1 times [2021-12-21 22:38:23,203 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:23,203 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082746241] [2021-12-21 22:38:23,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:23,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:23,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,206 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:23,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,208 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:23,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:23,208 INFO L85 PathProgramCache]: Analyzing trace with hash 786696712, now seen corresponding path program 1 times [2021-12-21 22:38:23,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:23,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568706542] [2021-12-21 22:38:23,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:23,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:23,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,229 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-21 22:38:23,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-21 22:38:23,251 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-21 22:38:24,142 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.12 10:38:24 BoogieIcfgContainer [2021-12-21 22:38:24,143 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-21 22:38:24,143 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-21 22:38:24,143 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-21 22:38:24,143 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-21 22:38:24,144 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.12 10:38:19" (3/4) ... [2021-12-21 22:38:24,145 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-21 22:38:24,173 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-21 22:38:24,173 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-21 22:38:24,173 INFO L158 Benchmark]: Toolchain (without parser) took 5948.35ms. Allocated memory was 119.5MB in the beginning and 482.3MB in the end (delta: 362.8MB). Free memory was 89.0MB in the beginning and 260.4MB in the end (delta: -171.4MB). Peak memory consumption was 191.4MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,173 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 86.0MB. Free memory was 46.0MB in the beginning and 46.0MB in the end (delta: 42.1kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-21 22:38:24,173 INFO L158 Benchmark]: CACSL2BoogieTranslator took 252.33ms. Allocated memory is still 119.5MB. Free memory was 88.6MB in the beginning and 93.3MB in the end (delta: -4.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,174 INFO L158 Benchmark]: Boogie Procedure Inliner took 32.82ms. Allocated memory is still 119.5MB. Free memory was 93.3MB in the beginning and 89.6MB in the end (delta: 3.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,174 INFO L158 Benchmark]: Boogie Preprocessor took 32.57ms. Allocated memory is still 119.5MB. Free memory was 89.6MB in the beginning and 87.0MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,174 INFO L158 Benchmark]: RCFGBuilder took 556.65ms. Allocated memory is still 119.5MB. Free memory was 86.4MB in the beginning and 56.0MB in the end (delta: 30.4MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,174 INFO L158 Benchmark]: BuchiAutomizer took 5038.41ms. Allocated memory was 119.5MB in the beginning and 482.3MB in the end (delta: 362.8MB). Free memory was 56.0MB in the beginning and 264.6MB in the end (delta: -208.5MB). Peak memory consumption was 156.4MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,175 INFO L158 Benchmark]: Witness Printer took 29.46ms. Allocated memory is still 482.3MB. Free memory was 264.6MB in the beginning and 260.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-21 22:38:24,176 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 86.0MB. Free memory was 46.0MB in the beginning and 46.0MB in the end (delta: 42.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 252.33ms. Allocated memory is still 119.5MB. Free memory was 88.6MB in the beginning and 93.3MB in the end (delta: -4.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 32.82ms. Allocated memory is still 119.5MB. Free memory was 93.3MB in the beginning and 89.6MB in the end (delta: 3.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 32.57ms. Allocated memory is still 119.5MB. Free memory was 89.6MB in the beginning and 87.0MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 556.65ms. Allocated memory is still 119.5MB. Free memory was 86.4MB in the beginning and 56.0MB in the end (delta: 30.4MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 5038.41ms. Allocated memory was 119.5MB in the beginning and 482.3MB in the end (delta: 362.8MB). Free memory was 56.0MB in the beginning and 264.6MB in the end (delta: -208.5MB). Peak memory consumption was 156.4MB. Max. memory is 16.1GB. * Witness Printer took 29.46ms. Allocated memory is still 482.3MB. Free memory was 264.6MB in the beginning and 260.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13407 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.3s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 15 MinimizatonAttempts, 5665 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 13407 states and ocurred in iteration 15. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9253 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9253 mSDsluCounter, 14655 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7271 mSDsCounter, 152 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 351 IncrementalHoareTripleChecker+Invalid, 503 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 152 mSolverCounterUnsat, 7384 mSDtfsCounter, 351 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2bb9fe30=0, token=0, NULL=1, tmp=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65a891cf=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4455954f=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@548407c=0, tmp_ndt_2=0, E_3=2, E_1=2, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3cc0f16a=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35fffe4d=0, m_st=0, NULL=0, t3_pc=0, __retres1=0, tmp___0=0, tmp___2=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@562920a7=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6a45e8dc=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1308f9d9=0, __retres1=0, M_E=2, __retres1=1, t2_i=1, \result=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@56202507=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6196eabc=0, t1_st=0, __retres1=0, local=0, t2_pc=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) [L434] COND FALSE !(T1_E == 0) [L439] COND FALSE !(T2_E == 0) [L444] COND FALSE !(T3_E == 0) [L449] COND FALSE !(E_M == 0) [L454] COND FALSE !(E_1 == 0) [L459] COND FALSE !(E_2 == 0) [L464] COND FALSE !(E_3 == 0) [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; [L208] COND FALSE !(m_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; [L227] COND FALSE !(t1_pc == 1) [L237] __retres1 = 0 [L239] return (__retres1); [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; [L246] COND FALSE !(t2_pc == 1) [L256] __retres1 = 0 [L258] return (__retres1); [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; [L265] COND FALSE !(t3_pc == 1) [L275] __retres1 = 0 [L277] return (__retres1); [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) [L482] COND FALSE !(T1_E == 1) [L487] COND FALSE !(T2_E == 1) [L492] COND FALSE !(T3_E == 1) [L497] COND FALSE !(E_M == 1) [L502] COND FALSE !(E_1 == 1) [L507] COND FALSE !(E_2 == 1) [L512] COND FALSE !(E_3 == 1) [L675] RET reset_delta_events() [L678] COND TRUE 1 [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-21 22:38:24,208 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)