./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version ff03de63 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.2-dev-ff03de6 [2021-12-21 22:38:32,003 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-21 22:38:32,005 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-21 22:38:32,029 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-21 22:38:32,030 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-21 22:38:32,033 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-21 22:38:32,034 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-21 22:38:32,039 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-21 22:38:32,040 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-21 22:38:32,044 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-21 22:38:32,044 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-21 22:38:32,045 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-21 22:38:32,046 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-21 22:38:32,047 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-21 22:38:32,048 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-21 22:38:32,049 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-21 22:38:32,050 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-21 22:38:32,050 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-21 22:38:32,053 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-21 22:38:32,057 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-21 22:38:32,058 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-21 22:38:32,059 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-21 22:38:32,060 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-21 22:38:32,061 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-21 22:38:32,066 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-21 22:38:32,066 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-21 22:38:32,066 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-21 22:38:32,067 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-21 22:38:32,068 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-21 22:38:32,068 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-21 22:38:32,069 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-21 22:38:32,069 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-21 22:38:32,071 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-21 22:38:32,071 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-21 22:38:32,072 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-21 22:38:32,072 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-21 22:38:32,073 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-21 22:38:32,073 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-21 22:38:32,073 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-21 22:38:32,074 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-21 22:38:32,074 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-21 22:38:32,075 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-21 22:38:32,105 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-21 22:38:32,105 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-21 22:38:32,105 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-21 22:38:32,106 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-21 22:38:32,107 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-21 22:38:32,107 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-21 22:38:32,107 INFO L138 SettingsManager]: * Use SBE=true [2021-12-21 22:38:32,107 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-21 22:38:32,107 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-21 22:38:32,107 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-21 22:38:32,108 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-21 22:38:32,108 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-21 22:38:32,108 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-21 22:38:32,108 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-21 22:38:32,109 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-21 22:38:32,110 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-21 22:38:32,110 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-21 22:38:32,110 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-21 22:38:32,111 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-21 22:38:32,111 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-21 22:38:32,111 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-21 22:38:32,111 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-21 22:38:32,111 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-21 22:38:32,112 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-21 22:38:32,112 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-21 22:38:32,112 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-21 22:38:32,113 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-21 22:38:32,113 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2021-12-21 22:38:32,309 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-21 22:38:32,329 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-21 22:38:32,331 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-21 22:38:32,332 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-21 22:38:32,332 INFO L275 PluginConnector]: CDTParser initialized [2021-12-21 22:38:32,333 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2021-12-21 22:38:32,382 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ea6ac732/2b88393dd49a4bbc89fa97d584e65dba/FLAG33d7d6d32 [2021-12-21 22:38:32,800 INFO L306 CDTParser]: Found 1 translation units. [2021-12-21 22:38:32,801 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2021-12-21 22:38:32,818 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ea6ac732/2b88393dd49a4bbc89fa97d584e65dba/FLAG33d7d6d32 [2021-12-21 22:38:33,163 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2ea6ac732/2b88393dd49a4bbc89fa97d584e65dba [2021-12-21 22:38:33,165 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-21 22:38:33,166 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-21 22:38:33,167 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-21 22:38:33,167 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-21 22:38:33,185 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-21 22:38:33,186 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,187 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11e8365 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33, skipping insertion in model container [2021-12-21 22:38:33,187 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,192 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-21 22:38:33,222 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-21 22:38:33,307 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2021-12-21 22:38:33,421 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-21 22:38:33,437 INFO L203 MainTranslator]: Completed pre-run [2021-12-21 22:38:33,448 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c[671,684] [2021-12-21 22:38:33,505 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-21 22:38:33,521 INFO L208 MainTranslator]: Completed translation [2021-12-21 22:38:33,522 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33 WrapperNode [2021-12-21 22:38:33,522 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-21 22:38:33,523 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-21 22:38:33,523 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-21 22:38:33,523 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-21 22:38:33,531 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,554 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,655 INFO L137 Inliner]: procedures = 48, calls = 62, calls flagged for inlining = 57, calls inlined = 210, statements flattened = 3198 [2021-12-21 22:38:33,655 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-21 22:38:33,656 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-21 22:38:33,656 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-21 22:38:33,656 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-21 22:38:33,662 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,662 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,671 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,672 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,711 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,734 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,751 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,763 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-21 22:38:33,767 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-21 22:38:33,767 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-21 22:38:33,768 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-21 22:38:33,768 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (1/1) ... [2021-12-21 22:38:33,774 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-21 22:38:33,786 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-21 22:38:33,797 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-21 22:38:33,806 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-21 22:38:33,835 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-21 22:38:33,835 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-21 22:38:33,835 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-21 22:38:33,835 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-21 22:38:33,927 INFO L234 CfgBuilder]: Building ICFG [2021-12-21 22:38:33,929 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-21 22:38:35,184 INFO L275 CfgBuilder]: Performing block encoding [2021-12-21 22:38:35,201 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-21 22:38:35,202 INFO L299 CfgBuilder]: Removed 13 assume(true) statements. [2021-12-21 22:38:35,205 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.12 10:38:35 BoogieIcfgContainer [2021-12-21 22:38:35,205 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-21 22:38:35,207 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-21 22:38:35,207 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-21 22:38:35,209 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-21 22:38:35,209 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:35,210 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.12 10:38:33" (1/3) ... [2021-12-21 22:38:35,211 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19d005a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.12 10:38:35, skipping insertion in model container [2021-12-21 22:38:35,211 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:35,211 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.12 10:38:33" (2/3) ... [2021-12-21 22:38:35,211 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@19d005a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.12 10:38:35, skipping insertion in model container [2021-12-21 22:38:35,211 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-21 22:38:35,211 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.12 10:38:35" (3/3) ... [2021-12-21 22:38:35,212 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2021-12-21 22:38:35,248 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-21 22:38:35,248 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-21 22:38:35,248 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-21 22:38:35,248 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-21 22:38:35,248 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-21 22:38:35,248 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-21 22:38:35,248 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-21 22:38:35,248 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-21 22:38:35,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:35,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2021-12-21 22:38:35,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:35,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:35,361 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,361 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-21 22:38:35,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:35,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1231 [2021-12-21 22:38:35,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:35,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:35,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,387 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,397 INFO L791 eck$LassoCheckResult]: Stem: 667#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1260#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 970#L1528true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24#L724true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1154#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 1022#L731-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 933#L736-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 999#L741-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1316#L746-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 174#L751-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 232#L756-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 833#L761-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 386#L766-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 339#L771-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 175#L776-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13#L781-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58#L1036true assume !(0 == ~M_E~0); 1028#L1036-2true assume !(0 == ~T1_E~0); 609#L1041-1true assume !(0 == ~T2_E~0); 971#L1046-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 197#L1051-1true assume !(0 == ~T4_E~0); 748#L1056-1true assume !(0 == ~T5_E~0); 797#L1061-1true assume !(0 == ~T6_E~0); 143#L1066-1true assume !(0 == ~T7_E~0); 1149#L1071-1true assume !(0 == ~T8_E~0); 729#L1076-1true assume !(0 == ~T9_E~0); 91#L1081-1true assume !(0 == ~T10_E~0); 309#L1086-1true assume 0 == ~E_M~0;~E_M~0 := 1; 1169#L1091-1true assume !(0 == ~E_1~0); 1030#L1096-1true assume !(0 == ~E_2~0); 1265#L1101-1true assume !(0 == ~E_3~0); 350#L1106-1true assume !(0 == ~E_4~0); 548#L1111-1true assume !(0 == ~E_5~0); 459#L1116-1true assume !(0 == ~E_6~0); 1087#L1121-1true assume !(0 == ~E_7~0); 345#L1126-1true assume 0 == ~E_8~0;~E_8~0 := 1; 530#L1131-1true assume !(0 == ~E_9~0); 619#L1136-1true assume !(0 == ~E_10~0); 899#L1141-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785#L514true assume 1 == ~m_pc~0; 738#L515true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 356#L525true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 302#L526true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1101#L1285true assume !(0 != activate_threads_~tmp~1#1); 1187#L1285-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151#L533true assume !(1 == ~t1_pc~0); 1042#L533-2true is_transmit1_triggered_~__retres1~1#1 := 0; 499#L544true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 380#L545true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 911#L1293true assume !(0 != activate_threads_~tmp___0~0#1); 643#L1293-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L552true assume 1 == ~t2_pc~0; 276#L553true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 934#L563true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 714#L564true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 976#L1301true assume !(0 != activate_threads_~tmp___1~0#1); 365#L1301-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 511#L571true assume 1 == ~t3_pc~0; 496#L572true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 684#L582true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111#L583true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 653#L1309true assume !(0 != activate_threads_~tmp___2~0#1); 462#L1309-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50#L590true assume !(1 == ~t4_pc~0); 510#L590-2true is_transmit4_triggered_~__retres1~4#1 := 0; 1286#L601true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 709#L602true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1112#L1317true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 668#L1317-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 460#L609true assume 1 == ~t5_pc~0; 1276#L610true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1098#L620true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69#L621true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1376#L1325true assume !(0 != activate_threads_~tmp___4~0#1); 455#L1325-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1275#L628true assume !(1 == ~t6_pc~0); 531#L628-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1254#L639true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1061#L640true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1178#L1333true assume !(0 != activate_threads_~tmp___5~0#1); 707#L1333-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 842#L647true assume 1 == ~t7_pc~0; 351#L648true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 888#L658true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 556#L659true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 352#L1341true assume !(0 != activate_threads_~tmp___6~0#1); 1248#L1341-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1218#L666true assume !(1 == ~t8_pc~0); 783#L666-2true is_transmit8_triggered_~__retres1~8#1 := 0; 364#L677true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 815#L678true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 477#L1349true assume !(0 != activate_threads_~tmp___7~0#1); 307#L1349-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1131#L685true assume 1 == ~t9_pc~0; 1296#L686true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 913#L696true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 893#L697true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 323#L1357true assume !(0 != activate_threads_~tmp___8~0#1); 1008#L1357-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 587#L704true assume !(1 == ~t10_pc~0); 1083#L704-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1036#L715true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L716true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78#L1365true assume !(0 != activate_threads_~tmp___9~0#1); 202#L1365-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 696#L1154true assume !(1 == ~M_E~0); 1175#L1154-2true assume !(1 == ~T1_E~0); 186#L1159-1true assume !(1 == ~T2_E~0); 1306#L1164-1true assume !(1 == ~T3_E~0); 475#L1169-1true assume !(1 == ~T4_E~0); 383#L1174-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 257#L1179-1true assume !(1 == ~T6_E~0); 179#L1184-1true assume !(1 == ~T7_E~0); 221#L1189-1true assume !(1 == ~T8_E~0); 299#L1194-1true assume !(1 == ~T9_E~0); 1356#L1199-1true assume !(1 == ~T10_E~0); 268#L1204-1true assume !(1 == ~E_M~0); 1212#L1209-1true assume !(1 == ~E_1~0); 663#L1214-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1304#L1219-1true assume !(1 == ~E_3~0); 1183#L1224-1true assume !(1 == ~E_4~0); 493#L1229-1true assume !(1 == ~E_5~0); 122#L1234-1true assume !(1 == ~E_6~0); 773#L1239-1true assume !(1 == ~E_7~0); 149#L1244-1true assume !(1 == ~E_8~0); 820#L1249-1true assume !(1 == ~E_9~0); 735#L1254-1true assume 1 == ~E_10~0;~E_10~0 := 2; 74#L1259-1true assume { :end_inline_reset_delta_events } true; 1164#L1565-2true [2021-12-21 22:38:35,405 INFO L793 eck$LassoCheckResult]: Loop: 1164#L1565-2true assume !false; 672#L1566true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279#L1011true assume false; 1307#L1026true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 581#L724-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 743#L1036-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1062#L1036-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1302#L1041-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 827#L1046-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1184#L1051-3true assume !(0 == ~T4_E~0); 744#L1056-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 195#L1061-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 196#L1066-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1321#L1071-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1065#L1076-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 71#L1081-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1238#L1086-3true assume 0 == ~E_M~0;~E_M~0 := 1; 96#L1091-3true assume !(0 == ~E_1~0); 1141#L1096-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1002#L1101-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1060#L1106-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1118#L1111-3true assume 0 == ~E_5~0;~E_5~0 := 1; 986#L1116-3true assume 0 == ~E_6~0;~E_6~0 := 1; 595#L1121-3true assume 0 == ~E_7~0;~E_7~0 := 1; 936#L1126-3true assume 0 == ~E_8~0;~E_8~0 := 1; 853#L1131-3true assume !(0 == ~E_9~0); 1297#L1136-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1272#L1141-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 599#L514-36true assume !(1 == ~m_pc~0); 394#L514-38true is_master_triggered_~__retres1~0#1 := 0; 291#L525-12true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1012#L526-12true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 641#L1285-36true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226#L1285-38true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L533-36true assume 1 == ~t1_pc~0; 466#L534-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 958#L544-12true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 737#L545-12true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683#L1293-36true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 509#L1293-38true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1366#L552-36true assume 1 == ~t2_pc~0; 223#L553-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 547#L563-12true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131#L564-12true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1173#L1301-36true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 208#L1301-38true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 830#L571-36true assume 1 == ~t3_pc~0; 452#L572-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 258#L582-12true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 334#L583-12true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 826#L1309-36true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 873#L1309-38true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 242#L590-36true assume !(1 == ~t4_pc~0); 879#L590-38true is_transmit4_triggered_~__retres1~4#1 := 0; 1015#L601-12true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 355#L602-12true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1311#L1317-36true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 791#L1317-38true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1053#L609-36true assume !(1 == ~t5_pc~0); 1327#L609-38true is_transmit5_triggered_~__retres1~5#1 := 0; 513#L620-12true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 377#L621-12true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 859#L1325-36true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 570#L1325-38true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 432#L628-36true assume 1 == ~t6_pc~0; 336#L629-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1132#L639-12true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 673#L640-12true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 749#L1333-36true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 601#L1333-38true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1093#L647-36true assume 1 == ~t7_pc~0; 543#L648-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84#L658-12true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104#L659-12true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93#L1341-36true assume !(0 != activate_threads_~tmp___6~0#1); 698#L1341-38true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 768#L666-36true assume 1 == ~t8_pc~0; 185#L667-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1193#L677-12true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 994#L678-12true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1210#L1349-36true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 275#L1349-38true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 583#L685-36true assume !(1 == ~t9_pc~0); 136#L685-38true is_transmit9_triggered_~__retres1~9#1 := 0; 874#L696-12true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 443#L697-12true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1264#L1357-36true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 362#L1357-38true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 369#L704-36true assume !(1 == ~t10_pc~0); 271#L704-38true is_transmit10_triggered_~__retres1~10#1 := 0; 1146#L715-12true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 644#L716-12true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 724#L1365-36true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 145#L1365-38true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1349#L1154-3true assume 1 == ~M_E~0;~M_E~0 := 2; 969#L1154-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 758#L1159-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1323#L1164-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1090#L1169-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 317#L1174-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1180#L1179-3true assume !(1 == ~T6_E~0); 916#L1184-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 85#L1189-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 921#L1194-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 282#L1199-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1360#L1204-3true assume 1 == ~E_M~0;~E_M~0 := 2; 489#L1209-3true assume 1 == ~E_1~0;~E_1~0 := 2; 20#L1214-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1013#L1219-3true assume !(1 == ~E_3~0); 652#L1224-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1370#L1229-3true assume 1 == ~E_5~0;~E_5~0 := 2; 671#L1234-3true assume 1 == ~E_6~0;~E_6~0 := 2; 150#L1239-3true assume 1 == ~E_7~0;~E_7~0 := 2; 526#L1244-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1069#L1249-3true assume 1 == ~E_9~0;~E_9~0 := 2; 987#L1254-3true assume 1 == ~E_10~0;~E_10~0 := 2; 655#L1259-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 752#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1282#L851-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 503#L852-1true start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 607#L1584true assume !(0 == start_simulation_~tmp~3#1); 636#L1584-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 156#L794-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 935#L851-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 234#L852-2true stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 348#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 977#L1546true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 326#L1547true start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1158#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 1164#L1565-2true [2021-12-21 22:38:35,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:35,410 INFO L85 PathProgramCache]: Analyzing trace with hash 121410427, now seen corresponding path program 1 times [2021-12-21 22:38:35,423 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:35,423 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347383333] [2021-12-21 22:38:35,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:35,424 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:35,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:35,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:35,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:35,628 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347383333] [2021-12-21 22:38:35,629 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347383333] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:35,629 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:35,629 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:35,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185359881] [2021-12-21 22:38:35,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:35,633 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:35,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:35,634 INFO L85 PathProgramCache]: Analyzing trace with hash 1515191513, now seen corresponding path program 1 times [2021-12-21 22:38:35,634 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:35,634 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511315477] [2021-12-21 22:38:35,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:35,635 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:35,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:35,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:35,690 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:35,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511315477] [2021-12-21 22:38:35,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511315477] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:35,690 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:35,690 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:35,690 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56981118] [2021-12-21 22:38:35,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:35,691 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:35,696 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:35,746 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:35,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:35,751 INFO L87 Difference]: Start difference. First operand has 1374 states, 1373 states have (on average 1.5069191551347414) internal successors, (2069), 1373 states have internal predecessors, (2069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:35,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:35,827 INFO L93 Difference]: Finished difference Result 1372 states and 2038 transitions. [2021-12-21 22:38:35,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:35,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1372 states and 2038 transitions. [2021-12-21 22:38:35,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:35,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1372 states to 1366 states and 2032 transitions. [2021-12-21 22:38:35,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:35,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:35,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2032 transitions. [2021-12-21 22:38:35,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:35,871 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-21 22:38:35,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2032 transitions. [2021-12-21 22:38:35,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:35,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4875549048316252) internal successors, (2032), 1365 states have internal predecessors, (2032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:35,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2032 transitions. [2021-12-21 22:38:35,938 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-21 22:38:35,938 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2032 transitions. [2021-12-21 22:38:35,939 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-21 22:38:35,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2032 transitions. [2021-12-21 22:38:35,944 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:35,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:35,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:35,948 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,948 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:35,949 INFO L791 eck$LassoCheckResult]: Stem: 3813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 3814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4021#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2806#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2807#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 4046#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4004#L736-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4005#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4035#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3115#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3116#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3219#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3464#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3395#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3117#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2777#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2778#L1036 assume !(0 == ~M_E~0); 2876#L1036-2 assume !(0 == ~T1_E~0); 3752#L1041-1 assume !(0 == ~T2_E~0); 3753#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3151#L1051-1 assume !(0 == ~T4_E~0); 3152#L1056-1 assume !(0 == ~T5_E~0); 3890#L1061-1 assume !(0 == ~T6_E~0); 3049#L1066-1 assume !(0 == ~T7_E~0); 3050#L1071-1 assume !(0 == ~T8_E~0); 3873#L1076-1 assume !(0 == ~T9_E~0); 2944#L1081-1 assume !(0 == ~T10_E~0); 2945#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3348#L1091-1 assume !(0 == ~E_1~0); 4050#L1096-1 assume !(0 == ~E_2~0); 4051#L1101-1 assume !(0 == ~E_3~0); 3409#L1106-1 assume !(0 == ~E_4~0); 3410#L1111-1 assume !(0 == ~E_5~0); 3566#L1116-1 assume !(0 == ~E_6~0); 3567#L1121-1 assume !(0 == ~E_7~0); 3402#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 3403#L1131-1 assume !(0 == ~E_9~0); 3653#L1136-1 assume !(0 == ~E_10~0); 3760#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3917#L514 assume 1 == ~m_pc~0; 3880#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3423#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3342#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3343#L1285 assume !(0 != activate_threads_~tmp~1#1); 4086#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3068#L533 assume !(1 == ~t1_pc~0); 3069#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3582#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3456#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 3782#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3783#L552 assume 1 == ~t2_pc~0; 3294#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3295#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3861#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3862#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 3437#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3438#L571 assume 1 == ~t3_pc~0; 3614#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3615#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2984#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2985#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 3572#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2860#L590 assume !(1 == ~t4_pc~0); 2861#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3625#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3858#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3859#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3815#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3568#L609 assume 1 == ~t5_pc~0; 3569#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4083#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2895#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2896#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 3563#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3564#L628 assume !(1 == ~t6_pc~0); 3497#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3496#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4068#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4069#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 3853#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3854#L647 assume 1 == ~t7_pc~0; 3411#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3412#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3690#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3418#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 3419#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4115#L666 assume !(1 == ~t8_pc~0); 3198#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3199#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3433#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3590#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 3345#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3346#L685 assume 1 == ~t9_pc~0; 4092#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3989#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3981#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3371#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 3372#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3724#L704 assume !(1 == ~t10_pc~0); 3363#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3362#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3888#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2916#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 2917#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3162#L1154 assume !(1 == ~M_E~0); 3841#L1154-2 assume !(1 == ~T1_E~0); 3134#L1159-1 assume !(1 == ~T2_E~0); 3135#L1164-1 assume !(1 == ~T3_E~0); 3587#L1169-1 assume !(1 == ~T4_E~0); 3459#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3266#L1179-1 assume !(1 == ~T6_E~0); 3120#L1184-1 assume !(1 == ~T7_E~0); 3121#L1189-1 assume !(1 == ~T8_E~0); 3196#L1194-1 assume !(1 == ~T9_E~0); 3335#L1199-1 assume !(1 == ~T10_E~0); 3281#L1204-1 assume !(1 == ~E_M~0); 3282#L1209-1 assume !(1 == ~E_1~0); 3808#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3809#L1219-1 assume !(1 == ~E_3~0); 4108#L1224-1 assume !(1 == ~E_4~0); 3607#L1229-1 assume !(1 == ~E_5~0); 3005#L1234-1 assume !(1 == ~E_6~0); 3006#L1239-1 assume !(1 == ~E_7~0); 3064#L1244-1 assume !(1 == ~E_8~0); 3065#L1249-1 assume !(1 == ~E_9~0); 3878#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 2907#L1259-1 assume { :end_inline_reset_delta_events } true; 2908#L1565-2 [2021-12-21 22:38:35,951 INFO L793 eck$LassoCheckResult]: Loop: 2908#L1565-2 assume !false; 3816#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3300#L1011 assume !false; 3301#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3350#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3104#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3969#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3131#L866 assume !(0 != eval_~tmp~0#1); 3133#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3719#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3720#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3884#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4070#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3943#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3944#L1051-3 assume !(0 == ~T4_E~0); 3885#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3148#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3149#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3150#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4071#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2899#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2900#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2958#L1091-3 assume !(0 == ~E_1~0); 2959#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4037#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4038#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4067#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4028#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3735#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3736#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3959#L1131-3 assume !(0 == ~E_9~0); 3960#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4119#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3738#L514-36 assume !(1 == ~m_pc~0); 3475#L514-38 is_master_triggered_~__retres1~0#1 := 0; 3325#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3326#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3781#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3207#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3208#L533-36 assume 1 == ~t1_pc~0; 3483#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3579#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3879#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3827#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3630#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3631#L552-36 assume 1 == ~t2_pc~0; 3200#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3202#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3021#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3022#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3174#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3175#L571-36 assume 1 == ~t3_pc~0; 3559#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3264#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3265#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3386#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3942#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3232#L590-36 assume !(1 == ~t4_pc~0); 3233#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 3842#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3420#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3421#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3921#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3922#L609-36 assume 1 == ~t5_pc~0; 3797#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3632#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3450#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3451#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3704#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3530#L628-36 assume 1 == ~t6_pc~0; 3387#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3388#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3817#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3818#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3742#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3743#L647-36 assume 1 == ~t7_pc~0; 3671#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2928#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2929#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2948#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 2949#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3843#L666-36 assume 1 == ~t8_pc~0; 3128#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3129#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4032#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4033#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3291#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3292#L685-36 assume 1 == ~t9_pc~0; 3718#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3033#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3548#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3549#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3430#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3431#L704-36 assume !(1 == ~t10_pc~0); 3025#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 3024#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3784#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3785#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3053#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3054#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4020#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3898#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3899#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4079#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3359#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3360#L1179-3 assume !(1 == ~T6_E~0); 3991#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2930#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2931#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3304#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3305#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3603#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2793#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2794#L1219-3 assume !(1 == ~E_3~0); 3792#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3793#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3812#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3066#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3067#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3646#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4029#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3795#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3796#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2874#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3619#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3620#L1584 assume !(0 == start_simulation_~tmp~3#1); 3750#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3080#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2775#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3222#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3223#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3406#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3374#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3375#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 2908#L1565-2 [2021-12-21 22:38:35,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:35,951 INFO L85 PathProgramCache]: Analyzing trace with hash -825627459, now seen corresponding path program 1 times [2021-12-21 22:38:35,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:35,953 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230301334] [2021-12-21 22:38:35,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:35,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:35,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,003 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,003 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230301334] [2021-12-21 22:38:36,003 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230301334] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,004 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,004 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,004 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292609024] [2021-12-21 22:38:36,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,004 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,005 INFO L85 PathProgramCache]: Analyzing trace with hash 2100759252, now seen corresponding path program 1 times [2021-12-21 22:38:36,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,005 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323648395] [2021-12-21 22:38:36,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,100 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323648395] [2021-12-21 22:38:36,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323648395] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,100 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,100 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,100 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979402991] [2021-12-21 22:38:36,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,102 INFO L87 Difference]: Start difference. First operand 1366 states and 2032 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,121 INFO L93 Difference]: Finished difference Result 1366 states and 2031 transitions. [2021-12-21 22:38:36,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2031 transitions. [2021-12-21 22:38:36,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2031 transitions. [2021-12-21 22:38:36,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2031 transitions. [2021-12-21 22:38:36,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,139 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-21 22:38:36,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2031 transitions. [2021-12-21 22:38:36,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4868228404099562) internal successors, (2031), 1365 states have internal predecessors, (2031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2031 transitions. [2021-12-21 22:38:36,177 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-21 22:38:36,177 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2031 transitions. [2021-12-21 22:38:36,177 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-21 22:38:36,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2031 transitions. [2021-12-21 22:38:36,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,185 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,186 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,186 INFO L791 eck$LassoCheckResult]: Stem: 6551#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 6552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6760#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5543#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5544#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6784#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6743#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6744#L741-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6774#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5852#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5853#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5958#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6203#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6134#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5854#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5516#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5517#L1036 assume !(0 == ~M_E~0); 5615#L1036-2 assume !(0 == ~T1_E~0); 6491#L1041-1 assume !(0 == ~T2_E~0); 6492#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5890#L1051-1 assume !(0 == ~T4_E~0); 5891#L1056-1 assume !(0 == ~T5_E~0); 6629#L1061-1 assume !(0 == ~T6_E~0); 5788#L1066-1 assume !(0 == ~T7_E~0); 5789#L1071-1 assume !(0 == ~T8_E~0); 6612#L1076-1 assume !(0 == ~T9_E~0); 5683#L1081-1 assume !(0 == ~T10_E~0); 5684#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6087#L1091-1 assume !(0 == ~E_1~0); 6788#L1096-1 assume !(0 == ~E_2~0); 6789#L1101-1 assume !(0 == ~E_3~0); 6148#L1106-1 assume !(0 == ~E_4~0); 6149#L1111-1 assume !(0 == ~E_5~0); 6305#L1116-1 assume !(0 == ~E_6~0); 6306#L1121-1 assume !(0 == ~E_7~0); 6141#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 6142#L1131-1 assume !(0 == ~E_9~0); 6392#L1136-1 assume !(0 == ~E_10~0); 6499#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6656#L514 assume 1 == ~m_pc~0; 6619#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6161#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6078#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6079#L1285 assume !(0 != activate_threads_~tmp~1#1); 6824#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5807#L533 assume !(1 == ~t1_pc~0); 5808#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6194#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6195#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 6521#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6522#L552 assume 1 == ~t2_pc~0; 6032#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6033#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6600#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6601#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 6173#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6174#L571 assume 1 == ~t3_pc~0; 6351#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6352#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5721#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5722#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 6311#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5597#L590 assume !(1 == ~t4_pc~0); 5598#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6364#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6596#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6597#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6553#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6307#L609 assume 1 == ~t5_pc~0; 6308#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6822#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5634#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5635#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 6302#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6303#L628 assume !(1 == ~t6_pc~0); 6236#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6235#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6807#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6808#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 6592#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6593#L647 assume 1 == ~t7_pc~0; 6150#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6151#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6427#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6153#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 6154#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6854#L666 assume !(1 == ~t8_pc~0); 5937#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5938#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6172#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6328#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 6084#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6085#L685 assume 1 == ~t9_pc~0; 6831#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6728#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6720#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6110#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 6111#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6463#L704 assume !(1 == ~t10_pc~0); 6102#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6101#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6627#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5653#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 5654#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5901#L1154 assume !(1 == ~M_E~0); 6580#L1154-2 assume !(1 == ~T1_E~0); 5873#L1159-1 assume !(1 == ~T2_E~0); 5874#L1164-1 assume !(1 == ~T3_E~0); 6326#L1169-1 assume !(1 == ~T4_E~0); 6198#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6003#L1179-1 assume !(1 == ~T6_E~0); 5859#L1184-1 assume !(1 == ~T7_E~0); 5860#L1189-1 assume !(1 == ~T8_E~0); 5935#L1194-1 assume !(1 == ~T9_E~0); 6074#L1199-1 assume !(1 == ~T10_E~0); 6018#L1204-1 assume !(1 == ~E_M~0); 6019#L1209-1 assume !(1 == ~E_1~0); 6545#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6546#L1219-1 assume !(1 == ~E_3~0); 6847#L1224-1 assume !(1 == ~E_4~0); 6346#L1229-1 assume !(1 == ~E_5~0); 5744#L1234-1 assume !(1 == ~E_6~0); 5745#L1239-1 assume !(1 == ~E_7~0); 5803#L1244-1 assume !(1 == ~E_8~0); 5804#L1249-1 assume !(1 == ~E_9~0); 6617#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 5646#L1259-1 assume { :end_inline_reset_delta_events } true; 5647#L1565-2 [2021-12-21 22:38:36,186 INFO L793 eck$LassoCheckResult]: Loop: 5647#L1565-2 assume !false; 6555#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6039#L1011 assume !false; 6040#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6089#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5843#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6708#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5867#L866 assume !(0 != eval_~tmp~0#1); 5869#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6456#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6457#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6623#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6809#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6682#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6683#L1051-3 assume !(0 == ~T4_E~0); 6624#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5887#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5888#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5889#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6810#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5638#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5639#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5693#L1091-3 assume !(0 == ~E_1~0); 5694#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6776#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6777#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6806#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6767#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6473#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6474#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6698#L1131-3 assume !(0 == ~E_9~0); 6699#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6858#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6477#L514-36 assume !(1 == ~m_pc~0); 6214#L514-38 is_master_triggered_~__retres1~0#1 := 0; 6062#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6063#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6520#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5946#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5947#L533-36 assume 1 == ~t1_pc~0; 6222#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6315#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6618#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6566#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6369#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6370#L552-36 assume 1 == ~t2_pc~0; 5939#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5941#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5760#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5761#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5913#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5914#L571-36 assume 1 == ~t3_pc~0; 6298#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6004#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6005#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6125#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6681#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5974#L590-36 assume !(1 == ~t4_pc~0); 5975#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 6581#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6159#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6160#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6660#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6661#L609-36 assume 1 == ~t5_pc~0; 6536#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6371#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6189#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6190#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6443#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6269#L628-36 assume 1 == ~t6_pc~0; 6128#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6129#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6556#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6557#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6481#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6482#L647-36 assume 1 == ~t7_pc~0; 6410#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5667#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5668#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5687#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 5688#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6582#L666-36 assume !(1 == ~t8_pc~0); 5872#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 5871#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6771#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6772#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6030#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6031#L685-36 assume !(1 == ~t9_pc~0); 5771#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 5772#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6287#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6288#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6169#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6170#L704-36 assume 1 == ~t10_pc~0; 5762#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5763#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6523#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6524#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5792#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5793#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6759#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6637#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6638#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6818#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6098#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6099#L1179-3 assume !(1 == ~T6_E~0); 6730#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5669#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5670#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6045#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6046#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6342#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5532#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5533#L1219-3 assume !(1 == ~E_3~0); 6531#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6532#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6554#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5805#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5806#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6389#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6768#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6534#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6535#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5613#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6360#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6361#L1584 assume !(0 == start_simulation_~tmp~3#1); 6489#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5819#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5514#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5961#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 5962#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6146#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6113#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6114#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 5647#L1565-2 [2021-12-21 22:38:36,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1224781439, now seen corresponding path program 1 times [2021-12-21 22:38:36,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852546050] [2021-12-21 22:38:36,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852546050] [2021-12-21 22:38:36,234 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852546050] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,234 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,234 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,234 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141256133] [2021-12-21 22:38:36,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,235 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,235 INFO L85 PathProgramCache]: Analyzing trace with hash 418713301, now seen corresponding path program 1 times [2021-12-21 22:38:36,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,235 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3359923] [2021-12-21 22:38:36,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3359923] [2021-12-21 22:38:36,316 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3359923] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,316 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069378837] [2021-12-21 22:38:36,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,317 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,317 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,317 INFO L87 Difference]: Start difference. First operand 1366 states and 2031 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,335 INFO L93 Difference]: Finished difference Result 1366 states and 2030 transitions. [2021-12-21 22:38:36,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2030 transitions. [2021-12-21 22:38:36,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2030 transitions. [2021-12-21 22:38:36,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2030 transitions. [2021-12-21 22:38:36,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,350 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-21 22:38:36,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2030 transitions. [2021-12-21 22:38:36,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4860907759882869) internal successors, (2030), 1365 states have internal predecessors, (2030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2030 transitions. [2021-12-21 22:38:36,366 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-21 22:38:36,366 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2030 transitions. [2021-12-21 22:38:36,366 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-21 22:38:36,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2030 transitions. [2021-12-21 22:38:36,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,372 INFO L791 eck$LassoCheckResult]: Stem: 9290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 9291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9499#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8282#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8283#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 9523#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9482#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9483#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9513#L746-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8591#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8592#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8697#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8942#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8873#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8593#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8255#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8256#L1036 assume !(0 == ~M_E~0); 8354#L1036-2 assume !(0 == ~T1_E~0); 9230#L1041-1 assume !(0 == ~T2_E~0); 9231#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8629#L1051-1 assume !(0 == ~T4_E~0); 8630#L1056-1 assume !(0 == ~T5_E~0); 9368#L1061-1 assume !(0 == ~T6_E~0); 8527#L1066-1 assume !(0 == ~T7_E~0); 8528#L1071-1 assume !(0 == ~T8_E~0); 9351#L1076-1 assume !(0 == ~T9_E~0); 8422#L1081-1 assume !(0 == ~T10_E~0); 8423#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8826#L1091-1 assume !(0 == ~E_1~0); 9527#L1096-1 assume !(0 == ~E_2~0); 9528#L1101-1 assume !(0 == ~E_3~0); 8887#L1106-1 assume !(0 == ~E_4~0); 8888#L1111-1 assume !(0 == ~E_5~0); 9044#L1116-1 assume !(0 == ~E_6~0); 9045#L1121-1 assume !(0 == ~E_7~0); 8880#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 8881#L1131-1 assume !(0 == ~E_9~0); 9131#L1136-1 assume !(0 == ~E_10~0); 9238#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9395#L514 assume 1 == ~m_pc~0; 9358#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8900#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8817#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8818#L1285 assume !(0 != activate_threads_~tmp~1#1); 9563#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8546#L533 assume !(1 == ~t1_pc~0); 8547#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9060#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8933#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8934#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 9260#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9261#L552 assume 1 == ~t2_pc~0; 8771#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8772#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9339#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9340#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 8912#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8913#L571 assume 1 == ~t3_pc~0; 9090#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9091#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8460#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8461#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 9050#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8336#L590 assume !(1 == ~t4_pc~0); 8337#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9103#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9335#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9336#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9292#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9046#L609 assume 1 == ~t5_pc~0; 9047#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9561#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8373#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8374#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 9041#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9042#L628 assume !(1 == ~t6_pc~0); 8975#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8974#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9546#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9547#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 9331#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9332#L647 assume 1 == ~t7_pc~0; 8889#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8890#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9166#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8892#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 8893#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9593#L666 assume !(1 == ~t8_pc~0); 8676#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8677#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8911#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9067#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 8823#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8824#L685 assume 1 == ~t9_pc~0; 9570#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9467#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9459#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8849#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 8850#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9202#L704 assume !(1 == ~t10_pc~0); 8841#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8840#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9366#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8392#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 8393#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8640#L1154 assume !(1 == ~M_E~0); 9319#L1154-2 assume !(1 == ~T1_E~0); 8612#L1159-1 assume !(1 == ~T2_E~0); 8613#L1164-1 assume !(1 == ~T3_E~0); 9065#L1169-1 assume !(1 == ~T4_E~0); 8937#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8742#L1179-1 assume !(1 == ~T6_E~0); 8598#L1184-1 assume !(1 == ~T7_E~0); 8599#L1189-1 assume !(1 == ~T8_E~0); 8674#L1194-1 assume !(1 == ~T9_E~0); 8813#L1199-1 assume !(1 == ~T10_E~0); 8757#L1204-1 assume !(1 == ~E_M~0); 8758#L1209-1 assume !(1 == ~E_1~0); 9284#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9285#L1219-1 assume !(1 == ~E_3~0); 9586#L1224-1 assume !(1 == ~E_4~0); 9085#L1229-1 assume !(1 == ~E_5~0); 8483#L1234-1 assume !(1 == ~E_6~0); 8484#L1239-1 assume !(1 == ~E_7~0); 8542#L1244-1 assume !(1 == ~E_8~0); 8543#L1249-1 assume !(1 == ~E_9~0); 9356#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 8385#L1259-1 assume { :end_inline_reset_delta_events } true; 8386#L1565-2 [2021-12-21 22:38:36,372 INFO L793 eck$LassoCheckResult]: Loop: 8386#L1565-2 assume !false; 9294#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8778#L1011 assume !false; 8779#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8828#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8582#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9447#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8606#L866 assume !(0 != eval_~tmp~0#1); 8608#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9195#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9196#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9362#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9548#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9421#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9422#L1051-3 assume !(0 == ~T4_E~0); 9363#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8626#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8627#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8628#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9549#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8377#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8378#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8432#L1091-3 assume !(0 == ~E_1~0); 8433#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9515#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9516#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9545#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9506#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9212#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9213#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9437#L1131-3 assume !(0 == ~E_9~0); 9438#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9597#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9216#L514-36 assume 1 == ~m_pc~0; 9217#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8801#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8802#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9259#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8685#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8686#L533-36 assume 1 == ~t1_pc~0; 8961#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9054#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9357#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9305#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9108#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9109#L552-36 assume 1 == ~t2_pc~0; 8678#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8680#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8499#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8500#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8652#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8653#L571-36 assume 1 == ~t3_pc~0; 9037#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8743#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8744#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8864#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8713#L590-36 assume !(1 == ~t4_pc~0); 8714#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 9320#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8898#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8899#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9399#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9400#L609-36 assume 1 == ~t5_pc~0; 9275#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9110#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8928#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8929#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9182#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9008#L628-36 assume 1 == ~t6_pc~0; 8867#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8868#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9295#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9296#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9220#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9221#L647-36 assume 1 == ~t7_pc~0; 9149#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8406#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8407#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8426#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 8427#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9321#L666-36 assume 1 == ~t8_pc~0; 8609#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8610#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9510#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9511#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8769#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8770#L685-36 assume !(1 == ~t9_pc~0); 8510#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 8511#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9026#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9027#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8908#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8909#L704-36 assume 1 == ~t10_pc~0; 8501#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8502#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9262#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9263#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8531#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8532#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9498#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9376#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9377#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9557#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8837#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8838#L1179-3 assume !(1 == ~T6_E~0); 9469#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8408#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8409#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8784#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8785#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9081#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8271#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8272#L1219-3 assume !(1 == ~E_3~0); 9270#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9271#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9293#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8544#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8545#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9128#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9507#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9273#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9274#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8352#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9099#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9100#L1584 assume !(0 == start_simulation_~tmp~3#1); 9228#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8558#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8253#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8700#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 8701#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8885#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8852#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 8853#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8386#L1565-2 [2021-12-21 22:38:36,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,373 INFO L85 PathProgramCache]: Analyzing trace with hash 736734333, now seen corresponding path program 1 times [2021-12-21 22:38:36,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196537768] [2021-12-21 22:38:36,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,374 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,440 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,440 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196537768] [2021-12-21 22:38:36,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196537768] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,440 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,441 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797613291] [2021-12-21 22:38:36,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,441 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 1 times [2021-12-21 22:38:36,441 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,442 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117016110] [2021-12-21 22:38:36,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,442 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,472 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,472 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [117016110] [2021-12-21 22:38:36,472 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [117016110] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,473 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404926461] [2021-12-21 22:38:36,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,473 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,473 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,474 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,474 INFO L87 Difference]: Start difference. First operand 1366 states and 2030 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,496 INFO L93 Difference]: Finished difference Result 1366 states and 2029 transitions. [2021-12-21 22:38:36,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2029 transitions. [2021-12-21 22:38:36,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2029 transitions. [2021-12-21 22:38:36,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2029 transitions. [2021-12-21 22:38:36,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,511 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-21 22:38:36,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2029 transitions. [2021-12-21 22:38:36,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4853587115666178) internal successors, (2029), 1365 states have internal predecessors, (2029), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2029 transitions. [2021-12-21 22:38:36,526 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-21 22:38:36,526 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2029 transitions. [2021-12-21 22:38:36,526 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-21 22:38:36,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2029 transitions. [2021-12-21 22:38:36,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,532 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,532 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,532 INFO L791 eck$LassoCheckResult]: Stem: 12030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 12031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12238#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11023#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11024#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 12263#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12221#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12222#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12252#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11332#L751-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11333#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11436#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11681#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11612#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11334#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10994#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10995#L1036 assume !(0 == ~M_E~0); 11093#L1036-2 assume !(0 == ~T1_E~0); 11969#L1041-1 assume !(0 == ~T2_E~0); 11970#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11368#L1051-1 assume !(0 == ~T4_E~0); 11369#L1056-1 assume !(0 == ~T5_E~0); 12107#L1061-1 assume !(0 == ~T6_E~0); 11266#L1066-1 assume !(0 == ~T7_E~0); 11267#L1071-1 assume !(0 == ~T8_E~0); 12090#L1076-1 assume !(0 == ~T9_E~0); 11161#L1081-1 assume !(0 == ~T10_E~0); 11162#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 11565#L1091-1 assume !(0 == ~E_1~0); 12267#L1096-1 assume !(0 == ~E_2~0); 12268#L1101-1 assume !(0 == ~E_3~0); 11626#L1106-1 assume !(0 == ~E_4~0); 11627#L1111-1 assume !(0 == ~E_5~0); 11783#L1116-1 assume !(0 == ~E_6~0); 11784#L1121-1 assume !(0 == ~E_7~0); 11619#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 11620#L1131-1 assume !(0 == ~E_9~0); 11870#L1136-1 assume !(0 == ~E_10~0); 11977#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12134#L514 assume 1 == ~m_pc~0; 12097#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11640#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11559#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11560#L1285 assume !(0 != activate_threads_~tmp~1#1); 12303#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11285#L533 assume !(1 == ~t1_pc~0); 11286#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11799#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11672#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11673#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 11999#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12000#L552 assume 1 == ~t2_pc~0; 11511#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11512#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12078#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12079#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 11654#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11655#L571 assume 1 == ~t3_pc~0; 11831#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11832#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11201#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11202#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 11789#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11077#L590 assume !(1 == ~t4_pc~0); 11078#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11842#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12075#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12076#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12032#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11785#L609 assume 1 == ~t5_pc~0; 11786#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12300#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11112#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11113#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 11780#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11781#L628 assume !(1 == ~t6_pc~0); 11714#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11713#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12285#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12286#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 12070#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12071#L647 assume 1 == ~t7_pc~0; 11628#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11629#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11907#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11635#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 11636#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12332#L666 assume !(1 == ~t8_pc~0); 11415#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11416#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11650#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11807#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 11563#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11564#L685 assume 1 == ~t9_pc~0; 12309#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12206#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12198#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11588#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 11589#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11941#L704 assume !(1 == ~t10_pc~0); 11580#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11579#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12105#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11133#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 11134#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11379#L1154 assume !(1 == ~M_E~0); 12058#L1154-2 assume !(1 == ~T1_E~0); 11351#L1159-1 assume !(1 == ~T2_E~0); 11352#L1164-1 assume !(1 == ~T3_E~0); 11804#L1169-1 assume !(1 == ~T4_E~0); 11676#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11483#L1179-1 assume !(1 == ~T6_E~0); 11337#L1184-1 assume !(1 == ~T7_E~0); 11338#L1189-1 assume !(1 == ~T8_E~0); 11413#L1194-1 assume !(1 == ~T9_E~0); 11552#L1199-1 assume !(1 == ~T10_E~0); 11498#L1204-1 assume !(1 == ~E_M~0); 11499#L1209-1 assume !(1 == ~E_1~0); 12025#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12026#L1219-1 assume !(1 == ~E_3~0); 12325#L1224-1 assume !(1 == ~E_4~0); 11824#L1229-1 assume !(1 == ~E_5~0); 11222#L1234-1 assume !(1 == ~E_6~0); 11223#L1239-1 assume !(1 == ~E_7~0); 11281#L1244-1 assume !(1 == ~E_8~0); 11282#L1249-1 assume !(1 == ~E_9~0); 12095#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 11124#L1259-1 assume { :end_inline_reset_delta_events } true; 11125#L1565-2 [2021-12-21 22:38:36,533 INFO L793 eck$LassoCheckResult]: Loop: 11125#L1565-2 assume !false; 12033#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11517#L1011 assume !false; 11518#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11567#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11321#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12186#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11348#L866 assume !(0 != eval_~tmp~0#1); 11350#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11936#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11937#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12101#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12287#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12160#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12161#L1051-3 assume !(0 == ~T4_E~0); 12102#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11365#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11366#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11367#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12288#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11116#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11117#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11175#L1091-3 assume !(0 == ~E_1~0); 11176#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12254#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12255#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12284#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12245#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11952#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11953#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12176#L1131-3 assume !(0 == ~E_9~0); 12177#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12336#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11955#L514-36 assume 1 == ~m_pc~0; 11956#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11542#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11543#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11998#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11424#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11425#L533-36 assume 1 == ~t1_pc~0; 11700#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11796#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12096#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12044#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11847#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11848#L552-36 assume 1 == ~t2_pc~0; 11417#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11419#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11238#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11239#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11391#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11392#L571-36 assume 1 == ~t3_pc~0; 11776#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11481#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11482#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11603#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12159#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11449#L590-36 assume !(1 == ~t4_pc~0); 11450#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 12059#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11637#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11638#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12138#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12139#L609-36 assume 1 == ~t5_pc~0; 12014#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11849#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11667#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11668#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11921#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11747#L628-36 assume 1 == ~t6_pc~0; 11604#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11605#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12034#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12035#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11959#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11960#L647-36 assume 1 == ~t7_pc~0; 11888#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11145#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11146#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11165#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 11166#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12060#L666-36 assume 1 == ~t8_pc~0; 11345#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11346#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12249#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12250#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11508#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11509#L685-36 assume !(1 == ~t9_pc~0); 11249#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 11250#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11765#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11766#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11647#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11648#L704-36 assume 1 == ~t10_pc~0; 11240#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11241#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12001#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12002#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11270#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11271#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12237#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12115#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12116#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12296#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11576#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11577#L1179-3 assume !(1 == ~T6_E~0); 12208#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11147#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11148#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11521#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11522#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11820#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11010#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11011#L1219-3 assume !(1 == ~E_3~0); 12009#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12010#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12029#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11283#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11284#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11863#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12246#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12012#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12013#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11091#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11836#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 11837#L1584 assume !(0 == start_simulation_~tmp~3#1); 11967#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11297#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10992#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11439#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 11440#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11623#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11591#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11592#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11125#L1565-2 [2021-12-21 22:38:36,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1829369535, now seen corresponding path program 1 times [2021-12-21 22:38:36,533 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174141240] [2021-12-21 22:38:36,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,534 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,556 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,557 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174141240] [2021-12-21 22:38:36,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174141240] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,557 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,557 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,557 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421987845] [2021-12-21 22:38:36,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,557 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 2 times [2021-12-21 22:38:36,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,558 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160006139] [2021-12-21 22:38:36,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,558 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,608 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,609 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160006139] [2021-12-21 22:38:36,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160006139] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,609 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,609 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,609 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471359845] [2021-12-21 22:38:36,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,609 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,609 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,610 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,610 INFO L87 Difference]: Start difference. First operand 1366 states and 2029 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,626 INFO L93 Difference]: Finished difference Result 1366 states and 2028 transitions. [2021-12-21 22:38:36,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2028 transitions. [2021-12-21 22:38:36,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2028 transitions. [2021-12-21 22:38:36,641 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2028 transitions. [2021-12-21 22:38:36,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,644 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-21 22:38:36,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2028 transitions. [2021-12-21 22:38:36,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4846266471449487) internal successors, (2028), 1365 states have internal predecessors, (2028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2028 transitions. [2021-12-21 22:38:36,660 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-21 22:38:36,660 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2028 transitions. [2021-12-21 22:38:36,660 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-21 22:38:36,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2028 transitions. [2021-12-21 22:38:36,666 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,667 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,667 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,668 INFO L791 eck$LassoCheckResult]: Stem: 14768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14977#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13760#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13761#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 15001#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14960#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14961#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14991#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14069#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14070#L756-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14175#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14420#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14351#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14071#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13733#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13734#L1036 assume !(0 == ~M_E~0); 13832#L1036-2 assume !(0 == ~T1_E~0); 14708#L1041-1 assume !(0 == ~T2_E~0); 14709#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14107#L1051-1 assume !(0 == ~T4_E~0); 14108#L1056-1 assume !(0 == ~T5_E~0); 14846#L1061-1 assume !(0 == ~T6_E~0); 14005#L1066-1 assume !(0 == ~T7_E~0); 14006#L1071-1 assume !(0 == ~T8_E~0); 14829#L1076-1 assume !(0 == ~T9_E~0); 13900#L1081-1 assume !(0 == ~T10_E~0); 13901#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 14304#L1091-1 assume !(0 == ~E_1~0); 15005#L1096-1 assume !(0 == ~E_2~0); 15006#L1101-1 assume !(0 == ~E_3~0); 14365#L1106-1 assume !(0 == ~E_4~0); 14366#L1111-1 assume !(0 == ~E_5~0); 14522#L1116-1 assume !(0 == ~E_6~0); 14523#L1121-1 assume !(0 == ~E_7~0); 14358#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 14359#L1131-1 assume !(0 == ~E_9~0); 14609#L1136-1 assume !(0 == ~E_10~0); 14716#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L514 assume 1 == ~m_pc~0; 14836#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14378#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14295#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14296#L1285 assume !(0 != activate_threads_~tmp~1#1); 15041#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14024#L533 assume !(1 == ~t1_pc~0); 14025#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14538#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14411#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14412#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 14738#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14739#L552 assume 1 == ~t2_pc~0; 14249#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14250#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14817#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14818#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 14390#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14391#L571 assume 1 == ~t3_pc~0; 14568#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14569#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13938#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13939#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 14528#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13814#L590 assume !(1 == ~t4_pc~0); 13815#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14581#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14813#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14814#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14770#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14524#L609 assume 1 == ~t5_pc~0; 14525#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15039#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13851#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13852#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 14519#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14520#L628 assume !(1 == ~t6_pc~0); 14453#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14452#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15024#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15025#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 14809#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14810#L647 assume 1 == ~t7_pc~0; 14367#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14368#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14644#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14370#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 14371#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15071#L666 assume !(1 == ~t8_pc~0); 14154#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14155#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14389#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14545#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 14301#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14302#L685 assume 1 == ~t9_pc~0; 15048#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14945#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14937#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14327#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 14328#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14680#L704 assume !(1 == ~t10_pc~0); 14319#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14318#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14844#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13870#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 13871#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14118#L1154 assume !(1 == ~M_E~0); 14797#L1154-2 assume !(1 == ~T1_E~0); 14090#L1159-1 assume !(1 == ~T2_E~0); 14091#L1164-1 assume !(1 == ~T3_E~0); 14543#L1169-1 assume !(1 == ~T4_E~0); 14415#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14220#L1179-1 assume !(1 == ~T6_E~0); 14076#L1184-1 assume !(1 == ~T7_E~0); 14077#L1189-1 assume !(1 == ~T8_E~0); 14152#L1194-1 assume !(1 == ~T9_E~0); 14291#L1199-1 assume !(1 == ~T10_E~0); 14235#L1204-1 assume !(1 == ~E_M~0); 14236#L1209-1 assume !(1 == ~E_1~0); 14762#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 14763#L1219-1 assume !(1 == ~E_3~0); 15064#L1224-1 assume !(1 == ~E_4~0); 14563#L1229-1 assume !(1 == ~E_5~0); 13961#L1234-1 assume !(1 == ~E_6~0); 13962#L1239-1 assume !(1 == ~E_7~0); 14020#L1244-1 assume !(1 == ~E_8~0); 14021#L1249-1 assume !(1 == ~E_9~0); 14834#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13863#L1259-1 assume { :end_inline_reset_delta_events } true; 13864#L1565-2 [2021-12-21 22:38:36,668 INFO L793 eck$LassoCheckResult]: Loop: 13864#L1565-2 assume !false; 14772#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14256#L1011 assume !false; 14257#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14306#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14060#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14925#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14084#L866 assume !(0 != eval_~tmp~0#1); 14086#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14673#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14674#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14840#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15026#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14899#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14900#L1051-3 assume !(0 == ~T4_E~0); 14841#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14104#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14105#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14106#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15027#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13855#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13856#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13910#L1091-3 assume !(0 == ~E_1~0); 13911#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14993#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14994#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15023#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14984#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14690#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14691#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14915#L1131-3 assume !(0 == ~E_9~0); 14916#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15075#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14694#L514-36 assume 1 == ~m_pc~0; 14695#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14279#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14280#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14737#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14163#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14164#L533-36 assume 1 == ~t1_pc~0; 14439#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14532#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14835#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14783#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14586#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14587#L552-36 assume 1 == ~t2_pc~0; 14156#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14158#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13977#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13978#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14130#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14131#L571-36 assume 1 == ~t3_pc~0; 14515#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14221#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14222#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14342#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14898#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14191#L590-36 assume !(1 == ~t4_pc~0); 14192#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 14798#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14376#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14377#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14877#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14878#L609-36 assume 1 == ~t5_pc~0; 14753#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14588#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14406#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14407#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14660#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14486#L628-36 assume 1 == ~t6_pc~0; 14345#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14346#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14773#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14774#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14698#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14699#L647-36 assume 1 == ~t7_pc~0; 14627#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13884#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13885#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13904#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 13905#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14799#L666-36 assume 1 == ~t8_pc~0; 14087#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14088#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14988#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14989#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14247#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14248#L685-36 assume !(1 == ~t9_pc~0); 13988#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 13989#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14504#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14505#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14386#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14387#L704-36 assume 1 == ~t10_pc~0; 13979#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13980#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14740#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14741#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14009#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14010#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14976#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14854#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14855#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15035#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14315#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14316#L1179-3 assume !(1 == ~T6_E~0); 14947#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13886#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13887#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14262#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14263#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14559#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13749#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13750#L1219-3 assume !(1 == ~E_3~0); 14748#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14749#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14771#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14022#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14023#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14606#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14985#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14751#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14752#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13830#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14577#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 14578#L1584 assume !(0 == start_simulation_~tmp~3#1); 14706#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14036#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13731#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14178#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14179#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14363#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14330#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14331#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 13864#L1565-2 [2021-12-21 22:38:36,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,668 INFO L85 PathProgramCache]: Analyzing trace with hash -1183425475, now seen corresponding path program 1 times [2021-12-21 22:38:36,668 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028655859] [2021-12-21 22:38:36,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,669 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,688 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028655859] [2021-12-21 22:38:36,688 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028655859] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,688 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,688 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530466087] [2021-12-21 22:38:36,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,689 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,689 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 3 times [2021-12-21 22:38:36,689 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,690 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593107266] [2021-12-21 22:38:36,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,690 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,716 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,716 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593107266] [2021-12-21 22:38:36,720 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593107266] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,720 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,720 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,720 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728692385] [2021-12-21 22:38:36,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,721 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,721 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,722 INFO L87 Difference]: Start difference. First operand 1366 states and 2028 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,738 INFO L93 Difference]: Finished difference Result 1366 states and 2027 transitions. [2021-12-21 22:38:36,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2027 transitions. [2021-12-21 22:38:36,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2027 transitions. [2021-12-21 22:38:36,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2027 transitions. [2021-12-21 22:38:36,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,768 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-21 22:38:36,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2027 transitions. [2021-12-21 22:38:36,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4838945827232797) internal successors, (2027), 1365 states have internal predecessors, (2027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2027 transitions. [2021-12-21 22:38:36,785 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-21 22:38:36,785 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2027 transitions. [2021-12-21 22:38:36,785 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-21 22:38:36,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2027 transitions. [2021-12-21 22:38:36,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,793 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,793 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,793 INFO L791 eck$LassoCheckResult]: Stem: 17507#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17508#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17716#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16499#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16500#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17740#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17699#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17700#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17730#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16808#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16809#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16914#L761-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17159#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17090#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16810#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16472#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16473#L1036 assume !(0 == ~M_E~0); 16571#L1036-2 assume !(0 == ~T1_E~0); 17447#L1041-1 assume !(0 == ~T2_E~0); 17448#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16846#L1051-1 assume !(0 == ~T4_E~0); 16847#L1056-1 assume !(0 == ~T5_E~0); 17585#L1061-1 assume !(0 == ~T6_E~0); 16744#L1066-1 assume !(0 == ~T7_E~0); 16745#L1071-1 assume !(0 == ~T8_E~0); 17568#L1076-1 assume !(0 == ~T9_E~0); 16639#L1081-1 assume !(0 == ~T10_E~0); 16640#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 17043#L1091-1 assume !(0 == ~E_1~0); 17744#L1096-1 assume !(0 == ~E_2~0); 17745#L1101-1 assume !(0 == ~E_3~0); 17104#L1106-1 assume !(0 == ~E_4~0); 17105#L1111-1 assume !(0 == ~E_5~0); 17261#L1116-1 assume !(0 == ~E_6~0); 17262#L1121-1 assume !(0 == ~E_7~0); 17097#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 17098#L1131-1 assume !(0 == ~E_9~0); 17348#L1136-1 assume !(0 == ~E_10~0); 17455#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17612#L514 assume 1 == ~m_pc~0; 17575#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17117#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17034#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17035#L1285 assume !(0 != activate_threads_~tmp~1#1); 17780#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16763#L533 assume !(1 == ~t1_pc~0); 16764#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17277#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17150#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17151#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 17477#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17478#L552 assume 1 == ~t2_pc~0; 16988#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16989#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17556#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17557#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 17129#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17130#L571 assume 1 == ~t3_pc~0; 17307#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17308#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16677#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16678#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 17267#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16553#L590 assume !(1 == ~t4_pc~0); 16554#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17320#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17552#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17553#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17509#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17263#L609 assume 1 == ~t5_pc~0; 17264#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17778#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16590#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16591#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 17258#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17259#L628 assume !(1 == ~t6_pc~0); 17192#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17191#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17763#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17764#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 17548#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17549#L647 assume 1 == ~t7_pc~0; 17106#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17107#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17383#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17109#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 17110#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17810#L666 assume !(1 == ~t8_pc~0); 16893#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16894#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17128#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17284#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 17040#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17041#L685 assume 1 == ~t9_pc~0; 17787#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17684#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17676#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17066#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 17067#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17419#L704 assume !(1 == ~t10_pc~0); 17058#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 17057#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17583#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16609#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 16610#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16857#L1154 assume !(1 == ~M_E~0); 17536#L1154-2 assume !(1 == ~T1_E~0); 16829#L1159-1 assume !(1 == ~T2_E~0); 16830#L1164-1 assume !(1 == ~T3_E~0); 17282#L1169-1 assume !(1 == ~T4_E~0); 17154#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16959#L1179-1 assume !(1 == ~T6_E~0); 16815#L1184-1 assume !(1 == ~T7_E~0); 16816#L1189-1 assume !(1 == ~T8_E~0); 16891#L1194-1 assume !(1 == ~T9_E~0); 17030#L1199-1 assume !(1 == ~T10_E~0); 16974#L1204-1 assume !(1 == ~E_M~0); 16975#L1209-1 assume !(1 == ~E_1~0); 17501#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 17502#L1219-1 assume !(1 == ~E_3~0); 17803#L1224-1 assume !(1 == ~E_4~0); 17302#L1229-1 assume !(1 == ~E_5~0); 16700#L1234-1 assume !(1 == ~E_6~0); 16701#L1239-1 assume !(1 == ~E_7~0); 16759#L1244-1 assume !(1 == ~E_8~0); 16760#L1249-1 assume !(1 == ~E_9~0); 17573#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16602#L1259-1 assume { :end_inline_reset_delta_events } true; 16603#L1565-2 [2021-12-21 22:38:36,794 INFO L793 eck$LassoCheckResult]: Loop: 16603#L1565-2 assume !false; 17511#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16995#L1011 assume !false; 16996#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17045#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16799#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17664#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16823#L866 assume !(0 != eval_~tmp~0#1); 16825#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17412#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17413#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17579#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17765#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17638#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17639#L1051-3 assume !(0 == ~T4_E~0); 17580#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16843#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16844#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16845#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17766#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16594#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16595#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16649#L1091-3 assume !(0 == ~E_1~0); 16650#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17732#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17733#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17762#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17723#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17429#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17430#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17654#L1131-3 assume !(0 == ~E_9~0); 17655#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17814#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17433#L514-36 assume !(1 == ~m_pc~0); 17170#L514-38 is_master_triggered_~__retres1~0#1 := 0; 17018#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17019#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17476#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16902#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16903#L533-36 assume 1 == ~t1_pc~0; 17178#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17271#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17574#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17522#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17325#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17326#L552-36 assume !(1 == ~t2_pc~0); 16896#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 16897#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16716#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16717#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16869#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16870#L571-36 assume 1 == ~t3_pc~0; 17254#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16960#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16961#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17081#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17637#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16930#L590-36 assume !(1 == ~t4_pc~0); 16931#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 17537#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17115#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17116#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17616#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17617#L609-36 assume 1 == ~t5_pc~0; 17492#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17327#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17145#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17146#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17399#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17225#L628-36 assume 1 == ~t6_pc~0; 17084#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17085#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17512#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17513#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17437#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17438#L647-36 assume 1 == ~t7_pc~0; 17366#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16623#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16624#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16643#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 16644#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17538#L666-36 assume 1 == ~t8_pc~0; 16826#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16827#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17727#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17728#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16986#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16987#L685-36 assume !(1 == ~t9_pc~0); 16727#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 16728#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17243#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17244#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17125#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17126#L704-36 assume !(1 == ~t10_pc~0); 16720#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 16719#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17479#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17480#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16748#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16749#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17715#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17593#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17594#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17774#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17054#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17055#L1179-3 assume !(1 == ~T6_E~0); 17686#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16625#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16626#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17001#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17002#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17298#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16491#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16492#L1219-3 assume !(1 == ~E_3~0); 17487#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17488#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17510#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16761#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16762#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17345#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17724#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17490#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17491#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16569#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17316#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17317#L1584 assume !(0 == start_simulation_~tmp~3#1); 17445#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16775#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16470#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16917#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 16918#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17102#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17069#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17070#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 16603#L1565-2 [2021-12-21 22:38:36,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,794 INFO L85 PathProgramCache]: Analyzing trace with hash 659050239, now seen corresponding path program 1 times [2021-12-21 22:38:36,794 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613744025] [2021-12-21 22:38:36,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,818 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613744025] [2021-12-21 22:38:36,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613744025] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,819 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,819 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898445611] [2021-12-21 22:38:36,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1179364202, now seen corresponding path program 1 times [2021-12-21 22:38:36,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358236248] [2021-12-21 22:38:36,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,852 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358236248] [2021-12-21 22:38:36,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358236248] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790193612] [2021-12-21 22:38:36,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,853 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,853 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,854 INFO L87 Difference]: Start difference. First operand 1366 states and 2027 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:36,871 INFO L93 Difference]: Finished difference Result 1366 states and 2026 transitions. [2021-12-21 22:38:36,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:36,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2026 transitions. [2021-12-21 22:38:36,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,886 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2026 transitions. [2021-12-21 22:38:36,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:36,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:36,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2026 transitions. [2021-12-21 22:38:36,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:36,890 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-21 22:38:36,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2026 transitions. [2021-12-21 22:38:36,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:36,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4831625183016106) internal successors, (2026), 1365 states have internal predecessors, (2026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:36,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2026 transitions. [2021-12-21 22:38:36,912 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-21 22:38:36,912 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2026 transitions. [2021-12-21 22:38:36,912 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-21 22:38:36,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2026 transitions. [2021-12-21 22:38:36,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:36,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:36,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:36,917 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,917 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:36,918 INFO L791 eck$LassoCheckResult]: Stem: 20247#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 20248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 20455#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19240#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19241#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20480#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20438#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20439#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20469#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19549#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19550#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19653#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19898#L766-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19829#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19551#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19211#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19212#L1036 assume !(0 == ~M_E~0); 19310#L1036-2 assume !(0 == ~T1_E~0); 20186#L1041-1 assume !(0 == ~T2_E~0); 20187#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19585#L1051-1 assume !(0 == ~T4_E~0); 19586#L1056-1 assume !(0 == ~T5_E~0); 20324#L1061-1 assume !(0 == ~T6_E~0); 19483#L1066-1 assume !(0 == ~T7_E~0); 19484#L1071-1 assume !(0 == ~T8_E~0); 20307#L1076-1 assume !(0 == ~T9_E~0); 19378#L1081-1 assume !(0 == ~T10_E~0); 19379#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 19782#L1091-1 assume !(0 == ~E_1~0); 20484#L1096-1 assume !(0 == ~E_2~0); 20485#L1101-1 assume !(0 == ~E_3~0); 19843#L1106-1 assume !(0 == ~E_4~0); 19844#L1111-1 assume !(0 == ~E_5~0); 20000#L1116-1 assume !(0 == ~E_6~0); 20001#L1121-1 assume !(0 == ~E_7~0); 19836#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 19837#L1131-1 assume !(0 == ~E_9~0); 20087#L1136-1 assume !(0 == ~E_10~0); 20194#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20351#L514 assume 1 == ~m_pc~0; 20314#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19857#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19776#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19777#L1285 assume !(0 != activate_threads_~tmp~1#1); 20520#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19502#L533 assume !(1 == ~t1_pc~0); 19503#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20016#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19889#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19890#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 20216#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20217#L552 assume 1 == ~t2_pc~0; 19728#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19729#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20295#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20296#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 19871#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19872#L571 assume 1 == ~t3_pc~0; 20048#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20049#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19418#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19419#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 20006#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19294#L590 assume !(1 == ~t4_pc~0); 19295#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20059#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20292#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20293#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20249#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20002#L609 assume 1 == ~t5_pc~0; 20003#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20517#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19329#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19330#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 19997#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19998#L628 assume !(1 == ~t6_pc~0); 19931#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19930#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20502#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20503#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 20287#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20288#L647 assume 1 == ~t7_pc~0; 19845#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19846#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20124#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19852#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 19853#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20549#L666 assume !(1 == ~t8_pc~0); 19632#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19633#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19867#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20024#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 19780#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19781#L685 assume 1 == ~t9_pc~0; 20526#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20423#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20415#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19805#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 19806#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20158#L704 assume !(1 == ~t10_pc~0); 19797#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19796#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20322#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19350#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 19351#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19596#L1154 assume !(1 == ~M_E~0); 20275#L1154-2 assume !(1 == ~T1_E~0); 19568#L1159-1 assume !(1 == ~T2_E~0); 19569#L1164-1 assume !(1 == ~T3_E~0); 20021#L1169-1 assume !(1 == ~T4_E~0); 19893#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19700#L1179-1 assume !(1 == ~T6_E~0); 19554#L1184-1 assume !(1 == ~T7_E~0); 19555#L1189-1 assume !(1 == ~T8_E~0); 19630#L1194-1 assume !(1 == ~T9_E~0); 19769#L1199-1 assume !(1 == ~T10_E~0); 19715#L1204-1 assume !(1 == ~E_M~0); 19716#L1209-1 assume !(1 == ~E_1~0); 20242#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 20243#L1219-1 assume !(1 == ~E_3~0); 20542#L1224-1 assume !(1 == ~E_4~0); 20041#L1229-1 assume !(1 == ~E_5~0); 19439#L1234-1 assume !(1 == ~E_6~0); 19440#L1239-1 assume !(1 == ~E_7~0); 19498#L1244-1 assume !(1 == ~E_8~0); 19499#L1249-1 assume !(1 == ~E_9~0); 20312#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19341#L1259-1 assume { :end_inline_reset_delta_events } true; 19342#L1565-2 [2021-12-21 22:38:36,920 INFO L793 eck$LassoCheckResult]: Loop: 19342#L1565-2 assume !false; 20250#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19734#L1011 assume !false; 19735#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19784#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19538#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20403#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19565#L866 assume !(0 != eval_~tmp~0#1); 19567#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20153#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20154#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20318#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20504#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20377#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20378#L1051-3 assume !(0 == ~T4_E~0); 20319#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19582#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19583#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19584#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20505#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19333#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19334#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19392#L1091-3 assume !(0 == ~E_1~0); 19393#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20471#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20472#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20501#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20462#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20169#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20170#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20393#L1131-3 assume !(0 == ~E_9~0); 20394#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20553#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20172#L514-36 assume !(1 == ~m_pc~0); 19909#L514-38 is_master_triggered_~__retres1~0#1 := 0; 19759#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19760#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20215#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19641#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19642#L533-36 assume 1 == ~t1_pc~0; 19917#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20013#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20313#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20261#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20064#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20065#L552-36 assume 1 == ~t2_pc~0; 19634#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19636#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19455#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19456#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19608#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19609#L571-36 assume 1 == ~t3_pc~0; 19993#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19698#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19699#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19820#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20376#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19666#L590-36 assume !(1 == ~t4_pc~0); 19667#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 20276#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19854#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19855#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20355#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20356#L609-36 assume 1 == ~t5_pc~0; 20231#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20066#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19884#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19885#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20138#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19964#L628-36 assume 1 == ~t6_pc~0; 19821#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19822#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20251#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20252#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20176#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20177#L647-36 assume 1 == ~t7_pc~0; 20105#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19362#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19363#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19382#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 19383#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20277#L666-36 assume 1 == ~t8_pc~0; 19562#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19563#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20466#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20467#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19725#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19726#L685-36 assume 1 == ~t9_pc~0; 20152#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19467#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19982#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19983#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19864#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19865#L704-36 assume 1 == ~t10_pc~0; 19457#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19458#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20218#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20219#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19487#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19488#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20454#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20332#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20333#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20513#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19793#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19794#L1179-3 assume !(1 == ~T6_E~0); 20425#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19364#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19365#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19738#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19739#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20037#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19227#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19228#L1219-3 assume !(1 == ~E_3~0); 20226#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20227#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20246#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19500#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19501#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20080#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20463#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20229#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20230#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19308#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20053#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20054#L1584 assume !(0 == start_simulation_~tmp~3#1); 20184#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19514#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19209#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19656#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 19657#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19841#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19808#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19809#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 19342#L1565-2 [2021-12-21 22:38:36,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,921 INFO L85 PathProgramCache]: Analyzing trace with hash -1913914371, now seen corresponding path program 1 times [2021-12-21 22:38:36,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323733458] [2021-12-21 22:38:36,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,944 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323733458] [2021-12-21 22:38:36,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323733458] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,945 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,945 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,945 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823377726] [2021-12-21 22:38:36,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,945 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:36,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:36,946 INFO L85 PathProgramCache]: Analyzing trace with hash -1709033325, now seen corresponding path program 1 times [2021-12-21 22:38:36,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:36,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359416016] [2021-12-21 22:38:36,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:36,949 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:36,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:36,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:36,994 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:36,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359416016] [2021-12-21 22:38:36,994 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359416016] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:36,995 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:36,995 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:36,995 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577265101] [2021-12-21 22:38:36,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:36,995 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:36,995 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:36,996 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:36,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:36,996 INFO L87 Difference]: Start difference. First operand 1366 states and 2026 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:37,012 INFO L93 Difference]: Finished difference Result 1366 states and 2025 transitions. [2021-12-21 22:38:37,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:37,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2025 transitions. [2021-12-21 22:38:37,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:37,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2025 transitions. [2021-12-21 22:38:37,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:37,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:37,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2025 transitions. [2021-12-21 22:38:37,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:37,036 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-21 22:38:37,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2025 transitions. [2021-12-21 22:38:37,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:37,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4824304538799415) internal successors, (2025), 1365 states have internal predecessors, (2025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2025 transitions. [2021-12-21 22:38:37,051 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-21 22:38:37,051 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2025 transitions. [2021-12-21 22:38:37,051 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-21 22:38:37,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2025 transitions. [2021-12-21 22:38:37,054 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:37,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:37,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:37,056 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,056 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,056 INFO L791 eck$LassoCheckResult]: Stem: 22985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 23194#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21977#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21978#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23218#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23177#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23178#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23208#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22286#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22287#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22392#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22637#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22568#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22288#L776-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21950#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21951#L1036 assume !(0 == ~M_E~0); 22049#L1036-2 assume !(0 == ~T1_E~0); 22925#L1041-1 assume !(0 == ~T2_E~0); 22926#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22324#L1051-1 assume !(0 == ~T4_E~0); 22325#L1056-1 assume !(0 == ~T5_E~0); 23063#L1061-1 assume !(0 == ~T6_E~0); 22222#L1066-1 assume !(0 == ~T7_E~0); 22223#L1071-1 assume !(0 == ~T8_E~0); 23046#L1076-1 assume !(0 == ~T9_E~0); 22117#L1081-1 assume !(0 == ~T10_E~0); 22118#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 22521#L1091-1 assume !(0 == ~E_1~0); 23222#L1096-1 assume !(0 == ~E_2~0); 23223#L1101-1 assume !(0 == ~E_3~0); 22582#L1106-1 assume !(0 == ~E_4~0); 22583#L1111-1 assume !(0 == ~E_5~0); 22739#L1116-1 assume !(0 == ~E_6~0); 22740#L1121-1 assume !(0 == ~E_7~0); 22575#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 22576#L1131-1 assume !(0 == ~E_9~0); 22826#L1136-1 assume !(0 == ~E_10~0); 22933#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23090#L514 assume 1 == ~m_pc~0; 23053#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22595#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22512#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22513#L1285 assume !(0 != activate_threads_~tmp~1#1); 23258#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22241#L533 assume !(1 == ~t1_pc~0); 22242#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22755#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22628#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22629#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 22955#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22956#L552 assume 1 == ~t2_pc~0; 22466#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22467#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23034#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23035#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 22607#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22608#L571 assume 1 == ~t3_pc~0; 22785#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22786#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22155#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22156#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 22745#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22031#L590 assume !(1 == ~t4_pc~0); 22032#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22798#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23030#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23031#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22987#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22741#L609 assume 1 == ~t5_pc~0; 22742#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23256#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22068#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22069#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 22736#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22737#L628 assume !(1 == ~t6_pc~0); 22670#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22669#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23241#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23242#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 23026#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23027#L647 assume 1 == ~t7_pc~0; 22584#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22585#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22861#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22587#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 22588#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23288#L666 assume !(1 == ~t8_pc~0); 22371#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22372#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22606#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22762#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 22518#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22519#L685 assume 1 == ~t9_pc~0; 23265#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23162#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23154#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22544#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 22545#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22897#L704 assume !(1 == ~t10_pc~0); 22536#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22535#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23061#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22087#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 22088#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22335#L1154 assume !(1 == ~M_E~0); 23014#L1154-2 assume !(1 == ~T1_E~0); 22307#L1159-1 assume !(1 == ~T2_E~0); 22308#L1164-1 assume !(1 == ~T3_E~0); 22760#L1169-1 assume !(1 == ~T4_E~0); 22632#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22437#L1179-1 assume !(1 == ~T6_E~0); 22293#L1184-1 assume !(1 == ~T7_E~0); 22294#L1189-1 assume !(1 == ~T8_E~0); 22369#L1194-1 assume !(1 == ~T9_E~0); 22508#L1199-1 assume !(1 == ~T10_E~0); 22452#L1204-1 assume !(1 == ~E_M~0); 22453#L1209-1 assume !(1 == ~E_1~0); 22979#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22980#L1219-1 assume !(1 == ~E_3~0); 23281#L1224-1 assume !(1 == ~E_4~0); 22780#L1229-1 assume !(1 == ~E_5~0); 22178#L1234-1 assume !(1 == ~E_6~0); 22179#L1239-1 assume !(1 == ~E_7~0); 22237#L1244-1 assume !(1 == ~E_8~0); 22238#L1249-1 assume !(1 == ~E_9~0); 23051#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22080#L1259-1 assume { :end_inline_reset_delta_events } true; 22081#L1565-2 [2021-12-21 22:38:37,056 INFO L793 eck$LassoCheckResult]: Loop: 22081#L1565-2 assume !false; 22989#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22473#L1011 assume !false; 22474#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22523#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22277#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23142#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22301#L866 assume !(0 != eval_~tmp~0#1); 22303#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22890#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22891#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23057#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23243#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23116#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23117#L1051-3 assume !(0 == ~T4_E~0); 23058#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22321#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22322#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22323#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23244#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22072#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22073#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22127#L1091-3 assume !(0 == ~E_1~0); 22128#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23210#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23211#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23240#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23201#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22907#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22908#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23132#L1131-3 assume !(0 == ~E_9~0); 23133#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23292#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22911#L514-36 assume 1 == ~m_pc~0; 22912#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22496#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22497#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22954#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22380#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22381#L533-36 assume 1 == ~t1_pc~0; 22656#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22749#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23052#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23000#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22803#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22804#L552-36 assume 1 == ~t2_pc~0; 22373#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22375#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22194#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22195#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22347#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22348#L571-36 assume 1 == ~t3_pc~0; 22732#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22438#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22439#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22559#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23115#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22408#L590-36 assume !(1 == ~t4_pc~0); 22409#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 23015#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22593#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22594#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23094#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23095#L609-36 assume 1 == ~t5_pc~0; 22970#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22805#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22623#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22624#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22877#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22703#L628-36 assume 1 == ~t6_pc~0; 22562#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22563#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22990#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22991#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22915#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22916#L647-36 assume 1 == ~t7_pc~0; 22844#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22101#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22102#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22121#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 22122#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23016#L666-36 assume 1 == ~t8_pc~0; 22304#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22305#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23205#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23206#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22464#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22465#L685-36 assume !(1 == ~t9_pc~0); 22205#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 22206#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22721#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22722#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22603#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22604#L704-36 assume 1 == ~t10_pc~0; 22196#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22197#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22957#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22958#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22226#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22227#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23193#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23071#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23072#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23252#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22532#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22533#L1179-3 assume !(1 == ~T6_E~0); 23164#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22103#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22104#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22479#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22480#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22776#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21966#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21967#L1219-3 assume !(1 == ~E_3~0); 22965#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22966#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22988#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22239#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22240#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22823#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23202#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22968#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22969#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22047#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22794#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 22795#L1584 assume !(0 == start_simulation_~tmp~3#1); 22923#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22253#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21948#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22395#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 22396#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22580#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22547#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22548#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 22081#L1565-2 [2021-12-21 22:38:37,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1581271233, now seen corresponding path program 1 times [2021-12-21 22:38:37,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,057 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748263102] [2021-12-21 22:38:37,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,057 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,082 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,082 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748263102] [2021-12-21 22:38:37,083 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748263102] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,083 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,083 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,083 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684064666] [2021-12-21 22:38:37,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,083 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:37,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483539, now seen corresponding path program 4 times [2021-12-21 22:38:37,084 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7337585] [2021-12-21 22:38:37,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,112 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,112 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [7337585] [2021-12-21 22:38:37,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [7337585] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,112 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,112 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657179977] [2021-12-21 22:38:37,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,113 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:37,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:37,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:37,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:37,113 INFO L87 Difference]: Start difference. First operand 1366 states and 2025 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:37,131 INFO L93 Difference]: Finished difference Result 1366 states and 2024 transitions. [2021-12-21 22:38:37,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:37,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1366 states and 2024 transitions. [2021-12-21 22:38:37,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:37,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1366 states to 1366 states and 2024 transitions. [2021-12-21 22:38:37,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1366 [2021-12-21 22:38:37,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1366 [2021-12-21 22:38:37,144 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1366 states and 2024 transitions. [2021-12-21 22:38:37,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:37,146 INFO L681 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-21 22:38:37,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states and 2024 transitions. [2021-12-21 22:38:37,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1366. [2021-12-21 22:38:37,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1366 states, 1366 states have (on average 1.4816983894582723) internal successors, (2024), 1365 states have internal predecessors, (2024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1366 states to 1366 states and 2024 transitions. [2021-12-21 22:38:37,168 INFO L704 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-21 22:38:37,168 INFO L587 BuchiCegarLoop]: Abstraction has 1366 states and 2024 transitions. [2021-12-21 22:38:37,168 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-21 22:38:37,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1366 states and 2024 transitions. [2021-12-21 22:38:37,171 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1227 [2021-12-21 22:38:37,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:37,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:37,173 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,173 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,173 INFO L791 eck$LassoCheckResult]: Stem: 25724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25933#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24716#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24717#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 25957#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25916#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25917#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25947#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25025#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25026#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25131#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25376#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 25307#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25027#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 24689#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24690#L1036 assume !(0 == ~M_E~0); 24788#L1036-2 assume !(0 == ~T1_E~0); 25664#L1041-1 assume !(0 == ~T2_E~0); 25665#L1046-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25063#L1051-1 assume !(0 == ~T4_E~0); 25064#L1056-1 assume !(0 == ~T5_E~0); 25802#L1061-1 assume !(0 == ~T6_E~0); 24961#L1066-1 assume !(0 == ~T7_E~0); 24962#L1071-1 assume !(0 == ~T8_E~0); 25785#L1076-1 assume !(0 == ~T9_E~0); 24856#L1081-1 assume !(0 == ~T10_E~0); 24857#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 25260#L1091-1 assume !(0 == ~E_1~0); 25961#L1096-1 assume !(0 == ~E_2~0); 25962#L1101-1 assume !(0 == ~E_3~0); 25321#L1106-1 assume !(0 == ~E_4~0); 25322#L1111-1 assume !(0 == ~E_5~0); 25478#L1116-1 assume !(0 == ~E_6~0); 25479#L1121-1 assume !(0 == ~E_7~0); 25314#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 25315#L1131-1 assume !(0 == ~E_9~0); 25565#L1136-1 assume !(0 == ~E_10~0); 25672#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25829#L514 assume 1 == ~m_pc~0; 25792#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25334#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25251#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25252#L1285 assume !(0 != activate_threads_~tmp~1#1); 25997#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24980#L533 assume !(1 == ~t1_pc~0); 24981#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25494#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25367#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25368#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 25694#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25695#L552 assume 1 == ~t2_pc~0; 25205#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25206#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25773#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25774#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 25346#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25347#L571 assume 1 == ~t3_pc~0; 25524#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25525#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24894#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24895#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 25484#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24770#L590 assume !(1 == ~t4_pc~0); 24771#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25537#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25769#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25770#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25726#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25480#L609 assume 1 == ~t5_pc~0; 25481#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25995#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24807#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24808#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 25475#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25476#L628 assume !(1 == ~t6_pc~0); 25409#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25408#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25980#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25981#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 25765#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25766#L647 assume 1 == ~t7_pc~0; 25323#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25324#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25600#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25328#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 25329#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26027#L666 assume !(1 == ~t8_pc~0); 25110#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25111#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25345#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25501#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 25257#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25258#L685 assume 1 == ~t9_pc~0; 26004#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25901#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25893#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25283#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 25284#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25636#L704 assume !(1 == ~t10_pc~0); 25275#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25274#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25800#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24826#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 24827#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25074#L1154 assume !(1 == ~M_E~0); 25753#L1154-2 assume !(1 == ~T1_E~0); 25046#L1159-1 assume !(1 == ~T2_E~0); 25047#L1164-1 assume !(1 == ~T3_E~0); 25499#L1169-1 assume !(1 == ~T4_E~0); 25371#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25176#L1179-1 assume !(1 == ~T6_E~0); 25032#L1184-1 assume !(1 == ~T7_E~0); 25033#L1189-1 assume !(1 == ~T8_E~0); 25108#L1194-1 assume !(1 == ~T9_E~0); 25247#L1199-1 assume !(1 == ~T10_E~0); 25191#L1204-1 assume !(1 == ~E_M~0); 25192#L1209-1 assume !(1 == ~E_1~0); 25718#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25719#L1219-1 assume !(1 == ~E_3~0); 26020#L1224-1 assume !(1 == ~E_4~0); 25519#L1229-1 assume !(1 == ~E_5~0); 24917#L1234-1 assume !(1 == ~E_6~0); 24918#L1239-1 assume !(1 == ~E_7~0); 24976#L1244-1 assume !(1 == ~E_8~0); 24977#L1249-1 assume !(1 == ~E_9~0); 25790#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 24819#L1259-1 assume { :end_inline_reset_delta_events } true; 24820#L1565-2 [2021-12-21 22:38:37,173 INFO L793 eck$LassoCheckResult]: Loop: 24820#L1565-2 assume !false; 25728#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25212#L1011 assume !false; 25213#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25262#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25016#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25881#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25040#L866 assume !(0 != eval_~tmp~0#1); 25042#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25629#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25630#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25796#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25982#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25855#L1046-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25856#L1051-3 assume !(0 == ~T4_E~0); 25797#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25060#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25061#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25062#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25983#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24811#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24812#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24866#L1091-3 assume !(0 == ~E_1~0); 24867#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25949#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25950#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25979#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25940#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25646#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25647#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25871#L1131-3 assume !(0 == ~E_9~0); 25872#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 26031#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25650#L514-36 assume 1 == ~m_pc~0; 25651#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25235#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25236#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25693#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25119#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25120#L533-36 assume 1 == ~t1_pc~0; 25395#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25488#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25791#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25739#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25542#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25543#L552-36 assume 1 == ~t2_pc~0; 25112#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25114#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24933#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24934#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25086#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25087#L571-36 assume !(1 == ~t3_pc~0); 25472#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 25177#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25178#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25298#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25854#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25147#L590-36 assume !(1 == ~t4_pc~0); 25148#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 25754#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25332#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25333#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25833#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25834#L609-36 assume 1 == ~t5_pc~0; 25709#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25544#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25362#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25363#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25616#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25442#L628-36 assume 1 == ~t6_pc~0; 25301#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25302#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25729#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25730#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25654#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25655#L647-36 assume !(1 == ~t7_pc~0); 25584#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 24840#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24841#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24860#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 24861#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25755#L666-36 assume 1 == ~t8_pc~0; 25043#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25044#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25944#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25945#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25203#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25204#L685-36 assume !(1 == ~t9_pc~0); 24944#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 24945#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25460#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25461#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25342#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25343#L704-36 assume 1 == ~t10_pc~0; 24935#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24936#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25696#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25697#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24965#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24966#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25932#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25810#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25811#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25991#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25271#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25272#L1179-3 assume !(1 == ~T6_E~0); 25903#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24842#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24843#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25218#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25219#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25515#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24708#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24709#L1219-3 assume !(1 == ~E_3~0); 25704#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25705#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25727#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24978#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24979#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25562#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25941#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25707#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25708#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24786#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25533#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 25534#L1584 assume !(0 == start_simulation_~tmp~3#1); 25662#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24992#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24687#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 25134#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 25135#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25319#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25286#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25287#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 24820#L1565-2 [2021-12-21 22:38:37,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,174 INFO L85 PathProgramCache]: Analyzing trace with hash 711809793, now seen corresponding path program 1 times [2021-12-21 22:38:37,174 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,174 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568920558] [2021-12-21 22:38:37,174 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,205 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568920558] [2021-12-21 22:38:37,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568920558] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,205 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,205 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1943501027] [2021-12-21 22:38:37,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,207 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:37,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,207 INFO L85 PathProgramCache]: Analyzing trace with hash -708994987, now seen corresponding path program 1 times [2021-12-21 22:38:37,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,210 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [66002681] [2021-12-21 22:38:37,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,210 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,248 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [66002681] [2021-12-21 22:38:37,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [66002681] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,249 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214823034] [2021-12-21 22:38:37,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,249 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:37,249 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:37,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:37,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:37,250 INFO L87 Difference]: Start difference. First operand 1366 states and 2024 transitions. cyclomatic complexity: 659 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:37,325 INFO L93 Difference]: Finished difference Result 2514 states and 3712 transitions. [2021-12-21 22:38:37,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:37,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2514 states and 3712 transitions. [2021-12-21 22:38:37,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2021-12-21 22:38:37,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2514 states to 2514 states and 3712 transitions. [2021-12-21 22:38:37,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2514 [2021-12-21 22:38:37,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2514 [2021-12-21 22:38:37,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2514 states and 3712 transitions. [2021-12-21 22:38:37,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:37,349 INFO L681 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-21 22:38:37,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2514 states and 3712 transitions. [2021-12-21 22:38:37,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2514 to 2514. [2021-12-21 22:38:37,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2514 states, 2514 states have (on average 1.4765314240254575) internal successors, (3712), 2513 states have internal predecessors, (3712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2514 states to 2514 states and 3712 transitions. [2021-12-21 22:38:37,407 INFO L704 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-21 22:38:37,407 INFO L587 BuchiCegarLoop]: Abstraction has 2514 states and 3712 transitions. [2021-12-21 22:38:37,407 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-21 22:38:37,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2514 states and 3712 transitions. [2021-12-21 22:38:37,414 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2353 [2021-12-21 22:38:37,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:37,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:37,415 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,415 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,415 INFO L791 eck$LassoCheckResult]: Stem: 29618#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29831#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28606#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28607#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 29857#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29814#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29815#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29846#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28915#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28916#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29021#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29266#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29197#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28917#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 28579#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28580#L1036 assume !(0 == ~M_E~0); 28678#L1036-2 assume !(0 == ~T1_E~0); 29558#L1041-1 assume !(0 == ~T2_E~0); 29559#L1046-1 assume !(0 == ~T3_E~0); 28953#L1051-1 assume !(0 == ~T4_E~0); 28954#L1056-1 assume !(0 == ~T5_E~0); 29697#L1061-1 assume !(0 == ~T6_E~0); 28851#L1066-1 assume !(0 == ~T7_E~0); 28852#L1071-1 assume !(0 == ~T8_E~0); 29680#L1076-1 assume !(0 == ~T9_E~0); 28746#L1081-1 assume !(0 == ~T10_E~0); 28747#L1086-1 assume 0 == ~E_M~0;~E_M~0 := 1; 29150#L1091-1 assume !(0 == ~E_1~0); 29861#L1096-1 assume !(0 == ~E_2~0); 29862#L1101-1 assume !(0 == ~E_3~0); 29211#L1106-1 assume !(0 == ~E_4~0); 29212#L1111-1 assume !(0 == ~E_5~0); 29368#L1116-1 assume !(0 == ~E_6~0); 29369#L1121-1 assume !(0 == ~E_7~0); 29204#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 29205#L1131-1 assume !(0 == ~E_9~0); 29458#L1136-1 assume !(0 == ~E_10~0); 29566#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29726#L514 assume 1 == ~m_pc~0; 29687#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29224#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29141#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29142#L1285 assume !(0 != activate_threads_~tmp~1#1); 29904#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28870#L533 assume !(1 == ~t1_pc~0); 28871#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29384#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29257#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29258#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 29588#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29589#L552 assume 1 == ~t2_pc~0; 29095#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29096#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29668#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29669#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 29236#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29237#L571 assume 1 == ~t3_pc~0; 29416#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29417#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28784#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28785#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 29374#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28660#L590 assume !(1 == ~t4_pc~0); 28661#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 29429#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29664#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29665#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29620#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29370#L609 assume 1 == ~t5_pc~0; 29371#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29902#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28697#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28698#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 29365#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29366#L628 assume !(1 == ~t6_pc~0); 29299#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29298#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29882#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29883#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 29660#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29661#L647 assume 1 == ~t7_pc~0; 29213#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29214#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29493#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29216#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 29217#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29939#L666 assume !(1 == ~t8_pc~0); 29000#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29001#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29235#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29392#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 29147#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29148#L685 assume 1 == ~t9_pc~0; 29915#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29798#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29790#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29173#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 29174#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29530#L704 assume !(1 == ~t10_pc~0); 29165#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29164#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29695#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28716#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 28717#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28964#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29647#L1154-2 assume !(1 == ~T1_E~0); 30126#L1159-1 assume !(1 == ~T2_E~0); 30124#L1164-1 assume !(1 == ~T3_E~0); 29945#L1169-1 assume !(1 == ~T4_E~0); 30121#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30119#L1179-1 assume !(1 == ~T6_E~0); 30116#L1184-1 assume !(1 == ~T7_E~0); 30114#L1189-1 assume !(1 == ~T8_E~0); 30112#L1194-1 assume !(1 == ~T9_E~0); 30110#L1199-1 assume !(1 == ~T10_E~0); 30108#L1204-1 assume !(1 == ~E_M~0); 30106#L1209-1 assume !(1 == ~E_1~0); 30103#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 30101#L1219-1 assume !(1 == ~E_3~0); 30099#L1224-1 assume !(1 == ~E_4~0); 30097#L1229-1 assume !(1 == ~E_5~0); 30095#L1234-1 assume !(1 == ~E_6~0); 30094#L1239-1 assume !(1 == ~E_7~0); 30093#L1244-1 assume !(1 == ~E_8~0); 29998#L1249-1 assume !(1 == ~E_9~0); 29996#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29986#L1259-1 assume { :end_inline_reset_delta_events } true; 29979#L1565-2 [2021-12-21 22:38:37,415 INFO L793 eck$LassoCheckResult]: Loop: 29979#L1565-2 assume !false; 29973#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29968#L1011 assume !false; 29967#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29966#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 29955#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29954#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29953#L866 assume !(0 != eval_~tmp~0#1); 29952#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29951#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29950#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29884#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29885#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29752#L1046-3 assume !(0 == ~T3_E~0); 29753#L1051-3 assume !(0 == ~T4_E~0); 29692#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28950#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28951#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28952#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29886#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28701#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28702#L1086-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28756#L1091-3 assume !(0 == ~E_1~0); 28757#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29848#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29849#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29881#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29838#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29540#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29541#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29768#L1131-3 assume !(0 == ~E_9~0); 29769#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29943#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29544#L514-36 assume 1 == ~m_pc~0; 29545#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29125#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29126#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29587#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29009#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29010#L533-36 assume 1 == ~t1_pc~0; 29285#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29378#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29686#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29633#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29434#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29435#L552-36 assume 1 == ~t2_pc~0; 29002#L553-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29004#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28823#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28824#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28976#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28977#L571-36 assume 1 == ~t3_pc~0; 29361#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29067#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29068#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29188#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29751#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29037#L590-36 assume !(1 == ~t4_pc~0); 29038#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 29649#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29222#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29223#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29730#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29731#L609-36 assume 1 == ~t5_pc~0; 29603#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29436#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29252#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29253#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29509#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29332#L628-36 assume 1 == ~t6_pc~0; 29191#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29192#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29623#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29624#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29548#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29549#L647-36 assume 1 == ~t7_pc~0; 29476#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28730#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28731#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28750#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 28751#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29650#L666-36 assume 1 == ~t8_pc~0; 28933#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28934#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29842#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29843#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29093#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29094#L685-36 assume !(1 == ~t9_pc~0); 28834#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 28835#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29350#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29351#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29232#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29233#L704-36 assume 1 == ~t10_pc~0; 28825#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28826#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29590#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29591#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28855#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28856#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29830#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29705#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29706#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29898#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29161#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29162#L1179-3 assume !(1 == ~T6_E~0); 29800#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28732#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28733#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29108#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29109#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29407#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28595#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28596#L1219-3 assume !(1 == ~E_3~0); 29598#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29599#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29621#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28868#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28869#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29455#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29839#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29601#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29602#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28676#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29425#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29426#L1584 assume !(0 == start_simulation_~tmp~3#1); 29556#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28882#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28577#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29024#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29025#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29209#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29176#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29177#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 29979#L1565-2 [2021-12-21 22:38:37,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1478663553, now seen corresponding path program 1 times [2021-12-21 22:38:37,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968947799] [2021-12-21 22:38:37,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,416 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,438 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,438 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968947799] [2021-12-21 22:38:37,438 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968947799] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,438 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,438 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9890728] [2021-12-21 22:38:37,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:37,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,439 INFO L85 PathProgramCache]: Analyzing trace with hash -2084436651, now seen corresponding path program 1 times [2021-12-21 22:38:37,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,439 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195961498] [2021-12-21 22:38:37,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,466 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,466 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195961498] [2021-12-21 22:38:37,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195961498] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149021702] [2021-12-21 22:38:37,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,467 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:37,467 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:37,467 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:37,467 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:37,467 INFO L87 Difference]: Start difference. First operand 2514 states and 3712 transitions. cyclomatic complexity: 1200 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:37,581 INFO L93 Difference]: Finished difference Result 4640 states and 6839 transitions. [2021-12-21 22:38:37,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:37,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4640 states and 6839 transitions. [2021-12-21 22:38:37,602 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2021-12-21 22:38:37,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4640 states to 4640 states and 6839 transitions. [2021-12-21 22:38:37,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4640 [2021-12-21 22:38:37,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4640 [2021-12-21 22:38:37,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4640 states and 6839 transitions. [2021-12-21 22:38:37,628 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:37,628 INFO L681 BuchiCegarLoop]: Abstraction has 4640 states and 6839 transitions. [2021-12-21 22:38:37,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4640 states and 6839 transitions. [2021-12-21 22:38:37,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4640 to 4638. [2021-12-21 22:38:37,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4638 states, 4638 states have (on average 1.4741267787839587) internal successors, (6837), 4637 states have internal predecessors, (6837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4638 states to 4638 states and 6837 transitions. [2021-12-21 22:38:37,714 INFO L704 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2021-12-21 22:38:37,714 INFO L587 BuchiCegarLoop]: Abstraction has 4638 states and 6837 transitions. [2021-12-21 22:38:37,714 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-21 22:38:37,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4638 states and 6837 transitions. [2021-12-21 22:38:37,728 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4447 [2021-12-21 22:38:37,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:37,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:37,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,730 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:37,730 INFO L791 eck$LassoCheckResult]: Stem: 36799#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 36800#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37024#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35772#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35773#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 37053#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37003#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37004#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37041#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36081#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36082#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36185#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36438#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36366#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36083#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35743#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35744#L1036 assume !(0 == ~M_E~0); 35842#L1036-2 assume !(0 == ~T1_E~0); 36734#L1041-1 assume !(0 == ~T2_E~0); 36735#L1046-1 assume !(0 == ~T3_E~0); 36117#L1051-1 assume !(0 == ~T4_E~0); 36118#L1056-1 assume !(0 == ~T5_E~0); 36879#L1061-1 assume !(0 == ~T6_E~0); 36015#L1066-1 assume !(0 == ~T7_E~0); 36016#L1071-1 assume !(0 == ~T8_E~0); 36862#L1076-1 assume !(0 == ~T9_E~0); 35910#L1081-1 assume !(0 == ~T10_E~0); 35911#L1086-1 assume !(0 == ~E_M~0); 36318#L1091-1 assume !(0 == ~E_1~0); 37057#L1096-1 assume !(0 == ~E_2~0); 37058#L1101-1 assume !(0 == ~E_3~0); 36381#L1106-1 assume !(0 == ~E_4~0); 36382#L1111-1 assume !(0 == ~E_5~0); 36543#L1116-1 assume !(0 == ~E_6~0); 36544#L1121-1 assume !(0 == ~E_7~0); 36374#L1126-1 assume 0 == ~E_8~0;~E_8~0 := 1; 36375#L1131-1 assume !(0 == ~E_9~0); 36632#L1136-1 assume !(0 == ~E_10~0); 36742#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36906#L514 assume 1 == ~m_pc~0; 36869#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36395#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36312#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36313#L1285 assume !(0 != activate_threads_~tmp~1#1); 37095#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36034#L533 assume !(1 == ~t1_pc~0); 36035#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36559#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36427#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36428#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 36764#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36765#L552 assume 1 == ~t2_pc~0; 36264#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36265#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36850#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36851#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 36409#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36410#L571 assume 1 == ~t3_pc~0; 36592#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36593#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35950#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35951#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 36549#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35826#L590 assume !(1 == ~t4_pc~0); 35827#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36603#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36847#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36848#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36801#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36545#L609 assume 1 == ~t5_pc~0; 36546#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37092#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35861#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35862#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 36540#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36541#L628 assume !(1 == ~t6_pc~0); 36471#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 36470#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37075#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37076#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 36842#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36843#L647 assume 1 == ~t7_pc~0; 36383#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36384#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36670#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36390#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 36391#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37128#L666 assume !(1 == ~t8_pc~0); 36164#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36165#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36405#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36568#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 36316#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36317#L685 assume 1 == ~t9_pc~0; 37101#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36985#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36977#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36342#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 36343#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36705#L704 assume !(1 == ~t10_pc~0); 36334#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36333#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36877#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35882#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 35883#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36128#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 36828#L1154-2 assume !(1 == ~T1_E~0); 36100#L1159-1 assume !(1 == ~T2_E~0); 36101#L1164-1 assume !(1 == ~T3_E~0); 37137#L1169-1 assume !(1 == ~T4_E~0); 37902#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37901#L1179-1 assume !(1 == ~T6_E~0); 37900#L1184-1 assume !(1 == ~T7_E~0); 37899#L1189-1 assume !(1 == ~T8_E~0); 37898#L1194-1 assume !(1 == ~T9_E~0); 37897#L1199-1 assume !(1 == ~T10_E~0); 37894#L1204-1 assume !(1 == ~E_M~0); 37890#L1209-1 assume !(1 == ~E_1~0); 37888#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 37886#L1219-1 assume !(1 == ~E_3~0); 37884#L1224-1 assume !(1 == ~E_4~0); 37882#L1229-1 assume !(1 == ~E_5~0); 37881#L1234-1 assume !(1 == ~E_6~0); 37241#L1239-1 assume !(1 == ~E_7~0); 37240#L1244-1 assume !(1 == ~E_8~0); 37239#L1249-1 assume !(1 == ~E_9~0); 37189#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 37180#L1259-1 assume { :end_inline_reset_delta_events } true; 37173#L1565-2 [2021-12-21 22:38:37,730 INFO L793 eck$LassoCheckResult]: Loop: 37173#L1565-2 assume !false; 37167#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37162#L1011 assume !false; 37161#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37160#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37149#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37148#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37146#L866 assume !(0 != eval_~tmp~0#1); 37145#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37144#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37142#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37143#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37591#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37588#L1046-3 assume !(0 == ~T3_E~0); 37586#L1051-3 assume !(0 == ~T4_E~0); 37584#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37582#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37580#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37578#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37575#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37573#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37571#L1086-3 assume !(0 == ~E_M~0); 37569#L1091-3 assume !(0 == ~E_1~0); 37567#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37565#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37562#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37560#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37558#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37556#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37554#L1126-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37552#L1131-3 assume !(0 == ~E_9~0); 37549#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37547#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37545#L514-36 assume 1 == ~m_pc~0; 37542#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37540#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37538#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37535#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37533#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37531#L533-36 assume 1 == ~t1_pc~0; 37528#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37526#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37524#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37522#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37520#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37519#L552-36 assume !(1 == ~t2_pc~0); 37517#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 37516#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37515#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37514#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37513#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37512#L571-36 assume 1 == ~t3_pc~0; 37510#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37509#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37508#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37507#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37506#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37505#L590-36 assume !(1 == ~t4_pc~0); 37502#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 37500#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37498#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37496#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37494#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37491#L609-36 assume 1 == ~t5_pc~0; 37488#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37486#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37484#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37482#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37480#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37479#L628-36 assume !(1 == ~t6_pc~0); 37475#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 37473#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37471#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37469#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37467#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37465#L647-36 assume 1 == ~t7_pc~0; 37461#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37459#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37457#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37455#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 37453#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37451#L666-36 assume 1 == ~t8_pc~0; 37447#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37445#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37443#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37441#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37439#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37437#L685-36 assume !(1 == ~t9_pc~0); 37433#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 37431#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37429#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37427#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 37425#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37423#L704-36 assume 1 == ~t10_pc~0; 37419#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37417#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37415#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37413#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37411#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37409#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37140#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37406#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37404#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37402#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37400#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37398#L1179-3 assume !(1 == ~T6_E~0); 37396#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37394#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37392#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37390#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37389#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37387#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37386#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37384#L1219-3 assume !(1 == ~E_3~0); 37381#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37379#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37377#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37375#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37373#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37371#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37368#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37366#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37343#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37339#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37337#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 37335#L1584 assume !(0 == start_simulation_~tmp~3#1); 37133#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 37207#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37196#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 37194#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 37193#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37192#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37190#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 37181#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 37173#L1565-2 [2021-12-21 22:38:37,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,731 INFO L85 PathProgramCache]: Analyzing trace with hash 171521155, now seen corresponding path program 1 times [2021-12-21 22:38:37,731 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23866615] [2021-12-21 22:38:37,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,731 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,754 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23866615] [2021-12-21 22:38:37,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23866615] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,754 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576761493] [2021-12-21 22:38:37,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,754 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:37,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:37,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1366330151, now seen corresponding path program 1 times [2021-12-21 22:38:37,755 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:37,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035952373] [2021-12-21 22:38:37,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:37,755 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:37,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:37,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:37,780 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:37,780 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035952373] [2021-12-21 22:38:37,780 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035952373] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:37,780 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:37,780 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:37,780 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285770475] [2021-12-21 22:38:37,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:37,781 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:37,781 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:37,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:37,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:37,781 INFO L87 Difference]: Start difference. First operand 4638 states and 6837 transitions. cyclomatic complexity: 2203 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:37,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:37,911 INFO L93 Difference]: Finished difference Result 8692 states and 12784 transitions. [2021-12-21 22:38:37,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:37,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8692 states and 12784 transitions. [2021-12-21 22:38:37,955 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2021-12-21 22:38:38,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8692 states to 8692 states and 12784 transitions. [2021-12-21 22:38:38,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8692 [2021-12-21 22:38:38,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8692 [2021-12-21 22:38:38,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8692 states and 12784 transitions. [2021-12-21 22:38:38,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:38,046 INFO L681 BuchiCegarLoop]: Abstraction has 8692 states and 12784 transitions. [2021-12-21 22:38:38,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8692 states and 12784 transitions. [2021-12-21 22:38:38,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8692 to 8688. [2021-12-21 22:38:38,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8688 states, 8688 states have (on average 1.4709944751381216) internal successors, (12780), 8687 states have internal predecessors, (12780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:38,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8688 states to 8688 states and 12780 transitions. [2021-12-21 22:38:38,208 INFO L704 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2021-12-21 22:38:38,208 INFO L587 BuchiCegarLoop]: Abstraction has 8688 states and 12780 transitions. [2021-12-21 22:38:38,209 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-21 22:38:38,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8688 states and 12780 transitions. [2021-12-21 22:38:38,242 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8477 [2021-12-21 22:38:38,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:38,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:38,244 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:38,244 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:38,244 INFO L791 eck$LassoCheckResult]: Stem: 50132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 50133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 50357#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49110#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49111#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 50381#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50337#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50338#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50371#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49420#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49421#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49526#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49774#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49704#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49422#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49083#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49084#L1036 assume !(0 == ~M_E~0); 49182#L1036-2 assume !(0 == ~T1_E~0); 50066#L1041-1 assume !(0 == ~T2_E~0); 50067#L1046-1 assume !(0 == ~T3_E~0); 49458#L1051-1 assume !(0 == ~T4_E~0); 49459#L1056-1 assume !(0 == ~T5_E~0); 50214#L1061-1 assume !(0 == ~T6_E~0); 49355#L1066-1 assume !(0 == ~T7_E~0); 49356#L1071-1 assume !(0 == ~T8_E~0); 50197#L1076-1 assume !(0 == ~T9_E~0); 49250#L1081-1 assume !(0 == ~T10_E~0); 49251#L1086-1 assume !(0 == ~E_M~0); 49657#L1091-1 assume !(0 == ~E_1~0); 50385#L1096-1 assume !(0 == ~E_2~0); 50386#L1101-1 assume !(0 == ~E_3~0); 49718#L1106-1 assume !(0 == ~E_4~0); 49719#L1111-1 assume !(0 == ~E_5~0); 49877#L1116-1 assume !(0 == ~E_6~0); 49878#L1121-1 assume !(0 == ~E_7~0); 49711#L1126-1 assume !(0 == ~E_8~0); 49712#L1131-1 assume !(0 == ~E_9~0); 49966#L1136-1 assume !(0 == ~E_10~0); 50075#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50242#L514 assume 1 == ~m_pc~0; 50204#L515 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49731#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49648#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49649#L1285 assume !(0 != activate_threads_~tmp~1#1); 50424#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49375#L533 assume !(1 == ~t1_pc~0); 49376#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49893#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49764#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49765#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 50097#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50098#L552 assume 1 == ~t2_pc~0; 49602#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49603#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50185#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50186#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 49743#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49744#L571 assume 1 == ~t3_pc~0; 49924#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49925#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49288#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49289#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 49883#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49164#L590 assume !(1 == ~t4_pc~0); 49165#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49937#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50181#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50182#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50134#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49879#L609 assume 1 == ~t5_pc~0; 49880#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50422#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49201#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49202#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 49874#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49875#L628 assume !(1 == ~t6_pc~0); 49807#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49806#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50405#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50406#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 50177#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50178#L647 assume 1 == ~t7_pc~0; 49720#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49721#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50001#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49723#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 49724#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50460#L666 assume !(1 == ~t8_pc~0); 49505#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49506#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49742#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49901#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 49654#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49655#L685 assume 1 == ~t9_pc~0; 50432#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50320#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50312#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49680#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 49681#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50038#L704 assume !(1 == ~t10_pc~0); 49672#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49671#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50212#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49220#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 49221#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49469#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 50161#L1154-2 assume !(1 == ~T1_E~0); 49441#L1159-1 assume !(1 == ~T2_E~0); 49442#L1164-1 assume !(1 == ~T3_E~0); 50721#L1169-1 assume !(1 == ~T4_E~0); 50719#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50717#L1179-1 assume !(1 == ~T6_E~0); 50715#L1184-1 assume !(1 == ~T7_E~0); 50714#L1189-1 assume !(1 == ~T8_E~0); 50702#L1194-1 assume !(1 == ~T9_E~0); 50482#L1199-1 assume !(1 == ~T10_E~0); 50483#L1204-1 assume !(1 == ~E_M~0); 50672#L1209-1 assume !(1 == ~E_1~0); 50668#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 50664#L1219-1 assume !(1 == ~E_3~0); 50660#L1224-1 assume !(1 == ~E_4~0); 50656#L1229-1 assume !(1 == ~E_5~0); 50650#L1234-1 assume !(1 == ~E_6~0); 50646#L1239-1 assume !(1 == ~E_7~0); 50642#L1244-1 assume !(1 == ~E_8~0); 50549#L1249-1 assume !(1 == ~E_9~0); 50534#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 50524#L1259-1 assume { :end_inline_reset_delta_events } true; 50517#L1565-2 [2021-12-21 22:38:38,245 INFO L793 eck$LassoCheckResult]: Loop: 50517#L1565-2 assume !false; 50511#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50506#L1011 assume !false; 50505#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50504#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50493#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50492#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50490#L866 assume !(0 != eval_~tmp~0#1); 50489#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50488#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50486#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50487#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52471#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52469#L1046-3 assume !(0 == ~T3_E~0); 52467#L1051-3 assume !(0 == ~T4_E~0); 52231#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52229#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52228#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52226#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52224#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52010#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52008#L1086-3 assume !(0 == ~E_M~0); 52006#L1091-3 assume !(0 == ~E_1~0); 52004#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52002#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52000#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51843#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51841#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51839#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51837#L1126-3 assume !(0 == ~E_8~0); 51835#L1131-3 assume !(0 == ~E_9~0); 51833#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51830#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51828#L514-36 assume 1 == ~m_pc~0; 51825#L515-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51823#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51822#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51820#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51818#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51816#L533-36 assume 1 == ~t1_pc~0; 51813#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51810#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51808#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51806#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51804#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51802#L552-36 assume !(1 == ~t2_pc~0); 51799#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 51796#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51794#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51792#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49481#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49482#L571-36 assume 1 == ~t3_pc~0; 50274#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49573#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49574#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49695#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51291#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51290#L590-36 assume !(1 == ~t4_pc~0); 51287#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 51285#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51283#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51281#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51279#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51276#L609-36 assume 1 == ~t5_pc~0; 51273#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51271#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51269#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51267#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51265#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51264#L628-36 assume !(1 == ~t6_pc~0); 51262#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 51260#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51257#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51255#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51253#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51251#L647-36 assume 1 == ~t7_pc~0; 51248#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51246#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51243#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51242#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 51240#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51237#L666-36 assume 1 == ~t8_pc~0; 51234#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51232#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51230#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51228#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51226#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51223#L685-36 assume !(1 == ~t9_pc~0); 51220#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 51218#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51216#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51214#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51041#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51039#L704-36 assume 1 == ~t10_pc~0; 51002#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51000#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50998#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50965#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50963#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50961#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50481#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50924#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50921#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50917#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50885#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50883#L1179-3 assume !(1 == ~T6_E~0); 50853#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50851#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50849#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50821#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50758#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50752#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50750#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50748#L1219-3 assume !(1 == ~E_3~0); 50746#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50744#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50742#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50740#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50738#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50735#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50734#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50733#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50724#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50720#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50718#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 50716#L1584 assume !(0 == start_simulation_~tmp~3#1); 50471#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 50712#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 50701#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 50683#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 50675#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50550#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50535#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50525#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 50517#L1565-2 [2021-12-21 22:38:38,245 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:38,246 INFO L85 PathProgramCache]: Analyzing trace with hash -711987835, now seen corresponding path program 1 times [2021-12-21 22:38:38,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:38,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876254805] [2021-12-21 22:38:38,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:38,246 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:38,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:38,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:38,273 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:38,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876254805] [2021-12-21 22:38:38,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876254805] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:38,273 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:38,273 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:38,273 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377519963] [2021-12-21 22:38:38,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:38,274 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:38,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:38,275 INFO L85 PathProgramCache]: Analyzing trace with hash -1247888677, now seen corresponding path program 1 times [2021-12-21 22:38:38,275 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:38,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826796693] [2021-12-21 22:38:38,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:38,276 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:38,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:38,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:38,303 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:38,304 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826796693] [2021-12-21 22:38:38,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826796693] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:38,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:38,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:38,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810998438] [2021-12-21 22:38:38,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:38,305 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:38,305 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:38,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:38,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:38,306 INFO L87 Difference]: Start difference. First operand 8688 states and 12780 transitions. cyclomatic complexity: 4100 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:38,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:38,423 INFO L93 Difference]: Finished difference Result 17011 states and 24827 transitions. [2021-12-21 22:38:38,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:38,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17011 states and 24827 transitions. [2021-12-21 22:38:38,556 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16793 [2021-12-21 22:38:38,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17011 states to 17011 states and 24827 transitions. [2021-12-21 22:38:38,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17011 [2021-12-21 22:38:38,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17011 [2021-12-21 22:38:38,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17011 states and 24827 transitions. [2021-12-21 22:38:38,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:38,623 INFO L681 BuchiCegarLoop]: Abstraction has 17011 states and 24827 transitions. [2021-12-21 22:38:38,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17011 states and 24827 transitions. [2021-12-21 22:38:38,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17011 to 16403. [2021-12-21 22:38:38,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16403 states, 16403 states have (on average 1.4613790160336524) internal successors, (23971), 16402 states have internal predecessors, (23971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:38,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16403 states to 16403 states and 23971 transitions. [2021-12-21 22:38:38,890 INFO L704 BuchiCegarLoop]: Abstraction has 16403 states and 23971 transitions. [2021-12-21 22:38:38,890 INFO L587 BuchiCegarLoop]: Abstraction has 16403 states and 23971 transitions. [2021-12-21 22:38:38,890 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-21 22:38:38,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16403 states and 23971 transitions. [2021-12-21 22:38:38,943 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16185 [2021-12-21 22:38:38,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:38,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:38,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:38,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:38,946 INFO L791 eck$LassoCheckResult]: Stem: 75907#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 75908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 76189#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74818#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74819#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 76222#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76159#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76160#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76208#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75133#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75134#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75246#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 75498#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75427#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75135#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74789#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74790#L1036 assume !(0 == ~M_E~0); 74888#L1036-2 assume !(0 == ~T1_E~0); 75830#L1041-1 assume !(0 == ~T2_E~0); 75831#L1046-1 assume !(0 == ~T3_E~0); 75175#L1051-1 assume !(0 == ~T4_E~0); 75176#L1056-1 assume !(0 == ~T5_E~0); 75994#L1061-1 assume !(0 == ~T6_E~0); 75062#L1066-1 assume !(0 == ~T7_E~0); 75063#L1071-1 assume !(0 == ~T8_E~0); 75979#L1076-1 assume !(0 == ~T9_E~0); 74955#L1081-1 assume !(0 == ~T10_E~0); 74956#L1086-1 assume !(0 == ~E_M~0); 75381#L1091-1 assume !(0 == ~E_1~0); 76228#L1096-1 assume !(0 == ~E_2~0); 76229#L1101-1 assume !(0 == ~E_3~0); 75441#L1106-1 assume !(0 == ~E_4~0); 75442#L1111-1 assume !(0 == ~E_5~0); 75613#L1116-1 assume !(0 == ~E_6~0); 75614#L1121-1 assume !(0 == ~E_7~0); 75434#L1126-1 assume !(0 == ~E_8~0); 75435#L1131-1 assume !(0 == ~E_9~0); 75716#L1136-1 assume !(0 == ~E_10~0); 75843#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76031#L514 assume !(1 == ~m_pc~0); 76032#L514-2 is_master_triggered_~__retres1~0#1 := 0; 75455#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75374#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75375#L1285 assume !(0 != activate_threads_~tmp~1#1); 76289#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75085#L533 assume !(1 == ~t1_pc~0); 75086#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75633#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75489#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75490#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 75872#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75873#L552 assume 1 == ~t2_pc~0; 75325#L553 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75326#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75963#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75964#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 75471#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75472#L571 assume 1 == ~t3_pc~0; 75671#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75672#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74996#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74997#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 75619#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74872#L590 assume !(1 == ~t4_pc~0); 74873#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75682#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75960#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75961#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75909#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75615#L609 assume 1 == ~t5_pc~0; 75616#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76283#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74907#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74908#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 75609#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75610#L628 assume !(1 == ~t6_pc~0); 75535#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 75534#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76252#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76253#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 75955#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75956#L647 assume 1 == ~t7_pc~0; 75443#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75444#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75760#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75450#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 75451#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76360#L666 assume !(1 == ~t8_pc~0); 75226#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 75227#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 75467#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75644#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 75378#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75379#L685 assume 1 == ~t9_pc~0; 76303#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76140#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76127#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75403#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 75404#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75799#L704 assume !(1 == ~t10_pc~0); 75395#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75394#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75992#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74927#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 74928#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75185#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 75940#L1154-2 assume !(1 == ~T1_E~0); 75153#L1159-1 assume !(1 == ~T2_E~0); 75154#L1164-1 assume !(1 == ~T3_E~0); 75639#L1169-1 assume !(1 == ~T4_E~0); 75493#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75296#L1179-1 assume !(1 == ~T6_E~0); 75139#L1184-1 assume !(1 == ~T7_E~0); 75140#L1189-1 assume !(1 == ~T8_E~0); 75224#L1194-1 assume !(1 == ~T9_E~0); 75366#L1199-1 assume !(1 == ~T10_E~0); 75311#L1204-1 assume !(1 == ~E_M~0); 75312#L1209-1 assume !(1 == ~E_1~0); 79540#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 79538#L1219-1 assume !(1 == ~E_3~0); 79536#L1224-1 assume !(1 == ~E_4~0); 79534#L1229-1 assume !(1 == ~E_5~0); 77516#L1234-1 assume !(1 == ~E_6~0); 77514#L1239-1 assume !(1 == ~E_7~0); 77512#L1244-1 assume !(1 == ~E_8~0); 77492#L1249-1 assume !(1 == ~E_9~0); 77477#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 77467#L1259-1 assume { :end_inline_reset_delta_events } true; 77460#L1565-2 [2021-12-21 22:38:38,946 INFO L793 eck$LassoCheckResult]: Loop: 77460#L1565-2 assume !false; 77454#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77449#L1011 assume !false; 77448#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77447#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77436#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77435#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77433#L866 assume !(0 != eval_~tmp~0#1); 77432#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77431#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77428#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77429#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78220#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78216#L1046-3 assume !(0 == ~T3_E~0); 78212#L1051-3 assume !(0 == ~T4_E~0); 78208#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78204#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78200#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78196#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 78192#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78188#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78184#L1086-3 assume !(0 == ~E_M~0); 78180#L1091-3 assume !(0 == ~E_1~0); 78176#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78172#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78168#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78164#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 78160#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78156#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 78152#L1126-3 assume !(0 == ~E_8~0); 78148#L1131-3 assume !(0 == ~E_9~0); 78144#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 78140#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78136#L514-36 assume !(1 == ~m_pc~0); 78132#L514-38 is_master_triggered_~__retres1~0#1 := 0; 78128#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78124#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78120#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78116#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78112#L533-36 assume 1 == ~t1_pc~0; 78105#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78100#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78096#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78092#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78088#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78083#L552-36 assume !(1 == ~t2_pc~0); 78075#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 78071#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78067#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78063#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78059#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78055#L571-36 assume !(1 == ~t3_pc~0); 78048#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 78043#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78039#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78035#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78031#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78027#L590-36 assume !(1 == ~t4_pc~0); 78019#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 78015#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78011#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78007#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78003#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77999#L609-36 assume 1 == ~t5_pc~0; 77991#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77987#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77983#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77979#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77975#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77971#L628-36 assume !(1 == ~t6_pc~0); 77963#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 77959#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77955#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77951#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77947#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77944#L647-36 assume 1 == ~t7_pc~0; 77937#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77932#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77928#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77924#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 77920#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77916#L666-36 assume 1 == ~t8_pc~0; 77909#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77904#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77900#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77896#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77892#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77888#L685-36 assume !(1 == ~t9_pc~0); 77881#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 77876#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77872#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77868#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77864#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77860#L704-36 assume 1 == ~t10_pc~0; 77853#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77848#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77844#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77840#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77836#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77832#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76413#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77825#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77820#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77816#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77814#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77812#L1179-3 assume !(1 == ~T6_E~0); 77810#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77808#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77806#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77804#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 77801#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77798#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77796#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77794#L1219-3 assume !(1 == ~E_3~0); 77792#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77790#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77788#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77786#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 77785#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 77782#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77781#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 77780#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77763#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77756#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77751#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 77748#L1584 assume !(0 == start_simulation_~tmp~3#1); 77029#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 77743#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 77729#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 77725#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 77513#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77493#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77478#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 77468#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 77460#L1565-2 [2021-12-21 22:38:38,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:38,947 INFO L85 PathProgramCache]: Analyzing trace with hash -2098669114, now seen corresponding path program 1 times [2021-12-21 22:38:38,947 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:38,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809277118] [2021-12-21 22:38:38,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:38,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:38,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:38,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:38,979 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:38,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809277118] [2021-12-21 22:38:38,979 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809277118] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:38,979 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:38,979 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:38,979 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685638207] [2021-12-21 22:38:38,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:38,981 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:38,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:38,981 INFO L85 PathProgramCache]: Analyzing trace with hash 616939165, now seen corresponding path program 1 times [2021-12-21 22:38:38,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:38,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35769734] [2021-12-21 22:38:38,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:38,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:38,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:39,006 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:39,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:39,007 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35769734] [2021-12-21 22:38:39,007 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35769734] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:39,007 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:39,007 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:39,007 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602297657] [2021-12-21 22:38:39,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:39,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:39,008 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:39,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:39,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:39,008 INFO L87 Difference]: Start difference. First operand 16403 states and 23971 transitions. cyclomatic complexity: 7584 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:39,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:39,328 INFO L93 Difference]: Finished difference Result 39772 states and 57640 transitions. [2021-12-21 22:38:39,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:39,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39772 states and 57640 transitions. [2021-12-21 22:38:39,703 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 38883 [2021-12-21 22:38:39,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39772 states to 39772 states and 57640 transitions. [2021-12-21 22:38:39,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39772 [2021-12-21 22:38:39,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39772 [2021-12-21 22:38:39,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39772 states and 57640 transitions. [2021-12-21 22:38:39,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:39,918 INFO L681 BuchiCegarLoop]: Abstraction has 39772 states and 57640 transitions. [2021-12-21 22:38:39,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39772 states and 57640 transitions. [2021-12-21 22:38:40,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39772 to 31137. [2021-12-21 22:38:40,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31137 states, 31137 states have (on average 1.454764428172271) internal successors, (45297), 31136 states have internal predecessors, (45297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:40,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31137 states to 31137 states and 45297 transitions. [2021-12-21 22:38:40,538 INFO L704 BuchiCegarLoop]: Abstraction has 31137 states and 45297 transitions. [2021-12-21 22:38:40,538 INFO L587 BuchiCegarLoop]: Abstraction has 31137 states and 45297 transitions. [2021-12-21 22:38:40,538 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-21 22:38:40,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31137 states and 45297 transitions. [2021-12-21 22:38:40,640 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30912 [2021-12-21 22:38:40,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:40,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:40,642 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:40,642 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:40,643 INFO L791 eck$LassoCheckResult]: Stem: 132047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 132048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 132285#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131001#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131002#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 132322#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132265#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132266#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132307#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131308#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131309#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131416#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131667#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 131597#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 131310#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 130974#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130975#L1036 assume !(0 == ~M_E~0); 131072#L1036-2 assume !(0 == ~T1_E~0); 131973#L1041-1 assume !(0 == ~T2_E~0); 131974#L1046-1 assume !(0 == ~T3_E~0); 131347#L1051-1 assume !(0 == ~T4_E~0); 131348#L1056-1 assume !(0 == ~T5_E~0); 132132#L1061-1 assume !(0 == ~T6_E~0); 131244#L1066-1 assume !(0 == ~T7_E~0); 131245#L1071-1 assume !(0 == ~T8_E~0); 132116#L1076-1 assume !(0 == ~T9_E~0); 131139#L1081-1 assume !(0 == ~T10_E~0); 131140#L1086-1 assume !(0 == ~E_M~0); 131550#L1091-1 assume !(0 == ~E_1~0); 132330#L1096-1 assume !(0 == ~E_2~0); 132331#L1101-1 assume !(0 == ~E_3~0); 131611#L1106-1 assume !(0 == ~E_4~0); 131612#L1111-1 assume !(0 == ~E_5~0); 131774#L1116-1 assume !(0 == ~E_6~0); 131775#L1121-1 assume !(0 == ~E_7~0); 131604#L1126-1 assume !(0 == ~E_8~0); 131605#L1131-1 assume !(0 == ~E_9~0); 131868#L1136-1 assume !(0 == ~E_10~0); 131986#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132164#L514 assume !(1 == ~m_pc~0); 132165#L514-2 is_master_triggered_~__retres1~0#1 := 0; 131624#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131540#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 131541#L1285 assume !(0 != activate_threads_~tmp~1#1); 132380#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131264#L533 assume !(1 == ~t1_pc~0); 131265#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131790#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131657#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131658#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 132012#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132013#L552 assume !(1 == ~t2_pc~0); 131732#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131733#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132102#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132103#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 131636#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131637#L571 assume 1 == ~t3_pc~0; 131824#L572 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 131825#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131177#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131178#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 131780#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131054#L590 assume !(1 == ~t4_pc~0); 131055#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131838#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132098#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132099#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132049#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131776#L609 assume 1 == ~t5_pc~0; 131777#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132377#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131091#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131092#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 131771#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131772#L628 assume !(1 == ~t6_pc~0); 131700#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 131699#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132354#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132355#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 132094#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132095#L647 assume 1 == ~t7_pc~0; 131613#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 131614#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131904#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131616#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 131617#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132426#L666 assume !(1 == ~t8_pc~0); 131396#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 131397#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131635#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131798#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 131547#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131548#L685 assume 1 == ~t9_pc~0; 132390#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132250#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132242#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131572#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 131573#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131945#L704 assume !(1 == ~t10_pc~0); 131565#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131564#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132130#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131109#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 131110#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131358#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 132079#L1154-2 assume !(1 == ~T1_E~0); 132409#L1159-1 assume !(1 == ~T2_E~0); 132452#L1164-1 assume !(1 == ~T3_E~0); 132453#L1169-1 assume !(1 == ~T4_E~0); 131661#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131662#L1179-1 assume !(1 == ~T6_E~0); 131315#L1184-1 assume !(1 == ~T7_E~0); 131316#L1189-1 assume !(1 == ~T8_E~0); 131535#L1194-1 assume !(1 == ~T9_E~0); 131536#L1199-1 assume !(1 == ~T10_E~0); 131479#L1204-1 assume !(1 == ~E_M~0); 131480#L1209-1 assume !(1 == ~E_1~0); 143194#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 143193#L1219-1 assume !(1 == ~E_3~0); 143192#L1224-1 assume !(1 == ~E_4~0); 143191#L1229-1 assume !(1 == ~E_5~0); 143190#L1234-1 assume !(1 == ~E_6~0); 143189#L1239-1 assume !(1 == ~E_7~0); 143188#L1244-1 assume !(1 == ~E_8~0); 143185#L1249-1 assume !(1 == ~E_9~0); 143184#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 143182#L1259-1 assume { :end_inline_reset_delta_events } true; 143099#L1565-2 [2021-12-21 22:38:40,643 INFO L793 eck$LassoCheckResult]: Loop: 143099#L1565-2 assume !false; 143084#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143073#L1011 assume !false; 143065#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 142658#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 142646#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 142642#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 142629#L866 assume !(0 != eval_~tmp~0#1); 142630#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 143770#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143768#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 143766#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143763#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 143761#L1046-3 assume !(0 == ~T3_E~0); 143759#L1051-3 assume !(0 == ~T4_E~0); 143757#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 143755#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 143753#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 143750#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 143748#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 143746#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 143744#L1086-3 assume !(0 == ~E_M~0); 143742#L1091-3 assume !(0 == ~E_1~0); 143740#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 143737#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 143735#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 143733#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 143731#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 143729#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 143727#L1126-3 assume !(0 == ~E_8~0); 143724#L1131-3 assume !(0 == ~E_9~0); 143722#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 143720#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143718#L514-36 assume !(1 == ~m_pc~0); 143716#L514-38 is_master_triggered_~__retres1~0#1 := 0; 143714#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 143711#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 143709#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 143707#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 143705#L533-36 assume 1 == ~t1_pc~0; 143702#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 143700#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143697#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 143695#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 143693#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143691#L552-36 assume !(1 == ~t2_pc~0); 136670#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 143688#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143685#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 143683#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 143681#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143679#L571-36 assume 1 == ~t3_pc~0; 143676#L572-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 143674#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143671#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 143669#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 143667#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143665#L590-36 assume !(1 == ~t4_pc~0); 143662#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 143660#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143658#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143656#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143655#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143654#L609-36 assume 1 == ~t5_pc~0; 143652#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 143651#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143650#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 143649#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 143648#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143647#L628-36 assume 1 == ~t6_pc~0; 143646#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 143644#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143643#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 143641#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 143639#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143637#L647-36 assume 1 == ~t7_pc~0; 143634#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 143632#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143630#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 143628#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 143625#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 143623#L666-36 assume 1 == ~t8_pc~0; 143620#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143618#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 143616#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 143614#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 143613#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 143611#L685-36 assume !(1 == ~t9_pc~0); 143608#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 143606#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143604#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 143602#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 143599#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 143597#L704-36 assume 1 == ~t10_pc~0; 143594#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 143592#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 143590#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 143588#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 143585#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143583#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 132464#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 143580#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 143578#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143574#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143571#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143569#L1179-3 assume !(1 == ~T6_E~0); 143567#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 143565#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 143563#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 143561#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 143558#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143554#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143552#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 143550#L1219-3 assume !(1 == ~E_3~0); 143548#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143546#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143543#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 143541#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 143539#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 143535#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 143533#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 143531#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 143348#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 143344#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 143343#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 143342#L1584 assume !(0 == start_simulation_~tmp~3#1); 132445#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 143324#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 143313#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 143311#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 143309#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143307#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143304#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 143183#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 143099#L1565-2 [2021-12-21 22:38:40,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:40,643 INFO L85 PathProgramCache]: Analyzing trace with hash 353984391, now seen corresponding path program 1 times [2021-12-21 22:38:40,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:40,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476429585] [2021-12-21 22:38:40,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:40,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:40,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:40,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:40,679 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:40,679 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476429585] [2021-12-21 22:38:40,679 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476429585] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:40,679 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:40,679 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:40,679 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172789266] [2021-12-21 22:38:40,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:40,679 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:40,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:40,680 INFO L85 PathProgramCache]: Analyzing trace with hash 1639444059, now seen corresponding path program 1 times [2021-12-21 22:38:40,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:40,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637441130] [2021-12-21 22:38:40,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:40,680 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:40,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:40,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:40,714 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:40,715 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637441130] [2021-12-21 22:38:40,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637441130] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:40,716 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:40,716 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:40,716 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959317705] [2021-12-21 22:38:40,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:40,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:40,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:40,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:40,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:40,717 INFO L87 Difference]: Start difference. First operand 31137 states and 45297 transitions. cyclomatic complexity: 14176 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:41,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:41,309 INFO L93 Difference]: Finished difference Result 75513 states and 109021 transitions. [2021-12-21 22:38:41,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:41,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75513 states and 109021 transitions. [2021-12-21 22:38:41,740 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 73953 [2021-12-21 22:38:41,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75513 states to 75513 states and 109021 transitions. [2021-12-21 22:38:41,985 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75513 [2021-12-21 22:38:42,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75513 [2021-12-21 22:38:42,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75513 states and 109021 transitions. [2021-12-21 22:38:42,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:42,234 INFO L681 BuchiCegarLoop]: Abstraction has 75513 states and 109021 transitions. [2021-12-21 22:38:42,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75513 states and 109021 transitions. [2021-12-21 22:38:42,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75513 to 59180. [2021-12-21 22:38:42,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59180 states, 59180 states have (on average 1.4490368367691788) internal successors, (85754), 59179 states have internal predecessors, (85754), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:43,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59180 states to 59180 states and 85754 transitions. [2021-12-21 22:38:43,179 INFO L704 BuchiCegarLoop]: Abstraction has 59180 states and 85754 transitions. [2021-12-21 22:38:43,179 INFO L587 BuchiCegarLoop]: Abstraction has 59180 states and 85754 transitions. [2021-12-21 22:38:43,179 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-21 22:38:43,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59180 states and 85754 transitions. [2021-12-21 22:38:43,306 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 58940 [2021-12-21 22:38:43,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:43,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:43,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:43,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:43,308 INFO L791 eck$LassoCheckResult]: Stem: 238702#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 238703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 238955#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 237661#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 237662#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 238985#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 238932#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 238933#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238973#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 237966#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237967#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 238074#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 238319#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238247#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 237968#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 237634#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237635#L1036 assume !(0 == ~M_E~0); 237732#L1036-2 assume !(0 == ~T1_E~0); 238628#L1041-1 assume !(0 == ~T2_E~0); 238629#L1046-1 assume !(0 == ~T3_E~0); 238007#L1051-1 assume !(0 == ~T4_E~0); 238008#L1056-1 assume !(0 == ~T5_E~0); 238789#L1061-1 assume !(0 == ~T6_E~0); 237903#L1066-1 assume !(0 == ~T7_E~0); 237904#L1071-1 assume !(0 == ~T8_E~0); 238772#L1076-1 assume !(0 == ~T9_E~0); 237799#L1081-1 assume !(0 == ~T10_E~0); 237800#L1086-1 assume !(0 == ~E_M~0); 238201#L1091-1 assume !(0 == ~E_1~0); 238992#L1096-1 assume !(0 == ~E_2~0); 238993#L1101-1 assume !(0 == ~E_3~0); 238261#L1106-1 assume !(0 == ~E_4~0); 238262#L1111-1 assume !(0 == ~E_5~0); 238429#L1116-1 assume !(0 == ~E_6~0); 238430#L1121-1 assume !(0 == ~E_7~0); 238254#L1126-1 assume !(0 == ~E_8~0); 238255#L1131-1 assume !(0 == ~E_9~0); 238524#L1136-1 assume !(0 == ~E_10~0); 238641#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 238820#L514 assume !(1 == ~m_pc~0); 238821#L514-2 is_master_triggered_~__retres1~0#1 := 0; 238274#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238192#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238193#L1285 assume !(0 != activate_threads_~tmp~1#1); 239032#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237922#L533 assume !(1 == ~t1_pc~0); 237923#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 238445#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 238310#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238311#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 238668#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238669#L552 assume !(1 == ~t2_pc~0); 238385#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 238386#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238759#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 238760#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 238286#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238287#L571 assume !(1 == ~t3_pc~0); 238496#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 238570#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237836#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 237837#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 238435#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237714#L590 assume !(1 == ~t4_pc~0); 237715#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 238488#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238752#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 238753#L1317 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 238704#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238431#L609 assume 1 == ~t5_pc~0; 238432#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239030#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237751#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 237752#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 238425#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238426#L628 assume !(1 == ~t6_pc~0); 238354#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 238353#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 239014#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 239015#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 238748#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 238749#L647 assume 1 == ~t7_pc~0; 238263#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 238264#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 238560#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 238266#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 238267#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239083#L666 assume !(1 == ~t8_pc~0); 238054#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 238055#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 238285#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 238453#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 238198#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 238199#L685 assume 1 == ~t9_pc~0; 239042#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 238915#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 238908#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 238223#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 238224#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238598#L704 assume !(1 == ~t10_pc~0); 238216#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 238215#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 238787#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 237769#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 237770#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238018#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 238733#L1154-2 assume !(1 == ~T1_E~0); 237990#L1159-1 assume !(1 == ~T2_E~0); 237991#L1164-1 assume !(1 == ~T3_E~0); 238451#L1169-1 assume !(1 == ~T4_E~0); 238314#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 238118#L1179-1 assume !(1 == ~T6_E~0); 237975#L1184-1 assume !(1 == ~T7_E~0); 237976#L1189-1 assume !(1 == ~T8_E~0); 238052#L1194-1 assume !(1 == ~T9_E~0); 238188#L1199-1 assume !(1 == ~T10_E~0); 238133#L1204-1 assume !(1 == ~E_M~0); 238134#L1209-1 assume !(1 == ~E_1~0); 292346#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 292345#L1219-1 assume !(1 == ~E_3~0); 292344#L1224-1 assume !(1 == ~E_4~0); 292343#L1229-1 assume !(1 == ~E_5~0); 292342#L1234-1 assume !(1 == ~E_6~0); 292341#L1239-1 assume !(1 == ~E_7~0); 237918#L1244-1 assume !(1 == ~E_8~0); 237919#L1249-1 assume !(1 == ~E_9~0); 294348#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 294346#L1259-1 assume { :end_inline_reset_delta_events } true; 294338#L1565-2 [2021-12-21 22:38:43,308 INFO L793 eck$LassoCheckResult]: Loop: 294338#L1565-2 assume !false; 294331#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 294324#L1011 assume !false; 238427#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 238203#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 237957#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 238892#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 237984#L866 assume !(0 != eval_~tmp~0#1); 237986#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 239109#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 296757#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 296756#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 239108#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 238861#L1046-3 assume !(0 == ~T3_E~0); 238862#L1051-3 assume !(0 == ~T4_E~0); 238784#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 238004#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 238005#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 238006#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 239017#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 237755#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 237756#L1086-3 assume !(0 == ~E_M~0); 237809#L1091-3 assume !(0 == ~E_1~0); 237810#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 238977#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 238978#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 239013#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 238964#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 238607#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 238608#L1126-3 assume !(0 == ~E_8~0); 238882#L1131-3 assume !(0 == ~E_9~0); 238883#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 239105#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 238610#L514-36 assume !(1 == ~m_pc~0); 238328#L514-38 is_master_triggered_~__retres1~0#1 := 0; 238174#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 238175#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238667#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 238063#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 238064#L533-36 assume 1 == ~t1_pc~0; 238339#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 238439#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 238780#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238719#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 238494#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238495#L552-36 assume !(1 == ~t2_pc~0); 239121#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 238548#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237875#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 237876#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 238030#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238031#L571-36 assume !(1 == ~t3_pc~0); 238868#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 238119#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238120#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 238238#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 238860#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238090#L590-36 assume !(1 == ~t4_pc~0); 238091#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 238735#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238272#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 238273#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 239110#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295364#L609-36 assume 1 == ~t5_pc~0; 295362#L610-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 295243#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295240#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 295238#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 295236#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 295234#L628-36 assume 1 == ~t6_pc~0; 295232#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 295229#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 295226#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 295224#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 295222#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295220#L647-36 assume 1 == ~t7_pc~0; 295217#L648-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 295215#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295212#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 295210#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 295209#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 238803#L666-36 assume 1 == ~t8_pc~0; 237987#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 237988#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 294839#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 294838#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 294837#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 294836#L685-36 assume !(1 == ~t9_pc~0); 294834#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 294833#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 294832#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 294831#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 294830#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 294829#L704-36 assume 1 == ~t10_pc~0; 294826#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 294824#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 294822#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 294820#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 294818#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294816#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 239123#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 294812#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 294810#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 239114#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 294807#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 294805#L1179-3 assume !(1 == ~T6_E~0); 294803#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 294802#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 294800#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 294798#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 294796#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 293575#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 294793#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 294792#L1219-3 assume !(1 == ~E_3~0); 294790#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 294788#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 294786#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 294784#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 294782#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 269359#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 294778#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 294776#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 294678#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 294674#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 294654#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 294619#L1584 assume !(0 == start_simulation_~tmp~3#1); 239104#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 294397#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 294386#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 294384#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 294382#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 294380#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 294357#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 294347#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 294338#L1565-2 [2021-12-21 22:38:43,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:43,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1601336824, now seen corresponding path program 1 times [2021-12-21 22:38:43,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:43,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069582619] [2021-12-21 22:38:43,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:43,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:43,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:43,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:43,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:43,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069582619] [2021-12-21 22:38:43,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069582619] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:43,350 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:43,350 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-21 22:38:43,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829321844] [2021-12-21 22:38:43,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:43,351 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:43,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:43,352 INFO L85 PathProgramCache]: Analyzing trace with hash 239296348, now seen corresponding path program 1 times [2021-12-21 22:38:43,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:43,352 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204704449] [2021-12-21 22:38:43,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:43,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:43,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:43,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:43,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:43,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204704449] [2021-12-21 22:38:43,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204704449] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:43,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:43,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:43,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8622436] [2021-12-21 22:38:43,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:43,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:43,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:43,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-21 22:38:43,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-21 22:38:43,379 INFO L87 Difference]: Start difference. First operand 59180 states and 85754 transitions. cyclomatic complexity: 26590 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:44,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:44,187 INFO L93 Difference]: Finished difference Result 155455 states and 225783 transitions. [2021-12-21 22:38:44,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-21 22:38:44,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155455 states and 225783 transitions. [2021-12-21 22:38:45,180 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 154872 [2021-12-21 22:38:45,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155455 states to 155455 states and 225783 transitions. [2021-12-21 22:38:45,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155455 [2021-12-21 22:38:45,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155455 [2021-12-21 22:38:45,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155455 states and 225783 transitions. [2021-12-21 22:38:45,782 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:45,782 INFO L681 BuchiCegarLoop]: Abstraction has 155455 states and 225783 transitions. [2021-12-21 22:38:45,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155455 states and 225783 transitions. [2021-12-21 22:38:46,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155455 to 61031. [2021-12-21 22:38:46,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61031 states, 61031 states have (on average 1.435418066228638) internal successors, (87605), 61030 states have internal predecessors, (87605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:47,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61031 states to 61031 states and 87605 transitions. [2021-12-21 22:38:47,060 INFO L704 BuchiCegarLoop]: Abstraction has 61031 states and 87605 transitions. [2021-12-21 22:38:47,060 INFO L587 BuchiCegarLoop]: Abstraction has 61031 states and 87605 transitions. [2021-12-21 22:38:47,060 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-21 22:38:47,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61031 states and 87605 transitions. [2021-12-21 22:38:47,239 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 60788 [2021-12-21 22:38:47,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:47,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:47,241 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:47,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:47,242 INFO L791 eck$LassoCheckResult]: Stem: 453400#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 453401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 453705#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 452309#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 452310#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 453743#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 453664#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 453665#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 453731#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 452624#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 452625#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 452738#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 452996#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 452922#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 452623#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 452282#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 452283#L1036 assume !(0 == ~M_E~0); 452380#L1036-2 assume !(0 == ~T1_E~0); 453319#L1041-1 assume !(0 == ~T2_E~0); 453320#L1046-1 assume !(0 == ~T3_E~0); 452664#L1051-1 assume !(0 == ~T4_E~0); 452665#L1056-1 assume !(0 == ~T5_E~0); 453496#L1061-1 assume !(0 == ~T6_E~0); 452556#L1066-1 assume !(0 == ~T7_E~0); 452557#L1071-1 assume !(0 == ~T8_E~0); 453477#L1076-1 assume !(0 == ~T9_E~0); 452449#L1081-1 assume !(0 == ~T10_E~0); 452450#L1086-1 assume !(0 == ~E_M~0); 452875#L1091-1 assume !(0 == ~E_1~0); 453747#L1096-1 assume !(0 == ~E_2~0); 453748#L1101-1 assume !(0 == ~E_3~0); 452937#L1106-1 assume !(0 == ~E_4~0); 452938#L1111-1 assume !(0 == ~E_5~0); 453113#L1116-1 assume !(0 == ~E_6~0); 453114#L1121-1 assume !(0 == ~E_7~0); 452929#L1126-1 assume !(0 == ~E_8~0); 452930#L1131-1 assume !(0 == ~E_9~0); 453208#L1136-1 assume !(0 == ~E_10~0); 453332#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 453535#L514 assume !(1 == ~m_pc~0); 453536#L514-2 is_master_triggered_~__retres1~0#1 := 0; 452950#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 452864#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 452865#L1285 assume !(0 != activate_threads_~tmp~1#1); 453794#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452576#L533 assume !(1 == ~t1_pc~0); 452577#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 453132#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 452986#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 452987#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 453364#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 453365#L552 assume !(1 == ~t2_pc~0); 453068#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 453069#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453463#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 453464#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 452963#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452964#L571 assume !(1 == ~t3_pc~0); 453183#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 453260#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 452488#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 452489#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 453120#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 452362#L590 assume !(1 == ~t4_pc~0); 452363#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 453182#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 453907#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 453802#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 453402#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 453115#L609 assume 1 == ~t5_pc~0; 453116#L610 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 453792#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 452399#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 452400#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 453109#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 453110#L628 assume !(1 == ~t6_pc~0); 453033#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 453032#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 453768#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 453769#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 453452#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 453453#L647 assume 1 == ~t7_pc~0; 452939#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 452940#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 453249#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 452942#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 452943#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 453866#L666 assume !(1 == ~t8_pc~0); 452717#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 452718#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 452962#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453139#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 452870#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 452871#L685 assume 1 == ~t9_pc~0; 453811#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 453646#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 453636#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 452897#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 452898#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 453289#L704 assume !(1 == ~t10_pc~0); 452890#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 452889#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 453493#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 452418#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 452419#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452676#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 453433#L1154-2 assume !(1 == ~T1_E~0); 452645#L1159-1 assume !(1 == ~T2_E~0); 452646#L1164-1 assume !(1 == ~T3_E~0); 453137#L1169-1 assume !(1 == ~T4_E~0); 452991#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 452783#L1179-1 assume !(1 == ~T6_E~0); 452631#L1184-1 assume !(1 == ~T7_E~0); 452632#L1189-1 assume !(1 == ~T8_E~0); 452715#L1194-1 assume !(1 == ~T9_E~0); 463174#L1199-1 assume !(1 == ~T10_E~0); 463172#L1204-1 assume !(1 == ~E_M~0); 463169#L1209-1 assume !(1 == ~E_1~0); 463167#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 462771#L1219-1 assume !(1 == ~E_3~0); 462769#L1224-1 assume !(1 == ~E_4~0); 462766#L1229-1 assume !(1 == ~E_5~0); 462764#L1234-1 assume !(1 == ~E_6~0); 460188#L1239-1 assume !(1 == ~E_7~0); 460186#L1244-1 assume !(1 == ~E_8~0); 460182#L1249-1 assume !(1 == ~E_9~0); 460180#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 457468#L1259-1 assume { :end_inline_reset_delta_events } true; 457466#L1565-2 [2021-12-21 22:38:47,242 INFO L793 eck$LassoCheckResult]: Loop: 457466#L1565-2 assume !false; 457464#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 457459#L1011 assume !false; 457420#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 457015#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 457004#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 457003#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 457001#L866 assume !(0 != eval_~tmp~0#1); 457002#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 472054#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 472051#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 471736#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471731#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 471726#L1046-3 assume !(0 == ~T3_E~0); 471725#L1051-3 assume !(0 == ~T4_E~0); 471724#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 471723#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 471719#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 471717#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 471715#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 471710#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 471708#L1086-3 assume !(0 == ~E_M~0); 471705#L1091-3 assume !(0 == ~E_1~0); 471703#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 471700#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 471631#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 471622#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 471616#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 471611#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 471603#L1126-3 assume !(0 == ~E_8~0); 471599#L1131-3 assume !(0 == ~E_9~0); 471596#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 471491#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 471489#L514-36 assume !(1 == ~m_pc~0); 471487#L514-38 is_master_triggered_~__retres1~0#1 := 0; 471486#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471484#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 471482#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 471480#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 471478#L533-36 assume !(1 == ~t1_pc~0); 471476#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 471474#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 471472#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 471470#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 471468#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 470699#L552-36 assume !(1 == ~t2_pc~0); 470698#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 470697#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 470696#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 470695#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 470694#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464892#L571-36 assume !(1 == ~t3_pc~0); 464891#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 464890#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 464889#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 464888#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 464887#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 464886#L590-36 assume !(1 == ~t4_pc~0); 464885#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 464883#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 464881#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 464879#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 464876#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 464873#L609-36 assume !(1 == ~t5_pc~0); 464871#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 464868#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 464866#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 464864#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 464862#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 464860#L628-36 assume 1 == ~t6_pc~0; 464858#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 464854#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 464852#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 464850#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 464848#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 464847#L647-36 assume !(1 == ~t7_pc~0); 464846#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 464844#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 464843#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 464842#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 464841#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 464840#L666-36 assume !(1 == ~t8_pc~0); 464839#L666-38 is_transmit8_triggered_~__retres1~8#1 := 0; 464837#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 464836#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 464835#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 464823#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 464821#L685-36 assume 1 == ~t9_pc~0; 464819#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 464816#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 464814#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 464813#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 464812#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 464811#L704-36 assume !(1 == ~t10_pc~0); 464810#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 464808#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 464796#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 464794#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 464792#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 464790#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 464786#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 464784#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 464782#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 464778#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 464772#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 464770#L1179-3 assume !(1 == ~T6_E~0); 464768#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 464756#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 464754#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 464752#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 464749#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 464745#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 464743#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 464741#L1219-3 assume !(1 == ~E_3~0); 464739#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 464737#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 464735#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 464733#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 464731#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 464727#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 464725#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 464723#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 463817#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 463813#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 463811#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 463809#L1584 assume !(0 == start_simulation_~tmp~3#1); 463807#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 460457#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 457646#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 457483#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 457479#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 457477#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 457475#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 457469#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 457466#L1565-2 [2021-12-21 22:38:47,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:47,243 INFO L85 PathProgramCache]: Analyzing trace with hash 360237834, now seen corresponding path program 1 times [2021-12-21 22:38:47,243 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:47,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919665271] [2021-12-21 22:38:47,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:47,244 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:47,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:47,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:47,268 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:47,268 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919665271] [2021-12-21 22:38:47,268 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919665271] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:47,268 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:47,268 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:38:47,268 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196172760] [2021-12-21 22:38:47,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:47,269 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:47,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:47,269 INFO L85 PathProgramCache]: Analyzing trace with hash 643981538, now seen corresponding path program 1 times [2021-12-21 22:38:47,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:47,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835854560] [2021-12-21 22:38:47,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:47,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:47,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:47,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:47,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:47,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835854560] [2021-12-21 22:38:47,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [835854560] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:47,292 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:47,292 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:47,292 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481594600] [2021-12-21 22:38:47,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:47,292 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:47,293 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:47,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:38:47,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:38:47,293 INFO L87 Difference]: Start difference. First operand 61031 states and 87605 transitions. cyclomatic complexity: 26590 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:47,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:47,993 INFO L93 Difference]: Finished difference Result 116082 states and 166006 transitions. [2021-12-21 22:38:48,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-21 22:38:48,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116082 states and 166006 transitions. [2021-12-21 22:38:48,477 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115680 [2021-12-21 22:38:48,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116082 states to 116082 states and 166006 transitions. [2021-12-21 22:38:48,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116082 [2021-12-21 22:38:48,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116082 [2021-12-21 22:38:48,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116082 states and 166006 transitions. [2021-12-21 22:38:48,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:48,856 INFO L681 BuchiCegarLoop]: Abstraction has 116082 states and 166006 transitions. [2021-12-21 22:38:48,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116082 states and 166006 transitions. [2021-12-21 22:38:50,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116082 to 115954. [2021-12-21 22:38:50,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115954 states, 115954 states have (on average 1.4305500457077807) internal successors, (165878), 115953 states have internal predecessors, (165878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:50,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115954 states to 115954 states and 165878 transitions. [2021-12-21 22:38:50,624 INFO L704 BuchiCegarLoop]: Abstraction has 115954 states and 165878 transitions. [2021-12-21 22:38:50,624 INFO L587 BuchiCegarLoop]: Abstraction has 115954 states and 165878 transitions. [2021-12-21 22:38:50,624 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-21 22:38:50,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115954 states and 165878 transitions. [2021-12-21 22:38:50,915 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 115552 [2021-12-21 22:38:50,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:50,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:50,917 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:50,918 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:50,918 INFO L791 eck$LassoCheckResult]: Stem: 630486#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 630487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 630753#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 629431#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 629432#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 630788#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 630726#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 630727#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 630774#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 629738#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 629739#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 629849#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 630102#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 630031#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 629740#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 629402#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 629403#L1036 assume !(0 == ~M_E~0); 629499#L1036-2 assume !(0 == ~T1_E~0); 630417#L1041-1 assume !(0 == ~T2_E~0); 630418#L1046-1 assume !(0 == ~T3_E~0); 629781#L1051-1 assume !(0 == ~T4_E~0); 629782#L1056-1 assume !(0 == ~T5_E~0); 630578#L1061-1 assume !(0 == ~T6_E~0); 629671#L1066-1 assume !(0 == ~T7_E~0); 629672#L1071-1 assume !(0 == ~T8_E~0); 630560#L1076-1 assume !(0 == ~T9_E~0); 629567#L1081-1 assume !(0 == ~T10_E~0); 629568#L1086-1 assume !(0 == ~E_M~0); 629982#L1091-1 assume !(0 == ~E_1~0); 630794#L1096-1 assume !(0 == ~E_2~0); 630795#L1101-1 assume !(0 == ~E_3~0); 630047#L1106-1 assume !(0 == ~E_4~0); 630048#L1111-1 assume !(0 == ~E_5~0); 630214#L1116-1 assume !(0 == ~E_6~0); 630215#L1121-1 assume !(0 == ~E_7~0); 630039#L1126-1 assume !(0 == ~E_8~0); 630040#L1131-1 assume !(0 == ~E_9~0); 630305#L1136-1 assume !(0 == ~E_10~0); 630427#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 630607#L514 assume !(1 == ~m_pc~0); 630608#L514-2 is_master_triggered_~__retres1~0#1 := 0; 630061#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 629974#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 629975#L1285 assume !(0 != activate_threads_~tmp~1#1); 630841#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 629693#L533 assume !(1 == ~t1_pc~0); 629694#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 630230#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 630093#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 630094#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 630451#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 630452#L552 assume !(1 == ~t2_pc~0); 630171#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 630172#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 630544#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 630545#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 630075#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 630076#L571 assume !(1 == ~t3_pc~0); 630280#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 630354#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 629606#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 629607#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 630219#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 629483#L590 assume !(1 == ~t4_pc~0); 629484#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 630279#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 630934#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 630843#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 630488#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630216#L609 assume !(1 == ~t5_pc~0); 630217#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 630835#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 629518#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 629519#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 630211#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 630212#L628 assume !(1 == ~t6_pc~0); 630137#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 630136#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 630816#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 630817#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 630533#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 630534#L647 assume 1 == ~t7_pc~0; 630049#L648 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 630050#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 630346#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 630056#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 630057#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 630891#L666 assume !(1 == ~t8_pc~0); 629829#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 629830#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 630071#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 630239#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 629978#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 629979#L685 assume 1 == ~t9_pc~0; 630847#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 630708#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 630698#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 630005#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 630006#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 630383#L704 assume !(1 == ~t10_pc~0); 629998#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 629997#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 630576#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 629539#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 629540#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 629790#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 630518#L1154-2 assume !(1 == ~T1_E~0); 629759#L1159-1 assume !(1 == ~T2_E~0); 629760#L1164-1 assume !(1 == ~T3_E~0); 630235#L1169-1 assume !(1 == ~T4_E~0); 630097#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 629897#L1179-1 assume !(1 == ~T6_E~0); 629745#L1184-1 assume !(1 == ~T7_E~0); 629746#L1189-1 assume !(1 == ~T8_E~0); 629827#L1194-1 assume !(1 == ~T9_E~0); 629967#L1199-1 assume !(1 == ~T10_E~0); 629913#L1204-1 assume !(1 == ~E_M~0); 629914#L1209-1 assume !(1 == ~E_1~0); 698995#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 698993#L1219-1 assume !(1 == ~E_3~0); 698991#L1224-1 assume !(1 == ~E_4~0); 698989#L1229-1 assume !(1 == ~E_5~0); 698987#L1234-1 assume !(1 == ~E_6~0); 698984#L1239-1 assume !(1 == ~E_7~0); 698982#L1244-1 assume !(1 == ~E_8~0); 677178#L1249-1 assume !(1 == ~E_9~0); 698979#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 698022#L1259-1 assume { :end_inline_reset_delta_events } true; 698020#L1565-2 [2021-12-21 22:38:50,918 INFO L793 eck$LassoCheckResult]: Loop: 698020#L1565-2 assume !false; 698017#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 698011#L1011 assume !false; 698009#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 698007#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 697995#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 697994#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 697989#L866 assume !(0 != eval_~tmp~0#1); 697990#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 739367#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 739365#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 739362#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 739360#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 739358#L1046-3 assume !(0 == ~T3_E~0); 739356#L1051-3 assume !(0 == ~T4_E~0); 739354#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 739352#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 739349#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 739345#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 739215#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 739212#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 739210#L1086-3 assume !(0 == ~E_M~0); 739208#L1091-3 assume !(0 == ~E_1~0); 739206#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 739204#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 739202#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 739199#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 739197#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 739195#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 739193#L1126-3 assume !(0 == ~E_8~0); 739191#L1131-3 assume !(0 == ~E_9~0); 739189#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 739186#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 739184#L514-36 assume !(1 == ~m_pc~0); 739182#L514-38 is_master_triggered_~__retres1~0#1 := 0; 739180#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 739178#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 739176#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 739175#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 739172#L533-36 assume !(1 == ~t1_pc~0); 739170#L533-38 is_transmit1_triggered_~__retres1~1#1 := 0; 739167#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 739165#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 739163#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 739161#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 739107#L552-36 assume !(1 == ~t2_pc~0); 684767#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 739090#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 739082#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 739074#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 739066#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 739058#L571-36 assume !(1 == ~t3_pc~0); 693975#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 738966#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 724287#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 724286#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 724285#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 718184#L590-36 assume 1 == ~t4_pc~0; 718185#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 718186#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 718188#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 718174#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 718172#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 718170#L609-36 assume !(1 == ~t5_pc~0); 718168#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 718166#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 718164#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 718161#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 718159#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 718157#L628-36 assume !(1 == ~t6_pc~0); 718154#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 698204#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 698192#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 698190#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 698188#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 698186#L647-36 assume !(1 == ~t7_pc~0); 698184#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 698181#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 698179#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 698177#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 698171#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 698169#L666-36 assume 1 == ~t8_pc~0; 698166#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 698165#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 698164#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 698163#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 698162#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 698161#L685-36 assume !(1 == ~t9_pc~0); 698158#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 698156#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 698154#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 698152#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 698150#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 698148#L704-36 assume !(1 == ~t10_pc~0); 698146#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 698142#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 698140#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 698138#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 698136#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 698134#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 675778#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 698130#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 698128#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 698125#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 698123#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 698121#L1179-3 assume !(1 == ~T6_E~0); 698119#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 698118#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 698116#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 698114#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 698112#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 698108#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 698107#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 698103#L1219-3 assume !(1 == ~E_3~0); 698101#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 698099#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 698097#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 698094#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 698092#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 676999#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 698089#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 698087#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 698064#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 698060#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 698058#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 698056#L1584 assume !(0 == start_simulation_~tmp~3#1); 698053#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 698045#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 698034#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 698031#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 698029#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 698027#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 698025#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 698023#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 698020#L1565-2 [2021-12-21 22:38:50,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:50,919 INFO L85 PathProgramCache]: Analyzing trace with hash -671092981, now seen corresponding path program 1 times [2021-12-21 22:38:50,919 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:50,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598261961] [2021-12-21 22:38:50,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:50,919 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:50,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:50,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:50,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:50,959 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598261961] [2021-12-21 22:38:50,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598261961] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:50,959 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:50,959 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:50,959 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714617266] [2021-12-21 22:38:50,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:50,960 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:50,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:50,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1139650272, now seen corresponding path program 1 times [2021-12-21 22:38:50,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:50,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945839866] [2021-12-21 22:38:50,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:50,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:50,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:50,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:50,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:50,980 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945839866] [2021-12-21 22:38:50,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945839866] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:50,981 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:50,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:50,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407809152] [2021-12-21 22:38:50,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:50,981 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:50,981 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:50,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:50,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:50,982 INFO L87 Difference]: Start difference. First operand 115954 states and 165878 transitions. cyclomatic complexity: 49956 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:52,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:38:52,438 INFO L93 Difference]: Finished difference Result 283541 states and 402559 transitions. [2021-12-21 22:38:52,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:38:52,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283541 states and 402559 transitions. [2021-12-21 22:38:54,047 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 277476 [2021-12-21 22:38:54,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283541 states to 283541 states and 402559 transitions. [2021-12-21 22:38:54,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283541 [2021-12-21 22:38:54,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283541 [2021-12-21 22:38:54,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283541 states and 402559 transitions. [2021-12-21 22:38:55,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:38:55,564 INFO L681 BuchiCegarLoop]: Abstraction has 283541 states and 402559 transitions. [2021-12-21 22:38:55,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283541 states and 402559 transitions. [2021-12-21 22:38:57,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283541 to 225089. [2021-12-21 22:38:57,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225089 states, 225089 states have (on average 1.4243743585870479) internal successors, (320611), 225088 states have internal predecessors, (320611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:38:58,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225089 states to 225089 states and 320611 transitions. [2021-12-21 22:38:58,755 INFO L704 BuchiCegarLoop]: Abstraction has 225089 states and 320611 transitions. [2021-12-21 22:38:58,755 INFO L587 BuchiCegarLoop]: Abstraction has 225089 states and 320611 transitions. [2021-12-21 22:38:58,755 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-21 22:38:58,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225089 states and 320611 transitions. [2021-12-21 22:38:59,383 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 224496 [2021-12-21 22:38:59,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:38:59,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:38:59,385 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:59,385 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:38:59,386 INFO L791 eck$LassoCheckResult]: Stem: 1029992#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1029993#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1030276#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1028934#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1028935#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1030314#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1030251#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1030252#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1030295#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1029238#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1029239#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1029347#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1029599#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1029527#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1029240#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1028907#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1028908#L1036 assume !(0 == ~M_E~0); 1029004#L1036-2 assume !(0 == ~T1_E~0); 1029917#L1041-1 assume !(0 == ~T2_E~0); 1029918#L1046-1 assume !(0 == ~T3_E~0); 1029278#L1051-1 assume !(0 == ~T4_E~0); 1029279#L1056-1 assume !(0 == ~T5_E~0); 1030090#L1061-1 assume !(0 == ~T6_E~0); 1029174#L1066-1 assume !(0 == ~T7_E~0); 1029175#L1071-1 assume !(0 == ~T8_E~0); 1030071#L1076-1 assume !(0 == ~T9_E~0); 1029071#L1081-1 assume !(0 == ~T10_E~0); 1029072#L1086-1 assume !(0 == ~E_M~0); 1029481#L1091-1 assume !(0 == ~E_1~0); 1030320#L1096-1 assume !(0 == ~E_2~0); 1030321#L1101-1 assume !(0 == ~E_3~0); 1029543#L1106-1 assume !(0 == ~E_4~0); 1029544#L1111-1 assume !(0 == ~E_5~0); 1029712#L1116-1 assume !(0 == ~E_6~0); 1029713#L1121-1 assume !(0 == ~E_7~0); 1029535#L1126-1 assume !(0 == ~E_8~0); 1029536#L1131-1 assume !(0 == ~E_9~0); 1029811#L1136-1 assume !(0 == ~E_10~0); 1029927#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1030126#L514 assume !(1 == ~m_pc~0); 1030127#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1029553#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1029472#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1029473#L1285 assume !(0 != activate_threads_~tmp~1#1); 1030378#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1029193#L533 assume !(1 == ~t1_pc~0); 1029194#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1029731#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029589#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1029590#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1029958#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029959#L552 assume !(1 == ~t2_pc~0); 1029668#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1029669#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1030055#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1030056#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1029565#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1029566#L571 assume !(1 == ~t3_pc~0); 1029784#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1029859#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1029109#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1029110#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1029717#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1028986#L590 assume !(1 == ~t4_pc~0); 1028987#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1029783#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1030520#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030383#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1029994#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1029714#L609 assume !(1 == ~t5_pc~0); 1029715#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1030376#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1029023#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1029024#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1029708#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1029709#L628 assume !(1 == ~t6_pc~0); 1029633#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1029632#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1030348#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1030349#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1030046#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1030047#L647 assume !(1 == ~t7_pc~0); 1030182#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1030212#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1029847#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1029545#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1029546#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1030445#L666 assume !(1 == ~t8_pc~0); 1029326#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1029327#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1029564#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1029739#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1029478#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1029479#L685 assume 1 == ~t9_pc~0; 1030389#L686 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1030233#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1030218#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1029503#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1029504#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1029888#L704 assume !(1 == ~t10_pc~0); 1029496#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1029495#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1030088#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1029042#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1029043#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1029289#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1030027#L1154-2 assume !(1 == ~T1_E~0); 1090385#L1159-1 assume !(1 == ~T2_E~0); 1030486#L1164-1 assume !(1 == ~T3_E~0); 1030487#L1169-1 assume !(1 == ~T4_E~0); 1029593#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1029594#L1179-1 assume !(1 == ~T6_E~0); 1029245#L1184-1 assume !(1 == ~T7_E~0); 1029246#L1189-1 assume !(1 == ~T8_E~0); 1029466#L1194-1 assume !(1 == ~T9_E~0); 1029467#L1199-1 assume !(1 == ~T10_E~0); 1029409#L1204-1 assume !(1 == ~E_M~0); 1029410#L1209-1 assume !(1 == ~E_1~0); 1095490#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1095489#L1219-1 assume !(1 == ~E_3~0); 1030423#L1224-1 assume !(1 == ~E_4~0); 1030424#L1229-1 assume !(1 == ~E_5~0); 1029132#L1234-1 assume !(1 == ~E_6~0); 1029133#L1239-1 assume !(1 == ~E_7~0); 1029189#L1244-1 assume !(1 == ~E_8~0); 1029190#L1249-1 assume !(1 == ~E_9~0); 1030078#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1029035#L1259-1 assume { :end_inline_reset_delta_events } true; 1029036#L1565-2 [2021-12-21 22:38:59,386 INFO L793 eck$LassoCheckResult]: Loop: 1029036#L1565-2 assume !false; 1133696#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1133690#L1011 assume !false; 1131135#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1130409#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1130397#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1130396#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1130391#L866 assume !(0 != eval_~tmp~0#1); 1130392#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1137362#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1137289#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1137271#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1137071#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1137066#L1046-3 assume !(0 == ~T3_E~0); 1137060#L1051-3 assume !(0 == ~T4_E~0); 1137013#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1136964#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1136962#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1136960#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1136958#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1136956#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1136954#L1086-3 assume !(0 == ~E_M~0); 1136951#L1091-3 assume !(0 == ~E_1~0); 1136948#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1136945#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1136916#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1136698#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1136692#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1136686#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1136587#L1126-3 assume !(0 == ~E_8~0); 1136427#L1131-3 assume !(0 == ~E_9~0); 1136424#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1136417#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1136409#L514-36 assume !(1 == ~m_pc~0); 1136401#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1136393#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1136385#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1136377#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1136365#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1136352#L533-36 assume 1 == ~t1_pc~0; 1136340#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1136341#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1136321#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1136312#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1135789#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1135687#L552-36 assume !(1 == ~t2_pc~0); 1135681#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1135676#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135671#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1135666#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1135661#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1135657#L571-36 assume !(1 == ~t3_pc~0); 1087478#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1135648#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135644#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1135640#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1135636#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135633#L590-36 assume !(1 == ~t4_pc~0); 1135629#L590-38 is_transmit4_triggered_~__retres1~4#1 := 0; 1135624#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1135619#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1135614#L1317-36 assume !(0 != activate_threads_~tmp___3~0#1); 1135610#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135606#L609-36 assume !(1 == ~t5_pc~0); 1135601#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1135597#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1135593#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135589#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1135585#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1135581#L628-36 assume !(1 == ~t6_pc~0); 1135573#L628-38 is_transmit6_triggered_~__retres1~6#1 := 0; 1135569#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135565#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1135561#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1135557#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1135552#L647-36 assume !(1 == ~t7_pc~0); 1077389#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1135546#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135542#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1135538#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 1135534#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1135531#L666-36 assume 1 == ~t8_pc~0; 1135527#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1135523#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1135519#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1135515#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1135511#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1135507#L685-36 assume 1 == ~t9_pc~0; 1135501#L686-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1135495#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1135489#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1135484#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1135480#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1135476#L704-36 assume !(1 == ~t10_pc~0); 1135471#L704-38 is_transmit10_triggered_~__retres1~10#1 := 0; 1135467#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1134156#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1134153#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1134151#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134149#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1091766#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1134145#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1134143#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1111765#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1134140#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1134138#L1179-3 assume !(1 == ~T6_E~0); 1134135#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1134133#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1134131#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1134129#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1134127#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1121765#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1134125#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1134123#L1219-3 assume !(1 == ~E_3~0); 1134121#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1134119#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1134117#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1134115#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1134112#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1094040#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1134109#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1134107#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1133737#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1133733#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1133731#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1133730#L1584 assume !(0 == start_simulation_~tmp~3#1); 1133728#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1133721#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1133710#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1133708#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1133706#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1133703#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1133701#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1133699#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1029036#L1565-2 [2021-12-21 22:38:59,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:59,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1730432140, now seen corresponding path program 1 times [2021-12-21 22:38:59,387 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:59,387 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308017504] [2021-12-21 22:38:59,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:59,387 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:59,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:59,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:59,413 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:59,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308017504] [2021-12-21 22:38:59,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308017504] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:59,414 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:59,414 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:59,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318578352] [2021-12-21 22:38:59,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:59,414 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:38:59,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:38:59,415 INFO L85 PathProgramCache]: Analyzing trace with hash 1422479329, now seen corresponding path program 1 times [2021-12-21 22:38:59,415 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:38:59,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673432932] [2021-12-21 22:38:59,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:38:59,415 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:38:59,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:38:59,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:38:59,437 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:38:59,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673432932] [2021-12-21 22:38:59,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673432932] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:38:59,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:38:59,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:38:59,438 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [707531866] [2021-12-21 22:38:59,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:38:59,438 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:38:59,438 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:38:59,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-21 22:38:59,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-21 22:38:59,439 INFO L87 Difference]: Start difference. First operand 225089 states and 320611 transitions. cyclomatic complexity: 95554 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:39:01,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-21 22:39:01,867 INFO L93 Difference]: Finished difference Result 535616 states and 758208 transitions. [2021-12-21 22:39:01,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-21 22:39:01,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 535616 states and 758208 transitions. [2021-12-21 22:39:05,079 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 523760 [2021-12-21 22:39:06,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 535616 states to 535616 states and 758208 transitions. [2021-12-21 22:39:06,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 535616 [2021-12-21 22:39:06,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 535616 [2021-12-21 22:39:06,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 535616 states and 758208 transitions. [2021-12-21 22:39:07,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-21 22:39:07,229 INFO L681 BuchiCegarLoop]: Abstraction has 535616 states and 758208 transitions. [2021-12-21 22:39:07,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 535616 states and 758208 transitions. [2021-12-21 22:39:11,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 535616 to 426832. [2021-12-21 22:39:12,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 426832 states, 426832 states have (on average 1.4204370806312554) internal successors, (606288), 426831 states have internal predecessors, (606288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-21 22:39:13,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 426832 states to 426832 states and 606288 transitions. [2021-12-21 22:39:13,170 INFO L704 BuchiCegarLoop]: Abstraction has 426832 states and 606288 transitions. [2021-12-21 22:39:13,171 INFO L587 BuchiCegarLoop]: Abstraction has 426832 states and 606288 transitions. [2021-12-21 22:39:13,171 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-21 22:39:13,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 426832 states and 606288 transitions. [2021-12-21 22:39:15,232 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 425856 [2021-12-21 22:39:15,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-21 22:39:15,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-21 22:39:15,236 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:39:15,236 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-21 22:39:15,236 INFO L791 eck$LassoCheckResult]: Stem: 1790743#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1790744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1791073#L1528 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1789649#L724 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1789650#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1791114#L731-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1791038#L736-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1791039#L741-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1791094#L746-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1789954#L751-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1789955#L756-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1790073#L761-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1790333#L766-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1790260#L771-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1789956#L776-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1789622#L781-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1789623#L1036 assume !(0 == ~M_E~0); 1789719#L1036-2 assume !(0 == ~T1_E~0); 1790666#L1041-1 assume !(0 == ~T2_E~0); 1790667#L1046-1 assume !(0 == ~T3_E~0); 1789997#L1051-1 assume !(0 == ~T4_E~0); 1789998#L1056-1 assume !(0 == ~T5_E~0); 1790842#L1061-1 assume !(0 == ~T6_E~0); 1789892#L1066-1 assume !(0 == ~T7_E~0); 1789893#L1071-1 assume !(0 == ~T8_E~0); 1790825#L1076-1 assume !(0 == ~T9_E~0); 1789786#L1081-1 assume !(0 == ~T10_E~0); 1789787#L1086-1 assume !(0 == ~E_M~0); 1790213#L1091-1 assume !(0 == ~E_1~0); 1791120#L1096-1 assume !(0 == ~E_2~0); 1791121#L1101-1 assume !(0 == ~E_3~0); 1790275#L1106-1 assume !(0 == ~E_4~0); 1790276#L1111-1 assume !(0 == ~E_5~0); 1790452#L1116-1 assume !(0 == ~E_6~0); 1790453#L1121-1 assume !(0 == ~E_7~0); 1790267#L1126-1 assume !(0 == ~E_8~0); 1790268#L1131-1 assume !(0 == ~E_9~0); 1790552#L1136-1 assume !(0 == ~E_10~0); 1790677#L1141-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1790882#L514 assume !(1 == ~m_pc~0); 1790883#L514-2 is_master_triggered_~__retres1~0#1 := 0; 1790285#L525 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1790204#L526 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1790205#L1285 assume !(0 != activate_threads_~tmp~1#1); 1791176#L1285-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1789911#L533 assume !(1 == ~t1_pc~0); 1789912#L533-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1790468#L544 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1790323#L545 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1790324#L1293 assume !(0 != activate_threads_~tmp___0~0#1); 1790709#L1293-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1790710#L552 assume !(1 == ~t2_pc~0); 1790403#L552-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1790404#L563 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1790809#L564 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1790810#L1301 assume !(0 != activate_threads_~tmp___1~0#1); 1790299#L1301-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1790300#L571 assume !(1 == ~t3_pc~0); 1790522#L571-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1790603#L582 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1789824#L583 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1789825#L1309 assume !(0 != activate_threads_~tmp___2~0#1); 1790457#L1309-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1789701#L590 assume !(1 == ~t4_pc~0); 1789702#L590-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1790521#L601 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1791365#L602 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1791182#L1317 assume !(0 != activate_threads_~tmp___3~0#1); 1790745#L1317-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1790454#L609 assume !(1 == ~t5_pc~0); 1790455#L609-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1791174#L620 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1789737#L621 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1789738#L1325 assume !(0 != activate_threads_~tmp___4~0#1); 1790448#L1325-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1790449#L628 assume !(1 == ~t6_pc~0); 1790371#L628-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1790370#L639 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1791149#L640 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1791150#L1333 assume !(0 != activate_threads_~tmp___5~0#1); 1790800#L1333-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1790801#L647 assume !(1 == ~t7_pc~0); 1790946#L647-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1790990#L658 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1790593#L659 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1790277#L1341 assume !(0 != activate_threads_~tmp___6~0#1); 1790278#L1341-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1791264#L666 assume !(1 == ~t8_pc~0); 1790052#L666-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1790053#L677 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1790298#L678 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1790478#L1349 assume !(0 != activate_threads_~tmp___7~0#1); 1790210#L1349-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1790211#L685 assume !(1 == ~t9_pc~0); 1791200#L685-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1791012#L696 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1790998#L697 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1790236#L1357 assume !(0 != activate_threads_~tmp___8~0#1); 1790237#L1357-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1790636#L704 assume !(1 == ~t10_pc~0); 1790230#L704-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1790229#L715 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1790840#L716 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1789757#L1365 assume !(0 != activate_threads_~tmp___9~0#1); 1789758#L1365-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790009#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1790781#L1154-2 assume !(1 == ~T1_E~0); 1791233#L1159-1 assume !(1 == ~T2_E~0); 1791318#L1164-1 assume !(1 == ~T3_E~0); 1791319#L1169-1 assume !(1 == ~T4_E~0); 1790327#L1174-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1790328#L1179-1 assume !(1 == ~T6_E~0); 1789963#L1184-1 assume !(1 == ~T7_E~0); 1789964#L1189-1 assume !(1 == ~T8_E~0); 1790198#L1194-1 assume !(1 == ~T9_E~0); 1790199#L1199-1 assume !(1 == ~T10_E~0); 1790139#L1204-1 assume !(1 == ~E_M~0); 1790140#L1209-1 assume !(1 == ~E_1~0); 1791261#L1214-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1791317#L1219-1 assume !(1 == ~E_3~0); 1791237#L1224-1 assume !(1 == ~E_4~0); 1790497#L1229-1 assume !(1 == ~E_5~0); 1789848#L1234-1 assume !(1 == ~E_6~0); 1789849#L1239-1 assume !(1 == ~E_7~0); 1789907#L1244-1 assume !(1 == ~E_8~0); 1789908#L1249-1 assume !(1 == ~E_9~0); 1790831#L1254-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1789749#L1259-1 assume { :end_inline_reset_delta_events } true; 1789750#L1565-2 [2021-12-21 22:39:15,236 INFO L793 eck$LassoCheckResult]: Loop: 1789750#L1565-2 assume !false; 1970260#L1566 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1970255#L1011 assume !false; 1970254#L862 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970252#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970241#L851 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970240#L852 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1970237#L866 assume !(0 != eval_~tmp~0#1); 1970238#L1026 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1980529#L724-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1980527#L1036-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1980523#L1036-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1980519#L1041-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1980514#L1046-3 assume !(0 == ~T3_E~0); 1980509#L1051-3 assume !(0 == ~T4_E~0); 1980504#L1056-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1980499#L1061-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1980494#L1066-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1980489#L1071-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1980484#L1076-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1980477#L1081-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1980472#L1086-3 assume !(0 == ~E_M~0); 1980467#L1091-3 assume !(0 == ~E_1~0); 1980462#L1096-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1980457#L1101-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1980452#L1106-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1980445#L1111-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1980440#L1116-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1980432#L1121-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1980426#L1126-3 assume !(0 == ~E_8~0); 1980420#L1131-3 assume !(0 == ~E_9~0); 1980415#L1136-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1980406#L1141-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1980397#L514-36 assume !(1 == ~m_pc~0); 1980347#L514-38 is_master_triggered_~__retres1~0#1 := 0; 1980338#L525-12 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1980327#L526-12 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1980317#L1285-36 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1980259#L1285-38 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1980250#L533-36 assume 1 == ~t1_pc~0; 1980214#L534-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1980185#L544-12 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1980154#L545-12 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1980144#L1293-36 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1979943#L1293-38 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1970463#L552-36 assume !(1 == ~t2_pc~0); 1970462#L552-38 is_transmit2_triggered_~__retres1~2#1 := 0; 1970461#L563-12 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1970460#L564-12 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1970458#L1301-36 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1970457#L1301-38 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1970456#L571-36 assume !(1 == ~t3_pc~0); 1911455#L571-38 is_transmit3_triggered_~__retres1~3#1 := 0; 1970455#L582-12 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1970453#L583-12 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1970452#L1309-36 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1970451#L1309-38 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1970446#L590-36 assume 1 == ~t4_pc~0; 1970447#L591-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1970448#L601-12 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1970454#L602-12 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1970437#L1317-36 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1970435#L1317-38 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1970433#L609-36 assume !(1 == ~t5_pc~0); 1970431#L609-38 is_transmit5_triggered_~__retres1~5#1 := 0; 1970430#L620-12 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1970428#L621-12 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1970426#L1325-36 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1970424#L1325-38 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1970422#L628-36 assume 1 == ~t6_pc~0; 1970418#L629-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1970415#L639-12 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1970413#L640-12 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1970411#L1333-36 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1970408#L1333-38 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1970406#L647-36 assume !(1 == ~t7_pc~0); 1945145#L647-38 is_transmit7_triggered_~__retres1~7#1 := 0; 1970403#L658-12 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1970401#L659-12 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1970399#L1341-36 assume !(0 != activate_threads_~tmp___6~0#1); 1970397#L1341-38 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1970395#L666-36 assume 1 == ~t8_pc~0; 1970392#L667-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1970389#L677-12 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1970387#L678-12 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1970385#L1349-36 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1970383#L1349-38 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1970381#L685-36 assume !(1 == ~t9_pc~0); 1886838#L685-38 is_transmit9_triggered_~__retres1~9#1 := 0; 1970379#L696-12 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1970377#L697-12 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1970375#L1357-36 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1970373#L1357-38 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1970371#L704-36 assume 1 == ~t10_pc~0; 1970368#L705-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1970365#L715-12 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1970363#L716-12 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1970361#L1365-36 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1970359#L1365-38 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1970357#L1154-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1894591#L1154-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1970355#L1159-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1970353#L1164-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1970160#L1169-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1970350#L1174-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1970348#L1179-3 assume !(1 == ~T6_E~0); 1970346#L1184-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1970343#L1189-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1970341#L1194-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1970339#L1199-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1970337#L1204-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1894563#L1209-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1970334#L1214-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1970332#L1219-3 assume !(1 == ~E_3~0); 1970330#L1224-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1970328#L1229-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1970326#L1234-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1970324#L1239-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1970322#L1244-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1962504#L1249-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1970319#L1254-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1970317#L1259-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970298#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970294#L851-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970292#L852-1 start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1970291#L1584 assume !(0 == start_simulation_~tmp~3#1); 1970289#L1584-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1970287#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1970274#L851-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1970272#L852-2 stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1970270#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1970269#L1546 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1970268#L1547 start_simulation_#t~ret31#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1970264#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1789750#L1565-2 [2021-12-21 22:39:15,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:39:15,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1513086067, now seen corresponding path program 1 times [2021-12-21 22:39:15,237 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:39:15,237 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559697057] [2021-12-21 22:39:15,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:39:15,238 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:39:15,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:39:15,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:39:15,261 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:39:15,262 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559697057] [2021-12-21 22:39:15,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559697057] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:39:15,262 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:39:15,262 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-21 22:39:15,262 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908754775] [2021-12-21 22:39:15,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:39:15,264 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-21 22:39:15,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-21 22:39:15,265 INFO L85 PathProgramCache]: Analyzing trace with hash -905041891, now seen corresponding path program 1 times [2021-12-21 22:39:15,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-21 22:39:15,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097803968] [2021-12-21 22:39:15,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-21 22:39:15,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-21 22:39:15,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-21 22:39:15,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-21 22:39:15,289 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-21 22:39:15,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097803968] [2021-12-21 22:39:15,289 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097803968] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-21 22:39:15,289 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-21 22:39:15,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-21 22:39:15,290 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13394341] [2021-12-21 22:39:15,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-21 22:39:15,290 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-21 22:39:15,290 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-21 22:39:15,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-21 22:39:15,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-21 22:39:15,291 INFO L87 Difference]: Start difference. First operand 426832 states and 606288 transitions. cyclomatic complexity: 179488 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)