./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e19ca921 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-e19ca92 [2021-12-22 20:30:28,612 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-22 20:30:28,641 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-22 20:30:28,662 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-22 20:30:28,664 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-22 20:30:28,666 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-22 20:30:28,668 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-22 20:30:28,672 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-22 20:30:28,674 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-22 20:30:28,677 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-22 20:30:28,678 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-22 20:30:28,678 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-22 20:30:28,679 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-22 20:30:28,681 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-22 20:30:28,682 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-22 20:30:28,683 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-22 20:30:28,684 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-22 20:30:28,685 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-22 20:30:28,688 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-22 20:30:28,692 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-22 20:30:28,693 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-22 20:30:28,694 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-22 20:30:28,695 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-22 20:30:28,696 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-22 20:30:28,698 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-22 20:30:28,698 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-22 20:30:28,698 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-22 20:30:28,699 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-22 20:30:28,699 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-22 20:30:28,700 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-22 20:30:28,700 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-22 20:30:28,701 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-22 20:30:28,702 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-22 20:30:28,703 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-22 20:30:28,704 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-22 20:30:28,704 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-22 20:30:28,705 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-22 20:30:28,705 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-22 20:30:28,705 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-22 20:30:28,706 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-22 20:30:28,706 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-22 20:30:28,708 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-22 20:30:28,729 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-22 20:30:28,731 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-22 20:30:28,731 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-22 20:30:28,731 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-22 20:30:28,732 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-22 20:30:28,733 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-22 20:30:28,733 INFO L138 SettingsManager]: * Use SBE=true [2021-12-22 20:30:28,733 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-22 20:30:28,733 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-22 20:30:28,733 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-22 20:30:28,734 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-22 20:30:28,734 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-22 20:30:28,734 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-22 20:30:28,734 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-22 20:30:28,734 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-22 20:30:28,734 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-22 20:30:28,735 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-22 20:30:28,736 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-22 20:30:28,736 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-22 20:30:28,736 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-22 20:30:28,736 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-22 20:30:28,736 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-22 20:30:28,736 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-22 20:30:28,736 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-22 20:30:28,737 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-12-22 20:30:28,737 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-22 20:30:28,737 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2021-12-22 20:30:28,930 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-22 20:30:28,958 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-22 20:30:28,960 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-22 20:30:28,961 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-22 20:30:28,962 INFO L275 PluginConnector]: CDTParser initialized [2021-12-22 20:30:28,962 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-12-22 20:30:29,039 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cc4b7fab/b1be91f7ddd34c7eb1748313c8ac12f2/FLAG2c6ae8067 [2021-12-22 20:30:29,412 INFO L306 CDTParser]: Found 1 translation units. [2021-12-22 20:30:29,413 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c [2021-12-22 20:30:29,425 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cc4b7fab/b1be91f7ddd34c7eb1748313c8ac12f2/FLAG2c6ae8067 [2021-12-22 20:30:29,811 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/6cc4b7fab/b1be91f7ddd34c7eb1748313c8ac12f2 [2021-12-22 20:30:29,813 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-22 20:30:29,814 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-22 20:30:29,815 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-22 20:30:29,815 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-22 20:30:29,829 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-22 20:30:29,830 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.12 08:30:29" (1/1) ... [2021-12-22 20:30:29,830 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1a346712 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:29, skipping insertion in model container [2021-12-22 20:30:29,831 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.12 08:30:29" (1/1) ... [2021-12-22 20:30:29,835 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-22 20:30:29,862 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-22 20:30:30,016 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-12-22 20:30:30,109 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-22 20:30:30,118 INFO L203 MainTranslator]: Completed pre-run [2021-12-22 20:30:30,126 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2021-12-22 20:30:30,230 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-22 20:30:30,244 INFO L208 MainTranslator]: Completed translation [2021-12-22 20:30:30,244 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30 WrapperNode [2021-12-22 20:30:30,245 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-22 20:30:30,246 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-22 20:30:30,246 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-22 20:30:30,246 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-22 20:30:30,251 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,273 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,349 INFO L137 Inliner]: procedures = 52, calls = 66, calls flagged for inlining = 61, calls inlined = 254, statements flattened = 3910 [2021-12-22 20:30:30,350 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-22 20:30:30,350 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-22 20:30:30,350 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-22 20:30:30,350 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-22 20:30:30,359 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,359 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,370 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,374 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,415 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,446 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,454 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,464 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-22 20:30:30,468 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-22 20:30:30,468 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-22 20:30:30,469 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-22 20:30:30,470 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (1/1) ... [2021-12-22 20:30:30,475 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-22 20:30:30,483 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-22 20:30:30,496 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-22 20:30:30,512 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-22 20:30:30,543 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-22 20:30:30,543 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-22 20:30:30,543 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-22 20:30:30,544 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-22 20:30:30,659 INFO L234 CfgBuilder]: Building ICFG [2021-12-22 20:30:30,660 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-22 20:30:32,075 INFO L275 CfgBuilder]: Performing block encoding [2021-12-22 20:30:32,086 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-22 20:30:32,086 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2021-12-22 20:30:32,089 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.12 08:30:32 BoogieIcfgContainer [2021-12-22 20:30:32,089 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-22 20:30:32,090 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-22 20:30:32,091 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-22 20:30:32,093 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-22 20:30:32,094 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-22 20:30:32,094 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 22.12 08:30:29" (1/3) ... [2021-12-22 20:30:32,095 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ede8f22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.12 08:30:32, skipping insertion in model container [2021-12-22 20:30:32,095 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-22 20:30:32,095 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.12 08:30:30" (2/3) ... [2021-12-22 20:30:32,095 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ede8f22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 22.12 08:30:32, skipping insertion in model container [2021-12-22 20:30:32,095 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-22 20:30:32,095 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.12 08:30:32" (3/3) ... [2021-12-22 20:30:32,096 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2021-12-22 20:30:32,123 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-22 20:30:32,123 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-22 20:30:32,123 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-22 20:30:32,124 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-22 20:30:32,124 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-22 20:30:32,124 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-22 20:30:32,124 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-22 20:30:32,124 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-22 20:30:32,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:32,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-12-22 20:30:32,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:32,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:32,215 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,215 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,215 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-22 20:30:32,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:32,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2021-12-22 20:30:32,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:32,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:32,244 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,245 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,256 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1609#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1450#L1731true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 696#L814true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 529#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 598#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1031#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1624#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 945#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 451#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 481#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 700#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 693#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244#L1174true assume !(0 == ~M_E~0); 1354#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 167#L1179-1true assume !(0 == ~T2_E~0); 119#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 188#L1194-1true assume !(0 == ~T5_E~0); 819#L1199-1true assume !(0 == ~T6_E~0); 979#L1204-1true assume !(0 == ~T7_E~0); 742#L1209-1true assume !(0 == ~T8_E~0); 1244#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1637#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 307#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 491#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1336#L1249-1true assume !(0 == ~E_4~0); 468#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 51#L1259-1true assume !(0 == ~E_6~0); 31#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1612#L1274-1true assume !(0 == ~E_9~0); 1325#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1466#L1289-1true assume !(0 == ~E_12~0); 508#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341#L566true assume 1 == ~m_pc~0; 39#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 972#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767#L578true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1189#L1455true assume !(0 != activate_threads_~tmp~1#1); 256#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1616#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714#L597true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1535#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1404#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397#L604true assume !(1 == ~t2_pc~0); 783#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1363#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413#L616true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1198#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 986#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465#L623true assume 1 == ~t3_pc~0; 359#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454#L635true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1025#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1242#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38#L642true assume !(1 == ~t4_pc~0); 663#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 265#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521#L654true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 796#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1123#L661true assume 1 == ~t5_pc~0; 149#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 708#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130#L673true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1100#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 827#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1490#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562#L692true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1115#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1401#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393#L699true assume 1 == ~t7_pc~0; 674#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 894#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144#L711true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 589#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 804#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L718true assume !(1 == ~t8_pc~0); 1250#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#L730true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 226#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 857#L737true assume 1 == ~t9_pc~0; 1502#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1284#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 735#L749true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1638#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 404#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1094#L756true assume 1 == ~t10_pc~0; 887#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 814#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5#L768true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 536#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 290#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 754#L775true assume !(1 == ~t11_pc~0); 445#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1262#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 223#L787true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 849#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L794true assume 1 == ~t12_pc~0; 117#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1101#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 975#L806true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 690#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L1307true assume !(1 == ~M_E~0); 541#L1307-2true assume !(1 == ~T1_E~0); 1445#L1312-1true assume !(1 == ~T2_E~0); 479#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 640#L1322-1true assume !(1 == ~T4_E~0); 295#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1414#L1337-1true assume !(1 == ~T7_E~0); 636#L1342-1true assume !(1 == ~T8_E~0); 1322#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 895#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1136#L1367-1true assume !(1 == ~E_1~0); 189#L1372-1true assume !(1 == ~E_2~0); 488#L1377-1true assume !(1 == ~E_3~0); 351#L1382-1true assume !(1 == ~E_4~0); 784#L1387-1true assume !(1 == ~E_5~0); 1258#L1392-1true assume !(1 == ~E_6~0); 363#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1389#L1402-1true assume !(1 == ~E_8~0); 195#L1407-1true assume !(1 == ~E_9~0); 1520#L1412-1true assume !(1 == ~E_10~0); 974#L1417-1true assume !(1 == ~E_11~0); 1696#L1422-1true assume !(1 == ~E_12~0); 1385#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2021-12-22 20:30:32,265 INFO L793 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 522#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 844#L1149true assume false; 1434#L1164true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419#L814-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999#L1174-3true assume !(0 == ~M_E~0); 992#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 717#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 896#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 577#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume !(0 == ~T8_E~0); 14#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 412#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 100#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1249-3true assume !(0 == ~E_4~0); 1446#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1237#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 765#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1504#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1321#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 411#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1379#L1289-3true assume !(0 == ~E_12~0); 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218#L566-39true assume !(1 == ~m_pc~0); 654#L566-41true is_master_triggered_~__retres1~0#1 := 0; 606#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396#L578-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 836#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298#L585-39true assume 1 == ~t1_pc~0; 968#L586-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L597-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1225#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 871#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L604-39true assume !(1 == ~t2_pc~0); 1222#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 339#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134#L616-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L623-39true assume !(1 == ~t3_pc~0); 650#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 853#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486#L635-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 803#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304#L642-39true assume 1 == ~t4_pc~0; 448#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 753#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#L654-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1184#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204#L661-39true assume !(1 == ~t5_pc~0); 25#L661-41true is_transmit5_triggered_~__retres1~5#1 := 0; 1627#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961#L673-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 977#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1145#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785#L692-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 289#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1491#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1248#L699-39true assume 1 == ~t7_pc~0; 579#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 381#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982#L711-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1269#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 511#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1388#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461#L730-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1153#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 707#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume 1 == ~t9_pc~0; 276#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 452#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1323#L749-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1449#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027#L756-39true assume 1 == ~t10_pc~0; 1376#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1515#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352#L768-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 460#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 431#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1694#L787-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1546#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 759#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467#L794-39true assume 1 == ~t12_pc~0; 277#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 914#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1347#L806-13true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 810#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1307#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1199#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610#L1312-3true assume !(1 == ~T2_E~0); 1604#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 828#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1672#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 533#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 957#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 632#L1352-3true assume !(1 == ~T10_E~0); 1112#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1508#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 20#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 343#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 927#L1392-3true assume !(1 == ~E_6~0); 1595#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1373#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 605#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 156#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1149#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 547#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1105#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1651#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 739#L962-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1433#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1215#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 647#L962-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1318#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 331#L1750true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1590#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2021-12-22 20:30:32,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:32,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2021-12-22 20:30:32,277 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:32,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1187568784] [2021-12-22 20:30:32,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:32,279 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:32,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:32,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:32,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:32,504 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1187568784] [2021-12-22 20:30:32,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1187568784] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:32,505 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:32,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:32,506 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484059782] [2021-12-22 20:30:32,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:32,509 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:32,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:32,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1819192778, now seen corresponding path program 1 times [2021-12-22 20:30:32,510 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:32,510 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394644319] [2021-12-22 20:30:32,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:32,511 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:32,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:32,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:32,547 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:32,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394644319] [2021-12-22 20:30:32,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394644319] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:32,547 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:32,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-22 20:30:32,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902515363] [2021-12-22 20:30:32,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:32,549 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:32,549 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:32,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-12-22 20:30:32,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-12-22 20:30:32,591 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:32,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:32,658 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2021-12-22 20:30:32,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-12-22 20:30:32,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2021-12-22 20:30:32,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:32,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2021-12-22 20:30:32,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:32,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:32,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2021-12-22 20:30:32,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:32,712 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-22 20:30:32,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2021-12-22 20:30:32,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:32,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:32,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2021-12-22 20:30:32,778 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-22 20:30:32,778 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2021-12-22 20:30:32,779 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-22 20:30:32,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2021-12-22 20:30:32,784 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:32,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:32,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:32,786 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,787 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:32,787 INFO L791 eck$LassoCheckResult]: Stem: 4201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5055#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4547#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4354#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4355#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4440#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4741#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4863#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4864#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3652#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3653#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4801#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4247#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4248#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4154#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4155#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4543#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3896#L1174 assume !(0 == ~M_E~0); 3897#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3748#L1179-1 assume !(0 == ~T2_E~0); 3650#L1184-1 assume !(0 == ~T3_E~0); 3651#L1189-1 assume !(0 == ~T4_E~0); 3689#L1194-1 assume !(0 == ~T5_E~0); 3789#L1199-1 assume !(0 == ~T6_E~0); 4684#L1204-1 assume !(0 == ~T7_E~0); 4603#L1209-1 assume !(0 == ~T8_E~0); 4604#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4992#L1219-1 assume !(0 == ~T10_E~0); 5077#L1224-1 assume !(0 == ~T11_E~0); 4014#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3609#L1244-1 assume !(0 == ~E_3~0); 3610#L1249-1 assume !(0 == ~E_4~0); 4271#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3460#L1264-1 assume !(0 == ~E_7~0); 3461#L1269-1 assume !(0 == ~E_8~0); 5082#L1274-1 assume !(0 == ~E_9~0); 5017#L1279-1 assume !(0 == ~E_10~0); 3693#L1284-1 assume !(0 == ~E_11~0); 3694#L1289-1 assume !(0 == ~E_12~0); 4323#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324#L566 assume 1 == ~m_pc~0; 3477#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4632#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4633#L1455 assume !(0 != activate_threads_~tmp~1#1); 3923#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3924#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4573#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4574#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5042#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5040#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4186#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4187#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4824#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4825#L623 assume 1 == ~t3_pc~0; 4101#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3441#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4252#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4859#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3474#L642 assume !(1 == ~t4_pc~0); 3475#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3940#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3941#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3546#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3547#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4664#L661 assume 1 == ~t5_pc~0; 3711#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3712#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3673#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4693#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4694#L680 assume !(1 == ~t6_pc~0); 4134#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4396#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4397#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5038#L699 assume 1 == ~t7_pc~0; 4524#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4525#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3701#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3702#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4426#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325#L718 assume !(1 == ~t8_pc~0); 4326#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3687#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3688#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3729#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3730#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3863#L737 assume 1 == ~t9_pc~0; 4728#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3998#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4599#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4600#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4172#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4173#L756 assume 1 == ~t10_pc~0; 4752#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4418#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3404#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3405#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3980#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3981#L775 assume !(1 == ~t11_pc~0); 4235#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4236#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3857#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3621#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3622#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3808#L794 assume 1 == ~t12_pc~0; 3648#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3626#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4819#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3774#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3775#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L1307 assume !(1 == ~M_E~0); 4255#L1307-2 assume !(1 == ~T1_E~0); 4366#L1312-1 assume !(1 == ~T2_E~0); 4285#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4286#L1322-1 assume !(1 == ~T4_E~0); 3989#L1327-1 assume !(1 == ~T5_E~0); 3990#L1332-1 assume !(1 == ~T6_E~0); 4528#L1337-1 assume !(1 == ~T7_E~0); 4490#L1342-1 assume !(1 == ~T8_E~0); 4491#L1347-1 assume !(1 == ~T9_E~0); 4888#L1352-1 assume !(1 == ~T10_E~0); 4761#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4152#L1362-1 assume !(1 == ~T12_E~0); 4153#L1367-1 assume !(1 == ~E_1~0); 3790#L1372-1 assume !(1 == ~E_2~0); 3791#L1377-1 assume !(1 == ~E_3~0); 4084#L1382-1 assume !(1 == ~E_4~0); 4085#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4104#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4105#L1402-1 assume !(1 == ~E_8~0); 3801#L1407-1 assume !(1 == ~E_9~0); 3802#L1412-1 assume !(1 == ~E_10~0); 4817#L1417-1 assume !(1 == ~E_11~0); 4818#L1422-1 assume !(1 == ~E_12~0); 5036#L1427-1 assume { :end_inline_reset_delta_events } true; 3605#L1768-2 [2021-12-22 20:30:32,788 INFO L793 eck$LassoCheckResult]: Loop: 3605#L1768-2 assume !false; 3606#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4344#L1149 assume !false; 4716#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4869#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3995#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3901#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3902#L976 assume !(0 != eval_~tmp~0#1); 5035#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4836#L1174-3 assume !(0 == ~M_E~0); 4829#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4578#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4579#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4762#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4413#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3764#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4005#L1209-3 assume !(0 == ~T8_E~0); 3425#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3426#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4184#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4185#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4203#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3613#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3614#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4057#L1249-3 assume !(0 == ~E_4~0); 4516#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4630#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3619#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3620#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5015#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4182#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4183#L1289-3 assume !(0 == ~E_12~0); 4171#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3847#L566-39 assume 1 == ~m_pc~0; 3848#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4450#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4162#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4163#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4705#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4706#L585-39 assume 1 == ~t1_pc~0; 4816#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3856#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3931#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3932#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4738#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4431#L604-39 assume 1 == ~t2_pc~0; 4432#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4063#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4064#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4481#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4482#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4046#L623-39 assume 1 == ~t3_pc~0; 3442#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3444#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4722#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3898#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3899#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4670#L642-39 assume 1 == ~t4_pc~0; 4241#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4242#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3770#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3771#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4868#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3819#L661-39 assume !(1 == ~t5_pc~0); 3450#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3451#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4811#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4812#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4725#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4726#L680-39 assume 1 == ~t6_pc~0; 3512#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3513#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4655#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3978#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3979#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4993#L699-39 assume !(1 == ~t7_pc~0); 4416#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4137#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4821#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4942#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4940#L718-39 assume 1 == ~t8_pc~0; 4329#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4330#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4262#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4263#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4565#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4534#L737-39 assume 1 == ~t9_pc~0; 3959#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3960#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4249#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5016#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4917#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4860#L756-39 assume !(1 == ~t10_pc~0); 4341#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4342#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4086#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4087#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4219#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4212#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4213#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5075#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L794-39 assume !(1 == ~t12_pc~0); 3955#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3956#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4776#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4677#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4970#L1312-3 assume !(1 == ~T2_E~0); 5081#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4695#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4696#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3640#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3611#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3612#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4358#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4483#L1352-3 assume !(1 == ~T10_E~0); 4484#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4923#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5074#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4070#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4071#L1392-3 assume !(1 == ~E_6~0); 4786#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4449#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3725#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3726#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4374#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4375#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3735#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4602#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4454#L1787 assume !(0 == start_simulation_~tmp~3#1); 4455#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4978#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3706#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4501#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4502#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4053#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4054#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4055#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3605#L1768-2 [2021-12-22 20:30:32,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:32,789 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2021-12-22 20:30:32,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:32,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873896703] [2021-12-22 20:30:32,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:32,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:32,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:32,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:32,843 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:32,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873896703] [2021-12-22 20:30:32,844 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873896703] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:32,844 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:32,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:32,844 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248514837] [2021-12-22 20:30:32,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:32,845 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:32,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:32,846 INFO L85 PathProgramCache]: Analyzing trace with hash -1764555615, now seen corresponding path program 1 times [2021-12-22 20:30:32,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:32,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058031884] [2021-12-22 20:30:32,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:32,846 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:32,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,010 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,010 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058031884] [2021-12-22 20:30:33,010 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058031884] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,010 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,011 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123579949] [2021-12-22 20:30:33,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,011 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,011 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,013 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,056 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2021-12-22 20:30:33,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2021-12-22 20:30:33,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-12-22 20:30:33,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:33,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:33,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2021-12-22 20:30:33,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:33,092 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-22 20:30:33,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2021-12-22 20:30:33,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:33,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2021-12-22 20:30:33,129 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-22 20:30:33,129 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2021-12-22 20:30:33,129 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-22 20:30:33,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2021-12-22 20:30:33,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:33,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:33,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,143 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,146 INFO L791 eck$LassoCheckResult]: Stem: 7584#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8438#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7930#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7737#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7738#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7823#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8124#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8246#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8247#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7035#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7036#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8184#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7630#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7631#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7537#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7538#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7926#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7279#L1174 assume !(0 == ~M_E~0); 7280#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7131#L1179-1 assume !(0 == ~T2_E~0); 7033#L1184-1 assume !(0 == ~T3_E~0); 7034#L1189-1 assume !(0 == ~T4_E~0); 7072#L1194-1 assume !(0 == ~T5_E~0); 7172#L1199-1 assume !(0 == ~T6_E~0); 8067#L1204-1 assume !(0 == ~T7_E~0); 7986#L1209-1 assume !(0 == ~T8_E~0); 7987#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8375#L1219-1 assume !(0 == ~T10_E~0); 8460#L1224-1 assume !(0 == ~T11_E~0); 7397#L1229-1 assume !(0 == ~T12_E~0); 6958#L1234-1 assume !(0 == ~E_1~0); 6959#L1239-1 assume !(0 == ~E_2~0); 6992#L1244-1 assume !(0 == ~E_3~0); 6993#L1249-1 assume !(0 == ~E_4~0); 7654#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6888#L1259-1 assume !(0 == ~E_6~0); 6843#L1264-1 assume !(0 == ~E_7~0); 6844#L1269-1 assume !(0 == ~E_8~0); 8465#L1274-1 assume !(0 == ~E_9~0); 8400#L1279-1 assume !(0 == ~E_10~0); 7076#L1284-1 assume !(0 == ~E_11~0); 7077#L1289-1 assume !(0 == ~E_12~0); 7706#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7707#L566 assume 1 == ~m_pc~0; 6860#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6861#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8015#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8016#L1455 assume !(0 != activate_threads_~tmp~1#1); 7306#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7307#L585 assume 1 == ~t1_pc~0; 6955#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6956#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7956#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7957#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8425#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L604 assume !(1 == ~t2_pc~0); 8035#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8036#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7569#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7570#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8207#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8208#L623 assume 1 == ~t3_pc~0; 7484#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6824#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7634#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7635#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8242#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6857#L642 assume !(1 == ~t4_pc~0); 6858#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7323#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7324#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6929#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6930#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8047#L661 assume 1 == ~t5_pc~0; 7094#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7095#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7056#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7057#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8076#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8077#L680 assume !(1 == ~t6_pc~0); 7517#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7518#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7779#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7780#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8308#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8421#L699 assume 1 == ~t7_pc~0; 7907#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7908#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7084#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7085#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7809#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7708#L718 assume !(1 == ~t8_pc~0); 7709#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7070#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7071#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7112#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7113#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7246#L737 assume 1 == ~t9_pc~0; 8111#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7381#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7982#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7983#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L756 assume 1 == ~t10_pc~0; 8135#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7801#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6787#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6788#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7363#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7364#L775 assume !(1 == ~t11_pc~0); 7618#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7619#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7240#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7004#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7005#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7191#L794 assume 1 == ~t12_pc~0; 7031#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7009#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8202#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7157#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7158#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7637#L1307 assume !(1 == ~M_E~0); 7638#L1307-2 assume !(1 == ~T1_E~0); 7749#L1312-1 assume !(1 == ~T2_E~0); 7668#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7669#L1322-1 assume !(1 == ~T4_E~0); 7372#L1327-1 assume !(1 == ~T5_E~0); 7373#L1332-1 assume !(1 == ~T6_E~0); 7911#L1337-1 assume !(1 == ~T7_E~0); 7873#L1342-1 assume !(1 == ~T8_E~0); 7874#L1347-1 assume !(1 == ~T9_E~0); 8271#L1352-1 assume !(1 == ~T10_E~0); 8144#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7535#L1362-1 assume !(1 == ~T12_E~0); 7536#L1367-1 assume !(1 == ~E_1~0); 7173#L1372-1 assume !(1 == ~E_2~0); 7174#L1377-1 assume !(1 == ~E_3~0); 7467#L1382-1 assume !(1 == ~E_4~0); 7468#L1387-1 assume !(1 == ~E_5~0); 8037#L1392-1 assume !(1 == ~E_6~0); 7487#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7488#L1402-1 assume !(1 == ~E_8~0); 7184#L1407-1 assume !(1 == ~E_9~0); 7185#L1412-1 assume !(1 == ~E_10~0); 8200#L1417-1 assume !(1 == ~E_11~0); 8201#L1422-1 assume !(1 == ~E_12~0); 8419#L1427-1 assume { :end_inline_reset_delta_events } true; 6988#L1768-2 [2021-12-22 20:30:33,147 INFO L793 eck$LassoCheckResult]: Loop: 6988#L1768-2 assume !false; 6989#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7727#L1149 assume !false; 8099#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8252#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7378#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7284#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7285#L976 assume !(0 != eval_~tmp~0#1); 8418#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8428#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8219#L1174-3 assume !(0 == ~M_E~0); 8212#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8145#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7796#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7146#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7147#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7388#L1209-3 assume !(0 == ~T8_E~0); 6808#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6809#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7567#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7568#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7586#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6996#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6997#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7440#L1249-3 assume !(0 == ~E_4~0); 7899#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8371#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8013#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7002#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7003#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8398#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7565#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7566#L1289-3 assume !(0 == ~E_12~0); 7554#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7230#L566-39 assume !(1 == ~m_pc~0); 7232#L566-41 is_master_triggered_~__retres1~0#1 := 0; 7833#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7545#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7546#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8088#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8089#L585-39 assume !(1 == ~t1_pc~0); 7238#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7239#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7314#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7315#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8121#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7814#L604-39 assume 1 == ~t2_pc~0; 7815#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7446#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7447#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7864#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7865#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7429#L623-39 assume 1 == ~t3_pc~0; 6825#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6827#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8105#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7281#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7282#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8053#L642-39 assume 1 == ~t4_pc~0; 7624#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7625#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7153#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7154#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8251#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7202#L661-39 assume !(1 == ~t5_pc~0); 6833#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 6834#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8194#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8195#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8108#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8109#L680-39 assume !(1 == ~t6_pc~0); 6897#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6896#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8038#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7361#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7362#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8376#L699-39 assume 1 == ~t7_pc~0; 7798#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7520#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7521#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8204#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8325#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8323#L718-39 assume 1 == ~t8_pc~0; 7712#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7713#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7645#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7646#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 7948#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7917#L737-39 assume !(1 == ~t9_pc~0); 7344#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 7343#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7632#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8399#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8300#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8243#L756-39 assume 1 == ~t10_pc~0; 8244#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7725#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7469#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7470#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7602#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6942#L775-39 assume !(1 == ~t11_pc~0); 6944#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 7595#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7596#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8458#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8006#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7653#L794-39 assume 1 == ~t12_pc~0; 7345#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7339#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8159#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8060#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6884#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6885#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8352#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8353#L1312-3 assume !(1 == ~T2_E~0); 8464#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8078#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8079#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7023#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6994#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6995#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7741#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7866#L1352-3 assume !(1 == ~T10_E~0); 7867#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8306#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8457#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8448#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6821#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6822#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7453#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7454#L1392-3 assume !(1 == ~E_6~0); 8169#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8415#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7832#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7108#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7109#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7757#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7758#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7118#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7119#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7985#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7837#L1787 assume !(0 == start_simulation_~tmp~3#1); 7838#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8361#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7089#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7884#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 7885#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7436#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7437#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 7438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1768-2 [2021-12-22 20:30:33,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2021-12-22 20:30:33,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454410693] [2021-12-22 20:30:33,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,199 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454410693] [2021-12-22 20:30:33,200 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454410693] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,200 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,200 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,200 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853643532] [2021-12-22 20:30:33,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,201 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:33,201 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,201 INFO L85 PathProgramCache]: Analyzing trace with hash 1578992735, now seen corresponding path program 1 times [2021-12-22 20:30:33,201 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,202 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023650639] [2021-12-22 20:30:33,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,202 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,275 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,275 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023650639] [2021-12-22 20:30:33,275 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023650639] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,275 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,275 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,276 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226009890] [2021-12-22 20:30:33,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,276 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,276 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,277 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,299 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2021-12-22 20:30:33,299 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2021-12-22 20:30:33,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-12-22 20:30:33,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:33,314 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:33,314 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2021-12-22 20:30:33,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:33,316 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-22 20:30:33,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2021-12-22 20:30:33,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:33,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2021-12-22 20:30:33,340 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-22 20:30:33,340 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2021-12-22 20:30:33,340 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-22 20:30:33,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2021-12-22 20:30:33,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:33,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:33,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,350 INFO L791 eck$LassoCheckResult]: Stem: 10967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11821#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11313#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11120#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11121#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11206#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11507#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11629#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11630#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10418#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10419#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11567#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11013#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11014#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10920#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10921#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11309#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10662#L1174 assume !(0 == ~M_E~0); 10663#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10514#L1179-1 assume !(0 == ~T2_E~0); 10416#L1184-1 assume !(0 == ~T3_E~0); 10417#L1189-1 assume !(0 == ~T4_E~0); 10455#L1194-1 assume !(0 == ~T5_E~0); 10555#L1199-1 assume !(0 == ~T6_E~0); 11450#L1204-1 assume !(0 == ~T7_E~0); 11369#L1209-1 assume !(0 == ~T8_E~0); 11370#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11758#L1219-1 assume !(0 == ~T10_E~0); 11843#L1224-1 assume !(0 == ~T11_E~0); 10780#L1229-1 assume !(0 == ~T12_E~0); 10341#L1234-1 assume !(0 == ~E_1~0); 10342#L1239-1 assume !(0 == ~E_2~0); 10375#L1244-1 assume !(0 == ~E_3~0); 10376#L1249-1 assume !(0 == ~E_4~0); 11037#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10271#L1259-1 assume !(0 == ~E_6~0); 10226#L1264-1 assume !(0 == ~E_7~0); 10227#L1269-1 assume !(0 == ~E_8~0); 11848#L1274-1 assume !(0 == ~E_9~0); 11783#L1279-1 assume !(0 == ~E_10~0); 10459#L1284-1 assume !(0 == ~E_11~0); 10460#L1289-1 assume !(0 == ~E_12~0); 11089#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11090#L566 assume 1 == ~m_pc~0; 10243#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10244#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11398#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11399#L1455 assume !(0 != activate_threads_~tmp~1#1); 10689#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10690#L585 assume 1 == ~t1_pc~0; 10338#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10339#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11339#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11340#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11806#L604 assume !(1 == ~t2_pc~0); 11418#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11419#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10952#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10953#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11590#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11591#L623 assume 1 == ~t3_pc~0; 10867#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10207#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11017#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11018#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11625#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10240#L642 assume !(1 == ~t4_pc~0); 10241#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10706#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10707#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10312#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10313#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11430#L661 assume 1 == ~t5_pc~0; 10477#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10478#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10439#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10440#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11459#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11460#L680 assume !(1 == ~t6_pc~0); 10900#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10901#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11162#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11163#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11691#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11804#L699 assume 1 == ~t7_pc~0; 11290#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11291#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10467#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10468#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11192#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11091#L718 assume !(1 == ~t8_pc~0); 11092#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10453#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10454#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10495#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10496#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10629#L737 assume 1 == ~t9_pc~0; 11494#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10764#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11365#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11366#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10938#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10939#L756 assume 1 == ~t10_pc~0; 11518#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11184#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10170#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10171#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10746#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10747#L775 assume !(1 == ~t11_pc~0); 11001#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11002#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10623#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10387#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10388#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10574#L794 assume 1 == ~t12_pc~0; 10414#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10392#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11585#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10540#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10541#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11020#L1307 assume !(1 == ~M_E~0); 11021#L1307-2 assume !(1 == ~T1_E~0); 11132#L1312-1 assume !(1 == ~T2_E~0); 11051#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11052#L1322-1 assume !(1 == ~T4_E~0); 10755#L1327-1 assume !(1 == ~T5_E~0); 10756#L1332-1 assume !(1 == ~T6_E~0); 11294#L1337-1 assume !(1 == ~T7_E~0); 11256#L1342-1 assume !(1 == ~T8_E~0); 11257#L1347-1 assume !(1 == ~T9_E~0); 11654#L1352-1 assume !(1 == ~T10_E~0); 11527#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10918#L1362-1 assume !(1 == ~T12_E~0); 10919#L1367-1 assume !(1 == ~E_1~0); 10556#L1372-1 assume !(1 == ~E_2~0); 10557#L1377-1 assume !(1 == ~E_3~0); 10850#L1382-1 assume !(1 == ~E_4~0); 10851#L1387-1 assume !(1 == ~E_5~0); 11420#L1392-1 assume !(1 == ~E_6~0); 10870#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10871#L1402-1 assume !(1 == ~E_8~0); 10567#L1407-1 assume !(1 == ~E_9~0); 10568#L1412-1 assume !(1 == ~E_10~0); 11583#L1417-1 assume !(1 == ~E_11~0); 11584#L1422-1 assume !(1 == ~E_12~0); 11802#L1427-1 assume { :end_inline_reset_delta_events } true; 10371#L1768-2 [2021-12-22 20:30:33,350 INFO L793 eck$LassoCheckResult]: Loop: 10371#L1768-2 assume !false; 10372#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11110#L1149 assume !false; 11482#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11635#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10761#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10667#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10668#L976 assume !(0 != eval_~tmp~0#1); 11801#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11811#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11602#L1174-3 assume !(0 == ~M_E~0); 11595#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11344#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11345#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11528#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11179#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10529#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10530#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10771#L1209-3 assume !(0 == ~T8_E~0); 10191#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10192#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10950#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10951#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10969#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10379#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10380#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10823#L1249-3 assume !(0 == ~E_4~0); 11282#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11754#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11396#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10385#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10386#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11781#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10948#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10949#L1289-3 assume !(0 == ~E_12~0); 10937#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10613#L566-39 assume 1 == ~m_pc~0; 10614#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11216#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10928#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10929#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11471#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11472#L585-39 assume !(1 == ~t1_pc~0); 10621#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10622#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10697#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10698#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11504#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11197#L604-39 assume 1 == ~t2_pc~0; 11198#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10829#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10830#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11247#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11248#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10812#L623-39 assume 1 == ~t3_pc~0; 10208#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10210#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11488#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10664#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10665#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11436#L642-39 assume !(1 == ~t4_pc~0); 11009#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 11008#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10536#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10537#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11634#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10585#L661-39 assume !(1 == ~t5_pc~0); 10216#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10217#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11578#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11491#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11492#L680-39 assume 1 == ~t6_pc~0; 10278#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11421#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10744#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10745#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11759#L699-39 assume 1 == ~t7_pc~0; 11181#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10903#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10904#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11587#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11708#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11706#L718-39 assume 1 == ~t8_pc~0; 11095#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11096#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11028#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11029#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11331#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11300#L737-39 assume 1 == ~t9_pc~0; 10725#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10726#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11015#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11782#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11683#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11626#L756-39 assume !(1 == ~t10_pc~0); 11107#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11108#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10852#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10853#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10985#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10325#L775-39 assume 1 == ~t11_pc~0; 10326#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10978#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10979#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11841#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11389#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11036#L794-39 assume !(1 == ~t12_pc~0); 10721#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10722#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11542#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11443#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10267#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10268#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11735#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11736#L1312-3 assume !(1 == ~T2_E~0); 11847#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11461#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11462#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10406#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10377#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10378#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11124#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11249#L1352-3 assume !(1 == ~T10_E~0); 11250#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11689#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11840#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11831#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10204#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10205#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10836#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10837#L1392-3 assume !(1 == ~E_6~0); 11552#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11798#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11215#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10491#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10492#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11140#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11141#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10501#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10502#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11368#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 11220#L1787 assume !(0 == start_simulation_~tmp~3#1); 11221#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11744#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10472#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11267#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 11268#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10819#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10820#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10821#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10371#L1768-2 [2021-12-22 20:30:33,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2021-12-22 20:30:33,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804806111] [2021-12-22 20:30:33,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,353 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,414 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,414 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804806111] [2021-12-22 20:30:33,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804806111] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,415 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,416 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890313674] [2021-12-22 20:30:33,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,417 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:33,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,418 INFO L85 PathProgramCache]: Analyzing trace with hash -601300672, now seen corresponding path program 1 times [2021-12-22 20:30:33,419 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029041448] [2021-12-22 20:30:33,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,420 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,472 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029041448] [2021-12-22 20:30:33,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029041448] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,473 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638823570] [2021-12-22 20:30:33,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,474 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,474 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,476 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,503 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2021-12-22 20:30:33,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2021-12-22 20:30:33,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-12-22 20:30:33,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:33,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:33,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2021-12-22 20:30:33,522 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:33,522 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-22 20:30:33,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2021-12-22 20:30:33,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:33,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2021-12-22 20:30:33,580 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-22 20:30:33,580 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2021-12-22 20:30:33,580 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-22 20:30:33,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2021-12-22 20:30:33,585 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:33,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:33,586 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,587 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,587 INFO L791 eck$LassoCheckResult]: Stem: 14351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 14352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15204#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14698#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14503#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14504#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14589#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14891#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15012#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15013#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13801#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13802#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14950#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14396#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14397#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14303#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14304#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14693#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14045#L1174 assume !(0 == ~M_E~0); 14046#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13897#L1179-1 assume !(0 == ~T2_E~0); 13799#L1184-1 assume !(0 == ~T3_E~0); 13800#L1189-1 assume !(0 == ~T4_E~0); 13838#L1194-1 assume !(0 == ~T5_E~0); 13938#L1199-1 assume !(0 == ~T6_E~0); 14833#L1204-1 assume !(0 == ~T7_E~0); 14752#L1209-1 assume !(0 == ~T8_E~0); 14753#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15141#L1219-1 assume !(0 == ~T10_E~0); 15226#L1224-1 assume !(0 == ~T11_E~0); 14164#L1229-1 assume !(0 == ~T12_E~0); 13726#L1234-1 assume !(0 == ~E_1~0); 13727#L1239-1 assume !(0 == ~E_2~0); 13760#L1244-1 assume !(0 == ~E_3~0); 13761#L1249-1 assume !(0 == ~E_4~0); 14420#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13654#L1259-1 assume !(0 == ~E_6~0); 13609#L1264-1 assume !(0 == ~E_7~0); 13610#L1269-1 assume !(0 == ~E_8~0); 15231#L1274-1 assume !(0 == ~E_9~0); 15166#L1279-1 assume !(0 == ~E_10~0); 13842#L1284-1 assume !(0 == ~E_11~0); 13843#L1289-1 assume !(0 == ~E_12~0); 14472#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14473#L566 assume 1 == ~m_pc~0; 13626#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13627#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14781#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14782#L1455 assume !(0 != activate_threads_~tmp~1#1); 14072#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14073#L585 assume 1 == ~t1_pc~0; 13721#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13722#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14722#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14723#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15191#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15189#L604 assume !(1 == ~t2_pc~0); 14801#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14802#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14335#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14336#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14975#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14976#L623 assume 1 == ~t3_pc~0; 14250#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13590#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14400#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14401#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15008#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13623#L642 assume !(1 == ~t4_pc~0); 13624#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14089#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14090#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13697#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13698#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14813#L661 assume 1 == ~t5_pc~0; 13860#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13861#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13822#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13823#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14844#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14845#L680 assume !(1 == ~t6_pc~0); 14283#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14284#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14545#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14546#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15074#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15187#L699 assume 1 == ~t7_pc~0; 14673#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14674#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13850#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13851#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14575#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14474#L718 assume !(1 == ~t8_pc~0); 14475#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13836#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13837#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13878#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13879#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14012#L737 assume 1 == ~t9_pc~0; 14878#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14148#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14748#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14749#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14321#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14322#L756 assume 1 == ~t10_pc~0; 14901#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14567#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13553#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13554#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14129#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14130#L775 assume !(1 == ~t11_pc~0); 14384#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14385#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14009#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13770#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13771#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13957#L794 assume 1 == ~t12_pc~0; 13798#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13775#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14968#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13925#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 13926#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14403#L1307 assume !(1 == ~M_E~0); 14404#L1307-2 assume !(1 == ~T1_E~0); 14515#L1312-1 assume !(1 == ~T2_E~0); 14434#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14435#L1322-1 assume !(1 == ~T4_E~0); 14138#L1327-1 assume !(1 == ~T5_E~0); 14139#L1332-1 assume !(1 == ~T6_E~0); 14677#L1337-1 assume !(1 == ~T7_E~0); 14639#L1342-1 assume !(1 == ~T8_E~0); 14640#L1347-1 assume !(1 == ~T9_E~0); 15037#L1352-1 assume !(1 == ~T10_E~0); 14910#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14301#L1362-1 assume !(1 == ~T12_E~0); 14302#L1367-1 assume !(1 == ~E_1~0); 13939#L1372-1 assume !(1 == ~E_2~0); 13940#L1377-1 assume !(1 == ~E_3~0); 14233#L1382-1 assume !(1 == ~E_4~0); 14234#L1387-1 assume !(1 == ~E_5~0); 14803#L1392-1 assume !(1 == ~E_6~0); 14255#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14256#L1402-1 assume !(1 == ~E_8~0); 13955#L1407-1 assume !(1 == ~E_9~0); 13956#L1412-1 assume !(1 == ~E_10~0); 14966#L1417-1 assume !(1 == ~E_11~0); 14967#L1422-1 assume !(1 == ~E_12~0); 15185#L1427-1 assume { :end_inline_reset_delta_events } true; 13754#L1768-2 [2021-12-22 20:30:33,587 INFO L793 eck$LassoCheckResult]: Loop: 13754#L1768-2 assume !false; 13755#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14495#L1149 assume !false; 14866#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15018#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14144#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14056#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14057#L976 assume !(0 != eval_~tmp~0#1); 15184#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15194#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14985#L1174-3 assume !(0 == ~M_E~0); 14978#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14727#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14728#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14912#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14562#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13915#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13916#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14154#L1209-3 assume !(0 == ~T8_E~0); 13574#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13575#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14333#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14334#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14353#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13762#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13763#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14209#L1249-3 assume !(0 == ~E_4~0); 14665#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15137#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14779#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13768#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13769#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15164#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14331#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14332#L1289-3 assume !(0 == ~E_12~0); 14320#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13993#L566-39 assume 1 == ~m_pc~0; 13994#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14599#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14311#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14312#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14854#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14855#L585-39 assume !(1 == ~t1_pc~0); 14004#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14005#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14080#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14081#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14887#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14580#L604-39 assume 1 == ~t2_pc~0; 14581#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14212#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14213#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14630#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14631#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14195#L623-39 assume 1 == ~t3_pc~0; 13591#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13593#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14871#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14047#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14048#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14819#L642-39 assume 1 == ~t4_pc~0; 14390#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14391#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13919#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15017#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13968#L661-39 assume 1 == ~t5_pc~0; 13969#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13600#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14960#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14961#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14874#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14875#L680-39 assume 1 == ~t6_pc~0; 13661#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13662#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14804#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14127#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14128#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15142#L699-39 assume 1 == ~t7_pc~0; 14564#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14286#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14287#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14970#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15091#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15089#L718-39 assume !(1 == ~t8_pc~0); 14480#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 14479#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14411#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14412#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 14713#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14683#L737-39 assume 1 == ~t9_pc~0; 14108#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14109#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14398#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15165#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15066#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15009#L756-39 assume 1 == ~t10_pc~0; 15010#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14491#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14235#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14236#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14368#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13708#L775-39 assume 1 == ~t11_pc~0; 13709#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14361#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14362#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 15224#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14772#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14419#L794-39 assume !(1 == ~t12_pc~0); 14104#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14105#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14925#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14826#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13650#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13651#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15118#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15119#L1312-3 assume !(1 == ~T2_E~0); 15230#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14843#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13789#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13758#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13759#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14507#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14632#L1352-3 assume !(1 == ~T10_E~0); 14633#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15072#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15223#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15214#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13584#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13585#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14219#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14220#L1392-3 assume !(1 == ~E_6~0); 14935#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15181#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14598#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13874#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13875#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14523#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14524#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13884#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13885#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14751#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14602#L1787 assume !(0 == start_simulation_~tmp~3#1); 14603#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15127#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13855#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14650#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 14651#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14202#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14203#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 14204#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13754#L1768-2 [2021-12-22 20:30:33,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,588 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2021-12-22 20:30:33,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,588 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489155451] [2021-12-22 20:30:33,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,624 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [489155451] [2021-12-22 20:30:33,625 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [489155451] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,625 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,625 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,625 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916082797] [2021-12-22 20:30:33,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,626 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:33,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1933371202, now seen corresponding path program 1 times [2021-12-22 20:30:33,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,626 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677236000] [2021-12-22 20:30:33,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,627 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1677236000] [2021-12-22 20:30:33,673 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1677236000] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,673 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,674 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188837763] [2021-12-22 20:30:33,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,674 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,674 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,675 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,694 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2021-12-22 20:30:33,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2021-12-22 20:30:33,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-12-22 20:30:33,710 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:33,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:33,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2021-12-22 20:30:33,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:33,713 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-22 20:30:33,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2021-12-22 20:30:33,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:33,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2021-12-22 20:30:33,733 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-22 20:30:33,733 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2021-12-22 20:30:33,734 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-22 20:30:33,734 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2021-12-22 20:30:33,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:33,738 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:33,739 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,739 INFO L791 eck$LassoCheckResult]: Stem: 17733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18587#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18081#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17886#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17887#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17972#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18273#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18395#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18396#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17184#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17185#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18333#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17779#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17780#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17686#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17687#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17428#L1174 assume !(0 == ~M_E~0); 17429#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17280#L1179-1 assume !(0 == ~T2_E~0); 17182#L1184-1 assume !(0 == ~T3_E~0); 17183#L1189-1 assume !(0 == ~T4_E~0); 17221#L1194-1 assume !(0 == ~T5_E~0); 17321#L1199-1 assume !(0 == ~T6_E~0); 18216#L1204-1 assume !(0 == ~T7_E~0); 18135#L1209-1 assume !(0 == ~T8_E~0); 18136#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18524#L1219-1 assume !(0 == ~T10_E~0); 18609#L1224-1 assume !(0 == ~T11_E~0); 17546#L1229-1 assume !(0 == ~T12_E~0); 17107#L1234-1 assume !(0 == ~E_1~0); 17108#L1239-1 assume !(0 == ~E_2~0); 17143#L1244-1 assume !(0 == ~E_3~0); 17144#L1249-1 assume !(0 == ~E_4~0); 17803#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17037#L1259-1 assume !(0 == ~E_6~0); 16992#L1264-1 assume !(0 == ~E_7~0); 16993#L1269-1 assume !(0 == ~E_8~0); 18614#L1274-1 assume !(0 == ~E_9~0); 18549#L1279-1 assume !(0 == ~E_10~0); 17225#L1284-1 assume !(0 == ~E_11~0); 17226#L1289-1 assume !(0 == ~E_12~0); 17855#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17856#L566 assume 1 == ~m_pc~0; 17009#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17010#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18164#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18165#L1455 assume !(0 != activate_threads_~tmp~1#1); 17455#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17456#L585 assume 1 == ~t1_pc~0; 17104#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17105#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18105#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18106#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18574#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18572#L604 assume !(1 == ~t2_pc~0); 18184#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18185#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17718#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17719#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18358#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18359#L623 assume 1 == ~t3_pc~0; 17633#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16973#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17783#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17784#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18391#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17006#L642 assume !(1 == ~t4_pc~0); 17007#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17472#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17473#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17078#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17079#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18196#L661 assume 1 == ~t5_pc~0; 17243#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17244#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17205#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17206#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18227#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18228#L680 assume !(1 == ~t6_pc~0); 17666#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17667#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17928#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17929#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18457#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18570#L699 assume 1 == ~t7_pc~0; 18056#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18057#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17233#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17234#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17958#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17857#L718 assume !(1 == ~t8_pc~0); 17858#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17219#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17220#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17261#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17262#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17395#L737 assume 1 == ~t9_pc~0; 18261#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17530#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18131#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18132#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17704#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17705#L756 assume 1 == ~t10_pc~0; 18284#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17950#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16936#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16937#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17512#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17513#L775 assume !(1 == ~t11_pc~0); 17767#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17768#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17389#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17153#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17154#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17340#L794 assume 1 == ~t12_pc~0; 17181#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17158#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18351#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17308#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17309#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17786#L1307 assume !(1 == ~M_E~0); 17787#L1307-2 assume !(1 == ~T1_E~0); 17898#L1312-1 assume !(1 == ~T2_E~0); 17817#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17818#L1322-1 assume !(1 == ~T4_E~0); 17521#L1327-1 assume !(1 == ~T5_E~0); 17522#L1332-1 assume !(1 == ~T6_E~0); 18060#L1337-1 assume !(1 == ~T7_E~0); 18022#L1342-1 assume !(1 == ~T8_E~0); 18023#L1347-1 assume !(1 == ~T9_E~0); 18420#L1352-1 assume !(1 == ~T10_E~0); 18293#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17684#L1362-1 assume !(1 == ~T12_E~0); 17685#L1367-1 assume !(1 == ~E_1~0); 17322#L1372-1 assume !(1 == ~E_2~0); 17323#L1377-1 assume !(1 == ~E_3~0); 17616#L1382-1 assume !(1 == ~E_4~0); 17617#L1387-1 assume !(1 == ~E_5~0); 18186#L1392-1 assume !(1 == ~E_6~0); 17638#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17639#L1402-1 assume !(1 == ~E_8~0); 17335#L1407-1 assume !(1 == ~E_9~0); 17336#L1412-1 assume !(1 == ~E_10~0); 18349#L1417-1 assume !(1 == ~E_11~0); 18350#L1422-1 assume !(1 == ~E_12~0); 18568#L1427-1 assume { :end_inline_reset_delta_events } true; 17137#L1768-2 [2021-12-22 20:30:33,740 INFO L793 eck$LassoCheckResult]: Loop: 17137#L1768-2 assume !false; 17138#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17876#L1149 assume !false; 18248#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18401#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17527#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17433#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17434#L976 assume !(0 != eval_~tmp~0#1); 18567#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18577#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18368#L1174-3 assume !(0 == ~M_E~0); 18361#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18110#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18111#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18295#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17945#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17298#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17299#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17537#L1209-3 assume !(0 == ~T8_E~0); 16957#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16958#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17716#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17717#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17735#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17145#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17146#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17589#L1249-3 assume !(0 == ~E_4~0); 18048#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18520#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18162#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17151#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17152#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18547#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17714#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17715#L1289-3 assume !(0 == ~E_12~0); 17703#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17379#L566-39 assume 1 == ~m_pc~0; 17380#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17982#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17694#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17695#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18237#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18238#L585-39 assume !(1 == ~t1_pc~0); 17387#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17388#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17463#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17464#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18270#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17963#L604-39 assume 1 == ~t2_pc~0; 17964#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17595#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17596#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18015#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18016#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17578#L623-39 assume 1 == ~t3_pc~0; 16976#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16978#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18254#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17430#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17431#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18202#L642-39 assume !(1 == ~t4_pc~0); 17777#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 17776#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17302#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17303#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18400#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17353#L661-39 assume !(1 == ~t5_pc~0); 16982#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 16983#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18343#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18344#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18258#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18259#L680-39 assume 1 == ~t6_pc~0; 17046#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17047#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18187#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17510#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17511#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18525#L699-39 assume 1 == ~t7_pc~0; 17947#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17669#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17670#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18353#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18473#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18471#L718-39 assume 1 == ~t8_pc~0; 17861#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17862#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17794#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17795#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18096#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18066#L737-39 assume 1 == ~t9_pc~0; 17491#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17492#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17781#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18548#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18449#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18392#L756-39 assume !(1 == ~t10_pc~0); 17873#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17874#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17618#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17619#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17751#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17091#L775-39 assume 1 == ~t11_pc~0; 17092#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17744#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17745#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18607#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18155#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17802#L794-39 assume 1 == ~t12_pc~0; 17494#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17488#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18308#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18209#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17033#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17034#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18501#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18502#L1312-3 assume !(1 == ~T2_E~0); 18613#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18225#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18226#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17170#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17141#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17142#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17890#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18013#L1352-3 assume !(1 == ~T10_E~0); 18014#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18454#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18606#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18597#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16967#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16968#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17602#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17603#L1392-3 assume !(1 == ~E_6~0); 18318#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18564#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17981#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17257#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17258#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17904#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17905#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17267#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17268#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18134#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17985#L1787 assume !(0 == start_simulation_~tmp~3#1); 17986#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18510#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17238#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18033#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 18034#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17585#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17586#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17587#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17137#L1768-2 [2021-12-22 20:30:33,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,744 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2021-12-22 20:30:33,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990783307] [2021-12-22 20:30:33,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,745 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,767 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,767 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990783307] [2021-12-22 20:30:33,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990783307] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,767 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,768 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,768 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234530424] [2021-12-22 20:30:33,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,769 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:33,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,771 INFO L85 PathProgramCache]: Analyzing trace with hash 673802017, now seen corresponding path program 1 times [2021-12-22 20:30:33,771 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,774 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908759941] [2021-12-22 20:30:33,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,774 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,808 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,808 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908759941] [2021-12-22 20:30:33,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908759941] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,811 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,811 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60837267] [2021-12-22 20:30:33,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,812 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,812 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,813 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,833 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2021-12-22 20:30:33,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2021-12-22 20:30:33,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-12-22 20:30:33,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:33,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:33,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2021-12-22 20:30:33,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:33,852 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-22 20:30:33,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2021-12-22 20:30:33,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:33,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2021-12-22 20:30:33,874 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-22 20:30:33,875 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2021-12-22 20:30:33,875 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-22 20:30:33,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2021-12-22 20:30:33,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:33,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:33,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:33,901 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,901 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:33,902 INFO L791 eck$LassoCheckResult]: Stem: 21116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 21117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21970#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21462#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21269#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21270#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21355#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21656#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21778#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21779#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20567#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20568#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21716#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21162#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21163#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21069#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21070#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21458#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20811#L1174 assume !(0 == ~M_E~0); 20812#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20663#L1179-1 assume !(0 == ~T2_E~0); 20565#L1184-1 assume !(0 == ~T3_E~0); 20566#L1189-1 assume !(0 == ~T4_E~0); 20604#L1194-1 assume !(0 == ~T5_E~0); 20704#L1199-1 assume !(0 == ~T6_E~0); 21599#L1204-1 assume !(0 == ~T7_E~0); 21518#L1209-1 assume !(0 == ~T8_E~0); 21519#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21907#L1219-1 assume !(0 == ~T10_E~0); 21992#L1224-1 assume !(0 == ~T11_E~0); 20929#L1229-1 assume !(0 == ~T12_E~0); 20490#L1234-1 assume !(0 == ~E_1~0); 20491#L1239-1 assume !(0 == ~E_2~0); 20524#L1244-1 assume !(0 == ~E_3~0); 20525#L1249-1 assume !(0 == ~E_4~0); 21186#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20420#L1259-1 assume !(0 == ~E_6~0); 20375#L1264-1 assume !(0 == ~E_7~0); 20376#L1269-1 assume !(0 == ~E_8~0); 21997#L1274-1 assume !(0 == ~E_9~0); 21932#L1279-1 assume !(0 == ~E_10~0); 20608#L1284-1 assume !(0 == ~E_11~0); 20609#L1289-1 assume !(0 == ~E_12~0); 21238#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21239#L566 assume 1 == ~m_pc~0; 20392#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20393#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21547#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21548#L1455 assume !(0 != activate_threads_~tmp~1#1); 20838#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20839#L585 assume 1 == ~t1_pc~0; 20487#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20488#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21488#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21489#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 21957#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21955#L604 assume !(1 == ~t2_pc~0); 21567#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21568#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21101#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21102#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21739#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21740#L623 assume 1 == ~t3_pc~0; 21016#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20356#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21166#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21167#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21774#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20389#L642 assume !(1 == ~t4_pc~0); 20390#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20855#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20856#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20461#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20462#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21579#L661 assume 1 == ~t5_pc~0; 20626#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20627#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20588#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20589#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21608#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21609#L680 assume !(1 == ~t6_pc~0); 21049#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21050#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21311#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21312#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 21840#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21953#L699 assume 1 == ~t7_pc~0; 21439#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21440#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20616#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20617#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21341#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21240#L718 assume !(1 == ~t8_pc~0); 21241#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20602#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20603#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20644#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20645#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20778#L737 assume 1 == ~t9_pc~0; 21643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20913#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21514#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21515#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21087#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21088#L756 assume 1 == ~t10_pc~0; 21667#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21333#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20319#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20320#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 20895#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20896#L775 assume !(1 == ~t11_pc~0); 21150#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21151#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20772#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20536#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20537#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20723#L794 assume 1 == ~t12_pc~0; 20563#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20541#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21734#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20689#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20690#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21169#L1307 assume !(1 == ~M_E~0); 21170#L1307-2 assume !(1 == ~T1_E~0); 21281#L1312-1 assume !(1 == ~T2_E~0); 21200#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21201#L1322-1 assume !(1 == ~T4_E~0); 20904#L1327-1 assume !(1 == ~T5_E~0); 20905#L1332-1 assume !(1 == ~T6_E~0); 21443#L1337-1 assume !(1 == ~T7_E~0); 21405#L1342-1 assume !(1 == ~T8_E~0); 21406#L1347-1 assume !(1 == ~T9_E~0); 21803#L1352-1 assume !(1 == ~T10_E~0); 21676#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21067#L1362-1 assume !(1 == ~T12_E~0); 21068#L1367-1 assume !(1 == ~E_1~0); 20705#L1372-1 assume !(1 == ~E_2~0); 20706#L1377-1 assume !(1 == ~E_3~0); 20999#L1382-1 assume !(1 == ~E_4~0); 21000#L1387-1 assume !(1 == ~E_5~0); 21569#L1392-1 assume !(1 == ~E_6~0); 21019#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21020#L1402-1 assume !(1 == ~E_8~0); 20716#L1407-1 assume !(1 == ~E_9~0); 20717#L1412-1 assume !(1 == ~E_10~0); 21732#L1417-1 assume !(1 == ~E_11~0); 21733#L1422-1 assume !(1 == ~E_12~0); 21951#L1427-1 assume { :end_inline_reset_delta_events } true; 20520#L1768-2 [2021-12-22 20:30:33,903 INFO L793 eck$LassoCheckResult]: Loop: 20520#L1768-2 assume !false; 20521#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21259#L1149 assume !false; 21631#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21784#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20910#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20816#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20817#L976 assume !(0 != eval_~tmp~0#1); 21950#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21960#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21751#L1174-3 assume !(0 == ~M_E~0); 21744#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21493#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21494#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21677#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21328#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20678#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20679#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20920#L1209-3 assume !(0 == ~T8_E~0); 20340#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20341#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21099#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21100#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21118#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20528#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20529#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20972#L1249-3 assume !(0 == ~E_4~0); 21431#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21903#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21545#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20534#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20535#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21930#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21097#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21098#L1289-3 assume !(0 == ~E_12~0); 21086#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20762#L566-39 assume 1 == ~m_pc~0; 20763#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21365#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21077#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21078#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21621#L585-39 assume !(1 == ~t1_pc~0); 20770#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20771#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20846#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20847#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21653#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21346#L604-39 assume 1 == ~t2_pc~0; 21347#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20978#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20979#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21396#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21397#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20961#L623-39 assume 1 == ~t3_pc~0; 20357#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20359#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21637#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20813#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20814#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21585#L642-39 assume 1 == ~t4_pc~0; 21156#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21157#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20685#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20686#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21783#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20734#L661-39 assume !(1 == ~t5_pc~0); 20365#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 20366#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21726#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21727#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21641#L680-39 assume 1 == ~t6_pc~0; 20427#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20428#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21570#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20893#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20894#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21908#L699-39 assume 1 == ~t7_pc~0; 21330#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21052#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21053#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21736#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21857#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21855#L718-39 assume 1 == ~t8_pc~0; 21244#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21245#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21177#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21178#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 21480#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21449#L737-39 assume 1 == ~t9_pc~0; 20874#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20875#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21164#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21931#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21832#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21775#L756-39 assume 1 == ~t10_pc~0; 21776#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21257#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21001#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21002#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21134#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20474#L775-39 assume 1 == ~t11_pc~0; 20475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21127#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21128#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21990#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21185#L794-39 assume !(1 == ~t12_pc~0); 20870#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 20871#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21691#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21592#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20416#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20417#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21884#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21885#L1312-3 assume !(1 == ~T2_E~0); 21996#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21610#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21611#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20555#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20526#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20527#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21273#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21398#L1352-3 assume !(1 == ~T10_E~0); 21399#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21838#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21989#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21980#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20353#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20354#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20985#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20986#L1392-3 assume !(1 == ~E_6~0); 21701#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21947#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21364#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20640#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20641#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21289#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21290#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20650#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20651#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21517#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 21369#L1787 assume !(0 == start_simulation_~tmp~3#1); 21370#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21893#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20621#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21416#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 21417#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20968#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20969#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 20970#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20520#L1768-2 [2021-12-22 20:30:33,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,903 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2021-12-22 20:30:33,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779651131] [2021-12-22 20:30:33,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,904 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,925 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,925 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779651131] [2021-12-22 20:30:33,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779651131] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,926 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,926 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,926 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [293065697] [2021-12-22 20:30:33,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,926 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:33,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:33,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1017478530, now seen corresponding path program 1 times [2021-12-22 20:30:33,927 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:33,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676504819] [2021-12-22 20:30:33,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:33,927 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:33,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:33,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:33,954 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:33,954 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676504819] [2021-12-22 20:30:33,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676504819] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:33,954 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:33,954 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:33,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626130833] [2021-12-22 20:30:33,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:33,955 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:33,955 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:33,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:33,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:33,956 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:33,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:33,990 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2021-12-22 20:30:33,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:33,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2021-12-22 20:30:33,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,003 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-12-22 20:30:34,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2021-12-22 20:30:34,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,008 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-22 20:30:34,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2021-12-22 20:30:34,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2021-12-22 20:30:34,027 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-22 20:30:34,028 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2021-12-22 20:30:34,028 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-22 20:30:34,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2021-12-22 20:30:34,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,033 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,033 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,033 INFO L791 eck$LassoCheckResult]: Stem: 24499#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25353#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24845#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24652#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24653#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24738#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25039#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25161#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25162#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23951#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25099#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24545#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24546#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24452#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24453#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24841#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24194#L1174 assume !(0 == ~M_E~0); 24195#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24046#L1179-1 assume !(0 == ~T2_E~0); 23948#L1184-1 assume !(0 == ~T3_E~0); 23949#L1189-1 assume !(0 == ~T4_E~0); 23987#L1194-1 assume !(0 == ~T5_E~0); 24087#L1199-1 assume !(0 == ~T6_E~0); 24982#L1204-1 assume !(0 == ~T7_E~0); 24901#L1209-1 assume !(0 == ~T8_E~0); 24902#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25290#L1219-1 assume !(0 == ~T10_E~0); 25375#L1224-1 assume !(0 == ~T11_E~0); 24312#L1229-1 assume !(0 == ~T12_E~0); 23873#L1234-1 assume !(0 == ~E_1~0); 23874#L1239-1 assume !(0 == ~E_2~0); 23907#L1244-1 assume !(0 == ~E_3~0); 23908#L1249-1 assume !(0 == ~E_4~0); 24569#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23803#L1259-1 assume !(0 == ~E_6~0); 23758#L1264-1 assume !(0 == ~E_7~0); 23759#L1269-1 assume !(0 == ~E_8~0); 25380#L1274-1 assume !(0 == ~E_9~0); 25315#L1279-1 assume !(0 == ~E_10~0); 23991#L1284-1 assume !(0 == ~E_11~0); 23992#L1289-1 assume !(0 == ~E_12~0); 24621#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24622#L566 assume 1 == ~m_pc~0; 23775#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23776#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24930#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24931#L1455 assume !(0 != activate_threads_~tmp~1#1); 24221#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24222#L585 assume 1 == ~t1_pc~0; 23870#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23871#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24871#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24872#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25340#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25338#L604 assume !(1 == ~t2_pc~0); 24950#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24951#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24484#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24485#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25122#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25123#L623 assume 1 == ~t3_pc~0; 24399#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23739#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24549#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24550#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23772#L642 assume !(1 == ~t4_pc~0); 23773#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24238#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24239#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23844#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23845#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24962#L661 assume 1 == ~t5_pc~0; 24009#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24010#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23971#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23972#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24991#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24992#L680 assume !(1 == ~t6_pc~0); 24432#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24433#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24694#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24695#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25223#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25336#L699 assume 1 == ~t7_pc~0; 24822#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24823#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23999#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24000#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24724#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24623#L718 assume !(1 == ~t8_pc~0); 24624#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23985#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23986#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24027#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24028#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24161#L737 assume 1 == ~t9_pc~0; 25026#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24296#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24897#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24898#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24470#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24471#L756 assume 1 == ~t10_pc~0; 25050#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24716#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23702#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23703#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24278#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24279#L775 assume !(1 == ~t11_pc~0); 24533#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24534#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24155#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23919#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23920#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24106#L794 assume 1 == ~t12_pc~0; 23946#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23924#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25117#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24072#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24073#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24552#L1307 assume !(1 == ~M_E~0); 24553#L1307-2 assume !(1 == ~T1_E~0); 24664#L1312-1 assume !(1 == ~T2_E~0); 24583#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24584#L1322-1 assume !(1 == ~T4_E~0); 24287#L1327-1 assume !(1 == ~T5_E~0); 24288#L1332-1 assume !(1 == ~T6_E~0); 24826#L1337-1 assume !(1 == ~T7_E~0); 24788#L1342-1 assume !(1 == ~T8_E~0); 24789#L1347-1 assume !(1 == ~T9_E~0); 25186#L1352-1 assume !(1 == ~T10_E~0); 25059#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24450#L1362-1 assume !(1 == ~T12_E~0); 24451#L1367-1 assume !(1 == ~E_1~0); 24088#L1372-1 assume !(1 == ~E_2~0); 24089#L1377-1 assume !(1 == ~E_3~0); 24382#L1382-1 assume !(1 == ~E_4~0); 24383#L1387-1 assume !(1 == ~E_5~0); 24952#L1392-1 assume !(1 == ~E_6~0); 24402#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24403#L1402-1 assume !(1 == ~E_8~0); 24099#L1407-1 assume !(1 == ~E_9~0); 24100#L1412-1 assume !(1 == ~E_10~0); 25115#L1417-1 assume !(1 == ~E_11~0); 25116#L1422-1 assume !(1 == ~E_12~0); 25334#L1427-1 assume { :end_inline_reset_delta_events } true; 23903#L1768-2 [2021-12-22 20:30:34,034 INFO L793 eck$LassoCheckResult]: Loop: 23903#L1768-2 assume !false; 23904#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24642#L1149 assume !false; 25014#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25167#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24293#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24199#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24200#L976 assume !(0 != eval_~tmp~0#1); 25333#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25343#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25134#L1174-3 assume !(0 == ~M_E~0); 25127#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24876#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24877#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25060#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24711#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24061#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24062#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24303#L1209-3 assume !(0 == ~T8_E~0); 23723#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23724#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24482#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24483#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24501#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23911#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23912#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24355#L1249-3 assume !(0 == ~E_4~0); 24814#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25286#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24928#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23917#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23918#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25313#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24480#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24481#L1289-3 assume !(0 == ~E_12~0); 24469#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24145#L566-39 assume 1 == ~m_pc~0; 24146#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24748#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24460#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24461#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25003#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25004#L585-39 assume !(1 == ~t1_pc~0); 24153#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24154#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24229#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24230#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25036#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24729#L604-39 assume 1 == ~t2_pc~0; 24730#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24361#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24362#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24779#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24780#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24344#L623-39 assume 1 == ~t3_pc~0; 23740#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23742#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25020#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24196#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24197#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24968#L642-39 assume 1 == ~t4_pc~0; 24539#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24540#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24068#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24069#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25166#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24117#L661-39 assume !(1 == ~t5_pc~0); 23748#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23749#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25109#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25110#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25023#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25024#L680-39 assume 1 == ~t6_pc~0; 23810#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23811#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24953#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24276#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24277#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25291#L699-39 assume 1 == ~t7_pc~0; 24713#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24435#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24436#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25119#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25240#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25238#L718-39 assume 1 == ~t8_pc~0; 24627#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24628#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24560#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24561#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24863#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24832#L737-39 assume 1 == ~t9_pc~0; 24257#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24258#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25314#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25215#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25158#L756-39 assume 1 == ~t10_pc~0; 25159#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24640#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24384#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24385#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24517#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23857#L775-39 assume 1 == ~t11_pc~0; 23858#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24510#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24511#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25373#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24921#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24568#L794-39 assume 1 == ~t12_pc~0; 24260#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24254#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25074#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24975#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23799#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23800#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25267#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25268#L1312-3 assume !(1 == ~T2_E~0); 25379#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24993#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24994#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23938#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23909#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23910#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24656#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24781#L1352-3 assume !(1 == ~T10_E~0); 24782#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25221#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25372#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25363#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23736#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23737#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24368#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24369#L1392-3 assume !(1 == ~E_6~0); 25084#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25330#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24747#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24023#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24024#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24672#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24673#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24033#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24034#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24900#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24752#L1787 assume !(0 == start_simulation_~tmp~3#1); 24753#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25276#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24799#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 24800#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24351#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24352#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 24353#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23903#L1768-2 [2021-12-22 20:30:34,034 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,034 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2021-12-22 20:30:34,034 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,035 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367288992] [2021-12-22 20:30:34,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367288992] [2021-12-22 20:30:34,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367288992] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804083658] [2021-12-22 20:30:34,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,058 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,058 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 1 times [2021-12-22 20:30:34,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,061 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733382304] [2021-12-22 20:30:34,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,063 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,092 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733382304] [2021-12-22 20:30:34,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733382304] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,093 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,093 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [668369459] [2021-12-22 20:30:34,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,094 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,094 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,095 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,115 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2021-12-22 20:30:34,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2021-12-22 20:30:34,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-12-22 20:30:34,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,129 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,129 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2021-12-22 20:30:34,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,130 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-22 20:30:34,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2021-12-22 20:30:34,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2021-12-22 20:30:34,150 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-22 20:30:34,150 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2021-12-22 20:30:34,150 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-22 20:30:34,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2021-12-22 20:30:34,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,164 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,165 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,165 INFO L791 eck$LassoCheckResult]: Stem: 27882#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27883#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28736#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28228#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28035#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28036#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28121#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28422#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28544#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28545#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27333#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27334#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28482#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27928#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27929#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27835#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27836#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28224#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27577#L1174 assume !(0 == ~M_E~0); 27578#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27429#L1179-1 assume !(0 == ~T2_E~0); 27331#L1184-1 assume !(0 == ~T3_E~0); 27332#L1189-1 assume !(0 == ~T4_E~0); 27370#L1194-1 assume !(0 == ~T5_E~0); 27470#L1199-1 assume !(0 == ~T6_E~0); 28365#L1204-1 assume !(0 == ~T7_E~0); 28284#L1209-1 assume !(0 == ~T8_E~0); 28285#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28673#L1219-1 assume !(0 == ~T10_E~0); 28758#L1224-1 assume !(0 == ~T11_E~0); 27695#L1229-1 assume !(0 == ~T12_E~0); 27256#L1234-1 assume !(0 == ~E_1~0); 27257#L1239-1 assume !(0 == ~E_2~0); 27290#L1244-1 assume !(0 == ~E_3~0); 27291#L1249-1 assume !(0 == ~E_4~0); 27952#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27186#L1259-1 assume !(0 == ~E_6~0); 27141#L1264-1 assume !(0 == ~E_7~0); 27142#L1269-1 assume !(0 == ~E_8~0); 28763#L1274-1 assume !(0 == ~E_9~0); 28698#L1279-1 assume !(0 == ~E_10~0); 27374#L1284-1 assume !(0 == ~E_11~0); 27375#L1289-1 assume !(0 == ~E_12~0); 28004#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28005#L566 assume 1 == ~m_pc~0; 27158#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27159#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28313#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28314#L1455 assume !(0 != activate_threads_~tmp~1#1); 27604#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27605#L585 assume 1 == ~t1_pc~0; 27253#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27254#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28254#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28255#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28723#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28721#L604 assume !(1 == ~t2_pc~0); 28333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27867#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27868#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28505#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28506#L623 assume 1 == ~t3_pc~0; 27782#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27122#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27932#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27933#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28540#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27155#L642 assume !(1 == ~t4_pc~0); 27156#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27621#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27622#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27227#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27228#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28345#L661 assume 1 == ~t5_pc~0; 27392#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27393#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27354#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27355#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28375#L680 assume !(1 == ~t6_pc~0); 27815#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27816#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28077#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28078#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28606#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28719#L699 assume 1 == ~t7_pc~0; 28205#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28206#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27382#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27383#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28107#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28006#L718 assume !(1 == ~t8_pc~0); 28007#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27368#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27369#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27410#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27411#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27544#L737 assume 1 == ~t9_pc~0; 28409#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27679#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28280#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28281#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 27853#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27854#L756 assume 1 == ~t10_pc~0; 28433#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28099#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27085#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27086#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27661#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27662#L775 assume !(1 == ~t11_pc~0); 27916#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 27917#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27538#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27302#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27303#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27489#L794 assume 1 == ~t12_pc~0; 27329#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27307#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28500#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27455#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27456#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27935#L1307 assume !(1 == ~M_E~0); 27936#L1307-2 assume !(1 == ~T1_E~0); 28047#L1312-1 assume !(1 == ~T2_E~0); 27966#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27967#L1322-1 assume !(1 == ~T4_E~0); 27670#L1327-1 assume !(1 == ~T5_E~0); 27671#L1332-1 assume !(1 == ~T6_E~0); 28209#L1337-1 assume !(1 == ~T7_E~0); 28171#L1342-1 assume !(1 == ~T8_E~0); 28172#L1347-1 assume !(1 == ~T9_E~0); 28569#L1352-1 assume !(1 == ~T10_E~0); 28442#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27833#L1362-1 assume !(1 == ~T12_E~0); 27834#L1367-1 assume !(1 == ~E_1~0); 27471#L1372-1 assume !(1 == ~E_2~0); 27472#L1377-1 assume !(1 == ~E_3~0); 27765#L1382-1 assume !(1 == ~E_4~0); 27766#L1387-1 assume !(1 == ~E_5~0); 28335#L1392-1 assume !(1 == ~E_6~0); 27785#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27786#L1402-1 assume !(1 == ~E_8~0); 27482#L1407-1 assume !(1 == ~E_9~0); 27483#L1412-1 assume !(1 == ~E_10~0); 28498#L1417-1 assume !(1 == ~E_11~0); 28499#L1422-1 assume !(1 == ~E_12~0); 28717#L1427-1 assume { :end_inline_reset_delta_events } true; 27286#L1768-2 [2021-12-22 20:30:34,165 INFO L793 eck$LassoCheckResult]: Loop: 27286#L1768-2 assume !false; 27287#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28025#L1149 assume !false; 28397#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28550#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27676#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27582#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27583#L976 assume !(0 != eval_~tmp~0#1); 28716#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28726#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28517#L1174-3 assume !(0 == ~M_E~0); 28510#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28259#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28260#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28443#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28094#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27444#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27445#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27686#L1209-3 assume !(0 == ~T8_E~0); 27106#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27107#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27865#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27866#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27884#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27294#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27295#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27738#L1249-3 assume !(0 == ~E_4~0); 28197#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28669#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28311#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27300#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27301#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28696#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27863#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27864#L1289-3 assume !(0 == ~E_12~0); 27852#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27528#L566-39 assume 1 == ~m_pc~0; 27529#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28131#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27843#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27844#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28386#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28387#L585-39 assume !(1 == ~t1_pc~0); 27536#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 27537#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27612#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27613#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28419#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28112#L604-39 assume 1 == ~t2_pc~0; 28113#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27744#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27745#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28162#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28163#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27727#L623-39 assume 1 == ~t3_pc~0; 27123#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27125#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28403#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27579#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27580#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28351#L642-39 assume 1 == ~t4_pc~0; 27922#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27923#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27451#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27452#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28549#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27500#L661-39 assume !(1 == ~t5_pc~0); 27131#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 27132#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28492#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28493#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28406#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28407#L680-39 assume 1 == ~t6_pc~0; 27193#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27194#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28336#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27659#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27660#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28674#L699-39 assume 1 == ~t7_pc~0; 28096#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27818#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27819#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28502#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28623#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28621#L718-39 assume 1 == ~t8_pc~0; 28010#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28011#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27943#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27944#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 28246#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28215#L737-39 assume 1 == ~t9_pc~0; 27640#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27641#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27930#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28697#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28598#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28541#L756-39 assume !(1 == ~t10_pc~0); 28022#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28023#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27767#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27768#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27900#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27240#L775-39 assume 1 == ~t11_pc~0; 27241#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27893#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27894#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28756#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28304#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27951#L794-39 assume !(1 == ~t12_pc~0); 27636#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27637#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28457#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28358#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27182#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27183#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28650#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28651#L1312-3 assume !(1 == ~T2_E~0); 28762#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28376#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28377#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27321#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27292#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27293#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28039#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28164#L1352-3 assume !(1 == ~T10_E~0); 28165#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28604#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28755#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28746#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27119#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27120#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27751#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27752#L1392-3 assume !(1 == ~E_6~0); 28467#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28713#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28130#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27406#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27407#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28055#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28056#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27416#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27417#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28283#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 28135#L1787 assume !(0 == start_simulation_~tmp~3#1); 28136#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28659#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27387#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28182#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 28183#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27734#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27735#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 27736#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27286#L1768-2 [2021-12-22 20:30:34,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,166 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2021-12-22 20:30:34,166 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26542958] [2021-12-22 20:30:34,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,167 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,187 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26542958] [2021-12-22 20:30:34,188 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26542958] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,188 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,188 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,188 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995039848] [2021-12-22 20:30:34,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,189 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 1 times [2021-12-22 20:30:34,189 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698576633] [2021-12-22 20:30:34,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,190 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698576633] [2021-12-22 20:30:34,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698576633] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,237 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,238 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601764492] [2021-12-22 20:30:34,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,239 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,258 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2021-12-22 20:30:34,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2021-12-22 20:30:34,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,272 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-12-22 20:30:34,272 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2021-12-22 20:30:34,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,275 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-22 20:30:34,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2021-12-22 20:30:34,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2021-12-22 20:30:34,294 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-22 20:30:34,295 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2021-12-22 20:30:34,295 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-22 20:30:34,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2021-12-22 20:30:34,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,300 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,300 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,301 INFO L791 eck$LassoCheckResult]: Stem: 31265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 31266#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32119#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31611#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31418#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31419#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31504#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31805#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31927#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31928#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30716#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30717#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31865#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31311#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31312#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31218#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31219#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31607#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30960#L1174 assume !(0 == ~M_E~0); 30961#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30812#L1179-1 assume !(0 == ~T2_E~0); 30714#L1184-1 assume !(0 == ~T3_E~0); 30715#L1189-1 assume !(0 == ~T4_E~0); 30753#L1194-1 assume !(0 == ~T5_E~0); 30853#L1199-1 assume !(0 == ~T6_E~0); 31748#L1204-1 assume !(0 == ~T7_E~0); 31667#L1209-1 assume !(0 == ~T8_E~0); 31668#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32056#L1219-1 assume !(0 == ~T10_E~0); 32141#L1224-1 assume !(0 == ~T11_E~0); 31078#L1229-1 assume !(0 == ~T12_E~0); 30639#L1234-1 assume !(0 == ~E_1~0); 30640#L1239-1 assume !(0 == ~E_2~0); 30673#L1244-1 assume !(0 == ~E_3~0); 30674#L1249-1 assume !(0 == ~E_4~0); 31335#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30569#L1259-1 assume !(0 == ~E_6~0); 30524#L1264-1 assume !(0 == ~E_7~0); 30525#L1269-1 assume !(0 == ~E_8~0); 32146#L1274-1 assume !(0 == ~E_9~0); 32081#L1279-1 assume !(0 == ~E_10~0); 30757#L1284-1 assume !(0 == ~E_11~0); 30758#L1289-1 assume !(0 == ~E_12~0); 31387#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31388#L566 assume 1 == ~m_pc~0; 30541#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30542#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31696#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31697#L1455 assume !(0 != activate_threads_~tmp~1#1); 30987#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30988#L585 assume 1 == ~t1_pc~0; 30636#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30637#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31637#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31638#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32106#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32104#L604 assume !(1 == ~t2_pc~0); 31716#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31717#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31250#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31251#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31888#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31889#L623 assume 1 == ~t3_pc~0; 31165#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30505#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31315#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31316#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31923#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30538#L642 assume !(1 == ~t4_pc~0); 30539#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31004#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31005#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30610#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30611#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31728#L661 assume 1 == ~t5_pc~0; 30775#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30776#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30737#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30738#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31757#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31758#L680 assume !(1 == ~t6_pc~0); 31198#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31199#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31460#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31461#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31989#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32102#L699 assume 1 == ~t7_pc~0; 31588#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31589#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30765#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30766#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31490#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31389#L718 assume !(1 == ~t8_pc~0); 31390#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30751#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30752#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30793#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30794#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30927#L737 assume 1 == ~t9_pc~0; 31792#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31062#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31663#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31664#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31236#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31237#L756 assume 1 == ~t10_pc~0; 31816#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31482#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30468#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30469#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31044#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31045#L775 assume !(1 == ~t11_pc~0); 31299#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31300#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30921#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30685#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30686#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30872#L794 assume 1 == ~t12_pc~0; 30712#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30690#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31883#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30838#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30839#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31318#L1307 assume !(1 == ~M_E~0); 31319#L1307-2 assume !(1 == ~T1_E~0); 31430#L1312-1 assume !(1 == ~T2_E~0); 31349#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31350#L1322-1 assume !(1 == ~T4_E~0); 31053#L1327-1 assume !(1 == ~T5_E~0); 31054#L1332-1 assume !(1 == ~T6_E~0); 31592#L1337-1 assume !(1 == ~T7_E~0); 31554#L1342-1 assume !(1 == ~T8_E~0); 31555#L1347-1 assume !(1 == ~T9_E~0); 31952#L1352-1 assume !(1 == ~T10_E~0); 31825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31216#L1362-1 assume !(1 == ~T12_E~0); 31217#L1367-1 assume !(1 == ~E_1~0); 30854#L1372-1 assume !(1 == ~E_2~0); 30855#L1377-1 assume !(1 == ~E_3~0); 31148#L1382-1 assume !(1 == ~E_4~0); 31149#L1387-1 assume !(1 == ~E_5~0); 31718#L1392-1 assume !(1 == ~E_6~0); 31168#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31169#L1402-1 assume !(1 == ~E_8~0); 30865#L1407-1 assume !(1 == ~E_9~0); 30866#L1412-1 assume !(1 == ~E_10~0); 31881#L1417-1 assume !(1 == ~E_11~0); 31882#L1422-1 assume !(1 == ~E_12~0); 32100#L1427-1 assume { :end_inline_reset_delta_events } true; 30669#L1768-2 [2021-12-22 20:30:34,301 INFO L793 eck$LassoCheckResult]: Loop: 30669#L1768-2 assume !false; 30670#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31408#L1149 assume !false; 31780#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31933#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31059#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30965#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30966#L976 assume !(0 != eval_~tmp~0#1); 32099#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32109#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31900#L1174-3 assume !(0 == ~M_E~0); 31893#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31642#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31643#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31477#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30827#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30828#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31069#L1209-3 assume !(0 == ~T8_E~0); 30489#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30490#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31248#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31249#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31267#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30677#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30678#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31121#L1249-3 assume !(0 == ~E_4~0); 31580#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32052#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31694#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30683#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30684#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32079#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31247#L1289-3 assume !(0 == ~E_12~0); 31235#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30911#L566-39 assume 1 == ~m_pc~0; 30912#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31514#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31226#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31227#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31769#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31770#L585-39 assume !(1 == ~t1_pc~0); 30919#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30920#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30995#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30996#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31802#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31495#L604-39 assume 1 == ~t2_pc~0; 31496#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31127#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31128#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31545#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31546#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31110#L623-39 assume 1 == ~t3_pc~0; 30506#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30508#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31786#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30962#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30963#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31734#L642-39 assume 1 == ~t4_pc~0; 31305#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31306#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30834#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30835#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31932#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30883#L661-39 assume !(1 == ~t5_pc~0); 30514#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 30515#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31875#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31876#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31789#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31790#L680-39 assume 1 == ~t6_pc~0; 30576#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30577#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31719#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31042#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31043#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32057#L699-39 assume 1 == ~t7_pc~0; 31479#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31201#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31202#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31885#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32006#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32004#L718-39 assume 1 == ~t8_pc~0; 31393#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31394#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31326#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31327#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31629#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31598#L737-39 assume !(1 == ~t9_pc~0); 31025#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 31024#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31313#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32080#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31981#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31924#L756-39 assume 1 == ~t10_pc~0; 31925#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31406#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31150#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31151#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31283#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30623#L775-39 assume 1 == ~t11_pc~0; 30624#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31276#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31277#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32139#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31687#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31334#L794-39 assume 1 == ~t12_pc~0; 31026#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31020#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31840#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31741#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30565#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30566#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32033#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32034#L1312-3 assume !(1 == ~T2_E~0); 32145#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31759#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31760#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30704#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30675#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30676#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31422#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31547#L1352-3 assume !(1 == ~T10_E~0); 31548#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31987#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32138#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32129#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30502#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30503#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31134#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31135#L1392-3 assume !(1 == ~E_6~0); 31850#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32096#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31513#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30789#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30790#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31438#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31439#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30799#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30800#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31666#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31518#L1787 assume !(0 == start_simulation_~tmp~3#1); 31519#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32042#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30770#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31565#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31566#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31117#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31118#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 31119#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30669#L1768-2 [2021-12-22 20:30:34,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,302 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2021-12-22 20:30:34,302 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,302 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745282686] [2021-12-22 20:30:34,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,302 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745282686] [2021-12-22 20:30:34,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745282686] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,323 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759890143] [2021-12-22 20:30:34,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,324 INFO L85 PathProgramCache]: Analyzing trace with hash -182660158, now seen corresponding path program 1 times [2021-12-22 20:30:34,324 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054911702] [2021-12-22 20:30:34,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,350 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054911702] [2021-12-22 20:30:34,350 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054911702] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,350 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,351 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,351 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489152494] [2021-12-22 20:30:34,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,351 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,351 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,352 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,352 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,352 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,370 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2021-12-22 20:30:34,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2021-12-22 20:30:34,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-12-22 20:30:34,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2021-12-22 20:30:34,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,384 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-22 20:30:34,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2021-12-22 20:30:34,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2021-12-22 20:30:34,406 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-22 20:30:34,406 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2021-12-22 20:30:34,406 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-22 20:30:34,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2021-12-22 20:30:34,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,411 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,411 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,412 INFO L791 eck$LassoCheckResult]: Stem: 34648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35502#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34996#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34801#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 34802#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34887#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35189#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35310#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35311#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34099#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34100#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35248#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34694#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34695#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34601#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34602#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34991#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34343#L1174 assume !(0 == ~M_E~0); 34344#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34195#L1179-1 assume !(0 == ~T2_E~0); 34097#L1184-1 assume !(0 == ~T3_E~0); 34098#L1189-1 assume !(0 == ~T4_E~0); 34136#L1194-1 assume !(0 == ~T5_E~0); 34236#L1199-1 assume !(0 == ~T6_E~0); 35131#L1204-1 assume !(0 == ~T7_E~0); 35050#L1209-1 assume !(0 == ~T8_E~0); 35051#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35439#L1219-1 assume !(0 == ~T10_E~0); 35524#L1224-1 assume !(0 == ~T11_E~0); 34462#L1229-1 assume !(0 == ~T12_E~0); 34024#L1234-1 assume !(0 == ~E_1~0); 34025#L1239-1 assume !(0 == ~E_2~0); 34058#L1244-1 assume !(0 == ~E_3~0); 34059#L1249-1 assume !(0 == ~E_4~0); 34718#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33952#L1259-1 assume !(0 == ~E_6~0); 33907#L1264-1 assume !(0 == ~E_7~0); 33908#L1269-1 assume !(0 == ~E_8~0); 35529#L1274-1 assume !(0 == ~E_9~0); 35464#L1279-1 assume !(0 == ~E_10~0); 34140#L1284-1 assume !(0 == ~E_11~0); 34141#L1289-1 assume !(0 == ~E_12~0); 34770#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34771#L566 assume 1 == ~m_pc~0; 33924#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33925#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35079#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35080#L1455 assume !(0 != activate_threads_~tmp~1#1); 34370#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34371#L585 assume 1 == ~t1_pc~0; 34019#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34020#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35020#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35021#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35489#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35487#L604 assume !(1 == ~t2_pc~0); 35099#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35100#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34633#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34634#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35273#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35274#L623 assume 1 == ~t3_pc~0; 34548#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33888#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34698#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34699#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35306#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33921#L642 assume !(1 == ~t4_pc~0); 33922#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34387#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34388#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33995#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 33996#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35111#L661 assume 1 == ~t5_pc~0; 34158#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34159#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34120#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34121#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35142#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35143#L680 assume !(1 == ~t6_pc~0); 34581#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34582#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34843#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34844#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35372#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35485#L699 assume 1 == ~t7_pc~0; 34971#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34972#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34148#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34149#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 34873#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34772#L718 assume !(1 == ~t8_pc~0); 34773#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34134#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34135#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34176#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34177#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34310#L737 assume 1 == ~t9_pc~0; 35176#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34445#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35046#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35047#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34619#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34620#L756 assume 1 == ~t10_pc~0; 35199#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34865#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33851#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33852#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34427#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34428#L775 assume !(1 == ~t11_pc~0); 34682#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34683#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34304#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34068#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34069#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34255#L794 assume 1 == ~t12_pc~0; 34096#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34073#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35266#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34223#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34224#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34701#L1307 assume !(1 == ~M_E~0); 34702#L1307-2 assume !(1 == ~T1_E~0); 34813#L1312-1 assume !(1 == ~T2_E~0); 34732#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34733#L1322-1 assume !(1 == ~T4_E~0); 34436#L1327-1 assume !(1 == ~T5_E~0); 34437#L1332-1 assume !(1 == ~T6_E~0); 34975#L1337-1 assume !(1 == ~T7_E~0); 34937#L1342-1 assume !(1 == ~T8_E~0); 34938#L1347-1 assume !(1 == ~T9_E~0); 35335#L1352-1 assume !(1 == ~T10_E~0); 35208#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34599#L1362-1 assume !(1 == ~T12_E~0); 34600#L1367-1 assume !(1 == ~E_1~0); 34237#L1372-1 assume !(1 == ~E_2~0); 34238#L1377-1 assume !(1 == ~E_3~0); 34531#L1382-1 assume !(1 == ~E_4~0); 34532#L1387-1 assume !(1 == ~E_5~0); 35101#L1392-1 assume !(1 == ~E_6~0); 34553#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34554#L1402-1 assume !(1 == ~E_8~0); 34250#L1407-1 assume !(1 == ~E_9~0); 34251#L1412-1 assume !(1 == ~E_10~0); 35264#L1417-1 assume !(1 == ~E_11~0); 35265#L1422-1 assume !(1 == ~E_12~0); 35483#L1427-1 assume { :end_inline_reset_delta_events } true; 34052#L1768-2 [2021-12-22 20:30:34,412 INFO L793 eck$LassoCheckResult]: Loop: 34052#L1768-2 assume !false; 34053#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34793#L1149 assume !false; 35164#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35316#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34442#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34354#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34355#L976 assume !(0 != eval_~tmp~0#1); 35482#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35492#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35283#L1174-3 assume !(0 == ~M_E~0); 35276#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35025#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35026#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35210#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34860#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34213#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34214#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34452#L1209-3 assume !(0 == ~T8_E~0); 33872#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33873#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34631#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34632#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34650#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34060#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34061#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34504#L1249-3 assume !(0 == ~E_4~0); 34963#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35435#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35077#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34066#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34067#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35462#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34629#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34630#L1289-3 assume !(0 == ~E_12~0); 34618#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34294#L566-39 assume 1 == ~m_pc~0; 34295#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34897#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34609#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34610#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35152#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35153#L585-39 assume !(1 == ~t1_pc~0); 34301#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 34302#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34378#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34379#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35185#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34877#L604-39 assume 1 == ~t2_pc~0; 34878#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34510#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34511#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34928#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34929#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34493#L623-39 assume 1 == ~t3_pc~0; 33889#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33891#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35169#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34345#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34346#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35117#L642-39 assume 1 == ~t4_pc~0; 34688#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34689#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34217#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34218#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35315#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34264#L661-39 assume !(1 == ~t5_pc~0); 33897#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 33898#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35258#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35259#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35172#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35173#L680-39 assume 1 == ~t6_pc~0; 33959#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33960#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35102#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34425#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34426#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35440#L699-39 assume 1 == ~t7_pc~0; 34862#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34584#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34585#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35268#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35389#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35387#L718-39 assume 1 == ~t8_pc~0; 34776#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34777#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34709#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34710#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 35011#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34981#L737-39 assume 1 == ~t9_pc~0; 34406#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34407#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34696#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35463#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35364#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35307#L756-39 assume !(1 == ~t10_pc~0); 34788#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 34789#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34533#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34534#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34666#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34006#L775-39 assume 1 == ~t11_pc~0; 34007#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34659#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34660#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35522#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35070#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34717#L794-39 assume !(1 == ~t12_pc~0); 34402#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 34403#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35223#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35124#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33948#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33949#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35416#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35417#L1312-3 assume !(1 == ~T2_E~0); 35528#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35140#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35141#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34087#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34056#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34057#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34805#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34930#L1352-3 assume !(1 == ~T10_E~0); 34931#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35370#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35521#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35512#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33882#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33883#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34517#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34518#L1392-3 assume !(1 == ~E_6~0); 35233#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35479#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34896#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34172#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34173#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 34819#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 34820#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34182#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34183#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35049#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34900#L1787 assume !(0 == start_simulation_~tmp~3#1); 34901#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35425#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34153#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34948#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34949#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34500#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34501#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 34502#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34052#L1768-2 [2021-12-22 20:30:34,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,413 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2021-12-22 20:30:34,413 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367569519] [2021-12-22 20:30:34,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,414 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,460 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367569519] [2021-12-22 20:30:34,460 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367569519] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,460 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269482339] [2021-12-22 20:30:34,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,461 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,461 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 2 times [2021-12-22 20:30:34,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584887206] [2021-12-22 20:30:34,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,462 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,490 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1584887206] [2021-12-22 20:30:34,490 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1584887206] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,490 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,490 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,490 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83726671] [2021-12-22 20:30:34,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,491 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,491 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,492 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,510 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2021-12-22 20:30:34,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2021-12-22 20:30:34,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-12-22 20:30:34,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,522 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2021-12-22 20:30:34,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,524 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-22 20:30:34,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2021-12-22 20:30:34,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2021-12-22 20:30:34,544 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-22 20:30:34,544 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2021-12-22 20:30:34,544 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-12-22 20:30:34,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2021-12-22 20:30:34,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,549 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,549 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,550 INFO L791 eck$LassoCheckResult]: Stem: 38031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 38032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38885#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38379#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38184#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38185#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38270#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38571#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38693#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38694#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37482#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37483#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38631#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38077#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38078#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37984#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 37985#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38374#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37726#L1174 assume !(0 == ~M_E~0); 37727#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37578#L1179-1 assume !(0 == ~T2_E~0); 37480#L1184-1 assume !(0 == ~T3_E~0); 37481#L1189-1 assume !(0 == ~T4_E~0); 37519#L1194-1 assume !(0 == ~T5_E~0); 37619#L1199-1 assume !(0 == ~T6_E~0); 38514#L1204-1 assume !(0 == ~T7_E~0); 38433#L1209-1 assume !(0 == ~T8_E~0); 38434#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38822#L1219-1 assume !(0 == ~T10_E~0); 38907#L1224-1 assume !(0 == ~T11_E~0); 37844#L1229-1 assume !(0 == ~T12_E~0); 37405#L1234-1 assume !(0 == ~E_1~0); 37406#L1239-1 assume !(0 == ~E_2~0); 37441#L1244-1 assume !(0 == ~E_3~0); 37442#L1249-1 assume !(0 == ~E_4~0); 38101#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37335#L1259-1 assume !(0 == ~E_6~0); 37290#L1264-1 assume !(0 == ~E_7~0); 37291#L1269-1 assume !(0 == ~E_8~0); 38912#L1274-1 assume !(0 == ~E_9~0); 38847#L1279-1 assume !(0 == ~E_10~0); 37523#L1284-1 assume !(0 == ~E_11~0); 37524#L1289-1 assume !(0 == ~E_12~0); 38153#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38154#L566 assume 1 == ~m_pc~0; 37307#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37308#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38462#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38463#L1455 assume !(0 != activate_threads_~tmp~1#1); 37753#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37754#L585 assume 1 == ~t1_pc~0; 37402#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37403#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38403#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38404#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38872#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38870#L604 assume !(1 == ~t2_pc~0); 38482#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38483#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38016#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38017#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38654#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38655#L623 assume 1 == ~t3_pc~0; 37931#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37271#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38081#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38082#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38689#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37304#L642 assume !(1 == ~t4_pc~0); 37305#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37770#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37771#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37377#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38494#L661 assume 1 == ~t5_pc~0; 37541#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37542#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37503#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37504#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38525#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38526#L680 assume !(1 == ~t6_pc~0); 37964#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37965#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38226#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38227#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38755#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38868#L699 assume 1 == ~t7_pc~0; 38354#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38355#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37531#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37532#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38256#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38155#L718 assume !(1 == ~t8_pc~0); 38156#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37517#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37518#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37559#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37560#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37693#L737 assume 1 == ~t9_pc~0; 38558#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37828#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38429#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38430#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38002#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38003#L756 assume 1 == ~t10_pc~0; 38582#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37234#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37235#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37810#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37811#L775 assume !(1 == ~t11_pc~0); 38065#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38066#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37687#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37451#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37452#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37638#L794 assume 1 == ~t12_pc~0; 37479#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37456#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38649#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37604#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37605#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38084#L1307 assume !(1 == ~M_E~0); 38085#L1307-2 assume !(1 == ~T1_E~0); 38196#L1312-1 assume !(1 == ~T2_E~0); 38115#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38116#L1322-1 assume !(1 == ~T4_E~0); 37819#L1327-1 assume !(1 == ~T5_E~0); 37820#L1332-1 assume !(1 == ~T6_E~0); 38358#L1337-1 assume !(1 == ~T7_E~0); 38320#L1342-1 assume !(1 == ~T8_E~0); 38321#L1347-1 assume !(1 == ~T9_E~0); 38718#L1352-1 assume !(1 == ~T10_E~0); 38591#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37982#L1362-1 assume !(1 == ~T12_E~0); 37983#L1367-1 assume !(1 == ~E_1~0); 37620#L1372-1 assume !(1 == ~E_2~0); 37621#L1377-1 assume !(1 == ~E_3~0); 37914#L1382-1 assume !(1 == ~E_4~0); 37915#L1387-1 assume !(1 == ~E_5~0); 38484#L1392-1 assume !(1 == ~E_6~0); 37934#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37935#L1402-1 assume !(1 == ~E_8~0); 37631#L1407-1 assume !(1 == ~E_9~0); 37632#L1412-1 assume !(1 == ~E_10~0); 38647#L1417-1 assume !(1 == ~E_11~0); 38648#L1422-1 assume !(1 == ~E_12~0); 38866#L1427-1 assume { :end_inline_reset_delta_events } true; 37435#L1768-2 [2021-12-22 20:30:34,550 INFO L793 eck$LassoCheckResult]: Loop: 37435#L1768-2 assume !false; 37436#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38174#L1149 assume !false; 38546#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38699#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37825#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37731#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37732#L976 assume !(0 != eval_~tmp~0#1); 38865#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38875#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38666#L1174-3 assume !(0 == ~M_E~0); 38659#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38408#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38409#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38593#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37596#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37597#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37835#L1209-3 assume !(0 == ~T8_E~0); 37255#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37256#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38014#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38015#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38033#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37443#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37444#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37887#L1249-3 assume !(0 == ~E_4~0); 38346#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38818#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38460#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37449#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37450#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38845#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38012#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38013#L1289-3 assume !(0 == ~E_12~0); 38001#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37677#L566-39 assume 1 == ~m_pc~0; 37678#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38280#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37992#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37993#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38535#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38536#L585-39 assume !(1 == ~t1_pc~0); 37685#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37686#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37761#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37762#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38261#L604-39 assume 1 == ~t2_pc~0; 38262#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37893#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37894#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38313#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38314#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37876#L623-39 assume 1 == ~t3_pc~0; 37274#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37276#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38552#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37728#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37729#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38500#L642-39 assume 1 == ~t4_pc~0; 38073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37600#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37601#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38698#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37651#L661-39 assume !(1 == ~t5_pc~0); 37280#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37281#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38641#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38642#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38555#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38556#L680-39 assume 1 == ~t6_pc~0; 37344#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37345#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38485#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37808#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37809#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38823#L699-39 assume 1 == ~t7_pc~0; 38245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37967#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37968#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38651#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38772#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38770#L718-39 assume 1 == ~t8_pc~0; 38160#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38161#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38092#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38093#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38394#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38363#L737-39 assume 1 == ~t9_pc~0; 37789#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37790#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38079#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38846#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38747#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38690#L756-39 assume 1 == ~t10_pc~0; 38691#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38169#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37916#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37917#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38049#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37389#L775-39 assume 1 == ~t11_pc~0; 37390#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38042#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38043#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38905#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38453#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38100#L794-39 assume 1 == ~t12_pc~0; 37792#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37786#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38606#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38507#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37331#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37332#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38799#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38800#L1312-3 assume !(1 == ~T2_E~0); 38911#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38523#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38524#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37468#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37439#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37440#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38188#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38311#L1352-3 assume !(1 == ~T10_E~0); 38312#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38752#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38904#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38895#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37265#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37266#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37900#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37901#L1392-3 assume !(1 == ~E_6~0); 38616#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38862#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38279#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37555#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37556#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38202#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38203#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37565#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37566#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38432#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 38283#L1787 assume !(0 == start_simulation_~tmp~3#1); 38284#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38808#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37536#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38331#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 38332#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37883#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37884#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 37885#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37435#L1768-2 [2021-12-22 20:30:34,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2021-12-22 20:30:34,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092286865] [2021-12-22 20:30:34,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092286865] [2021-12-22 20:30:34,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092286865] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,572 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698352195] [2021-12-22 20:30:34,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,573 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,574 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 2 times [2021-12-22 20:30:34,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,574 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682329798] [2021-12-22 20:30:34,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,601 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682329798] [2021-12-22 20:30:34,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682329798] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,601 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,602 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925636428] [2021-12-22 20:30:34,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,602 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,602 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,603 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,621 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2021-12-22 20:30:34,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2021-12-22 20:30:34,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-12-22 20:30:34,631 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2021-12-22 20:30:34,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,633 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-22 20:30:34,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2021-12-22 20:30:34,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2021-12-22 20:30:34,652 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-22 20:30:34,652 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2021-12-22 20:30:34,653 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-12-22 20:30:34,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2021-12-22 20:30:34,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,658 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,658 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,659 INFO L791 eck$LassoCheckResult]: Stem: 41414#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 42268#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41760#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41567#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41568#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41653#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41954#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42076#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42077#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40865#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40866#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42014#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41460#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41461#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41367#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41368#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 41756#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41109#L1174 assume !(0 == ~M_E~0); 41110#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40961#L1179-1 assume !(0 == ~T2_E~0); 40863#L1184-1 assume !(0 == ~T3_E~0); 40864#L1189-1 assume !(0 == ~T4_E~0); 40902#L1194-1 assume !(0 == ~T5_E~0); 41002#L1199-1 assume !(0 == ~T6_E~0); 41897#L1204-1 assume !(0 == ~T7_E~0); 41816#L1209-1 assume !(0 == ~T8_E~0); 41817#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42205#L1219-1 assume !(0 == ~T10_E~0); 42290#L1224-1 assume !(0 == ~T11_E~0); 41227#L1229-1 assume !(0 == ~T12_E~0); 40788#L1234-1 assume !(0 == ~E_1~0); 40789#L1239-1 assume !(0 == ~E_2~0); 40822#L1244-1 assume !(0 == ~E_3~0); 40823#L1249-1 assume !(0 == ~E_4~0); 41484#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 40718#L1259-1 assume !(0 == ~E_6~0); 40673#L1264-1 assume !(0 == ~E_7~0); 40674#L1269-1 assume !(0 == ~E_8~0); 42295#L1274-1 assume !(0 == ~E_9~0); 42230#L1279-1 assume !(0 == ~E_10~0); 40906#L1284-1 assume !(0 == ~E_11~0); 40907#L1289-1 assume !(0 == ~E_12~0); 41536#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41537#L566 assume 1 == ~m_pc~0; 40690#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 40691#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41845#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41846#L1455 assume !(0 != activate_threads_~tmp~1#1); 41136#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41137#L585 assume 1 == ~t1_pc~0; 40785#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40786#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41786#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41787#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42255#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42253#L604 assume !(1 == ~t2_pc~0); 41865#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41866#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41399#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41400#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42037#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42038#L623 assume 1 == ~t3_pc~0; 41314#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40654#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41464#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41465#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42072#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40687#L642 assume !(1 == ~t4_pc~0); 40688#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41153#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41154#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40759#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 40760#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41877#L661 assume 1 == ~t5_pc~0; 40924#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40925#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40886#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40887#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 41906#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41907#L680 assume !(1 == ~t6_pc~0); 41347#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41348#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41609#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41610#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42138#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42251#L699 assume 1 == ~t7_pc~0; 41737#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41738#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40914#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40915#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41639#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41538#L718 assume !(1 == ~t8_pc~0); 41539#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40900#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40901#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40942#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 40943#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41076#L737 assume 1 == ~t9_pc~0; 41941#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41211#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41812#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41813#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41385#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41386#L756 assume 1 == ~t10_pc~0; 41965#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41631#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40617#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40618#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41193#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41194#L775 assume !(1 == ~t11_pc~0); 41448#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41449#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41070#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40834#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40835#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41021#L794 assume 1 == ~t12_pc~0; 40861#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40839#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42032#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40987#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 40988#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41467#L1307 assume !(1 == ~M_E~0); 41468#L1307-2 assume !(1 == ~T1_E~0); 41579#L1312-1 assume !(1 == ~T2_E~0); 41498#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41499#L1322-1 assume !(1 == ~T4_E~0); 41202#L1327-1 assume !(1 == ~T5_E~0); 41203#L1332-1 assume !(1 == ~T6_E~0); 41741#L1337-1 assume !(1 == ~T7_E~0); 41703#L1342-1 assume !(1 == ~T8_E~0); 41704#L1347-1 assume !(1 == ~T9_E~0); 42101#L1352-1 assume !(1 == ~T10_E~0); 41974#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41365#L1362-1 assume !(1 == ~T12_E~0); 41366#L1367-1 assume !(1 == ~E_1~0); 41003#L1372-1 assume !(1 == ~E_2~0); 41004#L1377-1 assume !(1 == ~E_3~0); 41297#L1382-1 assume !(1 == ~E_4~0); 41298#L1387-1 assume !(1 == ~E_5~0); 41867#L1392-1 assume !(1 == ~E_6~0); 41317#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41318#L1402-1 assume !(1 == ~E_8~0); 41014#L1407-1 assume !(1 == ~E_9~0); 41015#L1412-1 assume !(1 == ~E_10~0); 42030#L1417-1 assume !(1 == ~E_11~0); 42031#L1422-1 assume !(1 == ~E_12~0); 42249#L1427-1 assume { :end_inline_reset_delta_events } true; 40818#L1768-2 [2021-12-22 20:30:34,659 INFO L793 eck$LassoCheckResult]: Loop: 40818#L1768-2 assume !false; 40819#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41557#L1149 assume !false; 41929#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42082#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41208#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41114#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 41115#L976 assume !(0 != eval_~tmp~0#1); 42248#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42258#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42049#L1174-3 assume !(0 == ~M_E~0); 42042#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41791#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41792#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41975#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41626#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40976#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40977#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41218#L1209-3 assume !(0 == ~T8_E~0); 40638#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40639#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41397#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41398#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41416#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40826#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40827#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41270#L1249-3 assume !(0 == ~E_4~0); 41729#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42201#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41843#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40832#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 40833#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42228#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41395#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41396#L1289-3 assume !(0 == ~E_12~0); 41384#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41060#L566-39 assume 1 == ~m_pc~0; 41061#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41663#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41375#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41376#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41918#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41919#L585-39 assume !(1 == ~t1_pc~0); 41068#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 41069#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41144#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41145#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41951#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41644#L604-39 assume 1 == ~t2_pc~0; 41645#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41276#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41277#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41694#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41695#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41259#L623-39 assume !(1 == ~t3_pc~0); 40656#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 40657#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41935#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41111#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41112#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41883#L642-39 assume !(1 == ~t4_pc~0); 41456#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41455#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40983#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40984#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42081#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41032#L661-39 assume !(1 == ~t5_pc~0); 40663#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 40664#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42024#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42025#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41938#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41939#L680-39 assume 1 == ~t6_pc~0; 40725#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40726#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41868#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41191#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41192#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42206#L699-39 assume 1 == ~t7_pc~0; 41628#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41350#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41351#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42034#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42155#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42153#L718-39 assume 1 == ~t8_pc~0; 41542#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41543#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41475#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41476#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 41778#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41747#L737-39 assume 1 == ~t9_pc~0; 41172#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41173#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41462#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42229#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42130#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42073#L756-39 assume !(1 == ~t10_pc~0); 41554#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41555#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41299#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41300#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41432#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40772#L775-39 assume 1 == ~t11_pc~0; 40773#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41425#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41426#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42288#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41836#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41483#L794-39 assume !(1 == ~t12_pc~0); 41168#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 41169#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41989#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41890#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40714#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40715#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42182#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42183#L1312-3 assume !(1 == ~T2_E~0); 42294#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41908#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41909#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40853#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40824#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40825#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41571#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41696#L1352-3 assume !(1 == ~T10_E~0); 41697#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42136#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42287#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42278#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40651#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40652#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41283#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41284#L1392-3 assume !(1 == ~E_6~0); 41999#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42245#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41662#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40938#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40939#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41587#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41588#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40948#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40949#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41815#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41667#L1787 assume !(0 == start_simulation_~tmp~3#1); 41668#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42191#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40919#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41714#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 41715#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41266#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41267#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 41268#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 40818#L1768-2 [2021-12-22 20:30:34,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,660 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2021-12-22 20:30:34,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803532855] [2021-12-22 20:30:34,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,660 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,683 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803532855] [2021-12-22 20:30:34,683 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803532855] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,683 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,683 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-22 20:30:34,683 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088517229] [2021-12-22 20:30:34,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,684 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,684 INFO L85 PathProgramCache]: Analyzing trace with hash 1824468511, now seen corresponding path program 1 times [2021-12-22 20:30:34,684 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539190080] [2021-12-22 20:30:34,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,685 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,710 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539190080] [2021-12-22 20:30:34,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539190080] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,710 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,711 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204300398] [2021-12-22 20:30:34,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,711 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,711 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:34,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:34,712 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,731 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2021-12-22 20:30:34,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:34,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2488 transitions. [2021-12-22 20:30:34,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-12-22 20:30:34,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2021-12-22 20:30:34,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2021-12-22 20:30:34,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2488 transitions. [2021-12-22 20:30:34,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,743 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-12-22 20:30:34,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2488 transitions. [2021-12-22 20:30:34,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2021-12-22 20:30:34,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2488 transitions. [2021-12-22 20:30:34,795 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-12-22 20:30:34,795 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2021-12-22 20:30:34,795 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-12-22 20:30:34,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2488 transitions. [2021-12-22 20:30:34,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2021-12-22 20:30:34,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,800 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,800 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,800 INFO L791 eck$LassoCheckResult]: Stem: 44797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45651#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45143#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44950#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 44951#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45036#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45337#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45459#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45460#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44248#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44249#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45397#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44843#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44844#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44750#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44751#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45139#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44492#L1174 assume !(0 == ~M_E~0); 44493#L1174-2 assume !(0 == ~T1_E~0); 44344#L1179-1 assume !(0 == ~T2_E~0); 44246#L1184-1 assume !(0 == ~T3_E~0); 44247#L1189-1 assume !(0 == ~T4_E~0); 44285#L1194-1 assume !(0 == ~T5_E~0); 44385#L1199-1 assume !(0 == ~T6_E~0); 45280#L1204-1 assume !(0 == ~T7_E~0); 45199#L1209-1 assume !(0 == ~T8_E~0); 45200#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45588#L1219-1 assume !(0 == ~T10_E~0); 45673#L1224-1 assume !(0 == ~T11_E~0); 44610#L1229-1 assume !(0 == ~T12_E~0); 44171#L1234-1 assume !(0 == ~E_1~0); 44172#L1239-1 assume !(0 == ~E_2~0); 44205#L1244-1 assume !(0 == ~E_3~0); 44206#L1249-1 assume !(0 == ~E_4~0); 44867#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44101#L1259-1 assume !(0 == ~E_6~0); 44056#L1264-1 assume !(0 == ~E_7~0); 44057#L1269-1 assume !(0 == ~E_8~0); 45678#L1274-1 assume !(0 == ~E_9~0); 45613#L1279-1 assume !(0 == ~E_10~0); 44289#L1284-1 assume !(0 == ~E_11~0); 44290#L1289-1 assume !(0 == ~E_12~0); 44919#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44920#L566 assume 1 == ~m_pc~0; 44073#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44074#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45228#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45229#L1455 assume !(0 != activate_threads_~tmp~1#1); 44519#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44520#L585 assume 1 == ~t1_pc~0; 44168#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44169#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45169#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45170#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45638#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45636#L604 assume !(1 == ~t2_pc~0); 45248#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45249#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44782#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44783#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45420#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45421#L623 assume 1 == ~t3_pc~0; 44697#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44037#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44847#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44848#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45455#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44070#L642 assume !(1 == ~t4_pc~0); 44071#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44536#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44537#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44142#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44143#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45260#L661 assume 1 == ~t5_pc~0; 44307#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44308#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44269#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44270#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45289#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45290#L680 assume !(1 == ~t6_pc~0); 44730#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44731#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44992#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44993#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45521#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45634#L699 assume 1 == ~t7_pc~0; 45120#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45121#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44297#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44298#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45022#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44921#L718 assume !(1 == ~t8_pc~0); 44922#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44283#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44284#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44325#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44326#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44459#L737 assume 1 == ~t9_pc~0; 45324#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44594#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45195#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45196#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 44768#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44769#L756 assume 1 == ~t10_pc~0; 45348#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45014#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44000#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44001#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44576#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44577#L775 assume !(1 == ~t11_pc~0); 44831#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 44832#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44453#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44217#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44218#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44404#L794 assume 1 == ~t12_pc~0; 44244#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44222#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45415#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44370#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44371#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44850#L1307 assume !(1 == ~M_E~0); 44851#L1307-2 assume !(1 == ~T1_E~0); 44962#L1312-1 assume !(1 == ~T2_E~0); 44881#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44882#L1322-1 assume !(1 == ~T4_E~0); 44585#L1327-1 assume !(1 == ~T5_E~0); 44586#L1332-1 assume !(1 == ~T6_E~0); 45124#L1337-1 assume !(1 == ~T7_E~0); 45086#L1342-1 assume !(1 == ~T8_E~0); 45087#L1347-1 assume !(1 == ~T9_E~0); 45484#L1352-1 assume !(1 == ~T10_E~0); 45357#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44748#L1362-1 assume !(1 == ~T12_E~0); 44749#L1367-1 assume !(1 == ~E_1~0); 44386#L1372-1 assume !(1 == ~E_2~0); 44387#L1377-1 assume !(1 == ~E_3~0); 44680#L1382-1 assume !(1 == ~E_4~0); 44681#L1387-1 assume !(1 == ~E_5~0); 45250#L1392-1 assume !(1 == ~E_6~0); 44700#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44701#L1402-1 assume !(1 == ~E_8~0); 44397#L1407-1 assume !(1 == ~E_9~0); 44398#L1412-1 assume !(1 == ~E_10~0); 45413#L1417-1 assume !(1 == ~E_11~0); 45414#L1422-1 assume !(1 == ~E_12~0); 45632#L1427-1 assume { :end_inline_reset_delta_events } true; 44201#L1768-2 [2021-12-22 20:30:34,801 INFO L793 eck$LassoCheckResult]: Loop: 44201#L1768-2 assume !false; 44202#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44940#L1149 assume !false; 45312#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45465#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44591#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44497#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44498#L976 assume !(0 != eval_~tmp~0#1); 45631#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45641#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45432#L1174-3 assume !(0 == ~M_E~0); 45425#L1174-5 assume !(0 == ~T1_E~0); 45174#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45175#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45358#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45009#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44359#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44360#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44601#L1209-3 assume !(0 == ~T8_E~0); 44021#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44022#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44780#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44781#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44799#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44209#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44210#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44653#L1249-3 assume !(0 == ~E_4~0); 45112#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45584#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45226#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44215#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44216#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45611#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44778#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44779#L1289-3 assume !(0 == ~E_12~0); 44767#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44443#L566-39 assume 1 == ~m_pc~0; 44444#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45046#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44758#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44759#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45301#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45302#L585-39 assume !(1 == ~t1_pc~0); 44451#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44452#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44527#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44528#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45334#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45027#L604-39 assume 1 == ~t2_pc~0; 45028#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44659#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44660#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45077#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45078#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44642#L623-39 assume 1 == ~t3_pc~0; 44038#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44040#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45318#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44494#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44495#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45266#L642-39 assume 1 == ~t4_pc~0; 44837#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44838#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44366#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44367#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45464#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44415#L661-39 assume 1 == ~t5_pc~0; 44416#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44047#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45407#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45408#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45321#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45322#L680-39 assume 1 == ~t6_pc~0; 44108#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44109#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45251#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44574#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44575#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45589#L699-39 assume 1 == ~t7_pc~0; 45011#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44733#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44734#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45538#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45536#L718-39 assume 1 == ~t8_pc~0; 44925#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44926#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44858#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44859#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 45161#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45130#L737-39 assume 1 == ~t9_pc~0; 44555#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44556#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44845#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45612#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45513#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45456#L756-39 assume 1 == ~t10_pc~0; 45457#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44938#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44682#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44683#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44815#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44155#L775-39 assume 1 == ~t11_pc~0; 44156#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44808#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44809#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45671#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45219#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44866#L794-39 assume !(1 == ~t12_pc~0); 44551#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 44552#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45372#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45273#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44097#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44098#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45565#L1307-5 assume !(1 == ~T1_E~0); 45566#L1312-3 assume !(1 == ~T2_E~0); 45677#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45291#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45292#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44236#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44207#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44208#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44954#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45079#L1352-3 assume !(1 == ~T10_E~0); 45080#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45519#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45670#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45661#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44034#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44035#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44666#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44667#L1392-3 assume !(1 == ~E_6~0); 45382#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45628#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45045#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44321#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44322#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44970#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44971#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44331#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44332#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45198#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 45050#L1787 assume !(0 == start_simulation_~tmp~3#1); 45051#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45574#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44302#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45097#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 45098#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44649#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44650#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 44651#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44201#L1768-2 [2021-12-22 20:30:34,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2021-12-22 20:30:34,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,802 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401061376] [2021-12-22 20:30:34,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,802 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,827 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401061376] [2021-12-22 20:30:34,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401061376] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,828 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,828 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,828 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357635267] [2021-12-22 20:30:34,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,828 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:34,829 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,829 INFO L85 PathProgramCache]: Analyzing trace with hash 599109159, now seen corresponding path program 1 times [2021-12-22 20:30:34,829 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,829 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97772047] [2021-12-22 20:30:34,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:34,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:34,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:34,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:34,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97772047] [2021-12-22 20:30:34,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97772047] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:34,853 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:34,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:34,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203014635] [2021-12-22 20:30:34,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:34,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:34,854 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:34,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:34,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:34,855 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:34,927 INFO L93 Difference]: Finished difference Result 3238 states and 4766 transitions. [2021-12-22 20:30:34,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:34,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3238 states and 4766 transitions. [2021-12-22 20:30:34,937 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2021-12-22 20:30:34,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3238 states to 3238 states and 4766 transitions. [2021-12-22 20:30:34,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3238 [2021-12-22 20:30:34,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3238 [2021-12-22 20:30:34,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3238 states and 4766 transitions. [2021-12-22 20:30:34,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:34,948 INFO L681 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2021-12-22 20:30:34,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3238 states and 4766 transitions. [2021-12-22 20:30:34,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3238 to 3238. [2021-12-22 20:30:34,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:34,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3238 states to 3238 states and 4766 transitions. [2021-12-22 20:30:34,987 INFO L704 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2021-12-22 20:30:34,987 INFO L587 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2021-12-22 20:30:34,987 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-12-22 20:30:34,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3238 states and 4766 transitions. [2021-12-22 20:30:34,993 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2021-12-22 20:30:34,993 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:34,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:34,995 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,995 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:34,995 INFO L791 eck$LassoCheckResult]: Stem: 49736#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50664#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50089#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49890#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 49891#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49977#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50295#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50432#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50433#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49185#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49186#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50362#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49782#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49783#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49688#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49689#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50085#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49429#L1174 assume !(0 == ~M_E~0); 49430#L1174-2 assume !(0 == ~T1_E~0); 49281#L1179-1 assume !(0 == ~T2_E~0); 49183#L1184-1 assume !(0 == ~T3_E~0); 49184#L1189-1 assume !(0 == ~T4_E~0); 49222#L1194-1 assume !(0 == ~T5_E~0); 49322#L1199-1 assume !(0 == ~T6_E~0); 50234#L1204-1 assume !(0 == ~T7_E~0); 50146#L1209-1 assume !(0 == ~T8_E~0); 50147#L1214-1 assume !(0 == ~T9_E~0); 50577#L1219-1 assume !(0 == ~T10_E~0); 50697#L1224-1 assume !(0 == ~T11_E~0); 49547#L1229-1 assume !(0 == ~T12_E~0); 49108#L1234-1 assume !(0 == ~E_1~0); 49109#L1239-1 assume !(0 == ~E_2~0); 49142#L1244-1 assume !(0 == ~E_3~0); 49143#L1249-1 assume !(0 == ~E_4~0); 49807#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49038#L1259-1 assume !(0 == ~E_6~0); 48992#L1264-1 assume !(0 == ~E_7~0); 48993#L1269-1 assume !(0 == ~E_8~0); 50710#L1274-1 assume !(0 == ~E_9~0); 50612#L1279-1 assume !(0 == ~E_10~0); 49226#L1284-1 assume !(0 == ~E_11~0); 49227#L1289-1 assume !(0 == ~E_12~0); 49859#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49860#L566 assume 1 == ~m_pc~0; 49009#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49010#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50177#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50178#L1455 assume !(0 != activate_threads_~tmp~1#1); 49456#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49457#L585 assume 1 == ~t1_pc~0; 49105#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49106#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50115#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50116#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 50640#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50638#L604 assume !(1 == ~t2_pc~0); 50197#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50198#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49720#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49721#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50388#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50389#L623 assume 1 == ~t3_pc~0; 49634#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48973#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49786#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49787#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50428#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49006#L642 assume !(1 == ~t4_pc~0); 49007#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49473#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49474#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49079#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49080#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50212#L661 assume 1 == ~t5_pc~0; 49244#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49245#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49206#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49207#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50243#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50244#L680 assume !(1 == ~t6_pc~0); 49667#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49668#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49932#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49933#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50501#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50636#L699 assume 1 == ~t7_pc~0; 50065#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50066#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49234#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49235#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 49963#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49861#L718 assume !(1 == ~t8_pc~0); 49862#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49220#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49221#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49262#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49263#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49396#L737 assume 1 == ~t9_pc~0; 50280#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49531#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50141#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50142#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 49706#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49707#L756 assume 1 == ~t10_pc~0; 50307#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49955#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48936#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48937#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49513#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49514#L775 assume !(1 == ~t11_pc~0); 49770#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 49771#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49390#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49154#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49155#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49341#L794 assume 1 == ~t12_pc~0; 49181#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49159#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50383#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49307#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49308#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49789#L1307 assume !(1 == ~M_E~0); 49790#L1307-2 assume !(1 == ~T1_E~0); 49902#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50663#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51311#L1322-1 assume !(1 == ~T4_E~0); 51310#L1327-1 assume !(1 == ~T5_E~0); 51306#L1332-1 assume !(1 == ~T6_E~0); 51305#L1337-1 assume !(1 == ~T7_E~0); 51304#L1342-1 assume !(1 == ~T8_E~0); 51303#L1347-1 assume !(1 == ~T9_E~0); 50460#L1352-1 assume !(1 == ~T10_E~0); 50461#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49686#L1362-1 assume !(1 == ~T12_E~0); 49687#L1367-1 assume !(1 == ~E_1~0); 51166#L1372-1 assume !(1 == ~E_2~0); 50805#L1377-1 assume !(1 == ~E_3~0); 50792#L1382-1 assume !(1 == ~E_4~0); 50790#L1387-1 assume !(1 == ~E_5~0); 50788#L1392-1 assume !(1 == ~E_6~0); 50786#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50784#L1402-1 assume !(1 == ~E_8~0); 50783#L1407-1 assume !(1 == ~E_9~0); 50780#L1412-1 assume !(1 == ~E_10~0); 50778#L1417-1 assume !(1 == ~E_11~0); 50769#L1422-1 assume !(1 == ~E_12~0); 50756#L1427-1 assume { :end_inline_reset_delta_events } true; 50752#L1768-2 [2021-12-22 20:30:34,996 INFO L793 eck$LassoCheckResult]: Loop: 50752#L1768-2 assume !false; 50747#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50744#L1149 assume !false; 50743#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50735#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50729#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50728#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50727#L976 assume !(0 != eval_~tmp~0#1); 50656#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50657#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50726#L1174-3 assume !(0 == ~M_E~0); 50725#L1174-5 assume !(0 == ~T1_E~0); 50723#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50724#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52061#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49950#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49296#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49297#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49538#L1209-3 assume !(0 == ~T8_E~0); 48957#L1214-3 assume !(0 == ~T9_E~0); 48958#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49718#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49719#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49738#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49146#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49147#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49590#L1249-3 assume !(0 == ~E_4~0); 50056#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50573#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50175#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49152#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49153#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50609#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49716#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49717#L1289-3 assume !(0 == ~E_12~0); 49705#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49380#L566-39 assume 1 == ~m_pc~0; 49381#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49987#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49696#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49697#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50255#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50256#L585-39 assume !(1 == ~t1_pc~0); 49388#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 49389#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49464#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49465#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50292#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49968#L604-39 assume 1 == ~t2_pc~0; 49969#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49596#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49597#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50019#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50020#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49579#L623-39 assume 1 == ~t3_pc~0; 48974#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48976#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50274#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49431#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49432#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50218#L642-39 assume 1 == ~t4_pc~0; 49776#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49777#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49303#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49304#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50437#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49352#L661-39 assume !(1 == ~t5_pc~0); 48982#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 48983#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50375#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50376#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50277#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50278#L680-39 assume 1 == ~t6_pc~0; 49045#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49046#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50200#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49511#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49512#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50578#L699-39 assume 1 == ~t7_pc~0; 49952#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49670#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49671#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50385#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50522#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50523#L718-39 assume 1 == ~t8_pc~0; 51540#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51538#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51535#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51533#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 51531#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51529#L737-39 assume 1 == ~t9_pc~0; 51526#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51525#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51524#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51523#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51522#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51521#L756-39 assume 1 == ~t10_pc~0; 51520#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51518#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51517#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51514#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51513#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49092#L775-39 assume 1 == ~t11_pc~0; 49093#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51346#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51343#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51341#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51340#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51339#L794-39 assume !(1 == ~t12_pc~0); 51336#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 50335#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50336#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50226#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49034#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49035#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50552#L1307-5 assume !(1 == ~T1_E~0); 50553#L1312-3 assume !(1 == ~T2_E~0); 50708#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50709#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51319#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51318#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51316#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51314#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50371#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50021#L1352-3 assume !(1 == ~T10_E~0); 50022#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50498#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50721#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50682#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48970#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48971#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49603#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49604#L1392-3 assume !(1 == ~E_6~0); 50346#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50628#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49986#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49258#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49259#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49910#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 49911#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49268#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49269#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50144#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 50145#L1787 assume !(0 == start_simulation_~tmp~3#1); 50654#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 50655#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 50791#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 50789#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 50787#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50785#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50770#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 50757#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 50752#L1768-2 [2021-12-22 20:30:34,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:34,996 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2021-12-22 20:30:34,996 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:34,996 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888608525] [2021-12-22 20:30:34,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:34,997 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:35,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:35,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:35,020 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:35,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888608525] [2021-12-22 20:30:35,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888608525] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:35,020 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:35,020 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:35,020 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171657431] [2021-12-22 20:30:35,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:35,021 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:35,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:35,021 INFO L85 PathProgramCache]: Analyzing trace with hash 1884496008, now seen corresponding path program 1 times [2021-12-22 20:30:35,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:35,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882336476] [2021-12-22 20:30:35,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:35,022 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:35,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:35,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:35,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:35,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882336476] [2021-12-22 20:30:35,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882336476] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:35,047 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:35,047 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:35,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118800692] [2021-12-22 20:30:35,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:35,047 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:35,047 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:35,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:35,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:35,048 INFO L87 Difference]: Start difference. First operand 3238 states and 4766 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:35,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:35,164 INFO L93 Difference]: Finished difference Result 6132 states and 9017 transitions. [2021-12-22 20:30:35,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:35,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6132 states and 9017 transitions. [2021-12-22 20:30:35,242 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2021-12-22 20:30:35,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6132 states to 6132 states and 9017 transitions. [2021-12-22 20:30:35,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6132 [2021-12-22 20:30:35,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6132 [2021-12-22 20:30:35,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6132 states and 9017 transitions. [2021-12-22 20:30:35,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:35,295 INFO L681 BuchiCegarLoop]: Abstraction has 6132 states and 9017 transitions. [2021-12-22 20:30:35,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6132 states and 9017 transitions. [2021-12-22 20:30:35,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6132 to 6130. [2021-12-22 20:30:35,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:35,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6130 states to 6130 states and 9015 transitions. [2021-12-22 20:30:35,451 INFO L704 BuchiCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2021-12-22 20:30:35,451 INFO L587 BuchiCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2021-12-22 20:30:35,451 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-12-22 20:30:35,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6130 states and 9015 transitions. [2021-12-22 20:30:35,463 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2021-12-22 20:30:35,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:35,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:35,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:35,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:35,465 INFO L791 eck$LassoCheckResult]: Stem: 59115#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 59116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 60013#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59465#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59271#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59272#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59357#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59665#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59799#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59800#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58565#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58566#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59727#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59161#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59162#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59068#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59069#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59462#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58809#L1174 assume !(0 == ~M_E~0); 58810#L1174-2 assume !(0 == ~T1_E~0); 58661#L1179-1 assume !(0 == ~T2_E~0); 58563#L1184-1 assume !(0 == ~T3_E~0); 58564#L1189-1 assume !(0 == ~T4_E~0); 58602#L1194-1 assume !(0 == ~T5_E~0); 58702#L1199-1 assume !(0 == ~T6_E~0); 59607#L1204-1 assume !(0 == ~T7_E~0); 59521#L1209-1 assume !(0 == ~T8_E~0); 59522#L1214-1 assume !(0 == ~T9_E~0); 59941#L1219-1 assume !(0 == ~T10_E~0); 60038#L1224-1 assume !(0 == ~T11_E~0); 58927#L1229-1 assume !(0 == ~T12_E~0); 58488#L1234-1 assume !(0 == ~E_1~0); 58489#L1239-1 assume !(0 == ~E_2~0); 58524#L1244-1 assume !(0 == ~E_3~0); 58525#L1249-1 assume !(0 == ~E_4~0); 59185#L1254-1 assume !(0 == ~E_5~0); 58418#L1259-1 assume !(0 == ~E_6~0); 58372#L1264-1 assume !(0 == ~E_7~0); 58373#L1269-1 assume !(0 == ~E_8~0); 60047#L1274-1 assume !(0 == ~E_9~0); 59971#L1279-1 assume !(0 == ~E_10~0); 58606#L1284-1 assume !(0 == ~E_11~0); 58607#L1289-1 assume !(0 == ~E_12~0); 59238#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59239#L566 assume 1 == ~m_pc~0; 58389#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58390#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59551#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59552#L1455 assume !(0 != activate_threads_~tmp~1#1); 58836#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58837#L585 assume 1 == ~t1_pc~0; 58485#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58486#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59491#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59492#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 59998#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59996#L604 assume !(1 == ~t2_pc~0); 59573#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59574#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59100#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59101#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59755#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59756#L623 assume 1 == ~t3_pc~0; 59015#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58353#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59165#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59166#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 59795#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58386#L642 assume !(1 == ~t4_pc~0); 58387#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58853#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58854#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58459#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58460#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59587#L661 assume 1 == ~t5_pc~0; 58624#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58625#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58586#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58587#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 59618#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59619#L680 assume !(1 == ~t6_pc~0); 59048#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59049#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59313#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59314#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 59868#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59994#L699 assume 1 == ~t7_pc~0; 59442#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59443#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58614#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58615#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59343#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59240#L718 assume !(1 == ~t8_pc~0); 59241#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58600#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58601#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58642#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 58643#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58776#L737 assume 1 == ~t9_pc~0; 59651#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58911#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59517#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59518#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59086#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59087#L756 assume 1 == ~t10_pc~0; 59677#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59335#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58316#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58317#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 58893#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58894#L775 assume !(1 == ~t11_pc~0); 59149#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59150#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58770#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58534#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58535#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58721#L794 assume 1 == ~t12_pc~0; 58562#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58539#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59746#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58687#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 58688#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59168#L1307 assume !(1 == ~M_E~0); 59169#L1307-2 assume !(1 == ~T1_E~0); 59283#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60012#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59412#L1322-1 assume !(1 == ~T4_E~0); 58902#L1327-1 assume !(1 == ~T5_E~0); 58903#L1332-1 assume !(1 == ~T6_E~0); 59446#L1337-1 assume !(1 == ~T7_E~0); 59407#L1342-1 assume !(1 == ~T8_E~0); 59408#L1347-1 assume !(1 == ~T9_E~0); 59969#L1352-1 assume !(1 == ~T10_E~0); 60296#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60294#L1362-1 assume !(1 == ~T12_E~0); 60292#L1367-1 assume !(1 == ~E_1~0); 60290#L1372-1 assume !(1 == ~E_2~0); 60288#L1377-1 assume !(1 == ~E_3~0); 58998#L1382-1 assume !(1 == ~E_4~0); 58999#L1387-1 assume !(1 == ~E_5~0); 60134#L1392-1 assume !(1 == ~E_6~0); 60132#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60130#L1402-1 assume !(1 == ~E_8~0); 60128#L1407-1 assume !(1 == ~E_9~0); 60126#L1412-1 assume !(1 == ~E_10~0); 60125#L1417-1 assume !(1 == ~E_11~0); 60105#L1422-1 assume !(1 == ~E_12~0); 60096#L1427-1 assume { :end_inline_reset_delta_events } true; 60089#L1768-2 [2021-12-22 20:30:35,465 INFO L793 eck$LassoCheckResult]: Loop: 60089#L1768-2 assume !false; 60083#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60079#L1149 assume !false; 60078#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60070#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60064#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60063#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60061#L976 assume !(0 != eval_~tmp~0#1); 60060#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60059#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60058#L1174-3 assume !(0 == ~M_E~0); 60057#L1174-5 assume !(0 == ~T1_E~0); 60055#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60056#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61900#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61898#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61896#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61894#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 61892#L1209-3 assume !(0 == ~T8_E~0); 61890#L1214-3 assume !(0 == ~T9_E~0); 61888#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 61886#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 61884#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 61867#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61862#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61857#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61851#L1249-3 assume !(0 == ~E_4~0); 61844#L1254-3 assume !(0 == ~E_5~0); 61839#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61834#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61829#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61824#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 61819#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 61812#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 61807#L1289-3 assume !(0 == ~E_12~0); 61802#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61797#L566-39 assume !(1 == ~m_pc~0); 61792#L566-41 is_master_triggered_~__retres1~0#1 := 0; 61785#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61778#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61773#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61768#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61763#L585-39 assume 1 == ~t1_pc~0; 61757#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 61751#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61744#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61739#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61734#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61730#L604-39 assume 1 == ~t2_pc~0; 61725#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 61720#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61715#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61710#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61704#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61699#L623-39 assume !(1 == ~t3_pc~0); 61693#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 61686#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61681#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61676#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61670#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61665#L642-39 assume 1 == ~t4_pc~0; 61660#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 61653#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61648#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61644#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61639#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61635#L661-39 assume !(1 == ~t5_pc~0); 61630#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 61623#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61617#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61612#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61606#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61601#L680-39 assume 1 == ~t6_pc~0; 61595#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61588#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61582#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61577#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61571#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 61566#L699-39 assume !(1 == ~t7_pc~0); 61560#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 61553#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 61546#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 61540#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61532#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61526#L718-39 assume !(1 == ~t8_pc~0); 61520#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 61511#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61503#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 61495#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 61486#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 61479#L737-39 assume !(1 == ~t9_pc~0); 61472#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 61462#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61454#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61447#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61430#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61422#L756-39 assume !(1 == ~t10_pc~0); 61414#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 61406#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61400#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61393#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 61385#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61378#L775-39 assume 1 == ~t11_pc~0; 61370#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 61361#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61354#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61346#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 61337#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61329#L794-39 assume !(1 == ~t12_pc~0); 61321#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 61312#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61305#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61297#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61288#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61280#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61273#L1307-5 assume !(1 == ~T1_E~0); 61265#L1312-3 assume !(1 == ~T2_E~0); 60046#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61251#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61242#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61234#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61227#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61221#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61169#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61161#L1352-3 assume !(1 == ~T10_E~0); 61155#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61149#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61144#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60980#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60979#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60978#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60977#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60973#L1392-3 assume !(1 == ~E_6~0); 60955#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60931#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60923#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60918#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60914#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60910#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60908#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60283#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60270#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60269#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60267#L1787 assume !(0 == start_simulation_~tmp~3#1); 60263#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60141#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60133#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60131#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 60129#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60127#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60106#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 60097#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 60089#L1768-2 [2021-12-22 20:30:35,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:35,466 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2021-12-22 20:30:35,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:35,466 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763069768] [2021-12-22 20:30:35,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:35,467 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:35,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:35,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:35,493 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:35,493 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763069768] [2021-12-22 20:30:35,493 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763069768] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:35,493 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:35,493 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-22 20:30:35,493 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920565303] [2021-12-22 20:30:35,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:35,494 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:35,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:35,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1635699163, now seen corresponding path program 1 times [2021-12-22 20:30:35,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:35,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197680144] [2021-12-22 20:30:35,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:35,495 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:35,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:35,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:35,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:35,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197680144] [2021-12-22 20:30:35,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197680144] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:35,523 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:35,523 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:35,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786053859] [2021-12-22 20:30:35,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:35,524 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:35,524 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:35,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:35,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:35,525 INFO L87 Difference]: Start difference. First operand 6130 states and 9015 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:35,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:35,616 INFO L93 Difference]: Finished difference Result 11989 states and 17511 transitions. [2021-12-22 20:30:35,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:35,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11989 states and 17511 transitions. [2021-12-22 20:30:35,651 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11778 [2021-12-22 20:30:35,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11989 states to 11989 states and 17511 transitions. [2021-12-22 20:30:35,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11989 [2021-12-22 20:30:35,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11989 [2021-12-22 20:30:35,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11989 states and 17511 transitions. [2021-12-22 20:30:35,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:35,701 INFO L681 BuchiCegarLoop]: Abstraction has 11989 states and 17511 transitions. [2021-12-22 20:30:35,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11989 states and 17511 transitions. [2021-12-22 20:30:35,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11989 to 11621. [2021-12-22 20:30:35,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:35,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11621 states to 11621 states and 16995 transitions. [2021-12-22 20:30:35,921 INFO L704 BuchiCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2021-12-22 20:30:35,921 INFO L587 BuchiCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2021-12-22 20:30:35,921 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-12-22 20:30:35,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11621 states and 16995 transitions. [2021-12-22 20:30:35,944 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11410 [2021-12-22 20:30:35,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:35,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:35,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:35,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:35,946 INFO L791 eck$LassoCheckResult]: Stem: 77251#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 77252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 78273#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77630#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77413#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 77414#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77503#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77848#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77995#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77996#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76688#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76689#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 77916#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77296#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77297#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77203#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77204#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77625#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76935#L1174 assume !(0 == ~M_E~0); 76936#L1174-2 assume !(0 == ~T1_E~0); 76786#L1179-1 assume !(0 == ~T2_E~0); 76686#L1184-1 assume !(0 == ~T3_E~0); 76687#L1189-1 assume !(0 == ~T4_E~0); 76725#L1194-1 assume !(0 == ~T5_E~0); 76827#L1199-1 assume !(0 == ~T6_E~0); 77780#L1204-1 assume !(0 == ~T7_E~0); 77688#L1209-1 assume !(0 == ~T8_E~0); 77689#L1214-1 assume !(0 == ~T9_E~0); 78157#L1219-1 assume !(0 == ~T10_E~0); 78316#L1224-1 assume !(0 == ~T11_E~0); 77056#L1229-1 assume !(0 == ~T12_E~0); 76613#L1234-1 assume !(0 == ~E_1~0); 76614#L1239-1 assume !(0 == ~E_2~0); 76647#L1244-1 assume !(0 == ~E_3~0); 76648#L1249-1 assume !(0 == ~E_4~0); 77320#L1254-1 assume !(0 == ~E_5~0); 76541#L1259-1 assume !(0 == ~E_6~0); 76498#L1264-1 assume !(0 == ~E_7~0); 76499#L1269-1 assume !(0 == ~E_8~0); 78348#L1274-1 assume !(0 == ~E_9~0); 78198#L1279-1 assume !(0 == ~E_10~0); 76729#L1284-1 assume !(0 == ~E_11~0); 76730#L1289-1 assume !(0 == ~E_12~0); 77379#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77380#L566 assume !(1 == ~m_pc~0); 77842#L566-2 is_master_triggered_~__retres1~0#1 := 0; 77843#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77721#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77722#L1455 assume !(0 != activate_threads_~tmp~1#1); 76962#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76963#L585 assume 1 == ~t1_pc~0; 76608#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76609#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77655#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77656#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 78238#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78232#L604 assume !(1 == ~t2_pc~0); 77744#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77745#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77234#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77235#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77949#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77950#L623 assume 1 == ~t3_pc~0; 77147#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76479#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77300#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77301#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 77988#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76512#L642 assume !(1 == ~t4_pc~0); 76513#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76979#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76980#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76584#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 76585#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77757#L661 assume 1 == ~t5_pc~0; 76749#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76750#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76709#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76710#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 77792#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77793#L680 assume !(1 == ~t6_pc~0); 77181#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 77182#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77457#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77458#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 78065#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78230#L699 assume 1 == ~t7_pc~0; 77599#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77600#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76737#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76738#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 77488#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77381#L718 assume !(1 == ~t8_pc~0); 77382#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 76723#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76724#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76769#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 76770#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76900#L737 assume 1 == ~t9_pc~0; 77828#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77041#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77683#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77684#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 77220#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77221#L756 assume 1 == ~t10_pc~0; 77856#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 77480#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76442#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76443#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 77021#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77022#L775 assume !(1 == ~t11_pc~0); 77283#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 77284#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76897#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76657#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76658#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76846#L794 assume 1 == ~t12_pc~0; 76685#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 76662#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77942#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76814#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 76815#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77303#L1307 assume !(1 == ~M_E~0); 77304#L1307-2 assume !(1 == ~T1_E~0); 77425#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77337#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77338#L1322-1 assume !(1 == ~T4_E~0); 77031#L1327-1 assume !(1 == ~T5_E~0); 77032#L1332-1 assume !(1 == ~T6_E~0); 78246#L1337-1 assume !(1 == ~T7_E~0); 78247#L1342-1 assume !(1 == ~T8_E~0); 78196#L1347-1 assume !(1 == ~T9_E~0); 78023#L1352-1 assume !(1 == ~T10_E~0); 77866#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77199#L1362-1 assume !(1 == ~T12_E~0); 77200#L1367-1 assume !(1 == ~E_1~0); 76828#L1372-1 assume !(1 == ~E_2~0); 76829#L1377-1 assume !(1 == ~E_3~0); 77130#L1382-1 assume !(1 == ~E_4~0); 77131#L1387-1 assume !(1 == ~E_5~0); 77746#L1392-1 assume !(1 == ~E_6~0); 77153#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 77154#L1402-1 assume !(1 == ~E_8~0); 76844#L1407-1 assume !(1 == ~E_9~0); 76845#L1412-1 assume !(1 == ~E_10~0); 77940#L1417-1 assume !(1 == ~E_11~0); 77941#L1422-1 assume !(1 == ~E_12~0); 78226#L1427-1 assume { :end_inline_reset_delta_events } true; 76641#L1768-2 [2021-12-22 20:30:35,946 INFO L793 eck$LassoCheckResult]: Loop: 76641#L1768-2 assume !false; 76642#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77405#L1149 assume !false; 77816#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78173#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 77037#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 76946#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76947#L976 assume !(0 != eval_~tmp~0#1); 78225#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87644#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87643#L1174-3 assume !(0 == ~M_E~0); 87642#L1174-5 assume !(0 == ~T1_E~0); 86444#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86445#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87517#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87516#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87515#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87514#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87513#L1209-3 assume !(0 == ~T8_E~0); 87512#L1214-3 assume !(0 == ~T9_E~0); 87511#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 87510#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 87509#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 87508#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87507#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87506#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 87505#L1249-3 assume !(0 == ~E_4~0); 87504#L1254-3 assume !(0 == ~E_5~0); 87503#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 87502#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87501#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 87500#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 87499#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 87498#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 87497#L1289-3 assume !(0 == ~E_12~0); 87496#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 87495#L566-39 assume !(1 == ~m_pc~0); 87494#L566-41 is_master_triggered_~__retres1~0#1 := 0; 87493#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87492#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87491#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87490#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87489#L585-39 assume !(1 == ~t1_pc~0); 87488#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 87486#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87485#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87484#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 87483#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87482#L604-39 assume !(1 == ~t2_pc~0); 87481#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 87479#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87478#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87477#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87476#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87475#L623-39 assume !(1 == ~t3_pc~0); 87473#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 87472#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87471#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87470#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87469#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87468#L642-39 assume !(1 == ~t4_pc~0); 87467#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 87465#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87464#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87463#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87462#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87461#L661-39 assume !(1 == ~t5_pc~0); 87459#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 87458#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87457#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87456#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87455#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87454#L680-39 assume !(1 == ~t6_pc~0); 87453#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 87451#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87450#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87449#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87448#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87447#L699-39 assume !(1 == ~t7_pc~0); 87445#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 87444#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87443#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87442#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87441#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87440#L718-39 assume !(1 == ~t8_pc~0); 87439#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 87437#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87436#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87435#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 87434#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87433#L737-39 assume 1 == ~t9_pc~0; 87431#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87430#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87429#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 87428#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 87427#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87426#L756-39 assume 1 == ~t10_pc~0; 87425#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 87423#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87422#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87421#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87420#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87419#L775-39 assume 1 == ~t11_pc~0; 87417#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87416#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87415#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87414#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87413#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 87412#L794-39 assume 1 == ~t12_pc~0; 87411#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 87409#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 87408#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87407#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 87406#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87405#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 87404#L1307-5 assume !(1 == ~T1_E~0); 87403#L1312-3 assume !(1 == ~T2_E~0); 78347#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87402#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87401#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 87400#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87399#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 87398#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 87397#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77925#L1352-3 assume !(1 == ~T10_E~0); 87396#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 87395#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 87394#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87393#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87392#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 87391#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87390#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 84567#L1392-3 assume !(1 == ~E_6~0); 87389#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 87388#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 87387#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 87386#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 87385#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 87384#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 87383#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 87369#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 87357#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 87356#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 87355#L1787 assume !(0 == start_simulation_~tmp~3#1); 87353#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 87346#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 87339#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 87338#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 87337#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87336#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77097#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 77098#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 76641#L1768-2 [2021-12-22 20:30:35,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:35,946 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2021-12-22 20:30:35,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:35,946 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407317839] [2021-12-22 20:30:35,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:35,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:35,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:35,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:35,991 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:35,991 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407317839] [2021-12-22 20:30:35,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407317839] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:35,991 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:35,991 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:35,991 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1938473706] [2021-12-22 20:30:35,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:35,992 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:35,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:35,992 INFO L85 PathProgramCache]: Analyzing trace with hash 421576388, now seen corresponding path program 1 times [2021-12-22 20:30:35,992 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:35,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744231848] [2021-12-22 20:30:35,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:35,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:36,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:36,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:36,048 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:36,048 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744231848] [2021-12-22 20:30:36,048 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744231848] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:36,048 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:36,048 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:36,048 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059208167] [2021-12-22 20:30:36,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:36,049 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:36,049 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:36,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:36,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:36,049 INFO L87 Difference]: Start difference. First operand 11621 states and 16995 transitions. cyclomatic complexity: 5382 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:36,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:36,419 INFO L93 Difference]: Finished difference Result 28292 states and 41065 transitions. [2021-12-22 20:30:36,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:36,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28292 states and 41065 transitions. [2021-12-22 20:30:36,535 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 27682 [2021-12-22 20:30:36,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28292 states to 28292 states and 41065 transitions. [2021-12-22 20:30:36,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28292 [2021-12-22 20:30:36,644 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28292 [2021-12-22 20:30:36,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28292 states and 41065 transitions. [2021-12-22 20:30:36,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:36,670 INFO L681 BuchiCegarLoop]: Abstraction has 28292 states and 41065 transitions. [2021-12-22 20:30:36,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28292 states and 41065 transitions. [2021-12-22 20:30:37,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28292 to 22174. [2021-12-22 20:30:37,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22174 states, 22174 states have (on average 1.4561197799224317) internal successors, (32288), 22173 states have internal predecessors, (32288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:37,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22174 states to 22174 states and 32288 transitions. [2021-12-22 20:30:37,082 INFO L704 BuchiCegarLoop]: Abstraction has 22174 states and 32288 transitions. [2021-12-22 20:30:37,082 INFO L587 BuchiCegarLoop]: Abstraction has 22174 states and 32288 transitions. [2021-12-22 20:30:37,082 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-12-22 20:30:37,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22174 states and 32288 transitions. [2021-12-22 20:30:37,148 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21960 [2021-12-22 20:30:37,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:37,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:37,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:37,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:37,151 INFO L791 eck$LassoCheckResult]: Stem: 117173#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 117174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 118113#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117532#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117328#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 117329#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117419#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 117744#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117875#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117876#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116606#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116607#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 117807#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117218#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 117219#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 117124#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 117125#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 117528#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116854#L1174 assume !(0 == ~M_E~0); 116855#L1174-2 assume !(0 == ~T1_E~0); 116704#L1179-1 assume !(0 == ~T2_E~0); 116604#L1184-1 assume !(0 == ~T3_E~0); 116605#L1189-1 assume !(0 == ~T4_E~0); 116644#L1194-1 assume !(0 == ~T5_E~0); 116746#L1199-1 assume !(0 == ~T6_E~0); 117682#L1204-1 assume !(0 == ~T7_E~0); 117591#L1209-1 assume !(0 == ~T8_E~0); 117592#L1214-1 assume !(0 == ~T9_E~0); 118016#L1219-1 assume !(0 == ~T10_E~0); 118143#L1224-1 assume !(0 == ~T11_E~0); 116977#L1229-1 assume !(0 == ~T12_E~0); 116530#L1234-1 assume !(0 == ~E_1~0); 116531#L1239-1 assume !(0 == ~E_2~0); 116564#L1244-1 assume !(0 == ~E_3~0); 116565#L1249-1 assume !(0 == ~E_4~0); 117243#L1254-1 assume !(0 == ~E_5~0); 116463#L1259-1 assume !(0 == ~E_6~0); 116420#L1264-1 assume !(0 == ~E_7~0); 116421#L1269-1 assume !(0 == ~E_8~0); 118160#L1274-1 assume !(0 == ~E_9~0); 118051#L1279-1 assume !(0 == ~E_10~0); 116647#L1284-1 assume !(0 == ~E_11~0); 116648#L1289-1 assume !(0 == ~E_12~0); 117297#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117298#L566 assume !(1 == ~m_pc~0); 117741#L566-2 is_master_triggered_~__retres1~0#1 := 0; 117742#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117625#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117626#L1455 assume !(0 != activate_threads_~tmp~1#1); 116881#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116882#L585 assume !(1 == ~t1_pc~0); 117069#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117070#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117560#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 117561#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 118086#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118084#L604 assume !(1 == ~t2_pc~0); 117645#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 117646#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117156#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117157#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117833#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117834#L623 assume 1 == ~t3_pc~0; 117068#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 116401#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117224#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117225#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 117869#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116434#L642 assume !(1 == ~t4_pc~0); 116435#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116900#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116901#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116504#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 116505#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117659#L661 assume 1 == ~t5_pc~0; 116667#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 116668#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116627#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116628#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 117691#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117692#L680 assume !(1 == ~t6_pc~0); 117104#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 117105#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117373#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117374#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 117942#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118081#L699 assume 1 == ~t7_pc~0; 117509#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 117510#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116655#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116656#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 117405#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 117299#L718 assume !(1 == ~t8_pc~0); 117300#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 116642#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 116643#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116685#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 116686#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116821#L737 assume 1 == ~t9_pc~0; 117729#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 116962#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117587#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 117588#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 117142#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117143#L756 assume 1 == ~t10_pc~0; 117756#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 117396#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116365#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 116366#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 116943#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116944#L775 assume !(1 == ~t11_pc~0); 117206#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 117207#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116815#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116576#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116577#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116766#L794 assume 1 == ~t12_pc~0; 116602#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 116581#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117828#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116731#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 116732#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117227#L1307 assume !(1 == ~M_E~0); 117228#L1307-2 assume !(1 == ~T1_E~0); 117340#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117257#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117258#L1322-1 assume !(1 == ~T4_E~0); 117475#L1327-1 assume !(1 == ~T5_E~0); 132513#L1332-1 assume !(1 == ~T6_E~0); 132511#L1337-1 assume !(1 == ~T7_E~0); 132509#L1342-1 assume !(1 == ~T8_E~0); 132507#L1347-1 assume !(1 == ~T9_E~0); 117901#L1352-1 assume !(1 == ~T10_E~0); 117765#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117122#L1362-1 assume !(1 == ~T12_E~0); 117123#L1367-1 assume !(1 == ~E_1~0); 116747#L1372-1 assume !(1 == ~E_2~0); 116748#L1377-1 assume !(1 == ~E_3~0); 117051#L1382-1 assume !(1 == ~E_4~0); 117052#L1387-1 assume !(1 == ~E_5~0); 117647#L1392-1 assume !(1 == ~E_6~0); 117074#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 117075#L1402-1 assume !(1 == ~E_8~0); 118079#L1407-1 assume !(1 == ~E_9~0); 131351#L1412-1 assume !(1 == ~E_10~0); 131349#L1417-1 assume !(1 == ~E_11~0); 131347#L1422-1 assume !(1 == ~E_12~0); 131341#L1427-1 assume { :end_inline_reset_delta_events } true; 131339#L1768-2 [2021-12-22 20:30:37,151 INFO L793 eck$LassoCheckResult]: Loop: 131339#L1768-2 assume !false; 131336#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 131332#L1149 assume !false; 131331#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 131323#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 131317#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 131316#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 131315#L976 assume !(0 != eval_~tmp~0#1); 118104#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 118095#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117844#L1174-3 assume !(0 == ~M_E~0); 117838#L1174-5 assume !(0 == ~T1_E~0); 117565#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117566#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117766#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117391#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 116720#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 116721#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116968#L1209-3 assume !(0 == ~T8_E~0); 116386#L1214-3 assume !(0 == ~T9_E~0); 116387#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117154#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117155#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117175#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 116568#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 116569#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117023#L1249-3 assume !(0 == ~E_4~0); 117501#L1254-3 assume !(0 == ~E_5~0); 118012#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117623#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 116574#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 116575#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 118125#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 137216#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 137214#L1289-3 assume !(0 == ~E_12~0); 137212#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137210#L566-39 assume !(1 == ~m_pc~0); 137208#L566-41 is_master_triggered_~__retres1~0#1 := 0; 137206#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137184#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137183#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136369#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118037#L585-39 assume !(1 == ~t1_pc~0); 118038#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 131752#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131750#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131748#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 131745#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131743#L604-39 assume 1 == ~t2_pc~0; 131740#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 131738#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131736#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131734#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131731#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131729#L623-39 assume !(1 == ~t3_pc~0); 131726#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 131724#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131722#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131720#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 131717#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131715#L642-39 assume 1 == ~t4_pc~0; 131712#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 131710#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131708#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131706#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 131703#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131701#L661-39 assume !(1 == ~t5_pc~0); 131698#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 131696#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131694#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131692#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 131689#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131687#L680-39 assume 1 == ~t6_pc~0; 131684#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131682#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131680#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131678#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 131675#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131673#L699-39 assume !(1 == ~t7_pc~0); 131670#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 131668#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131666#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131664#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 131661#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131659#L718-39 assume 1 == ~t8_pc~0; 131656#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 131654#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131652#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131650#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 131647#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 131645#L737-39 assume 1 == ~t9_pc~0; 131642#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131640#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131638#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131637#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 131633#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 131631#L756-39 assume !(1 == ~t10_pc~0); 131628#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 131627#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 131622#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131617#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 131616#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 131615#L775-39 assume !(1 == ~t11_pc~0); 131614#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 131612#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 131611#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 131610#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 131609#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 131608#L794-39 assume !(1 == ~t12_pc~0); 131606#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 131605#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131604#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 131603#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 131602#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131601#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 131600#L1307-5 assume !(1 == ~T1_E~0); 131429#L1312-3 assume !(1 == ~T2_E~0); 130506#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131426#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131424#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131422#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131420#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 131418#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 131417#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 131044#L1352-3 assume !(1 == ~T10_E~0); 131414#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 131412#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 131410#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131408#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 131406#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131405#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131403#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 117037#L1392-3 assume !(1 == ~E_6~0); 131400#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 131398#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 131396#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 131394#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 131392#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 131391#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 131389#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 131384#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 131371#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 131369#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 131367#L1787 assume !(0 == start_simulation_~tmp~3#1); 131365#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 131358#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 131350#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 131348#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 131346#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 131345#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 131344#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 131342#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 131339#L1768-2 [2021-12-22 20:30:37,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:37,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1220887001, now seen corresponding path program 1 times [2021-12-22 20:30:37,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:37,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274655678] [2021-12-22 20:30:37,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:37,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:37,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:37,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:37,184 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:37,184 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274655678] [2021-12-22 20:30:37,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274655678] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:37,184 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:37,184 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-22 20:30:37,184 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285044954] [2021-12-22 20:30:37,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:37,185 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:37,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:37,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1728296421, now seen corresponding path program 1 times [2021-12-22 20:30:37,185 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:37,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758780642] [2021-12-22 20:30:37,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:37,186 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:37,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:37,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:37,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:37,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758780642] [2021-12-22 20:30:37,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758780642] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:37,211 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:37,212 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:37,212 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155273924] [2021-12-22 20:30:37,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:37,212 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:37,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:37,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-22 20:30:37,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-22 20:30:37,213 INFO L87 Difference]: Start difference. First operand 22174 states and 32288 transitions. cyclomatic complexity: 10122 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:37,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:37,729 INFO L93 Difference]: Finished difference Result 61985 states and 90255 transitions. [2021-12-22 20:30:37,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-22 20:30:37,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61985 states and 90255 transitions. [2021-12-22 20:30:37,962 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 61464 [2021-12-22 20:30:38,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61985 states to 61985 states and 90255 transitions. [2021-12-22 20:30:38,313 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61985 [2021-12-22 20:30:38,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61985 [2021-12-22 20:30:38,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61985 states and 90255 transitions. [2021-12-22 20:30:38,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:38,430 INFO L681 BuchiCegarLoop]: Abstraction has 61985 states and 90255 transitions. [2021-12-22 20:30:38,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61985 states and 90255 transitions. [2021-12-22 20:30:38,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61985 to 22777. [2021-12-22 20:30:38,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22777 states, 22777 states have (on average 1.4440444307854414) internal successors, (32891), 22776 states have internal predecessors, (32891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:38,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22777 states to 22777 states and 32891 transitions. [2021-12-22 20:30:38,946 INFO L704 BuchiCegarLoop]: Abstraction has 22777 states and 32891 transitions. [2021-12-22 20:30:38,946 INFO L587 BuchiCegarLoop]: Abstraction has 22777 states and 32891 transitions. [2021-12-22 20:30:38,946 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-12-22 20:30:38,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22777 states and 32891 transitions. [2021-12-22 20:30:39,012 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22560 [2021-12-22 20:30:39,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:39,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:39,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:39,014 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:39,015 INFO L791 eck$LassoCheckResult]: Stem: 201349#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 201350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 202459#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201740#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 201510#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 201511#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 201612#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 201968#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 202137#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 202138#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 200778#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 200779#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 202047#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 201396#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 201397#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 201302#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 201303#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 201736#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201028#L1174 assume !(0 == ~M_E~0); 201029#L1174-2 assume !(0 == ~T1_E~0); 200876#L1179-1 assume !(0 == ~T2_E~0); 200776#L1184-1 assume !(0 == ~T3_E~0); 200777#L1189-1 assume !(0 == ~T4_E~0); 200816#L1194-1 assume !(0 == ~T5_E~0); 200919#L1199-1 assume !(0 == ~T6_E~0); 201900#L1204-1 assume !(0 == ~T7_E~0); 201803#L1209-1 assume !(0 == ~T8_E~0); 201804#L1214-1 assume !(0 == ~T9_E~0); 202324#L1219-1 assume !(0 == ~T10_E~0); 202504#L1224-1 assume !(0 == ~T11_E~0); 201154#L1229-1 assume !(0 == ~T12_E~0); 200702#L1234-1 assume !(0 == ~E_1~0); 200703#L1239-1 assume !(0 == ~E_2~0); 200736#L1244-1 assume !(0 == ~E_3~0); 200737#L1249-1 assume !(0 == ~E_4~0); 201421#L1254-1 assume !(0 == ~E_5~0); 200635#L1259-1 assume !(0 == ~E_6~0); 200592#L1264-1 assume !(0 == ~E_7~0); 200593#L1269-1 assume !(0 == ~E_8~0); 202534#L1274-1 assume !(0 == ~E_9~0); 202377#L1279-1 assume !(0 == ~E_10~0); 200819#L1284-1 assume !(0 == ~E_11~0); 200820#L1289-1 assume !(0 == ~E_12~0); 201479#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 201480#L566 assume !(1 == ~m_pc~0); 201965#L566-2 is_master_triggered_~__retres1~0#1 := 0; 201966#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 201838#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 201839#L1455 assume !(0 != activate_threads_~tmp~1#1); 201055#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 201056#L585 assume !(1 == ~t1_pc~0); 201246#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 201247#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 201767#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 201768#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 202421#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 202417#L604 assume !(1 == ~t2_pc~0); 201860#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 201861#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202396#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 202287#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 202082#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 202083#L623 assume 1 == ~t3_pc~0; 201245#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200573#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 201400#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 201401#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 202131#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 200606#L642 assume !(1 == ~t4_pc~0); 200607#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 201073#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 201074#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 200676#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 200677#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 201873#L661 assume 1 == ~t5_pc~0; 200839#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 200840#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 200799#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 200800#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 201911#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 201912#L680 assume !(1 == ~t6_pc~0); 201281#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 201282#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 201558#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 201559#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 202222#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 202415#L699 assume 1 == ~t7_pc~0; 201711#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 201712#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 200827#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 200828#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 201595#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 201481#L718 assume !(1 == ~t8_pc~0); 201482#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 200814#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 200815#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 200857#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 200858#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 200995#L737 assume 1 == ~t9_pc~0; 201950#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 201139#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 201796#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 201797#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 201320#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 201321#L756 assume 1 == ~t10_pc~0; 201986#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 201582#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 200537#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 200538#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 201118#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 201119#L775 assume !(1 == ~t11_pc~0); 201383#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 201384#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 200989#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 200748#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 200749#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 200939#L794 assume 1 == ~t12_pc~0; 200774#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 200753#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 202074#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 200902#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 200903#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 201403#L1307 assume !(1 == ~M_E~0); 201404#L1307-2 assume !(1 == ~T1_E~0); 201522#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 201437#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 201438#L1322-1 assume !(1 == ~T4_E~0); 201129#L1327-1 assume !(1 == ~T5_E~0); 201130#L1332-1 assume !(1 == ~T6_E~0); 201716#L1337-1 assume !(1 == ~T7_E~0); 201668#L1342-1 assume !(1 == ~T8_E~0); 201669#L1347-1 assume !(1 == ~T9_E~0); 202170#L1352-1 assume !(1 == ~T10_E~0); 201996#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 201300#L1362-1 assume !(1 == ~T12_E~0); 201301#L1367-1 assume !(1 == ~E_1~0); 200920#L1372-1 assume !(1 == ~E_2~0); 200921#L1377-1 assume !(1 == ~E_3~0); 201228#L1382-1 assume !(1 == ~E_4~0); 201229#L1387-1 assume !(1 == ~E_5~0); 201862#L1392-1 assume !(1 == ~E_6~0); 218469#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 218467#L1402-1 assume !(1 == ~E_8~0); 218465#L1407-1 assume !(1 == ~E_9~0); 218463#L1412-1 assume !(1 == ~E_10~0); 218461#L1417-1 assume !(1 == ~E_11~0); 218460#L1422-1 assume !(1 == ~E_12~0); 217937#L1427-1 assume { :end_inline_reset_delta_events } true; 217935#L1768-2 [2021-12-22 20:30:39,015 INFO L793 eck$LassoCheckResult]: Loop: 217935#L1768-2 assume !false; 217919#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 217387#L1149 assume !false; 217385#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 217005#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 216998#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 216996#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 216992#L976 assume !(0 != eval_~tmp~0#1); 216993#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 222919#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 222917#L1174-3 assume !(0 == ~M_E~0); 222915#L1174-5 assume !(0 == ~T1_E~0); 222910#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 222909#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 222908#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 222907#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 222906#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 222901#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 222896#L1209-3 assume !(0 == ~T8_E~0); 222893#L1214-3 assume !(0 == ~T9_E~0); 222889#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 222885#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 222882#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 222877#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 222874#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 222872#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 222870#L1249-3 assume !(0 == ~E_4~0); 222868#L1254-3 assume !(0 == ~E_5~0); 222866#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 222864#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 222861#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 222860#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 222855#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 222850#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 222848#L1289-3 assume !(0 == ~E_12~0); 222844#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222843#L566-39 assume !(1 == ~m_pc~0); 201687#L566-41 is_master_triggered_~__retres1~0#1 := 0; 201688#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222142#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222140#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 222107#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 218371#L585-39 assume !(1 == ~t1_pc~0); 218368#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 218365#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 218363#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 218361#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 218359#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 218358#L604-39 assume !(1 == ~t2_pc~0); 218357#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 218355#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 218353#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 218351#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 218348#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 218346#L623-39 assume !(1 == ~t3_pc~0); 218343#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 218340#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 218338#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218336#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 218334#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 218332#L642-39 assume !(1 == ~t4_pc~0); 218330#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 218326#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 218324#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 218322#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 218320#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 218318#L661-39 assume !(1 == ~t5_pc~0); 218315#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 218312#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 218310#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 218308#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 218306#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 218304#L680-39 assume !(1 == ~t6_pc~0); 218302#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 218298#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 218296#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 218294#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 218292#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 218290#L699-39 assume 1 == ~t7_pc~0; 218288#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 218284#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 218282#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 218280#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 218278#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 218276#L718-39 assume !(1 == ~t8_pc~0); 218274#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 218270#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 218268#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 218266#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 218264#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 218262#L737-39 assume 1 == ~t9_pc~0; 218259#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 218257#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 218255#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 218253#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 218251#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 218249#L756-39 assume 1 == ~t10_pc~0; 218247#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 218244#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 218242#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 218241#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 218240#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 218239#L775-39 assume !(1 == ~t11_pc~0); 218238#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 218236#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 218235#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 218234#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 218233#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 218232#L794-39 assume 1 == ~t12_pc~0; 218231#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 218067#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 218065#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 218063#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 218062#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 218059#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 218057#L1307-5 assume !(1 == ~T1_E~0); 218055#L1312-3 assume !(1 == ~T2_E~0); 203734#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 218052#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 218050#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 218047#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 218045#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 218043#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 218041#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 218038#L1352-3 assume !(1 == ~T10_E~0); 218036#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 218033#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 218031#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 218029#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 218027#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 218025#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218023#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 218018#L1392-3 assume !(1 == ~E_6~0); 218016#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 218014#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 218012#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 218010#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 218008#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 218005#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 218003#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 217998#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 217985#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 217982#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 217979#L1787 assume !(0 == start_simulation_~tmp~3#1); 217976#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 217957#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 217949#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 217947#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 217945#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 217943#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 217941#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 217938#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 217935#L1768-2 [2021-12-22 20:30:39,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:39,016 INFO L85 PathProgramCache]: Analyzing trace with hash 226193303, now seen corresponding path program 1 times [2021-12-22 20:30:39,016 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:39,016 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944219449] [2021-12-22 20:30:39,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:39,016 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:39,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:39,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:39,041 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:39,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944219449] [2021-12-22 20:30:39,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944219449] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:39,042 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:39,042 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:39,042 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335253147] [2021-12-22 20:30:39,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:39,042 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:39,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:39,043 INFO L85 PathProgramCache]: Analyzing trace with hash -1078383486, now seen corresponding path program 1 times [2021-12-22 20:30:39,043 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:39,043 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191459303] [2021-12-22 20:30:39,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:39,043 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:39,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:39,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:39,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:39,068 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [191459303] [2021-12-22 20:30:39,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [191459303] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:39,068 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:39,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:39,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178371559] [2021-12-22 20:30:39,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:39,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:39,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:39,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:39,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:39,069 INFO L87 Difference]: Start difference. First operand 22777 states and 32891 transitions. cyclomatic complexity: 10122 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:39,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:39,482 INFO L93 Difference]: Finished difference Result 55470 states and 79580 transitions. [2021-12-22 20:30:39,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:39,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55470 states and 79580 transitions. [2021-12-22 20:30:39,845 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 54434 [2021-12-22 20:30:40,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55470 states to 55470 states and 79580 transitions. [2021-12-22 20:30:40,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55470 [2021-12-22 20:30:40,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55470 [2021-12-22 20:30:40,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55470 states and 79580 transitions. [2021-12-22 20:30:40,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:40,111 INFO L681 BuchiCegarLoop]: Abstraction has 55470 states and 79580 transitions. [2021-12-22 20:30:40,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55470 states and 79580 transitions. [2021-12-22 20:30:40,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55470 to 43592. [2021-12-22 20:30:40,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43592 states, 43592 states have (on average 1.4387043494219123) internal successors, (62716), 43591 states have internal predecessors, (62716), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:40,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43592 states to 43592 states and 62716 transitions. [2021-12-22 20:30:40,828 INFO L704 BuchiCegarLoop]: Abstraction has 43592 states and 62716 transitions. [2021-12-22 20:30:40,828 INFO L587 BuchiCegarLoop]: Abstraction has 43592 states and 62716 transitions. [2021-12-22 20:30:40,828 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-12-22 20:30:40,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43592 states and 62716 transitions. [2021-12-22 20:30:40,952 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 43368 [2021-12-22 20:30:40,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:40,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:40,972 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:40,973 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:40,973 INFO L791 eck$LassoCheckResult]: Stem: 279606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 279607#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 280707#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 280008#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279771#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 279772#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279871#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 280236#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 280386#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 280387#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 279033#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 279034#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 280306#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 279654#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 279655#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 279554#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 279555#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 280003#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 279285#L1174 assume !(0 == ~M_E~0); 279286#L1174-2 assume !(0 == ~T1_E~0); 279131#L1179-1 assume !(0 == ~T2_E~0); 279031#L1184-1 assume !(0 == ~T3_E~0); 279032#L1189-1 assume !(0 == ~T4_E~0); 279071#L1194-1 assume !(0 == ~T5_E~0); 279175#L1199-1 assume !(0 == ~T6_E~0); 280166#L1204-1 assume !(0 == ~T7_E~0); 280071#L1209-1 assume !(0 == ~T8_E~0); 280072#L1214-1 assume !(0 == ~T9_E~0); 280572#L1219-1 assume !(0 == ~T10_E~0); 280768#L1224-1 assume !(0 == ~T11_E~0); 279408#L1229-1 assume !(0 == ~T12_E~0); 278958#L1234-1 assume !(0 == ~E_1~0); 278959#L1239-1 assume !(0 == ~E_2~0); 278992#L1244-1 assume !(0 == ~E_3~0); 278993#L1249-1 assume !(0 == ~E_4~0); 279679#L1254-1 assume !(0 == ~E_5~0); 278889#L1259-1 assume !(0 == ~E_6~0); 278848#L1264-1 assume !(0 == ~E_7~0); 278849#L1269-1 assume !(0 == ~E_8~0); 280793#L1274-1 assume !(0 == ~E_9~0); 280624#L1279-1 assume !(0 == ~E_10~0); 279074#L1284-1 assume !(0 == ~E_11~0); 279075#L1289-1 assume !(0 == ~E_12~0); 279738#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279739#L566 assume !(1 == ~m_pc~0); 280233#L566-2 is_master_triggered_~__retres1~0#1 := 0; 280234#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280101#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 280102#L1455 assume !(0 != activate_threads_~tmp~1#1); 279312#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279313#L585 assume !(1 == ~t1_pc~0); 279498#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 279499#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280032#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 280033#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 280670#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280666#L604 assume !(1 == ~t2_pc~0); 280126#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 280127#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279591#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 279592#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 280344#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280345#L623 assume !(1 == ~t3_pc~0); 278828#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 278829#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279658#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279659#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 280381#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278862#L642 assume !(1 == ~t4_pc~0); 278863#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 279329#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279330#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 278932#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 278933#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 280142#L661 assume 1 == ~t5_pc~0; 279094#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 279095#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 279054#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 279055#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 280177#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280178#L680 assume !(1 == ~t6_pc~0); 279533#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 279534#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279819#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279820#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 280469#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 280662#L699 assume 1 == ~t7_pc~0; 279980#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 279981#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 279082#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279083#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 279857#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279740#L718 assume !(1 == ~t8_pc~0); 279741#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 279069#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 279070#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279112#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 279113#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279251#L737 assume 1 == ~t9_pc~0; 280217#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 279393#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 280060#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 280061#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 279575#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 279576#L756 assume 1 == ~t10_pc~0; 280248#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 279845#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 278794#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 278795#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 279373#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 279374#L775 assume !(1 == ~t11_pc~0); 279641#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 279642#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279248#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 279002#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 279003#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279194#L794 assume 1 == ~t12_pc~0; 279030#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 279007#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 280332#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279160#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 279161#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 279661#L1307 assume !(1 == ~M_E~0); 279662#L1307-2 assume !(1 == ~T1_E~0); 279787#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 279696#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 279697#L1322-1 assume !(1 == ~T4_E~0); 279382#L1327-1 assume !(1 == ~T5_E~0); 279383#L1332-1 assume !(1 == ~T6_E~0); 280677#L1337-1 assume !(1 == ~T7_E~0); 280678#L1342-1 assume !(1 == ~T8_E~0); 280620#L1347-1 assume !(1 == ~T9_E~0); 280621#L1352-1 assume !(1 == ~T10_E~0); 280258#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 280259#L1362-1 assume !(1 == ~T12_E~0); 280485#L1367-1 assume !(1 == ~E_1~0); 280486#L1372-1 assume !(1 == ~E_2~0); 279707#L1377-1 assume !(1 == ~E_3~0); 279708#L1382-1 assume !(1 == ~E_4~0); 280128#L1387-1 assume !(1 == ~E_5~0); 280129#L1392-1 assume !(1 == ~E_6~0); 280578#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 280659#L1402-1 assume !(1 == ~E_8~0); 280660#L1407-1 assume !(1 == ~E_9~0); 280738#L1412-1 assume !(1 == ~E_10~0); 280739#L1417-1 assume !(1 == ~E_11~0); 280829#L1422-1 assume !(1 == ~E_12~0); 280657#L1427-1 assume { :end_inline_reset_delta_events } true; 280658#L1768-2 [2021-12-22 20:30:40,987 INFO L793 eck$LassoCheckResult]: Loop: 280658#L1768-2 assume !false; 302469#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 302462#L1149 assume !false; 302458#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 302222#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 302174#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 302165#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 302156#L976 assume !(0 != eval_~tmp~0#1); 280696#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 280682#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 280356#L1174-3 assume !(0 == ~M_E~0); 280349#L1174-5 assume !(0 == ~T1_E~0); 280037#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 280038#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 280261#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 279839#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 279150#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 279151#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 279398#L1209-3 assume !(0 == ~T8_E~0); 278815#L1214-3 assume !(0 == ~T9_E~0); 278816#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 279589#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 279590#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 279608#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 278994#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 278995#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 279454#L1249-3 assume !(0 == ~E_4~0); 279969#L1254-3 assume !(0 == ~E_5~0); 280566#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 280099#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 279000#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 279001#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 280619#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 279587#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 279588#L1289-3 assume !(0 == ~E_12~0); 279573#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 279574#L566-39 assume !(1 == ~m_pc~0); 318519#L566-41 is_master_triggered_~__retres1~0#1 := 0; 318518#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318517#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318511#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 318508#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 318506#L585-39 assume !(1 == ~t1_pc~0); 302547#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 318503#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318501#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 318499#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 318496#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 318494#L604-39 assume !(1 == ~t2_pc~0); 318485#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 318482#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318480#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 318478#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 318476#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 279439#L623-39 assume !(1 == ~t3_pc~0); 279440#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 279947#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280210#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 279287#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 279288#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280148#L642-39 assume 1 == ~t4_pc~0; 279648#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 279649#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279154#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 279155#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 280392#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 279202#L661-39 assume !(1 == ~t5_pc~0); 278838#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 278839#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280316#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 280317#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 280213#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280214#L680-39 assume 1 == ~t6_pc~0; 278896#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 278897#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 280130#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279371#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 279372#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 280721#L699-39 assume !(1 == ~t7_pc~0); 306645#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 306643#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306642#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306641#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 306639#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 306637#L718-39 assume !(1 == ~t8_pc~0); 306244#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 306240#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306235#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 306233#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 306231#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 305874#L737-39 assume 1 == ~t9_pc~0; 305868#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 305866#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 305863#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 305862#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 305860#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 305857#L756-39 assume !(1 == ~t10_pc~0); 305854#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 305822#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 305821#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 305820#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 305819#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 305818#L775-39 assume 1 == ~t11_pc~0; 305815#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 305814#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 305813#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 305812#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 305811#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 305809#L794-39 assume !(1 == ~t12_pc~0); 305806#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 305804#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 305802#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 305800#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 305798#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 305796#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 305795#L1307-5 assume !(1 == ~T1_E~0); 305792#L1312-3 assume !(1 == ~T2_E~0); 294132#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 305789#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 305787#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 305785#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 305781#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 305779#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 305777#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 298982#L1352-3 assume !(1 == ~T10_E~0); 305773#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 305771#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 305769#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 303718#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 303714#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 303709#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 303706#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 294059#L1392-3 assume !(1 == ~E_6~0); 303700#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 303696#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 303693#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 303689#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 303684#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 303680#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 303678#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 303398#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 303379#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 303374#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 303369#L1787 assume !(0 == start_simulation_~tmp~3#1); 303364#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 302867#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 302851#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 302841#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 302836#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 302607#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 302499#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 302488#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 280658#L1768-2 [2021-12-22 20:30:40,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:40,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1148113654, now seen corresponding path program 1 times [2021-12-22 20:30:40,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:40,989 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819270870] [2021-12-22 20:30:40,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:40,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:41,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:41,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:41,040 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:41,041 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [819270870] [2021-12-22 20:30:41,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [819270870] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:41,041 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:41,041 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-22 20:30:41,041 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1928975942] [2021-12-22 20:30:41,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:41,042 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:41,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:41,042 INFO L85 PathProgramCache]: Analyzing trace with hash 1661322882, now seen corresponding path program 1 times [2021-12-22 20:30:41,042 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:41,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988415028] [2021-12-22 20:30:41,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:41,043 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:41,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:41,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:41,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:41,066 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988415028] [2021-12-22 20:30:41,066 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988415028] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:41,066 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:41,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:41,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556678530] [2021-12-22 20:30:41,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:41,067 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:41,067 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:41,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-22 20:30:41,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-22 20:30:41,068 INFO L87 Difference]: Start difference. First operand 43592 states and 62716 transitions. cyclomatic complexity: 19132 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:41,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:41,545 INFO L93 Difference]: Finished difference Result 83567 states and 119801 transitions. [2021-12-22 20:30:41,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-22 20:30:41,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83567 states and 119801 transitions. [2021-12-22 20:30:41,927 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 83264 [2021-12-22 20:30:42,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83567 states to 83567 states and 119801 transitions. [2021-12-22 20:30:42,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83567 [2021-12-22 20:30:42,302 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83567 [2021-12-22 20:30:42,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83567 states and 119801 transitions. [2021-12-22 20:30:42,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:42,341 INFO L681 BuchiCegarLoop]: Abstraction has 83567 states and 119801 transitions. [2021-12-22 20:30:42,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83567 states and 119801 transitions. [2021-12-22 20:30:43,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83567 to 83503. [2021-12-22 20:30:43,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83503 states, 83503 states have (on average 1.433924529657617) internal successors, (119737), 83502 states have internal predecessors, (119737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:43,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83503 states to 83503 states and 119737 transitions. [2021-12-22 20:30:43,572 INFO L704 BuchiCegarLoop]: Abstraction has 83503 states and 119737 transitions. [2021-12-22 20:30:43,572 INFO L587 BuchiCegarLoop]: Abstraction has 83503 states and 119737 transitions. [2021-12-22 20:30:43,572 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-12-22 20:30:43,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83503 states and 119737 transitions. [2021-12-22 20:30:43,831 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 83200 [2021-12-22 20:30:43,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:43,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:43,834 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:43,834 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:43,834 INFO L791 eck$LassoCheckResult]: Stem: 406768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 406769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 407825#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 407147#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 406929#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 406930#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 407022#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 407369#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 407528#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 407529#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 406198#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 406199#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 407444#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 406815#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 406816#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 406719#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 406720#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 407142#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 406446#L1174 assume !(0 == ~M_E~0); 406447#L1174-2 assume !(0 == ~T1_E~0); 406294#L1179-1 assume !(0 == ~T2_E~0); 406196#L1184-1 assume !(0 == ~T3_E~0); 406197#L1189-1 assume !(0 == ~T4_E~0); 406236#L1194-1 assume !(0 == ~T5_E~0); 406339#L1199-1 assume !(0 == ~T6_E~0); 407302#L1204-1 assume !(0 == ~T7_E~0); 407207#L1209-1 assume !(0 == ~T8_E~0); 407208#L1214-1 assume !(0 == ~T9_E~0); 407700#L1219-1 assume !(0 == ~T10_E~0); 407862#L1224-1 assume !(0 == ~T11_E~0); 406571#L1229-1 assume !(0 == ~T12_E~0); 406122#L1234-1 assume !(0 == ~E_1~0); 406123#L1239-1 assume !(0 == ~E_2~0); 406158#L1244-1 assume !(0 == ~E_3~0); 406159#L1249-1 assume !(0 == ~E_4~0); 406841#L1254-1 assume !(0 == ~E_5~0); 406055#L1259-1 assume !(0 == ~E_6~0); 406014#L1264-1 assume !(0 == ~E_7~0); 406015#L1269-1 assume !(0 == ~E_8~0); 407890#L1274-1 assume !(0 == ~E_9~0); 407744#L1279-1 assume !(0 == ~E_10~0); 406239#L1284-1 assume !(0 == ~E_11~0); 406240#L1289-1 assume !(0 == ~E_12~0); 406897#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 406898#L566 assume !(1 == ~m_pc~0); 407366#L566-2 is_master_triggered_~__retres1~0#1 := 0; 407367#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 407241#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 407242#L1455 assume !(0 != activate_threads_~tmp~1#1); 406473#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406474#L585 assume !(1 == ~t1_pc~0); 406662#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 406663#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 407172#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 407173#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 407790#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407784#L604 assume !(1 == ~t2_pc~0); 407263#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 407264#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 406753#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 406754#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 407477#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407478#L623 assume !(1 == ~t3_pc~0); 405994#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405995#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406819#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 406820#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 407521#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406028#L642 assume !(1 == ~t4_pc~0); 406029#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 406490#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 406491#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 406096#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 406097#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 407278#L661 assume !(1 == ~t5_pc~0); 407447#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 407164#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 406219#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 406220#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 407313#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 407314#L680 assume !(1 == ~t6_pc~0); 406699#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 406700#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 406976#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 406977#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 407606#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 407782#L699 assume 1 == ~t7_pc~0; 407118#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 407119#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 406247#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 406248#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 407008#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 406899#L718 assume !(1 == ~t8_pc~0); 406900#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 406234#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 406235#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406275#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 406276#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 406412#L737 assume 1 == ~t9_pc~0; 407352#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 406556#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 407198#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 407199#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 406739#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 406740#L756 assume 1 == ~t10_pc~0; 407382#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 406999#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 405960#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 405961#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 406536#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 406537#L775 assume !(1 == ~t11_pc~0); 406802#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 406803#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 406406#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 406168#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 406169#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406357#L794 assume 1 == ~t12_pc~0; 406195#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 406173#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 407472#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 406322#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 406323#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 406822#L1307 assume !(1 == ~M_E~0); 406823#L1307-2 assume !(1 == ~T1_E~0); 406945#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 406857#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 406858#L1322-1 assume !(1 == ~T4_E~0); 407078#L1327-1 assume !(1 == ~T5_E~0); 445278#L1332-1 assume !(1 == ~T6_E~0); 407798#L1337-1 assume !(1 == ~T7_E~0); 407073#L1342-1 assume !(1 == ~T8_E~0); 407074#L1347-1 assume !(1 == ~T9_E~0); 407559#L1352-1 assume !(1 == ~T10_E~0); 407392#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 406717#L1362-1 assume !(1 == ~T12_E~0); 406718#L1367-1 assume !(1 == ~E_1~0); 406340#L1372-1 assume !(1 == ~E_2~0); 406341#L1377-1 assume !(1 == ~E_3~0); 406645#L1382-1 assume !(1 == ~E_4~0); 406646#L1387-1 assume !(1 == ~E_5~0); 407265#L1392-1 assume !(1 == ~E_6~0); 406667#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 406668#L1402-1 assume !(1 == ~E_8~0); 406351#L1407-1 assume !(1 == ~E_9~0); 406352#L1412-1 assume !(1 == ~E_10~0); 407470#L1417-1 assume !(1 == ~E_11~0); 407471#L1422-1 assume !(1 == ~E_12~0); 407777#L1427-1 assume { :end_inline_reset_delta_events } true; 407778#L1768-2 [2021-12-22 20:30:43,835 INFO L793 eck$LassoCheckResult]: Loop: 407778#L1768-2 assume !false; 454091#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 454086#L1149 assume !false; 454085#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 454003#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 453996#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 453995#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 453993#L976 assume !(0 != eval_~tmp~0#1); 453994#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 474501#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 474492#L1174-3 assume !(0 == ~M_E~0); 474327#L1174-5 assume !(0 == ~T1_E~0); 474313#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 474311#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 474278#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 474266#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 474256#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 474247#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 474240#L1209-3 assume !(0 == ~T8_E~0); 474235#L1214-3 assume !(0 == ~T9_E~0); 474231#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 474229#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 474228#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 474227#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 474226#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474225#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 474224#L1249-3 assume !(0 == ~E_4~0); 474222#L1254-3 assume !(0 == ~E_5~0); 474220#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 474218#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 474216#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 474214#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 474212#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 474196#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 474194#L1289-3 assume !(0 == ~E_12~0); 474192#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474189#L566-39 assume !(1 == ~m_pc~0); 474185#L566-41 is_master_triggered_~__retres1~0#1 := 0; 474183#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 474182#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 474181#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 472922#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 454991#L585-39 assume !(1 == ~t1_pc~0); 454989#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 454987#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 454985#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 454983#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 454981#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 454979#L604-39 assume !(1 == ~t2_pc~0); 454976#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 454974#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 454972#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 454970#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 454967#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 454963#L623-39 assume !(1 == ~t3_pc~0); 430258#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 454960#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454958#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 454955#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 454953#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 454951#L642-39 assume !(1 == ~t4_pc~0); 454950#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 454947#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454945#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 454943#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 454941#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 454939#L661-39 assume !(1 == ~t5_pc~0); 454936#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 454934#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 454932#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 454930#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 454928#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 454926#L680-39 assume !(1 == ~t6_pc~0); 454924#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 454921#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 454919#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 454917#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 454915#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 454913#L699-39 assume 1 == ~t7_pc~0; 454910#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 454907#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 454905#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 454903#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 454901#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 454899#L718-39 assume !(1 == ~t8_pc~0); 454896#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 454893#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 454891#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 454889#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 454887#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 454885#L737-39 assume !(1 == ~t9_pc~0); 454882#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 454879#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 454877#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 454875#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 454873#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 454871#L756-39 assume 1 == ~t10_pc~0; 454868#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 454865#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 454863#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 454861#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 454859#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 454857#L775-39 assume !(1 == ~t11_pc~0); 454854#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 454851#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 454849#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 454847#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 454845#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 454843#L794-39 assume !(1 == ~t12_pc~0); 454839#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 454837#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 454835#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 454833#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 454831#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454829#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 454826#L1307-5 assume !(1 == ~T1_E~0); 454824#L1312-3 assume !(1 == ~T2_E~0); 448377#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 454821#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 454819#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 454817#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 454815#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 454811#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 454810#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 448362#L1352-3 assume !(1 == ~T10_E~0); 454807#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 454805#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 454803#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 454801#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 454799#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 454798#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 454796#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 452884#L1392-3 assume !(1 == ~E_6~0); 454793#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 454791#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 454789#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 454787#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 454783#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 454781#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 454779#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 454774#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 454761#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 454759#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 454757#L1787 assume !(0 == start_simulation_~tmp~3#1); 454755#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 454115#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 454104#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 454103#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 454102#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 454100#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 454098#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 454096#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 407778#L1768-2 [2021-12-22 20:30:43,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:43,836 INFO L85 PathProgramCache]: Analyzing trace with hash -1479734059, now seen corresponding path program 1 times [2021-12-22 20:30:43,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:43,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274825033] [2021-12-22 20:30:43,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:43,836 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:43,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:43,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:43,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:43,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274825033] [2021-12-22 20:30:43,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274825033] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:43,863 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:43,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:43,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273941555] [2021-12-22 20:30:43,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:43,864 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:43,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:43,864 INFO L85 PathProgramCache]: Analyzing trace with hash -533760256, now seen corresponding path program 1 times [2021-12-22 20:30:43,864 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:43,864 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842489505] [2021-12-22 20:30:43,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:43,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:43,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:43,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:43,887 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:43,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842489505] [2021-12-22 20:30:43,888 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842489505] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:43,888 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:43,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:43,888 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520238116] [2021-12-22 20:30:43,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:43,889 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:43,889 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:43,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:43,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:43,890 INFO L87 Difference]: Start difference. First operand 83503 states and 119737 transitions. cyclomatic complexity: 36250 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:45,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:45,039 INFO L93 Difference]: Finished difference Result 202214 states and 288294 transitions. [2021-12-22 20:30:45,039 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:45,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202214 states and 288294 transitions. [2021-12-22 20:30:46,248 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 198568 [2021-12-22 20:30:46,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202214 states to 202214 states and 288294 transitions. [2021-12-22 20:30:46,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202214 [2021-12-22 20:30:46,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202214 [2021-12-22 20:30:46,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 202214 states and 288294 transitions. [2021-12-22 20:30:46,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:46,934 INFO L681 BuchiCegarLoop]: Abstraction has 202214 states and 288294 transitions. [2021-12-22 20:30:47,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202214 states and 288294 transitions. [2021-12-22 20:30:48,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202214 to 159918. [2021-12-22 20:30:48,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 159918 states, 159918 states have (on average 1.429570154704286) internal successors, (228614), 159917 states have internal predecessors, (228614), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:48,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159918 states to 159918 states and 228614 transitions. [2021-12-22 20:30:48,984 INFO L704 BuchiCegarLoop]: Abstraction has 159918 states and 228614 transitions. [2021-12-22 20:30:48,984 INFO L587 BuchiCegarLoop]: Abstraction has 159918 states and 228614 transitions. [2021-12-22 20:30:48,984 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-12-22 20:30:48,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 159918 states and 228614 transitions. [2021-12-22 20:30:49,805 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 159520 [2021-12-22 20:30:49,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:30:49,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:30:49,807 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:49,808 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:30:49,808 INFO L791 eck$LassoCheckResult]: Stem: 692506#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 692507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 693624#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 692897#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 692663#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 692664#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 692760#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 693132#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 693298#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 693299#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 691926#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 691927#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 693207#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 692551#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 692552#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 692454#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 692455#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 692892#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 692173#L1174 assume !(0 == ~M_E~0); 692174#L1174-2 assume !(0 == ~T1_E~0); 692021#L1179-1 assume !(0 == ~T2_E~0); 691924#L1184-1 assume !(0 == ~T3_E~0); 691925#L1189-1 assume !(0 == ~T4_E~0); 691964#L1194-1 assume !(0 == ~T5_E~0); 692064#L1199-1 assume !(0 == ~T6_E~0); 693057#L1204-1 assume !(0 == ~T7_E~0); 692961#L1209-1 assume !(0 == ~T8_E~0); 692962#L1214-1 assume !(0 == ~T9_E~0); 693493#L1219-1 assume !(0 == ~T10_E~0); 693683#L1224-1 assume !(0 == ~T11_E~0); 692301#L1229-1 assume !(0 == ~T12_E~0); 691852#L1234-1 assume !(0 == ~E_1~0); 691853#L1239-1 assume !(0 == ~E_2~0); 691886#L1244-1 assume !(0 == ~E_3~0); 691887#L1249-1 assume !(0 == ~E_4~0); 692576#L1254-1 assume !(0 == ~E_5~0); 691782#L1259-1 assume !(0 == ~E_6~0); 691741#L1264-1 assume !(0 == ~E_7~0); 691742#L1269-1 assume !(0 == ~E_8~0); 693726#L1274-1 assume !(0 == ~E_9~0); 693547#L1279-1 assume !(0 == ~E_10~0); 691967#L1284-1 assume !(0 == ~E_11~0); 691968#L1289-1 assume !(0 == ~E_12~0); 692632#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 692633#L566 assume !(1 == ~m_pc~0); 693126#L566-2 is_master_triggered_~__retres1~0#1 := 0; 693127#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692998#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 692999#L1455 assume !(0 != activate_threads_~tmp~1#1); 692200#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692201#L585 assume !(1 == ~t1_pc~0); 692393#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 692394#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692924#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 692925#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 693589#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 693587#L604 assume !(1 == ~t2_pc~0); 693018#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 693019#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692487#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692488#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 693246#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 693247#L623 assume !(1 == ~t3_pc~0); 691721#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691722#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692555#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 692556#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 693291#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691755#L642 assume !(1 == ~t4_pc~0); 691756#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 692221#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 692222#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691826#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 691827#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 693033#L661 assume !(1 == ~t5_pc~0); 693210#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 692914#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 691947#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 691948#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 693068#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 693069#L680 assume !(1 == ~t6_pc~0); 692431#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 692432#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692710#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 692711#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 693386#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 693584#L699 assume !(1 == ~t7_pc~0); 693585#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 693152#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691975#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 691976#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 692743#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 692634#L718 assume !(1 == ~t8_pc~0); 692635#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691962#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691963#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 692004#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 692005#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692139#L737 assume 1 == ~t9_pc~0; 693111#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 692286#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 692952#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 692953#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 692472#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 692473#L756 assume 1 == ~t10_pc~0; 693141#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 692735#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 691687#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 691688#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 692265#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 692266#L775 assume !(1 == ~t11_pc~0); 692539#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 692540#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 692136#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 691896#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 691897#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 692084#L794 assume 1 == ~t12_pc~0; 691923#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 691901#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 693238#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 692050#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 692051#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 692558#L1307 assume !(1 == ~M_E~0); 692559#L1307-2 assume !(1 == ~T1_E~0); 692676#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 692590#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 692591#L1322-1 assume !(1 == ~T4_E~0); 692275#L1327-1 assume !(1 == ~T5_E~0); 692276#L1332-1 assume !(1 == ~T6_E~0); 692867#L1337-1 assume !(1 == ~T7_E~0); 692816#L1342-1 assume !(1 == ~T8_E~0); 692817#L1347-1 assume !(1 == ~T9_E~0); 693334#L1352-1 assume !(1 == ~T10_E~0); 693153#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 692450#L1362-1 assume !(1 == ~T12_E~0); 692451#L1367-1 assume !(1 == ~E_1~0); 692065#L1372-1 assume !(1 == ~E_2~0); 692066#L1377-1 assume !(1 == ~E_3~0); 692376#L1382-1 assume !(1 == ~E_4~0); 692377#L1387-1 assume !(1 == ~E_5~0); 693020#L1392-1 assume !(1 == ~E_6~0); 692399#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 692400#L1402-1 assume !(1 == ~E_8~0); 692082#L1407-1 assume !(1 == ~E_9~0); 692083#L1412-1 assume !(1 == ~E_10~0); 693236#L1417-1 assume !(1 == ~E_11~0); 693237#L1422-1 assume !(1 == ~E_12~0); 693578#L1427-1 assume { :end_inline_reset_delta_events } true; 693579#L1768-2 [2021-12-22 20:30:49,808 INFO L793 eck$LassoCheckResult]: Loop: 693579#L1768-2 assume !false; 819665#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 819660#L1149 assume !false; 819658#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 819637#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 819630#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 819628#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 819624#L976 assume !(0 != eval_~tmp~0#1); 819625#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 849695#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 849694#L1174-3 assume !(0 == ~M_E~0); 849693#L1174-5 assume !(0 == ~T1_E~0); 849692#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 849691#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 849690#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 849689#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 849686#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 849683#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 849622#L1209-3 assume !(0 == ~T8_E~0); 849618#L1214-3 assume !(0 == ~T9_E~0); 849614#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 849610#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 849606#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 849602#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 849597#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 849593#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 849589#L1249-3 assume !(0 == ~E_4~0); 849585#L1254-3 assume !(0 == ~E_5~0); 849581#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 849578#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 849575#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 849572#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 849468#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 849464#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 849460#L1289-3 assume !(0 == ~E_12~0); 849456#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 849452#L566-39 assume !(1 == ~m_pc~0); 849448#L566-41 is_master_triggered_~__retres1~0#1 := 0; 849443#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 849439#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 849435#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 849431#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 849427#L585-39 assume !(1 == ~t1_pc~0); 834622#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 849419#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 849415#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 849412#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 849409#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 849406#L604-39 assume 1 == ~t2_pc~0; 849402#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 849397#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 849394#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 849382#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 849375#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 845196#L623-39 assume !(1 == ~t3_pc~0); 845193#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 845191#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 845189#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 845187#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 845185#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 845183#L642-39 assume !(1 == ~t4_pc~0); 845180#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 845177#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 845175#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 845173#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 845171#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 845170#L661-39 assume !(1 == ~t5_pc~0); 845163#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 845019#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 844722#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 844721#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 844720#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 844719#L680-39 assume 1 == ~t6_pc~0; 844717#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 844716#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 844715#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 844714#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 844713#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 819892#L699-39 assume !(1 == ~t7_pc~0); 819890#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 819888#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 819885#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 819883#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 819881#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 819879#L718-39 assume 1 == ~t8_pc~0; 819876#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 819874#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 819871#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 819869#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 819867#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 819865#L737-39 assume 1 == ~t9_pc~0; 819862#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 819860#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 819857#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 819855#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 819853#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 819851#L756-39 assume !(1 == ~t10_pc~0); 819848#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 819846#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 819843#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 819841#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 819839#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 819837#L775-39 assume 1 == ~t11_pc~0; 819834#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 819832#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 819829#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 819827#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 819825#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 819823#L794-39 assume !(1 == ~t12_pc~0); 819820#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 819818#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 819816#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 819814#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 819813#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 819811#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 819809#L1307-5 assume !(1 == ~T1_E~0); 819807#L1312-3 assume !(1 == ~T2_E~0); 805064#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 819804#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 819802#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 819801#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 819799#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 819797#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 819795#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 810023#L1352-3 assume !(1 == ~T10_E~0); 819792#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 819790#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 819788#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 819787#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 819785#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 819783#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 819781#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 804943#L1392-3 assume !(1 == ~E_6~0); 819778#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 819776#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 819774#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 819773#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 819772#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 819758#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 819756#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 819750#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 819736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 819733#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 819729#L1787 assume !(0 == start_simulation_~tmp~3#1); 819725#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 819701#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 819693#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 819690#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 819687#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 819684#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 819681#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 819679#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 693579#L1768-2 [2021-12-22 20:30:49,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:49,809 INFO L85 PathProgramCache]: Analyzing trace with hash 339991860, now seen corresponding path program 1 times [2021-12-22 20:30:49,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:49,809 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297613301] [2021-12-22 20:30:49,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:49,810 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:49,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:49,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:49,833 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:49,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297613301] [2021-12-22 20:30:49,833 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297613301] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:49,833 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:49,833 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:49,833 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833318686] [2021-12-22 20:30:49,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:49,834 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:30:49,834 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:30:49,834 INFO L85 PathProgramCache]: Analyzing trace with hash 1832103717, now seen corresponding path program 1 times [2021-12-22 20:30:49,834 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:30:49,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [183541634] [2021-12-22 20:30:49,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:30:49,835 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:30:49,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:30:49,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:30:49,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:30:49,855 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [183541634] [2021-12-22 20:30:49,855 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [183541634] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:30:49,855 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:30:49,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:30:49,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764060514] [2021-12-22 20:30:49,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:30:49,856 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:30:49,856 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:30:49,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:30:49,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:30:49,856 INFO L87 Difference]: Start difference. First operand 159918 states and 228614 transitions. cyclomatic complexity: 68712 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:51,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:30:51,696 INFO L93 Difference]: Finished difference Result 385421 states and 547955 transitions. [2021-12-22 20:30:51,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:30:51,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385421 states and 547955 transitions. [2021-12-22 20:30:53,664 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 378368 [2021-12-22 20:30:54,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385421 states to 385421 states and 547955 transitions. [2021-12-22 20:30:54,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385421 [2021-12-22 20:30:55,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385421 [2021-12-22 20:30:55,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385421 states and 547955 transitions. [2021-12-22 20:30:55,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:30:55,170 INFO L681 BuchiCegarLoop]: Abstraction has 385421 states and 547955 transitions. [2021-12-22 20:30:55,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385421 states and 547955 transitions. [2021-12-22 20:30:58,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385421 to 305997. [2021-12-22 20:30:58,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 305997 states, 305997 states have (on average 1.4255924077687037) internal successors, (436227), 305996 states have internal predecessors, (436227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:30:59,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305997 states to 305997 states and 436227 transitions. [2021-12-22 20:30:59,732 INFO L704 BuchiCegarLoop]: Abstraction has 305997 states and 436227 transitions. [2021-12-22 20:30:59,732 INFO L587 BuchiCegarLoop]: Abstraction has 305997 states and 436227 transitions. [2021-12-22 20:30:59,732 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-12-22 20:30:59,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 305997 states and 436227 transitions. [2021-12-22 20:31:00,552 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 305408 [2021-12-22 20:31:00,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-22 20:31:00,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-22 20:31:00,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:31:00,557 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-22 20:31:00,558 INFO L791 eck$LassoCheckResult]: Stem: 1237840#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1237841#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1238881#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1238233#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1238002#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1238003#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1238097#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1238470#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1238611#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1238612#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1237274#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1237275#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1238538#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1237885#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1237886#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1237790#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1237791#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1238228#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1237515#L1174 assume !(0 == ~M_E~0); 1237516#L1174-2 assume !(0 == ~T1_E~0); 1237368#L1179-1 assume !(0 == ~T2_E~0); 1237272#L1184-1 assume !(0 == ~T3_E~0); 1237273#L1189-1 assume !(0 == ~T4_E~0); 1237311#L1194-1 assume !(0 == ~T5_E~0); 1237410#L1199-1 assume !(0 == ~T6_E~0); 1238395#L1204-1 assume !(0 == ~T7_E~0); 1238299#L1209-1 assume !(0 == ~T8_E~0); 1238300#L1214-1 assume !(0 == ~T9_E~0); 1238770#L1219-1 assume !(0 == ~T10_E~0); 1238920#L1224-1 assume !(0 == ~T11_E~0); 1237639#L1229-1 assume !(0 == ~T12_E~0); 1237201#L1234-1 assume !(0 == ~E_1~0); 1237202#L1239-1 assume !(0 == ~E_2~0); 1237234#L1244-1 assume !(0 == ~E_3~0); 1237235#L1249-1 assume !(0 == ~E_4~0); 1237910#L1254-1 assume !(0 == ~E_5~0); 1237131#L1259-1 assume !(0 == ~E_6~0); 1237090#L1264-1 assume !(0 == ~E_7~0); 1237091#L1269-1 assume !(0 == ~E_8~0); 1238941#L1274-1 assume !(0 == ~E_9~0); 1238813#L1279-1 assume !(0 == ~E_10~0); 1237314#L1284-1 assume !(0 == ~E_11~0); 1237315#L1289-1 assume !(0 == ~E_12~0); 1237971#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1237972#L566 assume !(1 == ~m_pc~0); 1238464#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1238465#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1238333#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1238334#L1455 assume !(0 != activate_threads_~tmp~1#1); 1237542#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1237543#L585 assume !(1 == ~t1_pc~0); 1237731#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1237732#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1238262#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1238263#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1238855#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1238852#L604 assume !(1 == ~t2_pc~0); 1238355#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1238356#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1237823#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1237824#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1238569#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1238570#L623 assume !(1 == ~t3_pc~0); 1237070#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1237071#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1237890#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1237891#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1238606#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1237104#L642 assume !(1 == ~t4_pc~0); 1237105#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1237561#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1237562#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1237175#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1237176#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1238369#L661 assume !(1 == ~t5_pc~0); 1238544#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1238251#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1237294#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1237295#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1238408#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1238409#L680 assume !(1 == ~t6_pc~0); 1237768#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1237769#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1238047#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1238048#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1238681#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238849#L699 assume !(1 == ~t7_pc~0); 1238850#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1238488#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1237322#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1237323#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1238083#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1237973#L718 assume !(1 == ~t8_pc~0); 1237974#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1237309#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237310#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1237351#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1237352#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1237481#L737 assume !(1 == ~t9_pc~0); 1237623#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1237624#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1238291#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1238292#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1237809#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1237810#L756 assume 1 == ~t10_pc~0; 1238479#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1238074#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1237036#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1237037#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1237604#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1237605#L775 assume !(1 == ~t11_pc~0); 1237873#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1237874#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1237478#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1237244#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1237245#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1237427#L794 assume 1 == ~t12_pc~0; 1237271#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1237249#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1238562#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1237396#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1237397#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1237893#L1307 assume !(1 == ~M_E~0); 1237894#L1307-2 assume !(1 == ~T1_E~0); 1238017#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1237925#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1237926#L1322-1 assume !(1 == ~T4_E~0); 1237613#L1327-1 assume !(1 == ~T5_E~0); 1237614#L1332-1 assume !(1 == ~T6_E~0); 1238203#L1337-1 assume !(1 == ~T7_E~0); 1238150#L1342-1 assume !(1 == ~T8_E~0); 1238151#L1347-1 assume !(1 == ~T9_E~0); 1238811#L1352-1 assume !(1 == ~T10_E~0); 1238489#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1238490#L1362-1 assume !(1 == ~T12_E~0); 1238695#L1367-1 assume !(1 == ~E_1~0); 1238696#L1372-1 assume !(1 == ~E_2~0); 1237936#L1377-1 assume !(1 == ~E_3~0); 1237937#L1382-1 assume !(1 == ~E_4~0); 1238357#L1387-1 assume !(1 == ~E_5~0); 1238358#L1392-1 assume !(1 == ~E_6~0); 1237737#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1237738#L1402-1 assume !(1 == ~E_8~0); 1237425#L1407-1 assume !(1 == ~E_9~0); 1237426#L1412-1 assume !(1 == ~E_10~0); 1238560#L1417-1 assume !(1 == ~E_11~0); 1238561#L1422-1 assume !(1 == ~E_12~0); 1238844#L1427-1 assume { :end_inline_reset_delta_events } true; 1237228#L1768-2 [2021-12-22 20:31:00,558 INFO L793 eck$LassoCheckResult]: Loop: 1237228#L1768-2 assume !false; 1237229#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1237994#L1149 assume !false; 1238435#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1238617#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1237620#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1237526#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1237527#L976 assume !(0 != eval_~tmp~0#1); 1238843#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1538315#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1538313#L1174-3 assume !(0 == ~M_E~0); 1538311#L1174-5 assume !(0 == ~T1_E~0); 1538309#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1538306#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1538304#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1538302#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1538300#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1538298#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1538296#L1209-3 assume !(0 == ~T8_E~0); 1538294#L1214-3 assume !(0 == ~T9_E~0); 1538292#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1538291#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1538289#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1538287#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1538285#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1538283#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1538281#L1249-3 assume !(0 == ~E_4~0); 1538279#L1254-3 assume !(0 == ~E_5~0); 1538278#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1538233#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1538230#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1538218#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1538214#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1538210#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1538206#L1289-3 assume !(0 == ~E_12~0); 1538201#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1538196#L566-39 assume !(1 == ~m_pc~0); 1538188#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1538181#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1538175#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1538170#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1538167#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1538165#L585-39 assume !(1 == ~t1_pc~0); 1529944#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1538164#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1538163#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1538161#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1538160#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1538159#L604-39 assume 1 == ~t2_pc~0; 1538157#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1538158#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1538162#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1538149#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1538147#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1538146#L623-39 assume !(1 == ~t3_pc~0); 1526972#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1538145#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1538143#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1538141#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1538139#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1538137#L642-39 assume !(1 == ~t4_pc~0); 1538135#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1538127#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1538124#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1538122#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1538120#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1538118#L661-39 assume !(1 == ~t5_pc~0); 1538116#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1538114#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1538111#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1538109#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1538107#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1538105#L680-39 assume !(1 == ~t6_pc~0); 1538103#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1538100#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1538097#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1538091#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1538090#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238771#L699-39 assume !(1 == ~t7_pc~0); 1238772#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1541288#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1541287#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1541286#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1541284#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1541282#L718-39 assume !(1 == ~t8_pc~0); 1541280#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1541277#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1541275#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1541274#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 1541273#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1541272#L737-39 assume !(1 == ~t9_pc~0); 1290243#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1237887#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1237888#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1238812#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1238669#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1238607#L756-39 assume 1 == ~t10_pc~0; 1238608#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1237990#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1237716#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1237717#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1237855#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1237184#L775-39 assume !(1 == ~t11_pc~0); 1237186#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1237849#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1237850#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1238918#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1238323#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1237907#L794-39 assume !(1 == ~t12_pc~0); 1237574#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1237575#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1238506#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1238383#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1237127#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1237128#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1238742#L1307-5 assume !(1 == ~T1_E~0); 1238743#L1312-3 assume !(1 == ~T2_E~0); 1238940#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1238406#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1238407#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1237260#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1237232#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1237233#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1238009#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1238140#L1352-3 assume !(1 == ~T10_E~0); 1238141#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1238677#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1238916#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1238900#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1237065#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1237066#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1237700#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1237701#L1392-3 assume !(1 == ~E_6~0); 1536398#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1536397#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1536396#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1536394#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1536392#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1536390#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1238671#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1237355#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1237356#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1238294#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1238110#L1787 assume !(0 == start_simulation_~tmp~3#1); 1238111#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1238755#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1237327#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1238165#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1238166#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1237681#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1237682#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1237683#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1237228#L1768-2 [2021-12-22 20:31:00,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:31:00,559 INFO L85 PathProgramCache]: Analyzing trace with hash -1390345197, now seen corresponding path program 1 times [2021-12-22 20:31:00,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:31:00,559 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257613698] [2021-12-22 20:31:00,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:31:00,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:31:00,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:31:00,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:31:00,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:31:00,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257613698] [2021-12-22 20:31:00,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257613698] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:31:00,591 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:31:00,591 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:31:00,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231863555] [2021-12-22 20:31:00,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:31:00,591 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-22 20:31:00,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-22 20:31:00,592 INFO L85 PathProgramCache]: Analyzing trace with hash 473515650, now seen corresponding path program 1 times [2021-12-22 20:31:00,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-22 20:31:00,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039904194] [2021-12-22 20:31:00,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-22 20:31:00,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-22 20:31:00,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-22 20:31:00,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-22 20:31:00,619 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-22 20:31:00,619 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039904194] [2021-12-22 20:31:00,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039904194] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-22 20:31:00,619 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-22 20:31:00,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-22 20:31:00,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740885516] [2021-12-22 20:31:00,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-22 20:31:00,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-22 20:31:00,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-22 20:31:00,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-22 20:31:00,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-22 20:31:00,621 INFO L87 Difference]: Start difference. First operand 305997 states and 436227 transitions. cyclomatic complexity: 130246 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-22 20:31:04,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-22 20:31:04,348 INFO L93 Difference]: Finished difference Result 735148 states and 1042496 transitions. [2021-12-22 20:31:04,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-22 20:31:04,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 735148 states and 1042496 transitions. [2021-12-22 20:31:08,459 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 721312 [2021-12-22 20:31:10,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 735148 states to 735148 states and 1042496 transitions. [2021-12-22 20:31:10,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 735148 [2021-12-22 20:31:11,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 735148 [2021-12-22 20:31:11,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 735148 states and 1042496 transitions. [2021-12-22 20:31:11,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-22 20:31:11,874 INFO L681 BuchiCegarLoop]: Abstraction has 735148 states and 1042496 transitions. [2021-12-22 20:31:12,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735148 states and 1042496 transitions.