./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version ae007674 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.2.2-dev-ae00767 [2021-12-28 09:44:04,879 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-28 09:44:04,881 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-28 09:44:04,918 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-28 09:44:04,919 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-28 09:44:04,922 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-28 09:44:04,923 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-28 09:44:04,927 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-28 09:44:04,929 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-28 09:44:04,933 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-28 09:44:04,934 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-28 09:44:04,935 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-28 09:44:04,936 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-28 09:44:04,938 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-28 09:44:04,939 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-28 09:44:04,944 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-28 09:44:04,944 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-28 09:44:04,945 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-28 09:44:04,947 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-28 09:44:04,953 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-28 09:44:04,954 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-28 09:44:04,955 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-28 09:44:04,956 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-28 09:44:04,957 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-28 09:44:04,963 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-28 09:44:04,963 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-28 09:44:04,963 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-28 09:44:04,965 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-28 09:44:04,975 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-28 09:44:04,976 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-28 09:44:04,976 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-28 09:44:04,977 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-28 09:44:04,978 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-28 09:44:04,979 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-28 09:44:04,980 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-28 09:44:04,980 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-28 09:44:04,981 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-28 09:44:04,981 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-28 09:44:04,981 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-28 09:44:04,983 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-28 09:44:04,983 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-28 09:44:04,984 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-28 09:44:05,020 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-28 09:44:05,021 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-28 09:44:05,022 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-28 09:44:05,022 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-28 09:44:05,023 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-28 09:44:05,024 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-28 09:44:05,024 INFO L138 SettingsManager]: * Use SBE=true [2021-12-28 09:44:05,024 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-28 09:44:05,024 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-28 09:44:05,024 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-28 09:44:05,025 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-28 09:44:05,025 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-28 09:44:05,026 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-28 09:44:05,026 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-28 09:44:05,026 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-28 09:44:05,026 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-28 09:44:05,026 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-28 09:44:05,027 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-28 09:44:05,028 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-28 09:44:05,028 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-28 09:44:05,028 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-28 09:44:05,028 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-28 09:44:05,028 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-28 09:44:05,029 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-28 09:44:05,029 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-28 09:44:05,029 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-28 09:44:05,030 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-28 09:44:05,030 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2021-12-28 09:44:05,326 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-28 09:44:05,352 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-28 09:44:05,356 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-28 09:44:05,357 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-28 09:44:05,357 INFO L275 PluginConnector]: CDTParser initialized [2021-12-28 09:44:05,358 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-28 09:44:05,414 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7689c3b2/661b9a7b64de406587dd8e8ba965ce6a/FLAG73dc4d3f9 [2021-12-28 09:44:05,837 INFO L306 CDTParser]: Found 1 translation units. [2021-12-28 09:44:05,838 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2021-12-28 09:44:05,848 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7689c3b2/661b9a7b64de406587dd8e8ba965ce6a/FLAG73dc4d3f9 [2021-12-28 09:44:05,862 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b7689c3b2/661b9a7b64de406587dd8e8ba965ce6a [2021-12-28 09:44:05,864 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-28 09:44:05,865 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-28 09:44:05,868 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-28 09:44:05,868 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-28 09:44:05,871 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-28 09:44:05,872 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 09:44:05" (1/1) ... [2021-12-28 09:44:05,872 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63b141c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:05, skipping insertion in model container [2021-12-28 09:44:05,872 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 09:44:05" (1/1) ... [2021-12-28 09:44:05,877 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-28 09:44:05,910 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-28 09:44:06,044 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-28 09:44:06,101 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-28 09:44:06,114 INFO L203 MainTranslator]: Completed pre-run [2021-12-28 09:44:06,174 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c[643,656] [2021-12-28 09:44:06,188 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-28 09:44:06,205 INFO L208 MainTranslator]: Completed translation [2021-12-28 09:44:06,205 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06 WrapperNode [2021-12-28 09:44:06,205 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-28 09:44:06,206 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-28 09:44:06,206 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-28 09:44:06,206 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-28 09:44:06,214 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,228 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,265 INFO L137 Inliner]: procedures = 29, calls = 31, calls flagged for inlining = 26, calls inlined = 27, statements flattened = 303 [2021-12-28 09:44:06,265 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-28 09:44:06,266 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-28 09:44:06,266 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-28 09:44:06,266 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-28 09:44:06,273 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,273 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,276 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,276 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,281 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,296 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,297 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,299 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-28 09:44:06,299 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-28 09:44:06,300 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-28 09:44:06,300 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-28 09:44:06,300 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,309 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-28 09:44:06,318 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-28 09:44:06,332 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-28 09:44:06,345 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-28 09:44:06,370 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-28 09:44:06,370 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-28 09:44:06,370 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-28 09:44:06,370 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-28 09:44:06,444 INFO L234 CfgBuilder]: Building ICFG [2021-12-28 09:44:06,448 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-28 09:44:06,741 INFO L275 CfgBuilder]: Performing block encoding [2021-12-28 09:44:06,747 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-28 09:44:06,747 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-28 09:44:06,749 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:06 BoogieIcfgContainer [2021-12-28 09:44:06,749 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-28 09:44:06,750 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-28 09:44:06,750 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-28 09:44:06,752 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-28 09:44:06,753 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:06,753 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.12 09:44:05" (1/3) ... [2021-12-28 09:44:06,754 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4edac436 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.12 09:44:06, skipping insertion in model container [2021-12-28 09:44:06,754 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:06,754 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06" (2/3) ... [2021-12-28 09:44:06,754 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4edac436 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.12 09:44:06, skipping insertion in model container [2021-12-28 09:44:06,754 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:06,754 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:06" (3/3) ... [2021-12-28 09:44:06,761 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2021-12-28 09:44:06,805 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-28 09:44:06,805 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-28 09:44:06,805 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-28 09:44:06,805 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-28 09:44:06,805 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-28 09:44:06,806 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-28 09:44:06,806 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-28 09:44:06,806 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-28 09:44:06,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:06,848 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-28 09:44:06,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:06,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:06,857 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:06,857 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:06,858 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-28 09:44:06,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:06,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-12-28 09:44:06,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:06,872 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:06,874 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:06,874 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:06,881 INFO L791 eck$LassoCheckResult]: Stem: 99#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 64#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68#L222true assume !(1 == ~q_req_up~0); 10#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 31#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 37#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86#L275true assume !(0 == ~q_read_ev~0); 93#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 105#L65true assume !(1 == ~p_dw_pc~0); 29#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 53#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 63#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34#L315true assume !(0 != activate_threads_~tmp~1#1); 65#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 97#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 71#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 90#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5#L323true assume !(0 != activate_threads_~tmp___0~1#1); 46#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98#L293true assume !(1 == ~q_read_ev~0); 3#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 35#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2021-12-28 09:44:06,882 INFO L793 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 101#L364true assume false; 60#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82#L222-3true assume !(1 == ~q_req_up~0); 32#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 38#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 52#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 61#L65-3true assume !(1 == ~p_dw_pc~0); 18#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 94#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 72#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39#L315-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 83#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 57#L84-3true assume !(1 == ~c_dr_pc~0); 88#L84-5true is_do_read_c_triggered_~__retres1~1#1 := 0; 78#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 58#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 103#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 77#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 6#L293-5true assume !(1 == ~q_write_ev~0); 51#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 55#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2021-12-28 09:44:06,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:06,888 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2021-12-28 09:44:06,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:06,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623866118] [2021-12-28 09:44:06,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:06,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:06,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [623866118] [2021-12-28 09:44:07,058 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [623866118] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,058 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,058 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:07,060 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579222493] [2021-12-28 09:44:07,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,065 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:07,067 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1951455462, now seen corresponding path program 1 times [2021-12-28 09:44:07,068 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,068 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419738011] [2021-12-28 09:44:07,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,068 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1419738011] [2021-12-28 09:44:07,106 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1419738011] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,106 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,106 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-28 09:44:07,107 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135494128] [2021-12-28 09:44:07,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,108 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:07,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:07,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:07,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:07,135 INFO L87 Difference]: Start difference. First operand has 103 states, 102 states have (on average 1.5392156862745099) internal successors, (157), 102 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:07,154 INFO L93 Difference]: Finished difference Result 101 states and 144 transitions. [2021-12-28 09:44:07,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:07,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 144 transitions. [2021-12-28 09:44:07,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-28 09:44:07,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 95 states and 138 transitions. [2021-12-28 09:44:07,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2021-12-28 09:44:07,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2021-12-28 09:44:07,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 138 transitions. [2021-12-28 09:44:07,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:07,167 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-28 09:44:07,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 138 transitions. [2021-12-28 09:44:07,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2021-12-28 09:44:07,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4526315789473685) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2021-12-28 09:44:07,193 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-28 09:44:07,193 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 138 transitions. [2021-12-28 09:44:07,193 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-28 09:44:07,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 138 transitions. [2021-12-28 09:44:07,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-12-28 09:44:07,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,195 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,196 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,196 INFO L791 eck$LassoCheckResult]: Stem: 307#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 249#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 250#L222 assume !(1 == ~q_req_up~0); 245#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 281#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 300#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 298#L275 assume !(0 == ~q_read_ev~0); 299#L275-2 assume !(0 == ~q_write_ev~0); 286#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 287#L65 assume !(1 == ~p_dw_pc~0); 284#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 283#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 241#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 242#L315 assume !(0 != activate_threads_~tmp~1#1); 251#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 252#L84 assume 1 == ~c_dr_pc~0; 291#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 262#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 263#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 224#L323 assume !(0 != activate_threads_~tmp___0~1#1); 225#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306#L293 assume !(1 == ~q_read_ev~0); 213#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 214#L298-1 assume { :end_inline_reset_delta_events } true; 247#L419-2 [2021-12-28 09:44:07,196 INFO L793 eck$LassoCheckResult]: Loop: 247#L419-2 assume !false; 248#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 236#L364 assume !false; 285#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 259#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 218#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 266#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 267#L344 assume !(0 != eval_~tmp___1~0#1); 230#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231#L222-3 assume !(1 == ~q_req_up~0); 292#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 279#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 280#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 305#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 232#L65-3 assume !(1 == ~p_dw_pc~0); 233#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 270#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 264#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 265#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 293#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 219#L84-3 assume 1 == ~c_dr_pc~0; 220#L85-1 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 278#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 222#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 223#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 276#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 228#L293-5 assume !(1 == ~q_write_ev~0); 229#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 288#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 289#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 215#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 216#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 239#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 261#L436 assume !(0 != start_simulation_~tmp~4#1); 247#L419-2 [2021-12-28 09:44:07,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,197 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2021-12-28 09:44:07,197 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,197 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301689350] [2021-12-28 09:44:07,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,198 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,249 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301689350] [2021-12-28 09:44:07,250 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301689350] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,250 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,250 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-28 09:44:07,250 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562344189] [2021-12-28 09:44:07,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,251 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:07,251 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,251 INFO L85 PathProgramCache]: Analyzing trace with hash -1517218729, now seen corresponding path program 1 times [2021-12-28 09:44:07,252 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515996568] [2021-12-28 09:44:07,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,252 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,284 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515996568] [2021-12-28 09:44:07,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515996568] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,285 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:07,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508196712] [2021-12-28 09:44:07,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,286 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:07,286 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:07,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:07,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:07,287 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. cyclomatic complexity: 44 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:07,434 INFO L93 Difference]: Finished difference Result 312 states and 446 transitions. [2021-12-28 09:44:07,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-28 09:44:07,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 446 transitions. [2021-12-28 09:44:07,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2021-12-28 09:44:07,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 446 transitions. [2021-12-28 09:44:07,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2021-12-28 09:44:07,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2021-12-28 09:44:07,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 446 transitions. [2021-12-28 09:44:07,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:07,444 INFO L681 BuchiCegarLoop]: Abstraction has 312 states and 446 transitions. [2021-12-28 09:44:07,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 446 transitions. [2021-12-28 09:44:07,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2021-12-28 09:44:07,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4429530201342282) internal successors, (430), 297 states have internal predecessors, (430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 430 transitions. [2021-12-28 09:44:07,459 INFO L704 BuchiCegarLoop]: Abstraction has 298 states and 430 transitions. [2021-12-28 09:44:07,460 INFO L587 BuchiCegarLoop]: Abstraction has 298 states and 430 transitions. [2021-12-28 09:44:07,460 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-28 09:44:07,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 430 transitions. [2021-12-28 09:44:07,463 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2021-12-28 09:44:07,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,464 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,464 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,464 INFO L791 eck$LassoCheckResult]: Stem: 729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 713#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 668#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 669#L222 assume !(1 == ~q_req_up~0); 664#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 665#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 699#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 718#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 715#L275 assume !(0 == ~q_read_ev~0); 716#L275-2 assume !(0 == ~q_write_ev~0); 704#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 705#L65 assume !(1 == ~p_dw_pc~0); 702#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 701#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 660#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 661#L315 assume !(0 != activate_threads_~tmp~1#1); 670#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 671#L84 assume !(1 == ~c_dr_pc~0); 687#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 680#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 681#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 643#L323 assume !(0 != activate_threads_~tmp___0~1#1); 644#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728#L293 assume !(1 == ~q_read_ev~0); 635#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 636#L298-1 assume { :end_inline_reset_delta_events } true; 666#L419-2 [2021-12-28 09:44:07,464 INFO L793 eck$LassoCheckResult]: Loop: 666#L419-2 assume !false; 667#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 675#L364 assume !false; 703#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 674#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 642#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 682#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 683#L344 assume !(0 != eval_~tmp___1~0#1); 692#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 928#L222-3 assume !(1 == ~q_req_up~0); 927#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 926#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 925#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 924#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 923#L65-3 assume !(1 == ~p_dw_pc~0); 921#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 723#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 724#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 726#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 710#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 711#L84-3 assume !(1 == ~c_dr_pc~0); 917#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 695#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 696#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 912#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 693#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 694#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 645#L293-5 assume !(1 == ~q_write_ev~0); 646#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 706#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 707#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 633#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 634#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 656#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 657#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 677#L436 assume !(0 != start_simulation_~tmp~4#1); 666#L419-2 [2021-12-28 09:44:07,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,465 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2021-12-28 09:44:07,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,465 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [927845238] [2021-12-28 09:44:07,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,516 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [927845238] [2021-12-28 09:44:07,516 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [927845238] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,516 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-28 09:44:07,516 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387971734] [2021-12-28 09:44:07,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,517 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:07,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,517 INFO L85 PathProgramCache]: Analyzing trace with hash -340614410, now seen corresponding path program 1 times [2021-12-28 09:44:07,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88273200] [2021-12-28 09:44:07,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,518 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88273200] [2021-12-28 09:44:07,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88273200] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,545 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,545 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:07,545 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73668159] [2021-12-28 09:44:07,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:07,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:07,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-28 09:44:07,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-28 09:44:07,548 INFO L87 Difference]: Start difference. First operand 298 states and 430 transitions. cyclomatic complexity: 134 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:07,647 INFO L93 Difference]: Finished difference Result 683 states and 957 transitions. [2021-12-28 09:44:07,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-12-28 09:44:07,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 957 transitions. [2021-12-28 09:44:07,653 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2021-12-28 09:44:07,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 957 transitions. [2021-12-28 09:44:07,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2021-12-28 09:44:07,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2021-12-28 09:44:07,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 957 transitions. [2021-12-28 09:44:07,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:07,670 INFO L681 BuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2021-12-28 09:44:07,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 957 transitions. [2021-12-28 09:44:07,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2021-12-28 09:44:07,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.4011713030746706) internal successors, (957), 682 states have internal predecessors, (957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 957 transitions. [2021-12-28 09:44:07,712 INFO L704 BuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2021-12-28 09:44:07,712 INFO L587 BuchiCegarLoop]: Abstraction has 683 states and 957 transitions. [2021-12-28 09:44:07,713 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-28 09:44:07,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 957 transitions. [2021-12-28 09:44:07,716 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2021-12-28 09:44:07,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,718 INFO L791 eck$LassoCheckResult]: Stem: 1735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 1709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1661#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1662#L222 assume !(1 == ~q_req_up~0); 1657#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1658#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1694#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1715#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1711#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1712#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1726#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1767#L65 assume !(1 == ~p_dw_pc~0); 1765#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 1764#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1763#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1762#L315 assume !(0 != activate_threads_~tmp~1#1); 1761#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1760#L84 assume !(1 == ~c_dr_pc~0); 1759#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 1758#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1757#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1756#L323 assume !(0 != activate_threads_~tmp___0~1#1); 1755#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1754#L293 assume !(1 == ~q_read_ev~0); 1753#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1724#L298-1 assume { :end_inline_reset_delta_events } true; 1725#L419-2 [2021-12-28 09:44:07,718 INFO L793 eck$LassoCheckResult]: Loop: 1725#L419-2 assume !false; 2123#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2065#L364 assume !false; 1697#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1698#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2115#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2076#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1685#L344 assume !(0 != eval_~tmp___1~0#1); 1687#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2261#L222-3 assume !(1 == ~q_req_up~0); 2258#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2255#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2227#L275-5 assume !(0 == ~q_write_ev~0); 2253#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2291#L65-3 assume !(1 == ~p_dw_pc~0); 2289#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 2288#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2287#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2284#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 2282#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2280#L84-3 assume !(1 == ~c_dr_pc~0); 2279#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2277#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2276#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2274#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2271#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2268#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2204#L293-5 assume !(1 == ~q_write_ev~0); 2201#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2197#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2195#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2193#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2143#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2139#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2135#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2131#L436 assume !(0 != start_simulation_~tmp~4#1); 1725#L419-2 [2021-12-28 09:44:07,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2021-12-28 09:44:07,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132209407] [2021-12-28 09:44:07,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,763 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132209407] [2021-12-28 09:44:07,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132209407] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,763 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,764 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:07,764 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095476392] [2021-12-28 09:44:07,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,764 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:07,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,765 INFO L85 PathProgramCache]: Analyzing trace with hash -474627916, now seen corresponding path program 1 times [2021-12-28 09:44:07,765 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,765 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659244419] [2021-12-28 09:44:07,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659244419] [2021-12-28 09:44:07,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659244419] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,826 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:07,826 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151516405] [2021-12-28 09:44:07,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,826 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:07,826 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:07,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:07,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:07,828 INFO L87 Difference]: Start difference. First operand 683 states and 957 transitions. cyclomatic complexity: 278 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:07,853 INFO L93 Difference]: Finished difference Result 952 states and 1311 transitions. [2021-12-28 09:44:07,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:07,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1311 transitions. [2021-12-28 09:44:07,869 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2021-12-28 09:44:07,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1311 transitions. [2021-12-28 09:44:07,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2021-12-28 09:44:07,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2021-12-28 09:44:07,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1311 transitions. [2021-12-28 09:44:07,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:07,876 INFO L681 BuchiCegarLoop]: Abstraction has 952 states and 1311 transitions. [2021-12-28 09:44:07,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1311 transitions. [2021-12-28 09:44:07,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2021-12-28 09:44:07,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3794117647058823) internal successors, (938), 679 states have internal predecessors, (938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 938 transitions. [2021-12-28 09:44:07,889 INFO L704 BuchiCegarLoop]: Abstraction has 680 states and 938 transitions. [2021-12-28 09:44:07,889 INFO L587 BuchiCegarLoop]: Abstraction has 680 states and 938 transitions. [2021-12-28 09:44:07,889 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-28 09:44:07,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 938 transitions. [2021-12-28 09:44:07,892 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2021-12-28 09:44:07,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,893 INFO L791 eck$LassoCheckResult]: Stem: 3379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 3352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3302#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3303#L222 assume !(1 == ~q_req_up~0); 3300#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3301#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3336#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3358#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3355#L275 assume !(0 == ~q_read_ev~0); 3356#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3371#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3394#L65 assume !(1 == ~p_dw_pc~0); 3338#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 3392#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3393#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3368#L315 assume !(0 != activate_threads_~tmp~1#1); 3369#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3375#L84 assume !(1 == ~c_dr_pc~0); 3376#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 3314#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3315#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3279#L323 assume !(0 != activate_threads_~tmp___0~1#1); 3280#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3377#L293 assume !(1 == ~q_read_ev~0); 3378#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3270#L298-1 assume { :end_inline_reset_delta_events } true; 3370#L419-2 [2021-12-28 09:44:07,894 INFO L793 eck$LassoCheckResult]: Loop: 3370#L419-2 assume !false; 3439#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3311#L364 assume !false; 3438#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3437#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3435#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3434#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3432#L344 assume !(0 != eval_~tmp___1~0#1); 3433#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3473#L222-3 assume !(1 == ~q_req_up~0); 3471#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3469#L275-3 assume !(0 == ~q_read_ev~0); 3466#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 3465#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3463#L65-3 assume !(1 == ~p_dw_pc~0); 3462#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 3461#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3460#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3459#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3458#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3457#L84-3 assume !(1 == ~c_dr_pc~0); 3456#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 3455#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3454#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3453#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3452#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3451#L293-3 assume !(1 == ~q_read_ev~0); 3450#L293-5 assume !(1 == ~q_write_ev~0); 3448#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3446#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3445#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3444#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3443#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3442#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3441#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3440#L436 assume !(0 != start_simulation_~tmp~4#1); 3370#L419-2 [2021-12-28 09:44:07,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,894 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2021-12-28 09:44:07,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,894 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457748966] [2021-12-28 09:44:07,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,922 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457748966] [2021-12-28 09:44:07,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457748966] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,923 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-28 09:44:07,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919422869] [2021-12-28 09:44:07,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,924 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:07,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,924 INFO L85 PathProgramCache]: Analyzing trace with hash -593092810, now seen corresponding path program 1 times [2021-12-28 09:44:07,924 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289257750] [2021-12-28 09:44:07,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,925 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:07,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:07,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:07,946 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:07,946 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289257750] [2021-12-28 09:44:07,946 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289257750] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:07,946 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:07,947 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:07,947 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [164735854] [2021-12-28 09:44:07,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:07,947 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:07,947 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:07,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-12-28 09:44:07,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-12-28 09:44:07,948 INFO L87 Difference]: Start difference. First operand 680 states and 938 transitions. cyclomatic complexity: 260 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:07,991 INFO L93 Difference]: Finished difference Result 830 states and 1136 transitions. [2021-12-28 09:44:07,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-12-28 09:44:07,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1136 transitions. [2021-12-28 09:44:07,998 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2021-12-28 09:44:08,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1136 transitions. [2021-12-28 09:44:08,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2021-12-28 09:44:08,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2021-12-28 09:44:08,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1136 transitions. [2021-12-28 09:44:08,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,004 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1136 transitions. [2021-12-28 09:44:08,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1136 transitions. [2021-12-28 09:44:08,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2021-12-28 09:44:08,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.3717105263157894) internal successors, (834), 607 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 834 transitions. [2021-12-28 09:44:08,015 INFO L704 BuchiCegarLoop]: Abstraction has 608 states and 834 transitions. [2021-12-28 09:44:08,015 INFO L587 BuchiCegarLoop]: Abstraction has 608 states and 834 transitions. [2021-12-28 09:44:08,015 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-28 09:44:08,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 834 transitions. [2021-12-28 09:44:08,018 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2021-12-28 09:44:08,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,019 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,019 INFO L791 eck$LassoCheckResult]: Stem: 4890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 4871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 4825#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4826#L222 assume !(1 == ~q_req_up~0); 4821#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4822#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 4856#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 4876#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4873#L275 assume !(0 == ~q_read_ev~0); 4874#L275-2 assume !(0 == ~q_write_ev~0); 4861#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 4862#L65 assume !(1 == ~p_dw_pc~0); 4858#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 4868#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 4819#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 4820#L315 assume !(0 != activate_threads_~tmp~1#1); 4827#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 4828#L84 assume !(1 == ~c_dr_pc~0); 4844#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 4837#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 4838#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4799#L323 assume !(0 != activate_threads_~tmp___0~1#1); 4800#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4888#L293 assume !(1 == ~q_read_ev~0); 4791#L293-2 assume !(1 == ~q_write_ev~0); 4792#L298-1 assume { :end_inline_reset_delta_events } true; 4885#L419-2 [2021-12-28 09:44:08,019 INFO L793 eck$LassoCheckResult]: Loop: 4885#L419-2 assume !false; 5096#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 4832#L364 assume !false; 5093#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4831#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4798#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4839#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 4840#L344 assume !(0 != eval_~tmp___1~0#1); 4850#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5373#L222-3 assume !(1 == ~q_req_up~0); 5371#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5369#L275-3 assume !(0 == ~q_read_ev~0); 5367#L275-5 assume !(0 == ~q_write_ev~0); 5364#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5360#L65-3 assume !(1 == ~p_dw_pc~0); 5358#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 5357#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5356#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5353#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5352#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5351#L84-3 assume !(1 == ~c_dr_pc~0); 5350#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 5171#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5154#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5152#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5150#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5140#L293-3 assume !(1 == ~q_read_ev~0); 5135#L293-5 assume !(1 == ~q_write_ev~0); 5133#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5129#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5127#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5125#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5123#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5121#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5113#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5108#L436 assume !(0 != start_simulation_~tmp~4#1); 4885#L419-2 [2021-12-28 09:44:08,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,020 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2021-12-28 09:44:08,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,020 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389138235] [2021-12-28 09:44:08,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,021 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,028 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,057 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,058 INFO L85 PathProgramCache]: Analyzing trace with hash -727106316, now seen corresponding path program 1 times [2021-12-28 09:44:08,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,058 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161196482] [2021-12-28 09:44:08,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,085 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,085 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161196482] [2021-12-28 09:44:08,086 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161196482] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,086 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,086 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,086 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609989051] [2021-12-28 09:44:08,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,087 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,087 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:08,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:08,088 INFO L87 Difference]: Start difference. First operand 608 states and 834 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,144 INFO L93 Difference]: Finished difference Result 919 states and 1251 transitions. [2021-12-28 09:44:08,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-28 09:44:08,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1251 transitions. [2021-12-28 09:44:08,150 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2021-12-28 09:44:08,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1251 transitions. [2021-12-28 09:44:08,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2021-12-28 09:44:08,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2021-12-28 09:44:08,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1251 transitions. [2021-12-28 09:44:08,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,157 INFO L681 BuchiCegarLoop]: Abstraction has 919 states and 1251 transitions. [2021-12-28 09:44:08,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1251 transitions. [2021-12-28 09:44:08,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2021-12-28 09:44:08,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3559055118110237) internal successors, (861), 634 states have internal predecessors, (861), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 861 transitions. [2021-12-28 09:44:08,167 INFO L704 BuchiCegarLoop]: Abstraction has 635 states and 861 transitions. [2021-12-28 09:44:08,167 INFO L587 BuchiCegarLoop]: Abstraction has 635 states and 861 transitions. [2021-12-28 09:44:08,167 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-28 09:44:08,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 861 transitions. [2021-12-28 09:44:08,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2021-12-28 09:44:08,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,171 INFO L791 eck$LassoCheckResult]: Stem: 6446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 6418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 6369#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6370#L222 assume !(1 == ~q_req_up~0); 6365#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6366#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 6402#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 6424#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6420#L275 assume !(0 == ~q_read_ev~0); 6421#L275-2 assume !(0 == ~q_write_ev~0); 6406#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6407#L65 assume !(1 == ~p_dw_pc~0); 6404#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 6414#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6363#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6364#L315 assume !(0 != activate_threads_~tmp~1#1); 6371#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6372#L84 assume !(1 == ~c_dr_pc~0); 6390#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 6381#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6382#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6343#L323 assume !(0 != activate_threads_~tmp___0~1#1); 6344#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6444#L293 assume !(1 == ~q_read_ev~0); 6334#L293-2 assume !(1 == ~q_write_ev~0); 6335#L298-1 assume { :end_inline_reset_delta_events } true; 6435#L419-2 [2021-12-28 09:44:08,171 INFO L793 eck$LassoCheckResult]: Loop: 6435#L419-2 assume !false; 6958#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 6376#L364 assume !false; 6957#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6956#L255 assume !(0 == ~p_dw_st~0); 6954#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6955#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6927#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6887#L344 assume !(0 != eval_~tmp___1~0#1); 6349#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6350#L222-3 assume !(1 == ~q_req_up~0); 6430#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6431#L275-3 assume !(0 == ~q_read_ev~0); 6438#L275-5 assume !(0 == ~q_write_ev~0); 6439#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6351#L65-3 assume !(1 == ~p_dw_pc~0); 6352#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6436#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6437#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6440#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 6441#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6339#L84-3 assume !(1 == ~c_dr_pc~0); 6340#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6398#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6399#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6459#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6460#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6433#L293-3 assume !(1 == ~q_read_ev~0); 6434#L293-5 assume !(1 == ~q_write_ev~0); 6455#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6456#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6964#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6963#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6962#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 6961#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6960#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6959#L436 assume !(0 != start_simulation_~tmp~4#1); 6435#L419-2 [2021-12-28 09:44:08,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,172 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2021-12-28 09:44:08,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971106463] [2021-12-28 09:44:08,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,179 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,187 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,188 INFO L85 PathProgramCache]: Analyzing trace with hash -366252558, now seen corresponding path program 1 times [2021-12-28 09:44:08,188 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278405180] [2021-12-28 09:44:08,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,188 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,234 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278405180] [2021-12-28 09:44:08,235 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278405180] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,235 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,235 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,235 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598199497] [2021-12-28 09:44:08,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,235 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,235 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,236 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:08,236 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:08,236 INFO L87 Difference]: Start difference. First operand 635 states and 861 transitions. cyclomatic complexity: 228 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,281 INFO L93 Difference]: Finished difference Result 1521 states and 2071 transitions. [2021-12-28 09:44:08,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-28 09:44:08,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1521 states and 2071 transitions. [2021-12-28 09:44:08,290 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1493 [2021-12-28 09:44:08,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1521 states to 1521 states and 2071 transitions. [2021-12-28 09:44:08,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1521 [2021-12-28 09:44:08,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1521 [2021-12-28 09:44:08,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1521 states and 2071 transitions. [2021-12-28 09:44:08,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,316 INFO L681 BuchiCegarLoop]: Abstraction has 1521 states and 2071 transitions. [2021-12-28 09:44:08,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1521 states and 2071 transitions. [2021-12-28 09:44:08,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1521 to 653. [2021-12-28 09:44:08,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 653 states, 653 states have (on average 1.333843797856049) internal successors, (871), 652 states have internal predecessors, (871), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 653 states to 653 states and 871 transitions. [2021-12-28 09:44:08,329 INFO L704 BuchiCegarLoop]: Abstraction has 653 states and 871 transitions. [2021-12-28 09:44:08,329 INFO L587 BuchiCegarLoop]: Abstraction has 653 states and 871 transitions. [2021-12-28 09:44:08,329 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-28 09:44:08,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 653 states and 871 transitions. [2021-12-28 09:44:08,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2021-12-28 09:44:08,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,333 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,333 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,333 INFO L791 eck$LassoCheckResult]: Stem: 8606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8585#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8538#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8539#L222 assume !(1 == ~q_req_up~0); 8534#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8535#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8571#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8591#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8589#L275 assume !(0 == ~q_read_ev~0); 8590#L275-2 assume !(0 == ~q_write_ev~0); 8574#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8575#L65 assume !(1 == ~p_dw_pc~0); 8573#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8583#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8532#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8533#L315 assume !(0 != activate_threads_~tmp~1#1); 8540#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8541#L84 assume !(1 == ~c_dr_pc~0); 8559#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8550#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8551#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8512#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8513#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8605#L293 assume !(1 == ~q_read_ev~0); 8503#L293-2 assume !(1 == ~q_write_ev~0); 8504#L298-1 assume { :end_inline_reset_delta_events } true; 8598#L419-2 [2021-12-28 09:44:08,334 INFO L793 eck$LassoCheckResult]: Loop: 8598#L419-2 assume !false; 9009#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8991#L364 assume !false; 9008#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9007#L255 assume !(0 == ~p_dw_st~0); 9005#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 9006#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9001#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9002#L344 assume !(0 != eval_~tmp___1~0#1); 9039#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9038#L222-3 assume !(1 == ~q_req_up~0); 9037#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9036#L275-3 assume !(0 == ~q_read_ev~0); 9035#L275-5 assume !(0 == ~q_write_ev~0); 9034#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9032#L65-3 assume !(1 == ~p_dw_pc~0); 9031#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 9030#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9029#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9028#L315-3 assume !(0 != activate_threads_~tmp~1#1); 9027#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9026#L84-3 assume !(1 == ~c_dr_pc~0); 9025#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 9024#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9023#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9022#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9021#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9020#L293-3 assume !(1 == ~q_read_ev~0); 9019#L293-5 assume !(1 == ~q_write_ev~0); 9018#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9016#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9015#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9014#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9013#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 9012#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9011#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9010#L436 assume !(0 != start_simulation_~tmp~4#1); 8598#L419-2 [2021-12-28 09:44:08,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2021-12-28 09:44:08,334 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,335 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400510376] [2021-12-28 09:44:08,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,335 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,341 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,350 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1934570032, now seen corresponding path program 1 times [2021-12-28 09:44:08,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,351 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19301925] [2021-12-28 09:44:08,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,352 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,376 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19301925] [2021-12-28 09:44:08,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19301925] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,377 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,377 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:08,377 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916241650] [2021-12-28 09:44:08,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,378 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,378 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:08,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:08,380 INFO L87 Difference]: Start difference. First operand 653 states and 871 transitions. cyclomatic complexity: 220 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,400 INFO L93 Difference]: Finished difference Result 936 states and 1217 transitions. [2021-12-28 09:44:08,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:08,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1217 transitions. [2021-12-28 09:44:08,409 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2021-12-28 09:44:08,414 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1217 transitions. [2021-12-28 09:44:08,414 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2021-12-28 09:44:08,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2021-12-28 09:44:08,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1217 transitions. [2021-12-28 09:44:08,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,417 INFO L681 BuchiCegarLoop]: Abstraction has 936 states and 1217 transitions. [2021-12-28 09:44:08,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1217 transitions. [2021-12-28 09:44:08,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2021-12-28 09:44:08,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 936 states, 936 states have (on average 1.3002136752136753) internal successors, (1217), 935 states have internal predecessors, (1217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1217 transitions. [2021-12-28 09:44:08,430 INFO L704 BuchiCegarLoop]: Abstraction has 936 states and 1217 transitions. [2021-12-28 09:44:08,430 INFO L587 BuchiCegarLoop]: Abstraction has 936 states and 1217 transitions. [2021-12-28 09:44:08,431 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-28 09:44:08,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1217 transitions. [2021-12-28 09:44:08,435 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2021-12-28 09:44:08,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,437 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,437 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,437 INFO L791 eck$LassoCheckResult]: Stem: 10198#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 10177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10131#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10132#L222 assume !(1 == ~q_req_up~0); 10129#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10130#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 10163#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10182#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10192#L275 assume !(0 == ~q_read_ev~0); 10845#L275-2 assume !(0 == ~q_write_ev~0); 10843#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10840#L65 assume !(1 == ~p_dw_pc~0); 10839#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 10838#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10837#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10836#L315 assume !(0 != activate_threads_~tmp~1#1); 10835#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10834#L84 assume !(1 == ~c_dr_pc~0); 10833#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 10832#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10831#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10830#L323 assume !(0 != activate_threads_~tmp___0~1#1); 10208#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10197#L293 assume !(1 == ~q_read_ev~0); 10096#L293-2 assume !(1 == ~q_write_ev~0); 10097#L298-1 assume { :end_inline_reset_delta_events } true; 10189#L419-2 [2021-12-28 09:44:08,437 INFO L793 eck$LassoCheckResult]: Loop: 10189#L419-2 assume !false; 10957#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10140#L364 assume !false; 10169#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10139#L255 assume !(0 == ~p_dw_st~0); 10100#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10102#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10223#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10221#L344 assume !(0 != eval_~tmp___1~0#1); 10222#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11012#L222-3 assume !(1 == ~q_req_up~0); 11010#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11008#L275-3 assume !(0 == ~q_read_ev~0); 11006#L275-5 assume !(0 == ~q_write_ev~0); 11004#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 11002#L65-3 assume !(1 == ~p_dw_pc~0); 11000#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 10998#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10996#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10993#L315-3 assume !(0 != activate_threads_~tmp~1#1); 10991#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10990#L84-3 assume !(1 == ~c_dr_pc~0); 10987#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 10985#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10983#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10981#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10979#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10977#L293-3 assume !(1 == ~q_read_ev~0); 10975#L293-5 assume !(1 == ~q_write_ev~0); 10974#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10972#L255-1 assume !(0 == ~p_dw_st~0); 10970#L259-1 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10968#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10966#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10964#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10963#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10961#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10959#L436 assume !(0 != start_simulation_~tmp~4#1); 10189#L419-2 [2021-12-28 09:44:08,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1194945487, now seen corresponding path program 1 times [2021-12-28 09:44:08,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063591419] [2021-12-28 09:44:08,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,460 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063591419] [2021-12-28 09:44:08,460 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063591419] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,460 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,460 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:08,460 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029293216] [2021-12-28 09:44:08,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,461 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:08,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,461 INFO L85 PathProgramCache]: Analyzing trace with hash -282414912, now seen corresponding path program 1 times [2021-12-28 09:44:08,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,461 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394160992] [2021-12-28 09:44:08,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,462 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,500 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394160992] [2021-12-28 09:44:08,500 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394160992] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,500 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,500 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,500 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844373146] [2021-12-28 09:44:08,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,501 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,501 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,501 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:08,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:08,502 INFO L87 Difference]: Start difference. First operand 936 states and 1217 transitions. cyclomatic complexity: 284 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,509 INFO L93 Difference]: Finished difference Result 915 states and 1193 transitions. [2021-12-28 09:44:08,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:08,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 915 states and 1193 transitions. [2021-12-28 09:44:08,514 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2021-12-28 09:44:08,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 915 states to 915 states and 1193 transitions. [2021-12-28 09:44:08,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 915 [2021-12-28 09:44:08,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 915 [2021-12-28 09:44:08,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 915 states and 1193 transitions. [2021-12-28 09:44:08,520 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,520 INFO L681 BuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2021-12-28 09:44:08,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 915 states and 1193 transitions. [2021-12-28 09:44:08,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 915 to 915. [2021-12-28 09:44:08,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 915 states, 915 states have (on average 1.303825136612022) internal successors, (1193), 914 states have internal predecessors, (1193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 915 states to 915 states and 1193 transitions. [2021-12-28 09:44:08,545 INFO L704 BuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2021-12-28 09:44:08,545 INFO L587 BuchiCegarLoop]: Abstraction has 915 states and 1193 transitions. [2021-12-28 09:44:08,545 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-28 09:44:08,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 915 states and 1193 transitions. [2021-12-28 09:44:08,549 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 879 [2021-12-28 09:44:08,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,550 INFO L791 eck$LassoCheckResult]: Stem: 12063#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12043#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 11991#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11992#L222 assume !(1 == ~q_req_up~0); 11989#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11990#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12026#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12049#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12047#L275 assume !(0 == ~q_read_ev~0); 12048#L275-2 assume !(0 == ~q_write_ev~0); 12029#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12030#L65 assume !(1 == ~p_dw_pc~0); 12028#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12041#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 11984#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11985#L315 assume !(0 != activate_threads_~tmp~1#1); 11995#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 11996#L84 assume !(1 == ~c_dr_pc~0); 12013#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 12003#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12004#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11967#L323 assume !(0 != activate_threads_~tmp___0~1#1); 11968#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12062#L293 assume !(1 == ~q_read_ev~0); 11956#L293-2 assume !(1 == ~q_write_ev~0); 11957#L298-1 assume { :end_inline_reset_delta_events } true; 11993#L419-2 assume !false; 11994#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12762#L364 [2021-12-28 09:44:08,551 INFO L793 eck$LassoCheckResult]: Loop: 12762#L364 assume !false; 12031#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12032#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12806#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12805#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12803#L344 assume 0 != eval_~tmp___1~0#1; 12098#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 12017#L353 assume !(0 != eval_~tmp~2#1); 12019#L349 assume !(0 == ~c_dr_st~0); 12762#L364 [2021-12-28 09:44:08,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,551 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 1 times [2021-12-28 09:44:08,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607978672] [2021-12-28 09:44:08,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,557 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,565 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,565 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,565 INFO L85 PathProgramCache]: Analyzing trace with hash -479000201, now seen corresponding path program 1 times [2021-12-28 09:44:08,565 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,565 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824656687] [2021-12-28 09:44:08,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,566 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,568 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,574 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,574 INFO L85 PathProgramCache]: Analyzing trace with hash 519639655, now seen corresponding path program 1 times [2021-12-28 09:44:08,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972012847] [2021-12-28 09:44:08,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,575 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,599 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,600 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972012847] [2021-12-28 09:44:08,600 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972012847] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,600 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,600 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-28 09:44:08,600 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179128644] [2021-12-28 09:44:08,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,647 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:08,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:08,648 INFO L87 Difference]: Start difference. First operand 915 states and 1193 transitions. cyclomatic complexity: 281 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,668 INFO L93 Difference]: Finished difference Result 1272 states and 1634 transitions. [2021-12-28 09:44:08,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:08,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1272 states and 1634 transitions. [2021-12-28 09:44:08,675 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2021-12-28 09:44:08,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1272 states to 1272 states and 1634 transitions. [2021-12-28 09:44:08,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1272 [2021-12-28 09:44:08,681 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1272 [2021-12-28 09:44:08,681 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1272 states and 1634 transitions. [2021-12-28 09:44:08,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,682 INFO L681 BuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2021-12-28 09:44:08,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1272 states and 1634 transitions. [2021-12-28 09:44:08,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1272 to 1272. [2021-12-28 09:44:08,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1272 states, 1272 states have (on average 1.2845911949685536) internal successors, (1634), 1271 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1272 states to 1272 states and 1634 transitions. [2021-12-28 09:44:08,699 INFO L704 BuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2021-12-28 09:44:08,699 INFO L587 BuchiCegarLoop]: Abstraction has 1272 states and 1634 transitions. [2021-12-28 09:44:08,699 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-12-28 09:44:08,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1272 states and 1634 transitions. [2021-12-28 09:44:08,704 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1236 [2021-12-28 09:44:08,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,705 INFO L791 eck$LassoCheckResult]: Stem: 14255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 14235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 14185#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14186#L222 assume !(1 == ~q_req_up~0); 14183#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14184#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 14220#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 14242#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14240#L275 assume !(0 == ~q_read_ev~0); 14241#L275-2 assume !(0 == ~q_write_ev~0); 14223#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 14224#L65 assume !(1 == ~p_dw_pc~0); 14222#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 14232#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 14178#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14179#L315 assume !(0 != activate_threads_~tmp~1#1); 14189#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 14190#L84 assume !(1 == ~c_dr_pc~0); 14207#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 14198#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 14199#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14161#L323 assume !(0 != activate_threads_~tmp___0~1#1); 14162#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14254#L293 assume !(1 == ~q_read_ev~0); 14151#L293-2 assume !(1 == ~q_write_ev~0); 14152#L298-1 assume { :end_inline_reset_delta_events } true; 14249#L419-2 assume !false; 14945#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 14663#L364 [2021-12-28 09:44:08,705 INFO L793 eck$LassoCheckResult]: Loop: 14663#L364 assume !false; 14676#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14673#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14671#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14669#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 14668#L344 assume 0 != eval_~tmp___1~0#1; 14667#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 14665#L353 assume !(0 != eval_~tmp~2#1); 14664#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 14662#L368 assume !(0 != eval_~tmp___0~2#1); 14663#L364 [2021-12-28 09:44:08,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,706 INFO L85 PathProgramCache]: Analyzing trace with hash 219097361, now seen corresponding path program 2 times [2021-12-28 09:44:08,706 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,706 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552901388] [2021-12-28 09:44:08,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,707 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,711 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,718 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,718 INFO L85 PathProgramCache]: Analyzing trace with hash -1964106000, now seen corresponding path program 1 times [2021-12-28 09:44:08,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,719 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244055028] [2021-12-28 09:44:08,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,722 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,726 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:08,727 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,727 INFO L85 PathProgramCache]: Analyzing trace with hash -1071041536, now seen corresponding path program 1 times [2021-12-28 09:44:08,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655421253] [2021-12-28 09:44:08,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,727 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,731 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:08,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:08,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,558 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.12 09:44:09 BoogieIcfgContainer [2021-12-28 09:44:09,559 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-28 09:44:09,559 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-28 09:44:09,559 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-28 09:44:09,559 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-28 09:44:09,560 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:06" (3/4) ... [2021-12-28 09:44:09,561 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-28 09:44:09,591 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-28 09:44:09,591 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-28 09:44:09,592 INFO L158 Benchmark]: Toolchain (without parser) took 3726.33ms. Allocated memory was 65.0MB in the beginning and 98.6MB in the end (delta: 33.6MB). Free memory was 45.3MB in the beginning and 58.2MB in the end (delta: -12.9MB). Peak memory consumption was 19.1MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,592 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 65.0MB. Free memory was 45.8MB in the beginning and 45.7MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-28 09:44:09,592 INFO L158 Benchmark]: CACSL2BoogieTranslator took 337.36ms. Allocated memory is still 65.0MB. Free memory was 45.2MB in the beginning and 46.6MB in the end (delta: -1.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,593 INFO L158 Benchmark]: Boogie Procedure Inliner took 59.22ms. Allocated memory is still 65.0MB. Free memory was 46.6MB in the beginning and 44.3MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,593 INFO L158 Benchmark]: Boogie Preprocessor took 32.65ms. Allocated memory is still 65.0MB. Free memory was 44.3MB in the beginning and 42.7MB in the end (delta: 1.6MB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-28 09:44:09,593 INFO L158 Benchmark]: RCFGBuilder took 449.79ms. Allocated memory is still 65.0MB. Free memory was 42.5MB in the beginning and 44.1MB in the end (delta: -1.7MB). Peak memory consumption was 16.9MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,593 INFO L158 Benchmark]: BuchiAutomizer took 2808.90ms. Allocated memory was 65.0MB in the beginning and 98.6MB in the end (delta: 33.6MB). Free memory was 43.8MB in the beginning and 61.5MB in the end (delta: -17.7MB). Peak memory consumption was 49.4MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,594 INFO L158 Benchmark]: Witness Printer took 32.11ms. Allocated memory is still 98.6MB. Free memory was 61.5MB in the beginning and 58.2MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-28 09:44:09,595 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 65.0MB. Free memory was 45.8MB in the beginning and 45.7MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 337.36ms. Allocated memory is still 65.0MB. Free memory was 45.2MB in the beginning and 46.6MB in the end (delta: -1.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 59.22ms. Allocated memory is still 65.0MB. Free memory was 46.6MB in the beginning and 44.3MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 32.65ms. Allocated memory is still 65.0MB. Free memory was 44.3MB in the beginning and 42.7MB in the end (delta: 1.6MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 449.79ms. Allocated memory is still 65.0MB. Free memory was 42.5MB in the beginning and 44.1MB in the end (delta: -1.7MB). Peak memory consumption was 16.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 2808.90ms. Allocated memory was 65.0MB in the beginning and 98.6MB in the end (delta: 33.6MB). Free memory was 43.8MB in the beginning and 61.5MB in the end (delta: -17.7MB). Peak memory consumption was 49.4MB. Max. memory is 16.1GB. * Witness Printer took 32.11ms. Allocated memory is still 98.6MB. Free memory was 61.5MB in the beginning and 58.2MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1272 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.7s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.7s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 10 MinimizatonAttempts, 1660 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had 1272 states and ocurred in iteration 10. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1997 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1997 mSDsluCounter, 3046 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1683 mSDsCounter, 72 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 229 IncrementalHoareTripleChecker+Invalid, 301 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 72 mSolverCounterUnsat, 1363 mSDtfsCounter, 229 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25f4847f=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f892135=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@519ea3a6=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57f664e7=0, p_dw_pc=0, q_free=1, __retres1=1, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f77b4d6=0, kernel_st=1, p_num_write=0, q_buf_0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6dcdf36e=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) [L280] COND FALSE !((int )q_write_ev == 0) [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; [L65] COND FALSE !((int )p_dw_pc == 1) [L75] __retres1 = 0 [L77] return (__retres1); [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; [L84] COND FALSE !((int )c_dr_pc == 1) [L94] __retres1 = 0 [L96] return (__retres1); [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) [L298] COND FALSE !((int )q_write_ev == 1) [L416] RET reset_delta_events() [L419] COND TRUE 1 [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-28 09:44:09,638 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)