./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version ae007674 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-ae00767 [2021-12-28 09:44:06,017 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-12-28 09:44:06,019 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-12-28 09:44:06,050 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-12-28 09:44:06,050 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-12-28 09:44:06,051 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-12-28 09:44:06,052 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-12-28 09:44:06,053 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-12-28 09:44:06,055 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-12-28 09:44:06,059 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-12-28 09:44:06,060 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-12-28 09:44:06,061 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-12-28 09:44:06,062 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-12-28 09:44:06,064 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-12-28 09:44:06,065 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-12-28 09:44:06,069 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-12-28 09:44:06,071 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-12-28 09:44:06,072 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-12-28 09:44:06,073 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-12-28 09:44:06,078 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-12-28 09:44:06,079 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-12-28 09:44:06,079 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-12-28 09:44:06,080 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-12-28 09:44:06,081 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-12-28 09:44:06,086 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-12-28 09:44:06,086 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-12-28 09:44:06,087 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-12-28 09:44:06,097 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-12-28 09:44:06,097 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-12-28 09:44:06,098 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-12-28 09:44:06,098 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-12-28 09:44:06,099 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-12-28 09:44:06,100 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-12-28 09:44:06,100 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-12-28 09:44:06,101 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-12-28 09:44:06,101 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-12-28 09:44:06,102 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-12-28 09:44:06,102 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-12-28 09:44:06,102 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-12-28 09:44:06,103 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-12-28 09:44:06,104 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-12-28 09:44:06,105 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-12-28 09:44:06,131 INFO L113 SettingsManager]: Loading preferences was successful [2021-12-28 09:44:06,132 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-12-28 09:44:06,132 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-12-28 09:44:06,133 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-12-28 09:44:06,134 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-12-28 09:44:06,134 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-12-28 09:44:06,135 INFO L138 SettingsManager]: * Use SBE=true [2021-12-28 09:44:06,135 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-12-28 09:44:06,135 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-12-28 09:44:06,135 INFO L138 SettingsManager]: * Use old map elimination=false [2021-12-28 09:44:06,136 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-12-28 09:44:06,136 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-12-28 09:44:06,136 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-12-28 09:44:06,136 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-12-28 09:44:06,136 INFO L138 SettingsManager]: * sizeof long=4 [2021-12-28 09:44:06,136 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * sizeof long double=12 [2021-12-28 09:44:06,137 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-12-28 09:44:06,138 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-12-28 09:44:06,138 INFO L138 SettingsManager]: * Use constant arrays=true [2021-12-28 09:44:06,138 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-12-28 09:44:06,138 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-12-28 09:44:06,138 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-12-28 09:44:06,138 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-12-28 09:44:06,138 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-12-28 09:44:06,140 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-12-28 09:44:06,140 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2021-12-28 09:44:06,410 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-12-28 09:44:06,435 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-12-28 09:44:06,436 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-12-28 09:44:06,437 INFO L271 PluginConnector]: Initializing CDTParser... [2021-12-28 09:44:06,438 INFO L275 PluginConnector]: CDTParser initialized [2021-12-28 09:44:06,439 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-28 09:44:06,484 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d7085f1e/dc21744f258547918bfa4adeb5bffbf2/FLAG97618160a [2021-12-28 09:44:06,873 INFO L306 CDTParser]: Found 1 translation units. [2021-12-28 09:44:06,874 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2021-12-28 09:44:06,880 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d7085f1e/dc21744f258547918bfa4adeb5bffbf2/FLAG97618160a [2021-12-28 09:44:06,894 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7d7085f1e/dc21744f258547918bfa4adeb5bffbf2 [2021-12-28 09:44:06,895 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-12-28 09:44:06,897 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-12-28 09:44:06,899 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-12-28 09:44:06,899 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-12-28 09:44:06,901 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-12-28 09:44:06,902 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,903 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@136a1d7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:06, skipping insertion in model container [2021-12-28 09:44:06,903 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.12 09:44:06" (1/1) ... [2021-12-28 09:44:06,907 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-12-28 09:44:06,942 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-12-28 09:44:07,054 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-28 09:44:07,120 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-28 09:44:07,142 INFO L203 MainTranslator]: Completed pre-run [2021-12-28 09:44:07,155 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2021-12-28 09:44:07,182 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-12-28 09:44:07,197 INFO L208 MainTranslator]: Completed translation [2021-12-28 09:44:07,197 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07 WrapperNode [2021-12-28 09:44:07,198 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-12-28 09:44:07,198 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-12-28 09:44:07,199 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-12-28 09:44:07,199 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-12-28 09:44:07,203 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,222 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,256 INFO L137 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2021-12-28 09:44:07,258 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-12-28 09:44:07,258 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-12-28 09:44:07,259 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-12-28 09:44:07,259 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-12-28 09:44:07,264 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,265 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,271 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,271 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,283 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,293 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,296 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,301 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-12-28 09:44:07,302 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-12-28 09:44:07,303 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-12-28 09:44:07,303 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-12-28 09:44:07,304 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (1/1) ... [2021-12-28 09:44:07,308 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-12-28 09:44:07,316 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-12-28 09:44:07,330 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-12-28 09:44:07,353 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-12-28 09:44:07,386 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-12-28 09:44:07,387 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-12-28 09:44:07,387 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-12-28 09:44:07,387 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-12-28 09:44:07,461 INFO L234 CfgBuilder]: Building ICFG [2021-12-28 09:44:07,466 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2021-12-28 09:44:07,882 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2021-12-28 09:44:07,883 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2021-12-28 09:44:07,883 INFO L275 CfgBuilder]: Performing block encoding [2021-12-28 09:44:07,887 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-12-28 09:44:07,888 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2021-12-28 09:44:07,889 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:07 BoogieIcfgContainer [2021-12-28 09:44:07,889 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-12-28 09:44:07,890 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-12-28 09:44:07,890 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-12-28 09:44:07,891 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-12-28 09:44:07,892 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:07,892 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.12 09:44:06" (1/3) ... [2021-12-28 09:44:07,893 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0ed256 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.12 09:44:07, skipping insertion in model container [2021-12-28 09:44:07,893 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:07,893 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.12 09:44:07" (2/3) ... [2021-12-28 09:44:07,893 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0ed256 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.12 09:44:07, skipping insertion in model container [2021-12-28 09:44:07,893 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-12-28 09:44:07,893 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:07" (3/3) ... [2021-12-28 09:44:07,894 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2021-12-28 09:44:07,918 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-12-28 09:44:07,919 INFO L360 BuchiCegarLoop]: Hoare is false [2021-12-28 09:44:07,919 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-12-28 09:44:07,919 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-12-28 09:44:07,919 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-12-28 09:44:07,919 INFO L364 BuchiCegarLoop]: Difference is false [2021-12-28 09:44:07,919 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-12-28 09:44:07,919 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-12-28 09:44:07,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-28 09:44:07,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,957 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,957 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,957 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-12-28 09:44:07,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:07,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-12-28 09:44:07,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:07,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:07,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,976 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:07,980 INFO L791 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 39#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 29#L551true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31#L258true assume !(1 == ~q_req_up~0); 68#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 109#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 97#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48#L311true assume !(0 == ~q_read_ev~0); 98#L311-2true assume !(0 == ~q_write_ev~0); 76#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 35#L66true assume 1 == ~p_dw_pc~0; 130#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 90#L88true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 103#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 82#L95true assume 1 == ~c_dr_pc~0; 116#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 27#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7#L117true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 77#L395true assume !(0 != activate_threads_~tmp___0~1#1); 14#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 37#L334-1true assume { :end_inline_reset_delta_events } true; 127#L491-2true [2021-12-28 09:44:07,981 INFO L793 eck$LassoCheckResult]: Loop: 127#L491-2true assume !false; 128#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 94#L435true assume !true; 144#L451true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 106#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 110#L311-5true assume !(0 == ~q_write_ev~0); 69#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 108#L66-3true assume 1 == ~p_dw_pc~0; 91#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 11#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 126#L88-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 121#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 36#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 124#L95-3true assume 1 == ~c_dr_pc~0; 64#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 100#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 95#L117-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 85#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 140#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 101#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 102#L304-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 78#L510true assume !(0 == start_simulation_~tmp~4#1); 8#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 73#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 89#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 93#L304-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 34#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137#L473true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 75#L523true assume !(0 != start_simulation_~tmp___0~3#1); 127#L491-2true [2021-12-28 09:44:07,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:07,986 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2021-12-28 09:44:07,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:07,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687104615] [2021-12-28 09:44:07,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:07,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,146 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,146 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687104615] [2021-12-28 09:44:08,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687104615] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,147 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,147 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:08,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581277342] [2021-12-28 09:44:08,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,152 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:08,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,154 INFO L85 PathProgramCache]: Analyzing trace with hash 784504738, now seen corresponding path program 1 times [2021-12-28 09:44:08,154 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,154 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585517892] [2021-12-28 09:44:08,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,185 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585517892] [2021-12-28 09:44:08,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585517892] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,186 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-28 09:44:08,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778873996] [2021-12-28 09:44:08,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,188 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,188 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,214 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:08,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:08,217 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,253 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2021-12-28 09:44:08,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:08,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2021-12-28 09:44:08,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-28 09:44:08,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2021-12-28 09:44:08,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2021-12-28 09:44:08,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2021-12-28 09:44:08,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2021-12-28 09:44:08,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,270 INFO L681 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-28 09:44:08,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2021-12-28 09:44:08,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2021-12-28 09:44:08,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2021-12-28 09:44:08,298 INFO L704 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-28 09:44:08,298 INFO L587 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2021-12-28 09:44:08,298 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-12-28 09:44:08,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2021-12-28 09:44:08,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-12-28 09:44:08,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,302 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,302 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,303 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 336#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 387#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 410#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#L311 assume !(0 == ~q_read_ev~0); 366#L311-2 assume !(0 == ~q_write_ev~0); 396#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 345#L66 assume 1 == ~p_dw_pc~0; 347#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 380#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 375#L387 assume !(0 != activate_threads_~tmp~1#1); 376#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 400#L95 assume 1 == ~c_dr_pc~0; 402#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 333#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 298#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 299#L395 assume !(0 != activate_threads_~tmp___0~1#1); 311#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 344#L329-2 assume !(1 == ~q_write_ev~0); 350#L334-1 assume { :end_inline_reset_delta_events } true; 351#L491-2 [2021-12-28 09:44:08,306 INFO L793 eck$LassoCheckResult]: Loop: 351#L491-2 assume !false; 423#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 352#L435 assume !false; 381#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 382#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 411#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 412#L415 assume !(0 != eval_~tmp___1~0#1); 420#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#L258-3 assume !(1 == ~q_req_up~0); 385#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 418#L311-5 assume !(0 == ~q_write_ev~0); 393#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 394#L66-3 assume 1 == ~p_dw_pc~0; 406#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 308#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 422#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 348#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 349#L95-3 assume 1 == ~c_dr_pc~0; 389#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 390#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 408#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 409#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 361#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 403#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 372#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 373#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 413#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 335#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 405#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 407#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 342#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 395#L523 assume !(0 != start_simulation_~tmp___0~3#1); 351#L491-2 [2021-12-28 09:44:08,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2021-12-28 09:44:08,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080041198] [2021-12-28 09:44:08,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,378 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080041198] [2021-12-28 09:44:08,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080041198] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,379 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,379 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-28 09:44:08,379 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605687879] [2021-12-28 09:44:08,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,379 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:08,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,380 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2021-12-28 09:44:08,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840704608] [2021-12-28 09:44:08,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,412 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,412 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840704608] [2021-12-28 09:44:08,413 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840704608] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,413 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,413 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,413 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [233918015] [2021-12-28 09:44:08,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,413 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,414 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:08,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:08,415 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,607 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2021-12-28 09:44:08,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-28 09:44:08,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 696 transitions. [2021-12-28 09:44:08,610 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2021-12-28 09:44:08,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 696 transitions. [2021-12-28 09:44:08,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2021-12-28 09:44:08,614 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2021-12-28 09:44:08,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 696 transitions. [2021-12-28 09:44:08,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,616 INFO L681 BuchiCegarLoop]: Abstraction has 479 states and 696 transitions. [2021-12-28 09:44:08,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 696 transitions. [2021-12-28 09:44:08,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 466. [2021-12-28 09:44:08,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 683 transitions. [2021-12-28 09:44:08,634 INFO L704 BuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2021-12-28 09:44:08,634 INFO L587 BuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2021-12-28 09:44:08,634 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-12-28 09:44:08,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 683 transitions. [2021-12-28 09:44:08,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2021-12-28 09:44:08,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,637 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,637 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,637 INFO L791 eck$LassoCheckResult]: Stem: 1065#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 967#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 968#L258 assume !(1 == ~q_req_up~0); 971#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1014#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1015#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1046#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 994#L311 assume !(0 == ~q_read_ev~0); 995#L311-2 assume !(0 == ~q_write_ev~0); 1026#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 975#L66 assume !(1 == ~p_dw_pc~0); 976#L66-2 assume !(2 == ~p_dw_pc~0); 987#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1007#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1008#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1003#L387 assume !(0 != activate_threads_~tmp~1#1); 1004#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1031#L95 assume 1 == ~c_dr_pc~0; 1033#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 964#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 926#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 927#L395 assume !(0 != activate_threads_~tmp___0~1#1); 939#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 972#L329-2 assume !(1 == ~q_write_ev~0); 979#L334-1 assume { :end_inline_reset_delta_events } true; 980#L491-2 [2021-12-28 09:44:08,637 INFO L793 eck$LassoCheckResult]: Loop: 980#L491-2 assume !false; 1064#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 981#L435 assume !false; 1009#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1010#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 925#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1047#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1048#L415 assume !(0 != eval_~tmp___1~0#1); 1056#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1012#L258-3 assume !(1 == ~q_req_up~0); 1013#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1051#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1054#L311-5 assume !(0 == ~q_write_ev~0); 1021#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1022#L66-3 assume !(1 == ~p_dw_pc~0); 999#L66-5 assume !(2 == ~p_dw_pc~0); 930#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 931#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 935#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1061#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 977#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 978#L95-3 assume 1 == ~c_dr_pc~0; 1017#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1018#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1044#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1045#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1066#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1328#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1327#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1326#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1325#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1323#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1322#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1321#L510 assume !(0 == start_simulation_~tmp~4#1); 928#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 929#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 966#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1039#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1043#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 973#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 974#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1025#L523 assume !(0 != start_simulation_~tmp___0~3#1); 980#L491-2 [2021-12-28 09:44:08,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,638 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2021-12-28 09:44:08,638 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340733136] [2021-12-28 09:44:08,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,638 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,686 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340733136] [2021-12-28 09:44:08,686 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340733136] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,686 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,687 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-12-28 09:44:08,687 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363726768] [2021-12-28 09:44:08,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,687 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:08,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2021-12-28 09:44:08,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,689 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515958139] [2021-12-28 09:44:08,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,690 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,730 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515958139] [2021-12-28 09:44:08,730 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515958139] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,730 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,730 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,730 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762583094] [2021-12-28 09:44:08,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,731 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,731 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:08,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:08,731 INFO L87 Difference]: Start difference. First operand 466 states and 683 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:08,855 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2021-12-28 09:44:08,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-28 09:44:08,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1581 transitions. [2021-12-28 09:44:08,861 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1070 [2021-12-28 09:44:08,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1581 transitions. [2021-12-28 09:44:08,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2021-12-28 09:44:08,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2021-12-28 09:44:08,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1581 transitions. [2021-12-28 09:44:08,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:08,873 INFO L681 BuchiCegarLoop]: Abstraction has 1105 states and 1581 transitions. [2021-12-28 09:44:08,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1581 transitions. [2021-12-28 09:44:08,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1072. [2021-12-28 09:44:08,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:08,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1538 transitions. [2021-12-28 09:44:08,900 INFO L704 BuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2021-12-28 09:44:08,900 INFO L587 BuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2021-12-28 09:44:08,900 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-12-28 09:44:08,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1072 states and 1538 transitions. [2021-12-28 09:44:08,903 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1038 [2021-12-28 09:44:08,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:08,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:08,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,905 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:08,906 INFO L791 eck$LassoCheckResult]: Stem: 2664#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 2569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2555#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2556#L258 assume !(1 == ~q_req_up~0); 2557#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2603#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2604#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2642#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2581#L311 assume !(0 == ~q_read_ev~0); 2582#L311-2 assume !(0 == ~q_write_ev~0); 2618#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2563#L66 assume !(1 == ~p_dw_pc~0); 2564#L66-2 assume !(2 == ~p_dw_pc~0); 2574#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 2599#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2600#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2593#L387 assume !(0 != activate_threads_~tmp~1#1); 2594#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2626#L95 assume !(1 == ~c_dr_pc~0); 2627#L95-2 assume !(2 == ~c_dr_pc~0); 2605#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 2550#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2511#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2512#L395 assume !(0 != activate_threads_~tmp___0~1#1); 2526#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2527#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2560#L329-2 assume !(1 == ~q_write_ev~0); 2567#L334-1 assume { :end_inline_reset_delta_events } true; 2568#L491-2 [2021-12-28 09:44:08,906 INFO L793 eck$LassoCheckResult]: Loop: 2568#L491-2 assume !false; 2663#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2565#L435 assume !false; 2597#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2598#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2510#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2647#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2648#L415 assume !(0 != eval_~tmp___1~0#1); 2655#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3311#L258-3 assume !(1 == ~q_req_up~0); 3312#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3532#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 3531#L311-5 assume !(0 == ~q_write_ev~0); 3530#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3529#L66-3 assume !(1 == ~p_dw_pc~0); 2585#L66-5 assume !(2 == ~p_dw_pc~0); 2586#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 3576#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3575#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3574#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3573#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3571#L95-3 assume !(1 == ~c_dr_pc~0); 3570#L95-5 assume !(2 == ~c_dr_pc~0); 3569#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 3568#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2640#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2641#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2534#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2535#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2573#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2666#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2590#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2591#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3365#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3363#L510 assume !(0 == start_simulation_~tmp~4#1); 3361#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3360#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3358#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3356#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3354#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3353#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3352#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3351#L523 assume !(0 != start_simulation_~tmp___0~3#1); 2568#L491-2 [2021-12-28 09:44:08,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,907 INFO L85 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2021-12-28 09:44:08,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463036566] [2021-12-28 09:44:08,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,957 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1463036566] [2021-12-28 09:44:08,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1463036566] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,957 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,957 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:08,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145257866] [2021-12-28 09:44:08,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,958 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:08,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:08,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2021-12-28 09:44:08,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:08,958 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902494769] [2021-12-28 09:44:08,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:08,958 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:08,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:08,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:08,989 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:08,989 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902494769] [2021-12-28 09:44:08,990 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902494769] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:08,990 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:08,990 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:08,990 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [979693046] [2021-12-28 09:44:08,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:08,991 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:08,991 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:08,992 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:08,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:08,992 INFO L87 Difference]: Start difference. First operand 1072 states and 1538 transitions. cyclomatic complexity: 470 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,024 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2021-12-28 09:44:09,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:09,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1742 states and 2482 transitions. [2021-12-28 09:44:09,041 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2021-12-28 09:44:09,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1742 states to 1742 states and 2482 transitions. [2021-12-28 09:44:09,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1742 [2021-12-28 09:44:09,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1742 [2021-12-28 09:44:09,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1742 states and 2482 transitions. [2021-12-28 09:44:09,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,053 INFO L681 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2021-12-28 09:44:09,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states and 2482 transitions. [2021-12-28 09:44:09,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1742. [2021-12-28 09:44:09,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 1742 states and 2482 transitions. [2021-12-28 09:44:09,082 INFO L704 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2021-12-28 09:44:09,082 INFO L587 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2021-12-28 09:44:09,082 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-12-28 09:44:09,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1742 states and 2482 transitions. [2021-12-28 09:44:09,097 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2021-12-28 09:44:09,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:09,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:09,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,100 INFO L791 eck$LassoCheckResult]: Stem: 5488#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 5394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5380#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5381#L258 assume !(1 == ~q_req_up~0); 5382#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5429#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5430#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5468#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5407#L311 assume !(0 == ~q_read_ev~0); 5408#L311-2 assume !(0 == ~q_write_ev~0); 5445#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5388#L66 assume !(1 == ~p_dw_pc~0); 5389#L66-2 assume !(2 == ~p_dw_pc~0); 5399#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 5422#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5423#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5416#L387 assume !(0 != activate_threads_~tmp~1#1); 5417#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5455#L95 assume !(1 == ~c_dr_pc~0); 5456#L95-2 assume !(2 == ~c_dr_pc~0); 5431#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 5375#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5335#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5336#L395 assume !(0 != activate_threads_~tmp___0~1#1); 5350#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5351#L329 assume !(1 == ~q_read_ev~0); 5385#L329-2 assume !(1 == ~q_write_ev~0); 5392#L334-1 assume { :end_inline_reset_delta_events } true; 5393#L491-2 [2021-12-28 09:44:09,101 INFO L793 eck$LassoCheckResult]: Loop: 5393#L491-2 assume !false; 5623#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5619#L435 assume !false; 5616#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5611#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5607#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5604#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5599#L415 assume !(0 != eval_~tmp___1~0#1); 5600#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5723#L258-3 assume !(1 == ~q_req_up~0); 5721#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5719#L311-3 assume !(0 == ~q_read_ev~0); 5717#L311-5 assume !(0 == ~q_write_ev~0); 5715#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5713#L66-3 assume !(1 == ~p_dw_pc~0); 5711#L66-5 assume !(2 == ~p_dw_pc~0); 5708#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 5706#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5703#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5701#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 5699#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5697#L95-3 assume !(1 == ~c_dr_pc~0); 5695#L95-5 assume !(2 == ~c_dr_pc~0); 5693#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 5691#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5689#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5687#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 5685#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5683#L329-3 assume !(1 == ~q_read_ev~0); 5681#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5679#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5677#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5670#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5663#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5656#L510 assume !(0 == start_simulation_~tmp~4#1); 5651#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5647#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5643#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5640#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5637#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5634#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5630#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 5627#L523 assume !(0 != start_simulation_~tmp___0~3#1); 5393#L491-2 [2021-12-28 09:44:09,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,102 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2021-12-28 09:44:09,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771655412] [2021-12-28 09:44:09,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,115 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:09,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,145 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,146 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2021-12-28 09:44:09,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99178854] [2021-12-28 09:44:09,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,170 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [99178854] [2021-12-28 09:44:09,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [99178854] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:09,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280837282] [2021-12-28 09:44:09,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,171 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:09,171 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:09,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:09,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:09,172 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,226 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2021-12-28 09:44:09,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-12-28 09:44:09,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2947 states and 4108 transitions. [2021-12-28 09:44:09,241 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2907 [2021-12-28 09:44:09,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2947 states to 2947 states and 4108 transitions. [2021-12-28 09:44:09,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2947 [2021-12-28 09:44:09,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2947 [2021-12-28 09:44:09,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2947 states and 4108 transitions. [2021-12-28 09:44:09,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,269 INFO L681 BuchiCegarLoop]: Abstraction has 2947 states and 4108 transitions. [2021-12-28 09:44:09,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2947 states and 4108 transitions. [2021-12-28 09:44:09,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2947 to 1805. [2021-12-28 09:44:09,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2545 transitions. [2021-12-28 09:44:09,293 INFO L704 BuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2021-12-28 09:44:09,293 INFO L587 BuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2021-12-28 09:44:09,293 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-12-28 09:44:09,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2545 transitions. [2021-12-28 09:44:09,299 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1771 [2021-12-28 09:44:09,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:09,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:09,300 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,300 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,300 INFO L791 eck$LassoCheckResult]: Stem: 10196#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 10102#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 10087#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10088#L258 assume !(1 == ~q_req_up~0); 10089#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10136#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 10137#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 10173#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10114#L311 assume !(0 == ~q_read_ev~0); 10115#L311-2 assume !(0 == ~q_write_ev~0); 10151#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10095#L66 assume !(1 == ~p_dw_pc~0); 10096#L66-2 assume !(2 == ~p_dw_pc~0); 10107#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 10129#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10130#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10123#L387 assume !(0 != activate_threads_~tmp~1#1); 10124#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10159#L95 assume !(1 == ~c_dr_pc~0); 10160#L95-2 assume !(2 == ~c_dr_pc~0); 10138#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 10082#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10040#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10041#L395 assume !(0 != activate_threads_~tmp___0~1#1); 10055#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10056#L329 assume !(1 == ~q_read_ev~0); 10092#L329-2 assume !(1 == ~q_write_ev~0); 10100#L334-1 assume { :end_inline_reset_delta_events } true; 10101#L491-2 [2021-12-28 09:44:09,300 INFO L793 eck$LassoCheckResult]: Loop: 10101#L491-2 assume !false; 10436#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 10369#L435 assume !false; 10366#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10364#L291 assume !(0 == ~p_dw_st~0); 10360#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10358#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10347#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10345#L415 assume !(0 != eval_~tmp___1~0#1); 10344#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10343#L258-3 assume !(1 == ~q_req_up~0); 10342#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10341#L311-3 assume !(0 == ~q_read_ev~0); 10340#L311-5 assume !(0 == ~q_write_ev~0); 10339#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 10338#L66-3 assume !(1 == ~p_dw_pc~0); 10336#L66-5 assume !(2 == ~p_dw_pc~0); 10337#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 10312#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 10313#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10306#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 10307#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 10297#L95-3 assume !(1 == ~c_dr_pc~0); 10298#L95-5 assume !(2 == ~c_dr_pc~0); 10468#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 10467#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 10466#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10465#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 10464#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10463#L329-3 assume !(1 == ~q_read_ev~0); 10462#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 10461#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10460#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10457#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10455#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10452#L510 assume !(0 == start_simulation_~tmp~4#1); 10450#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10449#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10447#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10446#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10445#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 10444#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10443#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10440#L523 assume !(0 != start_simulation_~tmp___0~3#1); 10101#L491-2 [2021-12-28 09:44:09,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,301 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2021-12-28 09:44:09,301 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,301 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649944773] [2021-12-28 09:44:09,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,306 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:09,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,313 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,314 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2021-12-28 09:44:09,314 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,314 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024443613] [2021-12-28 09:44:09,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,355 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,355 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024443613] [2021-12-28 09:44:09,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024443613] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,355 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-12-28 09:44:09,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362254353] [2021-12-28 09:44:09,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,356 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:09,356 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:09,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-12-28 09:44:09,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-12-28 09:44:09,356 INFO L87 Difference]: Start difference. First operand 1805 states and 2545 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,414 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2021-12-28 09:44:09,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-12-28 09:44:09,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4219 states and 5928 transitions. [2021-12-28 09:44:09,466 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4181 [2021-12-28 09:44:09,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4219 states to 4219 states and 5928 transitions. [2021-12-28 09:44:09,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4219 [2021-12-28 09:44:09,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4219 [2021-12-28 09:44:09,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4219 states and 5928 transitions. [2021-12-28 09:44:09,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,487 INFO L681 BuchiCegarLoop]: Abstraction has 4219 states and 5928 transitions. [2021-12-28 09:44:09,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4219 states and 5928 transitions. [2021-12-28 09:44:09,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4219 to 1883. [2021-12-28 09:44:09,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 2606 transitions. [2021-12-28 09:44:09,522 INFO L704 BuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2021-12-28 09:44:09,522 INFO L587 BuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2021-12-28 09:44:09,522 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-12-28 09:44:09,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1883 states and 2606 transitions. [2021-12-28 09:44:09,527 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1849 [2021-12-28 09:44:09,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:09,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:09,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,529 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,529 INFO L791 eck$LassoCheckResult]: Stem: 16230#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 16136#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 16120#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16121#L258 assume !(1 == ~q_req_up~0); 16124#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16171#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 16172#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 16210#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16149#L311 assume !(0 == ~q_read_ev~0); 16150#L311-2 assume !(0 == ~q_write_ev~0); 16186#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16128#L66 assume !(1 == ~p_dw_pc~0); 16129#L66-2 assume !(2 == ~p_dw_pc~0); 16140#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 16165#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16166#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16161#L387 assume !(0 != activate_threads_~tmp~1#1); 16162#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16195#L95 assume !(1 == ~c_dr_pc~0); 16196#L95-2 assume !(2 == ~c_dr_pc~0); 16173#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 16117#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16078#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16079#L395 assume !(0 != activate_threads_~tmp___0~1#1); 16092#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16093#L329 assume !(1 == ~q_read_ev~0); 16125#L329-2 assume !(1 == ~q_write_ev~0); 16132#L334-1 assume { :end_inline_reset_delta_events } true; 16133#L491-2 [2021-12-28 09:44:09,529 INFO L793 eck$LassoCheckResult]: Loop: 16133#L491-2 assume !false; 16431#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 16324#L435 assume !false; 16429#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16418#L291 assume !(0 == ~p_dw_st~0); 16419#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 16420#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16414#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16415#L415 assume !(0 != eval_~tmp___1~0#1); 16475#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16474#L258-3 assume !(1 == ~q_req_up~0); 16473#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16472#L311-3 assume !(0 == ~q_read_ev~0); 16471#L311-5 assume !(0 == ~q_write_ev~0); 16470#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 16469#L66-3 assume !(1 == ~p_dw_pc~0); 16153#L66-5 assume !(2 == ~p_dw_pc~0); 16154#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 16444#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 16443#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 16440#L387-3 assume !(0 != activate_threads_~tmp~1#1); 16438#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 16436#L95-3 assume !(1 == ~c_dr_pc~0); 16421#L95-5 assume !(2 == ~c_dr_pc~0); 16279#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 16272#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16271#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16270#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 16269#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16268#L329-3 assume !(1 == ~q_read_ev~0); 16267#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 16265#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16266#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16261#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16260#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16257#L510 assume !(0 == start_simulation_~tmp~4#1); 16258#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 16442#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 16439#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 16437#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 16435#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 16434#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16433#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 16432#L523 assume !(0 != start_simulation_~tmp___0~3#1); 16133#L491-2 [2021-12-28 09:44:09,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,530 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2021-12-28 09:44:09,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968061492] [2021-12-28 09:44:09,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,533 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,540 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:09,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,556 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,557 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2021-12-28 09:44:09,557 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,557 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307992602] [2021-12-28 09:44:09,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,558 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307992602] [2021-12-28 09:44:09,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307992602] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,581 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:09,581 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395487965] [2021-12-28 09:44:09,581 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,581 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:09,582 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:09,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:09,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:09,582 INFO L87 Difference]: Start difference. First operand 1883 states and 2606 transitions. cyclomatic complexity: 727 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,607 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2021-12-28 09:44:09,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:09,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4013 transitions. [2021-12-28 09:44:09,629 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2021-12-28 09:44:09,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4013 transitions. [2021-12-28 09:44:09,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2021-12-28 09:44:09,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2021-12-28 09:44:09,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4013 transitions. [2021-12-28 09:44:09,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,642 INFO L681 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2021-12-28 09:44:09,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4013 transitions. [2021-12-28 09:44:09,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2972. [2021-12-28 09:44:09,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2972 states to 2972 states and 4013 transitions. [2021-12-28 09:44:09,673 INFO L704 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2021-12-28 09:44:09,673 INFO L587 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2021-12-28 09:44:09,673 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-12-28 09:44:09,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2972 states and 4013 transitions. [2021-12-28 09:44:09,680 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2021-12-28 09:44:09,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:09,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:09,681 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,681 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,681 INFO L791 eck$LassoCheckResult]: Stem: 21114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 20997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 20982#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20983#L258 assume !(1 == ~q_req_up~0); 20984#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21032#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 21033#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 21077#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21078#L311 assume !(0 == ~q_read_ev~0); 21084#L311-2 assume !(0 == ~q_write_ev~0); 21085#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 20989#L66 assume !(1 == ~p_dw_pc~0); 20990#L66-2 assume !(2 == ~p_dw_pc~0); 21111#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 21112#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21068#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21069#L387 assume !(0 != activate_threads_~tmp~1#1); 21087#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21088#L95 assume !(1 == ~c_dr_pc~0); 21089#L95-2 assume !(2 == ~c_dr_pc~0); 21090#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 20976#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 20977#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21052#L395 assume !(0 != activate_threads_~tmp___0~1#1); 21053#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20987#L329 assume !(1 == ~q_read_ev~0); 20988#L329-2 assume !(1 == ~q_write_ev~0); 20995#L334-1 assume { :end_inline_reset_delta_events } true; 20996#L491-2 [2021-12-28 09:44:09,682 INFO L793 eck$LassoCheckResult]: Loop: 20996#L491-2 assume !false; 21205#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 21180#L435 assume !false; 21200#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21198#L291 assume !(0 == ~p_dw_st~0); 21196#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21194#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21191#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21187#L415 assume !(0 != eval_~tmp___1~0#1); 21188#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21261#L258-3 assume !(1 == ~q_req_up~0); 21260#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21259#L311-3 assume !(0 == ~q_read_ev~0); 21258#L311-5 assume !(0 == ~q_write_ev~0); 21257#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 21256#L66-3 assume !(1 == ~p_dw_pc~0); 21255#L66-5 assume !(2 == ~p_dw_pc~0); 21254#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 21253#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 21252#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 21250#L387-3 assume !(0 != activate_threads_~tmp~1#1); 21248#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 21246#L95-3 assume !(1 == ~c_dr_pc~0); 21244#L95-5 assume !(2 == ~c_dr_pc~0); 21242#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 21240#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 21238#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 21236#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 21234#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21232#L329-3 assume !(1 == ~q_read_ev~0); 21230#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 21228#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21226#L291-1 assume !(0 == ~p_dw_st~0); 21224#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21222#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21220#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21217#L510 assume !(0 == start_simulation_~tmp~4#1); 21215#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 21214#L291-2 assume !(0 == ~p_dw_st~0); 21213#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 21212#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 21211#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 21210#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 21209#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21208#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 21207#L523 assume !(0 != start_simulation_~tmp___0~3#1); 20996#L491-2 [2021-12-28 09:44:09,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,682 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2021-12-28 09:44:09,682 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420555866] [2021-12-28 09:44:09,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,683 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,696 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420555866] [2021-12-28 09:44:09,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420555866] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,697 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,697 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:09,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1954514814] [2021-12-28 09:44:09,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,697 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-12-28 09:44:09,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,698 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2021-12-28 09:44:09,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,698 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740986374] [2021-12-28 09:44:09,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740986374] [2021-12-28 09:44:09,711 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740986374] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,711 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-12-28 09:44:09,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732126344] [2021-12-28 09:44:09,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,712 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-12-28 09:44:09,712 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:09,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:09,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:09,713 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. cyclomatic complexity: 1048 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,723 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2021-12-28 09:44:09,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:09,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 3987 transitions. [2021-12-28 09:44:09,747 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2021-12-28 09:44:09,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 3987 transitions. [2021-12-28 09:44:09,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2021-12-28 09:44:09,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2021-12-28 09:44:09,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 3987 transitions. [2021-12-28 09:44:09,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,760 INFO L681 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2021-12-28 09:44:09,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 3987 transitions. [2021-12-28 09:44:09,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2950. [2021-12-28 09:44:09,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3987 transitions. [2021-12-28 09:44:09,789 INFO L704 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2021-12-28 09:44:09,789 INFO L587 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2021-12-28 09:44:09,789 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-12-28 09:44:09,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2950 states and 3987 transitions. [2021-12-28 09:44:09,795 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2021-12-28 09:44:09,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:09,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:09,796 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,796 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:09,796 INFO L791 eck$LassoCheckResult]: Stem: 27027#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 26926#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 26911#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26912#L258 assume !(1 == ~q_req_up~0); 26913#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26961#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 26962#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 27000#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26937#L311 assume !(0 == ~q_read_ev~0); 26938#L311-2 assume !(0 == ~q_write_ev~0); 26978#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 26919#L66 assume !(1 == ~p_dw_pc~0); 26920#L66-2 assume !(2 == ~p_dw_pc~0); 26930#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 26954#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 26955#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 26948#L387 assume !(0 != activate_threads_~tmp~1#1); 26949#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 26985#L95 assume !(1 == ~c_dr_pc~0); 26986#L95-2 assume !(2 == ~c_dr_pc~0); 26963#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 26906#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 26867#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 26868#L395 assume !(0 != activate_threads_~tmp___0~1#1); 26883#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26884#L329 assume !(1 == ~q_read_ev~0); 26916#L329-2 assume !(1 == ~q_write_ev~0); 26924#L334-1 assume { :end_inline_reset_delta_events } true; 26925#L491-2 assume !false; 27122#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 27121#L435 [2021-12-28 09:44:09,797 INFO L793 eck$LassoCheckResult]: Loop: 27121#L435 assume !false; 27119#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 27117#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 27115#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 27112#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27109#L415 assume 0 != eval_~tmp___1~0#1; 27105#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 27101#L424 assume !(0 != eval_~tmp~2#1); 27102#L420 assume !(0 == ~c_dr_st~0); 27121#L435 [2021-12-28 09:44:09,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,797 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2021-12-28 09:44:09,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658215590] [2021-12-28 09:44:09,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,801 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:09,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,806 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,806 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2021-12-28 09:44:09,806 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,807 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924550853] [2021-12-28 09:44:09,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,807 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,809 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:09,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:09,811 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:09,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:09,811 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2021-12-28 09:44:09,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:09,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757827749] [2021-12-28 09:44:09,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:09,823 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:09,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-12-28 09:44:09,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-12-28 09:44:09,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-12-28 09:44:09,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757827749] [2021-12-28 09:44:09,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757827749] provided 1 perfect and 0 imperfect interpolant sequences [2021-12-28 09:44:09,837 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-12-28 09:44:09,838 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-12-28 09:44:09,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791593273] [2021-12-28 09:44:09,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-12-28 09:44:09,878 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-12-28 09:44:09,878 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-12-28 09:44:09,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-12-28 09:44:09,879 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:09,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-12-28 09:44:09,936 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2021-12-28 09:44:09,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-12-28 09:44:09,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4412 states and 5918 transitions. [2021-12-28 09:44:09,948 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4373 [2021-12-28 09:44:09,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4412 states to 4412 states and 5918 transitions. [2021-12-28 09:44:09,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4412 [2021-12-28 09:44:09,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4412 [2021-12-28 09:44:09,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4412 states and 5918 transitions. [2021-12-28 09:44:09,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-12-28 09:44:09,983 INFO L681 BuchiCegarLoop]: Abstraction has 4412 states and 5918 transitions. [2021-12-28 09:44:09,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4412 states and 5918 transitions. [2021-12-28 09:44:10,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4412 to 3868. [2021-12-28 09:44:10,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-12-28 09:44:10,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5220 transitions. [2021-12-28 09:44:10,031 INFO L704 BuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2021-12-28 09:44:10,031 INFO L587 BuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2021-12-28 09:44:10,031 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-12-28 09:44:10,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3868 states and 5220 transitions. [2021-12-28 09:44:10,042 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3829 [2021-12-28 09:44:10,042 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-12-28 09:44:10,042 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-12-28 09:44:10,042 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:10,043 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-12-28 09:44:10,043 INFO L791 eck$LassoCheckResult]: Stem: 34395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 34295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 34281#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34282#L258 assume !(1 == ~q_req_up~0); 34283#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34328#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 34329#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 34367#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34306#L311 assume !(0 == ~q_read_ev~0); 34307#L311-2 assume !(0 == ~q_write_ev~0); 34343#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 34289#L66 assume !(1 == ~p_dw_pc~0); 34290#L66-2 assume !(2 == ~p_dw_pc~0); 34301#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 34322#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 34323#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34316#L387 assume !(0 != activate_threads_~tmp~1#1); 34317#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 34352#L95 assume !(1 == ~c_dr_pc~0); 34353#L95-2 assume !(2 == ~c_dr_pc~0); 34330#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 34276#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 34237#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 34238#L395 assume !(0 != activate_threads_~tmp___0~1#1); 34252#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34253#L329 assume !(1 == ~q_read_ev~0); 34286#L329-2 assume !(1 == ~q_write_ev~0); 34293#L334-1 assume { :end_inline_reset_delta_events } true; 34294#L491-2 assume !false; 35647#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 35638#L435 [2021-12-28 09:44:10,043 INFO L793 eck$LassoCheckResult]: Loop: 35638#L435 assume !false; 35631#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 35623#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 35617#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 35616#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 35615#L415 assume 0 != eval_~tmp___1~0#1; 35612#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 35608#L424 assume !(0 != eval_~tmp~2#1); 35609#L420 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 35648#L439 assume !(0 != eval_~tmp___0~2#1); 35638#L435 [2021-12-28 09:44:10,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:10,044 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2021-12-28 09:44:10,044 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:10,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1065802805] [2021-12-28 09:44:10,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:10,044 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:10,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,068 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:10,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,073 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:10,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:10,074 INFO L85 PathProgramCache]: Analyzing trace with hash -418551849, now seen corresponding path program 1 times [2021-12-28 09:44:10,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:10,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098588308] [2021-12-28 09:44:10,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:10,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:10,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,076 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:10,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,078 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:10,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-12-28 09:44:10,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788583, now seen corresponding path program 1 times [2021-12-28 09:44:10,079 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-12-28 09:44:10,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330491169] [2021-12-28 09:44:10,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-12-28 09:44:10,079 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-12-28 09:44:10,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,096 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-12-28 09:44:10,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-12-28 09:44:10,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-12-28 09:44:10,870 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.12 09:44:10 BoogieIcfgContainer [2021-12-28 09:44:10,871 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-12-28 09:44:10,871 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-12-28 09:44:10,871 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-12-28 09:44:10,871 INFO L275 PluginConnector]: Witness Printer initialized [2021-12-28 09:44:10,872 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.12 09:44:07" (3/4) ... [2021-12-28 09:44:10,873 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-12-28 09:44:10,900 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-12-28 09:44:10,900 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-12-28 09:44:10,900 INFO L158 Benchmark]: Toolchain (without parser) took 4003.38ms. Allocated memory was 71.3MB in the beginning and 272.6MB in the end (delta: 201.3MB). Free memory was 53.3MB in the beginning and 209.1MB in the end (delta: -155.8MB). Peak memory consumption was 45.6MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,901 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 71.3MB. Free memory was 52.3MB in the beginning and 52.3MB in the end (delta: 44.4kB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-28 09:44:10,901 INFO L158 Benchmark]: CACSL2BoogieTranslator took 298.83ms. Allocated memory is still 71.3MB. Free memory was 53.2MB in the beginning and 52.2MB in the end (delta: 966.7kB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,901 INFO L158 Benchmark]: Boogie Procedure Inliner took 59.38ms. Allocated memory is still 71.3MB. Free memory was 52.2MB in the beginning and 49.7MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,901 INFO L158 Benchmark]: Boogie Preprocessor took 43.24ms. Allocated memory is still 71.3MB. Free memory was 49.7MB in the beginning and 47.8MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2021-12-28 09:44:10,901 INFO L158 Benchmark]: RCFGBuilder took 586.84ms. Allocated memory is still 71.3MB. Free memory was 47.6MB in the beginning and 49.4MB in the end (delta: -1.8MB). Peak memory consumption was 23.6MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,902 INFO L158 Benchmark]: BuchiAutomizer took 2981.03ms. Allocated memory was 71.3MB in the beginning and 272.6MB in the end (delta: 201.3MB). Free memory was 49.4MB in the beginning and 212.3MB in the end (delta: -162.9MB). Peak memory consumption was 90.3MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,902 INFO L158 Benchmark]: Witness Printer took 29.00ms. Allocated memory is still 272.6MB. Free memory was 212.3MB in the beginning and 209.1MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-12-28 09:44:10,903 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 71.3MB. Free memory was 52.3MB in the beginning and 52.3MB in the end (delta: 44.4kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 298.83ms. Allocated memory is still 71.3MB. Free memory was 53.2MB in the beginning and 52.2MB in the end (delta: 966.7kB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 59.38ms. Allocated memory is still 71.3MB. Free memory was 52.2MB in the beginning and 49.7MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.24ms. Allocated memory is still 71.3MB. Free memory was 49.7MB in the beginning and 47.8MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 586.84ms. Allocated memory is still 71.3MB. Free memory was 47.6MB in the beginning and 49.4MB in the end (delta: -1.8MB). Peak memory consumption was 23.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 2981.03ms. Allocated memory was 71.3MB in the beginning and 272.6MB in the end (delta: 201.3MB). Free memory was 49.4MB in the beginning and 212.3MB in the end (delta: -162.9MB). Peak memory consumption was 90.3MB. Max. memory is 16.1GB. * Witness Printer took 29.00ms. Allocated memory is still 272.6MB. Free memory was 212.3MB in the beginning and 209.1MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.9s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.5s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 9 MinimizatonAttempts, 4068 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 3868 states and ocurred in iteration 9. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3109 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3109 mSDsluCounter, 4252 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2626 mSDsCounter, 105 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 261 IncrementalHoareTripleChecker+Invalid, 366 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 105 mSolverCounterUnsat, 1626 mSDtfsCounter, 261 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3ccffb2c=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@949941f=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5775618e=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f3c9da8=0, t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4342aac8=0, p_dw_pc=0, q_free=1, __retres1=1, fast_clk_edge=2, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, slow_clk_edge=2, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d438893=0, kernel_st=1, p_num_write=0, q_buf_0=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60cd7a86=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) [L316] COND FALSE !((int )q_write_ev == 0) [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; [L66] COND FALSE !((int )p_dw_pc == 1) [L76] COND FALSE !((int )p_dw_pc == 2) [L86] __retres1 = 0 [L88] return (__retres1); [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; [L95] COND FALSE !((int )c_dr_pc == 1) [L105] COND FALSE !((int )c_dr_pc == 2) [L115] __retres1 = 0 [L117] return (__retres1); [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) [L334] COND FALSE !((int )q_write_ev == 1) [L488] RET reset_delta_events() [L491] COND TRUE 1 [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-12-28 09:44:10,951 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)