./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/config/KojakReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/config/svcomp-Reach-64bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 56ff1aa7a746f87b9c1b788d1f6729b885abef13666f4b3b25250b45ff5a6786 ......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE --- Real Ultimate output --- This is Ultimate 0.2.1-dev-b2eff8b [2021-10-29 02:56:12,508 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-10-29 02:56:12,511 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-10-29 02:56:12,573 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-10-29 02:56:12,574 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-10-29 02:56:12,580 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-10-29 02:56:12,582 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-10-29 02:56:12,586 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-10-29 02:56:12,589 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-10-29 02:56:12,595 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-10-29 02:56:12,596 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-10-29 02:56:12,597 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-10-29 02:56:12,598 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-10-29 02:56:12,600 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-10-29 02:56:12,602 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-10-29 02:56:12,608 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-10-29 02:56:12,610 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-10-29 02:56:12,611 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-10-29 02:56:12,614 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-10-29 02:56:12,623 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-10-29 02:56:12,625 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-10-29 02:56:12,626 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-10-29 02:56:12,631 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-10-29 02:56:12,632 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-10-29 02:56:12,636 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-10-29 02:56:12,636 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-10-29 02:56:12,637 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-10-29 02:56:12,639 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-10-29 02:56:12,639 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-10-29 02:56:12,641 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-10-29 02:56:12,641 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-10-29 02:56:12,642 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-10-29 02:56:12,644 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-10-29 02:56:12,645 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-10-29 02:56:12,646 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-10-29 02:56:12,647 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-10-29 02:56:12,647 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-10-29 02:56:12,648 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-10-29 02:56:12,648 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-10-29 02:56:12,649 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-10-29 02:56:12,649 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-10-29 02:56:12,650 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/config/svcomp-Reach-64bit-Kojak_Default.epf [2021-10-29 02:56:12,696 INFO L113 SettingsManager]: Loading preferences was successful [2021-10-29 02:56:12,696 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-10-29 02:56:12,697 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-10-29 02:56:12,698 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2021-10-29 02:56:12,698 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-10-29 02:56:12,698 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-10-29 02:56:12,699 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-10-29 02:56:12,699 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-10-29 02:56:12,699 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-10-29 02:56:12,699 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-10-29 02:56:12,700 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-10-29 02:56:12,707 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-10-29 02:56:12,707 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-10-29 02:56:12,707 INFO L138 SettingsManager]: * Use constant arrays=true [2021-10-29 02:56:12,707 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-10-29 02:56:12,707 INFO L136 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2021-10-29 02:56:12,708 INFO L138 SettingsManager]: * Timeout in seconds=1000000 [2021-10-29 02:56:12,708 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-10-29 02:56:12,708 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2021-10-29 02:56:12,708 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-10-29 02:56:12,708 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-10-29 02:56:12,709 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-10-29 02:56:12,709 INFO L138 SettingsManager]: * Trace refinement strategy=PENGUIN [2021-10-29 02:56:12,709 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-10-29 02:56:12,709 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-10-29 02:56:12,709 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 56ff1aa7a746f87b9c1b788d1f6729b885abef13666f4b3b25250b45ff5a6786 [2021-10-29 02:56:13,028 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-10-29 02:56:13,060 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-10-29 02:56:13,065 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-10-29 02:56:13,066 INFO L271 PluginConnector]: Initializing CDTParser... [2021-10-29 02:56:13,067 INFO L275 PluginConnector]: CDTParser initialized [2021-10-29 02:56:13,068 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i [2021-10-29 02:56:13,139 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/data/e41866e96/dbcb600bdf0a48a2bbb218d4fb8d4dfc/FLAG7965b8989 [2021-10-29 02:56:13,926 INFO L306 CDTParser]: Found 1 translation units. [2021-10-29 02:56:13,927 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i [2021-10-29 02:56:13,982 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/data/e41866e96/dbcb600bdf0a48a2bbb218d4fb8d4dfc/FLAG7965b8989 [2021-10-29 02:56:14,467 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/data/e41866e96/dbcb600bdf0a48a2bbb218d4fb8d4dfc [2021-10-29 02:56:14,474 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-10-29 02:56:14,475 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-10-29 02:56:14,477 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-10-29 02:56:14,477 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-10-29 02:56:14,480 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-10-29 02:56:14,481 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.10 02:56:14" (1/1) ... [2021-10-29 02:56:14,482 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e0c5aa4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:14, skipping insertion in model container [2021-10-29 02:56:14,483 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.10 02:56:14" (1/1) ... [2021-10-29 02:56:14,490 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-10-29 02:56:14,577 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-10-29 02:56:15,256 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i[115668,115681] [2021-10-29 02:56:15,957 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-29 02:56:15,985 INFO L203 MainTranslator]: Completed pre-run [2021-10-29 02:56:16,088 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i[115668,115681] [2021-10-29 02:56:16,280 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-10-29 02:56:16,414 INFO L208 MainTranslator]: Completed translation [2021-10-29 02:56:16,415 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16 WrapperNode [2021-10-29 02:56:16,415 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-10-29 02:56:16,416 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-10-29 02:56:16,417 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-10-29 02:56:16,417 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-10-29 02:56:16,424 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,525 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,689 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-10-29 02:56:16,691 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-10-29 02:56:16,691 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-10-29 02:56:16,692 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-10-29 02:56:16,701 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,701 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,739 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,740 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,893 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,925 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,951 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,982 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-10-29 02:56:16,983 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-10-29 02:56:16,983 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-10-29 02:56:16,983 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-10-29 02:56:16,984 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.10 02:56:16" (1/1) ... [2021-10-29 02:56:16,992 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2021-10-29 02:56:17,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/z3 [2021-10-29 02:56:17,021 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2021-10-29 02:56:17,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2021-10-29 02:56:17,077 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_rds_radio_text [2021-10-29 02:56:17,077 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_rds_radio_text [2021-10-29 02:56:17,077 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2021-10-29 02:56:17,078 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2021-10-29 02:56:17,078 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2021-10-29 02:56:17,078 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2021-10-29 02:56:17,078 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2021-10-29 02:56:17,079 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-10-29 02:56:17,079 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_is_valid [2021-10-29 02:56:17,079 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_is_valid [2021-10-29 02:56:17,080 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_wait_stc [2021-10-29 02:56:17,080 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_wait_stc [2021-10-29 02:56:17,080 INFO L130 BoogieDeclarations]: Found specification of procedure dev_to_usecs [2021-10-29 02:56:17,080 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_to_usecs [2021-10-29 02:56:17,080 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_mute [2021-10-29 02:56:17,080 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_mute [2021-10-29 02:56:17,080 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2021-10-29 02:56:17,080 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2021-10-29 02:56:17,081 INFO L130 BoogieDeclarations]: Found specification of procedure wait_for_completion_timeout [2021-10-29 02:56:17,081 INFO L138 BoogieDeclarations]: Found implementation of procedure wait_for_completion_timeout [2021-10-29 02:56:17,081 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2021-10-29 02:56:17,081 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2021-10-29 02:56:17,081 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_power_state [2021-10-29 02:56:17,081 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_power_state [2021-10-29 02:56:17,081 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_choose_econtrol_action [2021-10-29 02:56:17,082 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_choose_econtrol_action [2021-10-29 02:56:17,082 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_len [2021-10-29 02:56:17,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_len [2021-10-29 02:56:17,082 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2021-10-29 02:56:17,082 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2021-10-29 02:56:17,082 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2021-10-29 02:56:17,082 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2021-10-29 02:56:17,082 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_econtrol_tune [2021-10-29 02:56:17,083 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_econtrol_tune [2021-10-29 02:56:17,083 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-10-29 02:56:17,083 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_unlock [2021-10-29 02:56:17,083 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_unlock [2021-10-29 02:56:17,083 INFO L130 BoogieDeclarations]: Found specification of procedure copy_to_user [2021-10-29 02:56:17,083 INFO L138 BoogieDeclarations]: Found implementation of procedure copy_to_user [2021-10-29 02:56:17,083 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2021-10-29 02:56:17,083 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2021-10-29 02:56:17,084 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2021-10-29 02:56:17,084 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2021-10-29 02:56:17,084 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__copy_from_user_1 [2021-10-29 02:56:17,084 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__copy_from_user_1 [2021-10-29 02:56:17,084 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2021-10-29 02:56:17,085 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2021-10-29 02:56:17,085 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_strlen [2021-10-29 02:56:17,085 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_strlen [2021-10-29 02:56:17,085 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_set_value [2021-10-29 02:56:17,085 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_set_value [2021-10-29 02:56:17,086 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_tx_rds_buff [2021-10-29 02:56:17,086 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_tx_rds_buff [2021-10-29 02:56:17,086 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2021-10-29 02:56:17,086 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2021-10-29 02:56:17,086 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-10-29 02:56:17,086 INFO L130 BoogieDeclarations]: Found specification of procedure v4l2_ctrl_query_fill [2021-10-29 02:56:17,086 INFO L138 BoogieDeclarations]: Found implementation of procedure v4l2_ctrl_query_fill [2021-10-29 02:56:17,086 INFO L130 BoogieDeclarations]: Found specification of procedure validate_range [2021-10-29 02:56:17,087 INFO L138 BoogieDeclarations]: Found implementation of procedure validate_range [2021-10-29 02:56:17,087 INFO L130 BoogieDeclarations]: Found specification of procedure regulator_bulk_free [2021-10-29 02:56:17,087 INFO L138 BoogieDeclarations]: Found implementation of procedure regulator_bulk_free [2021-10-29 02:56:17,088 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_econtrol_integers [2021-10-29 02:56:17,088 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_econtrol_integers [2021-10-29 02:56:17,089 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2021-10-29 02:56:17,089 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2021-10-29 02:56:17,089 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2021-10-29 02:56:17,090 INFO L130 BoogieDeclarations]: Found specification of procedure regulator_bulk_disable [2021-10-29 02:56:17,090 INFO L138 BoogieDeclarations]: Found implementation of procedure regulator_bulk_disable [2021-10-29 02:56:17,090 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-10-29 02:56:17,090 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_free [2021-10-29 02:56:17,091 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_free [2021-10-29 02:56:17,091 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2021-10-29 02:56:17,091 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2021-10-29 02:56:17,091 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_send_command [2021-10-29 02:56:17,091 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_send_command [2021-10-29 02:56:17,091 INFO L130 BoogieDeclarations]: Found specification of procedure v4l2_get_subdevdata [2021-10-29 02:56:17,091 INFO L138 BoogieDeclarations]: Found implementation of procedure v4l2_get_subdevdata [2021-10-29 02:56:17,092 INFO L130 BoogieDeclarations]: Found specification of procedure usecs_to_jiffies [2021-10-29 02:56:17,092 INFO L138 BoogieDeclarations]: Found implementation of procedure usecs_to_jiffies [2021-10-29 02:56:17,092 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_property [2021-10-29 02:56:17,092 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_property [2021-10-29 02:56:17,092 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2021-10-29 02:56:17,092 INFO L130 BoogieDeclarations]: Found specification of procedure strlcpy [2021-10-29 02:56:17,092 INFO L138 BoogieDeclarations]: Found implementation of procedure strlcpy [2021-10-29 02:56:17,092 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-10-29 02:56:17,093 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2021-10-29 02:56:17,093 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_read_property [2021-10-29 02:56:17,093 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_read_property [2021-10-29 02:56:17,093 INFO L130 BoogieDeclarations]: Found specification of procedure might_fault [2021-10-29 02:56:17,093 INFO L138 BoogieDeclarations]: Found implementation of procedure might_fault [2021-10-29 02:56:17,093 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_s_frequency [2021-10-29 02:56:17,093 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_s_frequency [2021-10-29 02:56:17,093 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_copy_from_user_7 [2021-10-29 02:56:17,094 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_copy_from_user_7 [2021-10-29 02:56:17,094 INFO L130 BoogieDeclarations]: Found specification of procedure kmalloc [2021-10-29 02:56:17,094 INFO L138 BoogieDeclarations]: Found implementation of procedure kmalloc [2021-10-29 02:56:17,094 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_lock_nested [2021-10-29 02:56:17,095 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_lock_nested [2021-10-29 02:56:17,095 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-10-29 02:56:17,095 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_tx_tune_status [2021-10-29 02:56:17,095 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_tx_tune_status [2021-10-29 02:56:17,095 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_ret_val [2021-10-29 02:56:17,096 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_ret_val [2021-10-29 02:56:17,096 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_update_tune_status [2021-10-29 02:56:17,096 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_update_tune_status [2021-10-29 02:56:17,096 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_rds_ps_name [2021-10-29 02:56:17,096 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_rds_ps_name [2021-10-29 02:56:17,096 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_queryctrl [2021-10-29 02:56:17,097 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_queryctrl [2021-10-29 02:56:17,097 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_s_modulator [2021-10-29 02:56:17,097 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_s_modulator [2021-10-29 02:56:17,097 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2021-10-29 02:56:17,097 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2021-10-29 02:56:17,097 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2021-10-29 02:56:17,097 INFO L130 BoogieDeclarations]: Found specification of procedure strncpy [2021-10-29 02:56:17,097 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-10-29 02:56:17,097 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-10-29 02:56:18,090 INFO L758 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2021-10-29 03:03:54,759 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-10-29 03:03:54,759 INFO L299 CfgBuilder]: Removed 139 assume(true) statements. [2021-10-29 03:03:54,763 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.10 03:03:54 BoogieIcfgContainer [2021-10-29 03:03:54,764 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-10-29 03:03:54,765 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2021-10-29 03:03:54,765 INFO L271 PluginConnector]: Initializing CodeCheck... [2021-10-29 03:03:54,775 INFO L275 PluginConnector]: CodeCheck initialized [2021-10-29 03:03:54,776 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.10 03:03:54" (1/1) ... [2021-10-29 03:03:54,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-10-29 03:03:54,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:54,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1184 states to 807 states and 1184 transitions. [2021-10-29 03:03:54,863 INFO L276 IsEmpty]: Start isEmpty. Operand 807 states and 1184 transitions. [2021-10-29 03:03:54,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2021-10-29 03:03:54,879 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:54,880 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:55,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:55,533 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:55,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:55,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 809 states and 1220 transitions. [2021-10-29 03:03:55,691 INFO L276 IsEmpty]: Start isEmpty. Operand 809 states and 1220 transitions. [2021-10-29 03:03:55,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2021-10-29 03:03:55,699 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:55,699 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:55,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:55,878 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:56,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:56,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1262 states to 813 states and 1262 transitions. [2021-10-29 03:03:56,137 INFO L276 IsEmpty]: Start isEmpty. Operand 813 states and 1262 transitions. [2021-10-29 03:03:56,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2021-10-29 03:03:56,144 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:56,145 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:56,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:56,331 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:56,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:56,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1305 states to 818 states and 1305 transitions. [2021-10-29 03:03:56,857 INFO L276 IsEmpty]: Start isEmpty. Operand 818 states and 1305 transitions. [2021-10-29 03:03:56,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2021-10-29 03:03:56,863 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:56,863 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:57,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:57,099 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:03:57,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:57,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1314 states to 822 states and 1314 transitions. [2021-10-29 03:03:57,438 INFO L276 IsEmpty]: Start isEmpty. Operand 822 states and 1314 transitions. [2021-10-29 03:03:57,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-10-29 03:03:57,442 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:57,443 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:57,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:57,572 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:03:57,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:57,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1317 states to 824 states and 1317 transitions. [2021-10-29 03:03:57,593 INFO L276 IsEmpty]: Start isEmpty. Operand 824 states and 1317 transitions. [2021-10-29 03:03:57,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-10-29 03:03:57,597 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:57,598 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:57,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:57,764 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:03:57,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:57,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 827 states and 1322 transitions. [2021-10-29 03:03:57,822 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1322 transitions. [2021-10-29 03:03:57,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-10-29 03:03:57,827 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:57,827 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:57,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:57,957 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:03:57,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:57,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1322 states to 828 states and 1322 transitions. [2021-10-29 03:03:57,989 INFO L276 IsEmpty]: Start isEmpty. Operand 828 states and 1322 transitions. [2021-10-29 03:03:57,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-10-29 03:03:57,992 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:57,993 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:58,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:58,167 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:58,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:58,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1317 states to 827 states and 1317 transitions. [2021-10-29 03:03:58,258 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1317 transitions. [2021-10-29 03:03:58,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-10-29 03:03:58,262 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:58,262 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:58,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:58,454 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:59,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:59,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1355 states to 833 states and 1355 transitions. [2021-10-29 03:03:59,636 INFO L276 IsEmpty]: Start isEmpty. Operand 833 states and 1355 transitions. [2021-10-29 03:03:59,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-10-29 03:03:59,640 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:59,640 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:03:59,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:03:59,747 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:03:59,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:03:59,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1360 states to 836 states and 1360 transitions. [2021-10-29 03:03:59,942 INFO L276 IsEmpty]: Start isEmpty. Operand 836 states and 1360 transitions. [2021-10-29 03:03:59,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-10-29 03:03:59,946 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:03:59,947 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:00,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:00,156 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:00,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:00,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1360 states to 837 states and 1360 transitions. [2021-10-29 03:04:00,185 INFO L276 IsEmpty]: Start isEmpty. Operand 837 states and 1360 transitions. [2021-10-29 03:04:00,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2021-10-29 03:04:00,189 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:00,190 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:00,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:00,404 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:02,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:02,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1400 states to 844 states and 1400 transitions. [2021-10-29 03:04:02,015 INFO L276 IsEmpty]: Start isEmpty. Operand 844 states and 1400 transitions. [2021-10-29 03:04:02,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2021-10-29 03:04:02,019 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:02,019 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:02,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:02,248 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:02,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:02,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1393 states to 843 states and 1393 transitions. [2021-10-29 03:04:02,424 INFO L276 IsEmpty]: Start isEmpty. Operand 843 states and 1393 transitions. [2021-10-29 03:04:02,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-10-29 03:04:02,428 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:02,428 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:02,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:02,536 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:03,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:03,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1399 states to 846 states and 1399 transitions. [2021-10-29 03:04:03,502 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1399 transitions. [2021-10-29 03:04:03,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-10-29 03:04:03,506 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:03,506 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:03,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:03,751 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:03,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:03,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1400 states to 847 states and 1400 transitions. [2021-10-29 03:04:03,952 INFO L276 IsEmpty]: Start isEmpty. Operand 847 states and 1400 transitions. [2021-10-29 03:04:03,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-10-29 03:04:03,956 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:03,957 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:04,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:04,226 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:04,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:04,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1393 states to 846 states and 1393 transitions. [2021-10-29 03:04:04,416 INFO L276 IsEmpty]: Start isEmpty. Operand 846 states and 1393 transitions. [2021-10-29 03:04:04,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-10-29 03:04:04,421 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:04,421 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:04,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:04,593 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:05,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:05,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1396 states to 848 states and 1396 transitions. [2021-10-29 03:04:05,088 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 1396 transitions. [2021-10-29 03:04:05,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-10-29 03:04:05,092 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:05,092 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:05,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:05,202 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:05,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:05,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1399 states to 850 states and 1399 transitions. [2021-10-29 03:04:05,735 INFO L276 IsEmpty]: Start isEmpty. Operand 850 states and 1399 transitions. [2021-10-29 03:04:05,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-10-29 03:04:05,739 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:05,739 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:05,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:06,202 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:08,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:08,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1449 states to 857 states and 1449 transitions. [2021-10-29 03:04:08,594 INFO L276 IsEmpty]: Start isEmpty. Operand 857 states and 1449 transitions. [2021-10-29 03:04:08,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-10-29 03:04:08,598 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:08,598 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:08,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:08,706 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:08,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:09,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1456 states to 861 states and 1456 transitions. [2021-10-29 03:04:09,004 INFO L276 IsEmpty]: Start isEmpty. Operand 861 states and 1456 transitions. [2021-10-29 03:04:09,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-10-29 03:04:09,008 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:09,008 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:09,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:09,133 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:09,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:09,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1456 states to 862 states and 1456 transitions. [2021-10-29 03:04:09,159 INFO L276 IsEmpty]: Start isEmpty. Operand 862 states and 1456 transitions. [2021-10-29 03:04:09,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-10-29 03:04:09,163 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:09,163 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:09,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:09,272 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:09,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:09,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1459 states to 864 states and 1459 transitions. [2021-10-29 03:04:09,852 INFO L276 IsEmpty]: Start isEmpty. Operand 864 states and 1459 transitions. [2021-10-29 03:04:09,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-10-29 03:04:09,855 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:09,856 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:09,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:10,140 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:12,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:12,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1506 states to 870 states and 1506 transitions. [2021-10-29 03:04:12,616 INFO L276 IsEmpty]: Start isEmpty. Operand 870 states and 1506 transitions. [2021-10-29 03:04:12,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-10-29 03:04:12,620 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:12,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:12,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:12,724 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:14,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:14,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1542 states to 873 states and 1542 transitions. [2021-10-29 03:04:14,145 INFO L276 IsEmpty]: Start isEmpty. Operand 873 states and 1542 transitions. [2021-10-29 03:04:14,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-10-29 03:04:14,148 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:14,149 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:14,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:14,323 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:14,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:14,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 876 states and 1546 transitions. [2021-10-29 03:04:14,347 INFO L276 IsEmpty]: Start isEmpty. Operand 876 states and 1546 transitions. [2021-10-29 03:04:14,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-10-29 03:04:14,350 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:14,351 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:14,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:14,465 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:14,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:14,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 877 states and 1546 transitions. [2021-10-29 03:04:14,489 INFO L276 IsEmpty]: Start isEmpty. Operand 877 states and 1546 transitions. [2021-10-29 03:04:14,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-10-29 03:04:14,493 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:14,493 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:14,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:14,619 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-10-29 03:04:15,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:15,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1550 states to 879 states and 1550 transitions. [2021-10-29 03:04:15,593 INFO L276 IsEmpty]: Start isEmpty. Operand 879 states and 1550 transitions. [2021-10-29 03:04:15,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-10-29 03:04:15,596 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:15,597 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:15,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:15,701 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-10-29 03:04:16,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:16,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1551 states to 880 states and 1551 transitions. [2021-10-29 03:04:16,043 INFO L276 IsEmpty]: Start isEmpty. Operand 880 states and 1551 transitions. [2021-10-29 03:04:16,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-10-29 03:04:16,046 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:16,047 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:16,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:16,149 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:16,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:16,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 883 states and 1555 transitions. [2021-10-29 03:04:16,178 INFO L276 IsEmpty]: Start isEmpty. Operand 883 states and 1555 transitions. [2021-10-29 03:04:16,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-10-29 03:04:16,181 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:16,181 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:16,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:16,291 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2021-10-29 03:04:16,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:16,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 884 states and 1555 transitions. [2021-10-29 03:04:16,319 INFO L276 IsEmpty]: Start isEmpty. Operand 884 states and 1555 transitions. [2021-10-29 03:04:16,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-10-29 03:04:16,323 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:16,323 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:16,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:16,430 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:16,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:16,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 885 states and 1555 transitions. [2021-10-29 03:04:16,544 INFO L276 IsEmpty]: Start isEmpty. Operand 885 states and 1555 transitions. [2021-10-29 03:04:16,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:16,548 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:16,551 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:16,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:16,654 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:16,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:16,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1559 states to 888 states and 1559 transitions. [2021-10-29 03:04:16,683 INFO L276 IsEmpty]: Start isEmpty. Operand 888 states and 1559 transitions. [2021-10-29 03:04:16,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:16,687 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:16,687 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:16,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:16,832 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-10-29 03:04:17,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:17,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1561 states to 890 states and 1561 transitions. [2021-10-29 03:04:17,153 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 1561 transitions. [2021-10-29 03:04:17,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:17,157 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:17,157 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:17,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:17,257 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-10-29 03:04:17,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:17,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1561 states to 891 states and 1561 transitions. [2021-10-29 03:04:17,278 INFO L276 IsEmpty]: Start isEmpty. Operand 891 states and 1561 transitions. [2021-10-29 03:04:17,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:17,282 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:17,282 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:17,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:17,385 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:20,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:20,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1602 states to 898 states and 1602 transitions. [2021-10-29 03:04:20,100 INFO L276 IsEmpty]: Start isEmpty. Operand 898 states and 1602 transitions. [2021-10-29 03:04:20,103 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:20,103 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:20,104 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:20,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:20,204 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2021-10-29 03:04:21,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:21,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1632 states to 902 states and 1632 transitions. [2021-10-29 03:04:21,349 INFO L276 IsEmpty]: Start isEmpty. Operand 902 states and 1632 transitions. [2021-10-29 03:04:21,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-10-29 03:04:21,351 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:21,351 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:21,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:21,451 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-10-29 03:04:21,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:21,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1632 states to 903 states and 1632 transitions. [2021-10-29 03:04:21,487 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1632 transitions. [2021-10-29 03:04:21,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-10-29 03:04:21,490 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:21,490 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:21,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:21,589 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:21,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:21,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1633 states to 903 states and 1631 transitions. [2021-10-29 03:04:21,628 INFO L276 IsEmpty]: Start isEmpty. Operand 903 states and 1631 transitions. [2021-10-29 03:04:21,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-10-29 03:04:21,631 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:21,631 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:21,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:21,789 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:22,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:22,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1638 states to 906 states and 1636 transitions. [2021-10-29 03:04:22,448 INFO L276 IsEmpty]: Start isEmpty. Operand 906 states and 1636 transitions. [2021-10-29 03:04:22,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-10-29 03:04:22,450 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:22,451 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:22,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:22,551 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:23,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:23,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1665 states to 909 states and 1663 transitions. [2021-10-29 03:04:23,325 INFO L276 IsEmpty]: Start isEmpty. Operand 909 states and 1663 transitions. [2021-10-29 03:04:23,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2021-10-29 03:04:23,328 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:23,328 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:23,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:23,438 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:23,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:23,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1672 states to 913 states and 1670 transitions. [2021-10-29 03:04:23,527 INFO L276 IsEmpty]: Start isEmpty. Operand 913 states and 1670 transitions. [2021-10-29 03:04:23,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2021-10-29 03:04:23,529 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:23,529 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:23,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:23,632 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:23,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:23,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1673 states to 913 states and 1669 transitions. [2021-10-29 03:04:23,664 INFO L276 IsEmpty]: Start isEmpty. Operand 913 states and 1669 transitions. [2021-10-29 03:04:23,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2021-10-29 03:04:23,666 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:23,667 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:23,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:23,781 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:25,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:25,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1680 states to 916 states and 1676 transitions. [2021-10-29 03:04:25,467 INFO L276 IsEmpty]: Start isEmpty. Operand 916 states and 1676 transitions. [2021-10-29 03:04:25,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:25,469 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:25,470 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:25,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:25,577 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:25,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:25,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1684 states to 919 states and 1680 transitions. [2021-10-29 03:04:25,612 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1680 transitions. [2021-10-29 03:04:25,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:25,615 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:25,615 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:25,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:25,719 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:25,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:25,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1685 states to 919 states and 1679 transitions. [2021-10-29 03:04:25,750 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1679 transitions. [2021-10-29 03:04:25,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:25,752 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:25,753 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:25,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:25,914 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:26,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:26,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 921 states and 1682 transitions. [2021-10-29 03:04:26,647 INFO L276 IsEmpty]: Start isEmpty. Operand 921 states and 1682 transitions. [2021-10-29 03:04:26,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:26,650 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:26,650 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:26,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:26,748 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:27,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:27,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 923 states and 1685 transitions. [2021-10-29 03:04:27,899 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1685 transitions. [2021-10-29 03:04:27,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:27,901 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:27,901 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:27,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:28,010 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-10-29 03:04:28,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:28,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1693 states to 924 states and 1687 transitions. [2021-10-29 03:04:28,449 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1687 transitions. [2021-10-29 03:04:28,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-10-29 03:04:28,452 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:28,452 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:28,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:28,559 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2021-10-29 03:04:28,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:28,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1694 states to 925 states and 1688 transitions. [2021-10-29 03:04:28,958 INFO L276 IsEmpty]: Start isEmpty. Operand 925 states and 1688 transitions. [2021-10-29 03:04:28,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:28,962 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:28,962 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:29,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:29,073 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-10-29 03:04:29,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:29,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1694 states to 926 states and 1688 transitions. [2021-10-29 03:04:29,102 INFO L276 IsEmpty]: Start isEmpty. Operand 926 states and 1688 transitions. [2021-10-29 03:04:29,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-10-29 03:04:29,105 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:29,105 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:29,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:29,217 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-10-29 03:04:29,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:29,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1694 states to 927 states and 1688 transitions. [2021-10-29 03:04:29,244 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1688 transitions. [2021-10-29 03:04:29,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-10-29 03:04:29,247 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:29,247 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:29,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:29,371 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:29,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:29,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1698 states to 930 states and 1692 transitions. [2021-10-29 03:04:29,408 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1692 transitions. [2021-10-29 03:04:29,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-10-29 03:04:29,411 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:29,411 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:29,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:29,571 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:29,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:29,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1699 states to 930 states and 1691 transitions. [2021-10-29 03:04:29,609 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1691 transitions. [2021-10-29 03:04:29,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-10-29 03:04:29,612 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:29,612 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:29,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:29,718 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-10-29 03:04:30,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:30,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1702 states to 932 states and 1694 transitions. [2021-10-29 03:04:30,448 INFO L276 IsEmpty]: Start isEmpty. Operand 932 states and 1694 transitions. [2021-10-29 03:04:30,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-10-29 03:04:30,450 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:30,450 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:30,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:30,555 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-10-29 03:04:30,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:30,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1702 states to 933 states and 1694 transitions. [2021-10-29 03:04:30,579 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1694 transitions. [2021-10-29 03:04:30,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-10-29 03:04:30,582 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:30,582 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:30,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:30,684 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:30,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:30,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1710 states to 937 states and 1702 transitions. [2021-10-29 03:04:30,745 INFO L276 IsEmpty]: Start isEmpty. Operand 937 states and 1702 transitions. [2021-10-29 03:04:30,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-10-29 03:04:30,750 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:30,751 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:30,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:30,853 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:31,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:31,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 940 states and 1707 transitions. [2021-10-29 03:04:31,124 INFO L276 IsEmpty]: Start isEmpty. Operand 940 states and 1707 transitions. [2021-10-29 03:04:31,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-10-29 03:04:31,126 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:31,126 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:31,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:31,240 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-10-29 03:04:31,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:31,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1719 states to 943 states and 1711 transitions. [2021-10-29 03:04:31,284 INFO L276 IsEmpty]: Start isEmpty. Operand 943 states and 1711 transitions. [2021-10-29 03:04:31,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-10-29 03:04:31,286 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:31,286 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:31,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:31,386 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:31,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:31,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 947 states and 1717 transitions. [2021-10-29 03:04:31,441 INFO L276 IsEmpty]: Start isEmpty. Operand 947 states and 1717 transitions. [2021-10-29 03:04:31,443 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-10-29 03:04:31,443 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:31,448 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:31,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:31,548 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:32,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:32,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1731 states to 950 states and 1723 transitions. [2021-10-29 03:04:32,297 INFO L276 IsEmpty]: Start isEmpty. Operand 950 states and 1723 transitions. [2021-10-29 03:04:32,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-10-29 03:04:32,299 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:32,299 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:32,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:32,405 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:32,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:32,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1735 states to 953 states and 1727 transitions. [2021-10-29 03:04:32,440 INFO L276 IsEmpty]: Start isEmpty. Operand 953 states and 1727 transitions. [2021-10-29 03:04:32,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-10-29 03:04:32,442 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:32,443 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:32,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:32,543 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-10-29 03:04:33,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:33,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1738 states to 955 states and 1730 transitions. [2021-10-29 03:04:33,121 INFO L276 IsEmpty]: Start isEmpty. Operand 955 states and 1730 transitions. [2021-10-29 03:04:33,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:33,123 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:33,124 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:33,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:33,221 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:33,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:33,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 958 states and 1734 transitions. [2021-10-29 03:04:33,258 INFO L276 IsEmpty]: Start isEmpty. Operand 958 states and 1734 transitions. [2021-10-29 03:04:33,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:33,261 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:33,261 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:33,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:33,359 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:33,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:33,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1747 states to 961 states and 1739 transitions. [2021-10-29 03:04:33,628 INFO L276 IsEmpty]: Start isEmpty. Operand 961 states and 1739 transitions. [2021-10-29 03:04:33,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:33,630 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:33,630 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:33,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:33,725 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:33,758 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:33,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1751 states to 964 states and 1743 transitions. [2021-10-29 03:04:33,762 INFO L276 IsEmpty]: Start isEmpty. Operand 964 states and 1743 transitions. [2021-10-29 03:04:33,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:33,764 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:33,764 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:33,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:33,859 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-10-29 03:04:34,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:34,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1755 states to 966 states and 1747 transitions. [2021-10-29 03:04:34,617 INFO L276 IsEmpty]: Start isEmpty. Operand 966 states and 1747 transitions. [2021-10-29 03:04:34,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:34,619 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:34,620 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:34,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:34,714 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-10-29 03:04:35,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:35,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 968 states and 1749 transitions. [2021-10-29 03:04:35,158 INFO L276 IsEmpty]: Start isEmpty. Operand 968 states and 1749 transitions. [2021-10-29 03:04:35,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:35,166 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:35,166 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:35,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:35,263 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-10-29 03:04:35,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:35,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 969 states and 1749 transitions. [2021-10-29 03:04:35,288 INFO L276 IsEmpty]: Start isEmpty. Operand 969 states and 1749 transitions. [2021-10-29 03:04:35,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-10-29 03:04:35,290 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:35,291 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:35,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:35,385 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2021-10-29 03:04:35,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:35,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 970 states and 1749 transitions. [2021-10-29 03:04:35,877 INFO L276 IsEmpty]: Start isEmpty. Operand 970 states and 1749 transitions. [2021-10-29 03:04:35,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-10-29 03:04:35,879 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:35,879 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:35,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:35,971 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:36,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 973 states and 1753 transitions. [2021-10-29 03:04:36,008 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1753 transitions. [2021-10-29 03:04:36,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-10-29 03:04:36,010 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,010 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:36,100 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:36,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1766 states to 976 states and 1758 transitions. [2021-10-29 03:04:36,362 INFO L276 IsEmpty]: Start isEmpty. Operand 976 states and 1758 transitions. [2021-10-29 03:04:36,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-10-29 03:04:36,364 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,364 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:36,455 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:36,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1770 states to 979 states and 1762 transitions. [2021-10-29 03:04:36,496 INFO L276 IsEmpty]: Start isEmpty. Operand 979 states and 1762 transitions. [2021-10-29 03:04:36,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-10-29 03:04:36,497 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,497 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:36,601 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2021-10-29 03:04:36,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1770 states to 980 states and 1762 transitions. [2021-10-29 03:04:36,630 INFO L276 IsEmpty]: Start isEmpty. Operand 980 states and 1762 transitions. [2021-10-29 03:04:36,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-10-29 03:04:36,632 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,632 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:36,714 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:36,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1770 states to 981 states and 1762 transitions. [2021-10-29 03:04:36,749 INFO L276 IsEmpty]: Start isEmpty. Operand 981 states and 1762 transitions. [2021-10-29 03:04:36,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-10-29 03:04:36,750 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,750 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:36,887 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-10-29 03:04:36,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:36,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1774 states to 984 states and 1766 transitions. [2021-10-29 03:04:36,928 INFO L276 IsEmpty]: Start isEmpty. Operand 984 states and 1766 transitions. [2021-10-29 03:04:36,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-10-29 03:04:36,930 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:36,930 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:36,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:37,024 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2021-10-29 03:04:37,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:37,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 985 states and 1768 transitions. [2021-10-29 03:04:37,574 INFO L276 IsEmpty]: Start isEmpty. Operand 985 states and 1768 transitions. [2021-10-29 03:04:37,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-10-29 03:04:37,576 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:37,577 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:37,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:37,661 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-10-29 03:04:37,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:37,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 986 states and 1768 transitions. [2021-10-29 03:04:37,757 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 1768 transitions. [2021-10-29 03:04:37,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2021-10-29 03:04:37,758 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:37,758 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:37,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:37,838 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-10-29 03:04:37,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:37,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 987 states and 1768 transitions. [2021-10-29 03:04:37,864 INFO L276 IsEmpty]: Start isEmpty. Operand 987 states and 1768 transitions. [2021-10-29 03:04:37,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2021-10-29 03:04:37,866 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:37,866 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:38,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:40,281 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:04:42,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:42,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1810 states to 992 states and 1796 transitions. [2021-10-29 03:04:42,112 INFO L276 IsEmpty]: Start isEmpty. Operand 992 states and 1796 transitions. [2021-10-29 03:04:42,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2021-10-29 03:04:42,114 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:42,114 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:42,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:42,716 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:04:43,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:43,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1812 states to 994 states and 1798 transitions. [2021-10-29 03:04:43,985 INFO L276 IsEmpty]: Start isEmpty. Operand 994 states and 1798 transitions. [2021-10-29 03:04:43,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2021-10-29 03:04:43,987 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:43,987 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:44,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:45,973 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:04:50,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:50,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1846 states to 998 states and 1823 transitions. [2021-10-29 03:04:50,198 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1823 transitions. [2021-10-29 03:04:50,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2021-10-29 03:04:50,201 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:50,201 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:50,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:50,900 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:04:52,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:52,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1847 states to 999 states and 1824 transitions. [2021-10-29 03:04:52,500 INFO L276 IsEmpty]: Start isEmpty. Operand 999 states and 1824 transitions. [2021-10-29 03:04:52,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2021-10-29 03:04:52,503 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:52,503 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:52,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:54,326 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:04:58,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:04:58,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1003 states and 1847 transitions. [2021-10-29 03:04:58,740 INFO L276 IsEmpty]: Start isEmpty. Operand 1003 states and 1847 transitions. [2021-10-29 03:04:58,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2021-10-29 03:04:58,742 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:04:58,742 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:04:58,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:04:59,495 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:05:01,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:05:01,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1884 states to 1004 states and 1848 transitions. [2021-10-29 03:05:01,224 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1848 transitions. [2021-10-29 03:05:01,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2021-10-29 03:05:01,227 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:05:01,227 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:05:01,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:05:03,343 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:05:08,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:05:08,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1922 states to 1008 states and 1869 transitions. [2021-10-29 03:05:08,372 INFO L276 IsEmpty]: Start isEmpty. Operand 1008 states and 1869 transitions. [2021-10-29 03:05:08,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2021-10-29 03:05:08,375 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:05:08,375 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:05:08,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-10-29 03:05:09,207 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-10-29 03:05:11,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-10-29 03:05:11,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1923 states to 1009 states and 1870 transitions. [2021-10-29 03:05:11,184 INFO L276 IsEmpty]: Start isEmpty. Operand 1009 states and 1870 transitions. [2021-10-29 03:05:11,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2021-10-29 03:05:11,186 INFO L427 CodeCheckObserver]: Error Path is FOUND. [2021-10-29 03:05:11,187 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-10-29 03:05:11,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-29 03:05:11,928 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-29 03:05:12,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-29 03:05:22,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-29 03:05:22,165 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-10-29 03:05:28,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-10-29 03:05:29,559 WARN L480 CodeCheckObserver]: This program is UNSAFE, Check terminated with 87 iterations. [2021-10-29 03:05:30,023 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 29.10 03:05:30 ImpRootNode [2021-10-29 03:05:30,024 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2021-10-29 03:05:30,024 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-10-29 03:05:30,024 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-10-29 03:05:30,024 INFO L275 PluginConnector]: Witness Printer initialized [2021-10-29 03:05:30,025 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.10 03:03:54" (3/4) ... [2021-10-29 03:05:30,027 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-10-29 03:05:30,465 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/witness.graphml [2021-10-29 03:05:30,465 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-10-29 03:05:30,467 INFO L168 Benchmark]: Toolchain (without parser) took 555990.38 ms. Allocated memory was 107.0 MB in the beginning and 562.0 MB in the end (delta: 455.1 MB). Free memory was 80.8 MB in the beginning and 314.2 MB in the end (delta: -233.4 MB). Peak memory consumption was 406.4 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,467 INFO L168 Benchmark]: CDTParser took 0.26 ms. Allocated memory is still 107.0 MB. Free memory was 84.2 MB in the beginning and 84.2 MB in the end (delta: 59.8 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-10-29 03:05:30,468 INFO L168 Benchmark]: CACSL2BoogieTranslator took 1938.71 ms. Allocated memory was 107.0 MB in the beginning and 146.8 MB in the end (delta: 39.8 MB). Free memory was 80.5 MB in the beginning and 78.8 MB in the end (delta: 1.6 MB). Peak memory consumption was 74.2 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,468 INFO L168 Benchmark]: Boogie Procedure Inliner took 274.03 ms. Allocated memory is still 146.8 MB. Free memory was 78.8 MB in the beginning and 61.4 MB in the end (delta: 17.5 MB). Peak memory consumption was 16.8 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,469 INFO L168 Benchmark]: Boogie Preprocessor took 290.86 ms. Allocated memory is still 146.8 MB. Free memory was 61.4 MB in the beginning and 76.5 MB in the end (delta: -15.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,469 INFO L168 Benchmark]: RCFGBuilder took 457780.85 ms. Allocated memory was 146.8 MB in the beginning and 562.0 MB in the end (delta: 415.2 MB). Free memory was 76.5 MB in the beginning and 299.5 MB in the end (delta: -223.0 MB). Peak memory consumption was 345.7 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,471 INFO L168 Benchmark]: CodeCheck took 95258.91 ms. Allocated memory is still 562.0 MB. Free memory was 299.5 MB in the beginning and 144.1 MB in the end (delta: 155.4 MB). Peak memory consumption was 154.4 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,471 INFO L168 Benchmark]: Witness Printer took 440.97 ms. Allocated memory is still 562.0 MB. Free memory was 144.1 MB in the beginning and 314.2 MB in the end (delta: -170.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 16.1 GB. [2021-10-29 03:05:30,473 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 52 procedures, 808 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 94.7s, OverallIterations: 87, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: -75024008 SDtfs, -1933731400 SDslu, -890390660 SDs, 0 SdLazy, -1641093226 SolverSat, -75026170 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 116.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 73056 GetRequests, 72656 SyntacticMatches, 100 SemanticMatches, 300 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50802 ImplicationChecksByTransitivity, 59.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 1.0s SsaConstructionTime, 12.8s SatisfiabilityAnalysisTime, 16.4s InterpolantComputationTime, 6156 NumberOfCodeBlocks, 6156 NumberOfCodeBlocksAsserted, 87 NumberOfCheckSat, 5963 ConstructedInterpolants, 0 QuantifiedInterpolants, 8858 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 86 InterpolantComputations, 77 PerfectInterpolantSequences, 3048/3090 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 3957]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L3980] struct v4l2_subdev *si4713_subdev_tuner_ops_group1 ; [L3981] int ldv_irq_1_3 = 0; [L3982] void *ldv_irq_data_1_1 ; [L3983] int ldv_irq_1_0 = 0; [L3984] void *ldv_irq_data_1_0 ; [L3985] int ldv_state_variable_0 ; [L3986] struct v4l2_frequency *si4713_subdev_tuner_ops_group0 ; [L3987] struct v4l2_control *si4713_subdev_core_ops_group2 ; [L3988] int ldv_state_variable_2 ; [L3989] void *ldv_irq_data_1_3 ; [L3990] void *ldv_irq_data_1_2 ; [L3991] int ldv_irq_1_2 = 0; [L3992] int LDV_IN_INTERRUPT = 1; [L3993] int ldv_irq_1_1 = 0; [L3994] int ldv_irq_line_1_3 ; [L3995] struct v4l2_subdev *si4713_subdev_core_ops_group1 ; [L3996] struct v4l2_ext_controls *si4713_subdev_core_ops_group0 ; [L3997] int ldv_state_variable_3 ; [L3998] int ldv_irq_line_1_0 ; [L3999] int ref_cnt ; [L4000] struct v4l2_modulator *si4713_subdev_tuner_ops_group2 ; [L4001] int ldv_irq_line_1_1 ; [L4002] struct i2c_client *si4713_i2c_driver_group0 ; [L4003] int ldv_state_variable_1 ; [L4004] int ldv_irq_line_1_2 ; [L4005] int ldv_state_variable_4 ; [L4144] static int debug ; [L4145] static char const *si4713_supply_names[2U] = { "vio", "vdd"}; [L4146-L4156] static long limiter_times[40U] = { 2000L, 250L, 1000L, 500L, 510L, 1000L, 255L, 2000L, 170L, 3000L, 127L, 4020L, 102L, 5010L, 85L, 6020L, 73L, 7010L, 64L, 7990L, 57L, 8970L, 51L, 10030L, 25L, 20470L, 17L, 30110L, 13L, 39380L, 10L, 51190L, 8L, 63690L, 7L, 73140L, 6L, 85330L, 5L, 102390L}; [L4157-L4160] static unsigned long acomp_rtimes[10U] = { 0UL, 100000UL, 1UL, 200000UL, 2UL, 350000UL, 3UL, 525000UL, 4UL, 1000000UL}; [L4161-L4162] static unsigned long preemphasis_values[6U] = { 2UL, 0UL, 1UL, 1UL, 0UL, 2UL}; [L5779-L5781] static struct v4l2_subdev_core_ops const si4713_subdev_core_ops = {0, 0, 0, 0, 0, 0, 0, & si4713_queryctrl, & si4713_g_ctrl, & si4713_s_ctrl, & si4713_g_ext_ctrls, & si4713_s_ext_ctrls, 0, 0, 0, & si4713_ioctl, 0, 0, 0, 0, 0, 0}; [L5949-L5951] static struct v4l2_subdev_tuner_ops const si4713_subdev_tuner_ops = {0, 0, & si4713_s_frequency, & si4713_g_frequency, 0, 0, & si4713_g_modulator, & si4713_s_modulator, 0, 0}; [L5952-L5953] static struct v4l2_subdev_ops const si4713_subdev_ops = {& si4713_subdev_core_ops, & si4713_subdev_tuner_ops, 0, 0, 0, 0, 0, 0}; [L6083] static struct i2c_device_id const si4713_id[2U] = { {{'s', 'i', '4', '7', '1', '3', '\000'}, 0UL}}; [L6084] struct i2c_device_id const __mod_i2c_device_table ; [L6085-L6089] static struct i2c_driver si4713_i2c_driver = {0U, 0, 0, & si4713_probe, & si4713_remove, 0, 0, 0, 0, 0, {"si4713", 0, 0, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, (struct i2c_device_id const *)(& si4713_id), 0, 0, {0, 0}}; [L6105] int ldv_retval_0 ; [L6106] int ldv_retval_1 ; [L6271] unsigned int ldvarg1 ; [L6272] unsigned int tmp ; [L6273] void *ldvarg0 ; [L6274] void *tmp___0 ; [L6275] struct v4l2_queryctrl *ldvarg2 ; [L6276] void *tmp___1 ; [L6277] struct i2c_device_id *ldvarg3 ; [L6278] void *tmp___2 ; [L6279] int tmp___3 ; [L6280] int tmp___4 ; [L6281] int tmp___5 ; [L6282] int tmp___6 ; [L6283] int tmp___7 ; [L6285] tmp = __VERIFIER_nondet_uint() [L6286] ldvarg1 = tmp VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6287] CALL, EXPR ldv_zalloc(1UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6287] RET, EXPR ldv_zalloc(1UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6287] tmp___0 = ldv_zalloc(1UL) [L6288] ldvarg0 = tmp___0 VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6289] CALL, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6289] RET, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6289] tmp___1 = ldv_zalloc(68UL) [L6290] ldvarg2 = (struct v4l2_queryctrl *)tmp___1 VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6291] CALL, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6291] RET, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6291] tmp___2 = ldv_zalloc(32UL) [L6292] ldvarg3 = (struct i2c_device_id *)tmp___2 [L6294] ldv_state_variable_4 = 0 [L6295] ldv_state_variable_1 = 1 [L6296] ref_cnt = 0 [L6297] ldv_state_variable_0 = 1 [L6298] ldv_state_variable_3 = 0 [L6299] ldv_state_variable_2 = 0 VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6301] tmp___3 = __VERIFIER_nondet_int() [L6303] case 0: [L6356] case 1: [L6362] case 2: VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6363] COND TRUE ldv_state_variable_0 != 0 [L6364] tmp___5 = __VERIFIER_nondet_int() [L6366] case 0: [L6374] case 1: VAL [__mod_i2c_device_table=0, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6375] COND TRUE ldv_state_variable_0 == 1 [L6092] int tmp ; [L4108] int tmp ; [L6677] return __VERIFIER_nondet_int(); [L4110] tmp = i2c_register_driver(& __this_module, driver) [L4111] return (tmp); [L6094] tmp = i2c_add_driver(& si4713_i2c_driver) [L6095] return (tmp); [L6376] ldv_retval_0 = si4713_module_init() [L6377] COND TRUE ldv_retval_0 == 0 [L6378] ldv_state_variable_0 = 3 [L6379] ldv_state_variable_2 = 1 [L6111] void *tmp ; VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6113] CALL, EXPR ldv_zalloc(1168UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6113] RET, EXPR ldv_zalloc(1168UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6113] tmp = ldv_zalloc(1168UL) [L6114] si4713_i2c_driver_group0 = (struct i2c_client *)tmp [L6381] ldv_state_variable_3 = 1 [L6256] void *tmp ; [L6257] void *tmp___0 ; [L6258] void *tmp___1 ; VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6260] CALL, EXPR ldv_zalloc(44UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6260] RET, EXPR ldv_zalloc(44UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6260] tmp = ldv_zalloc(44UL) [L6261] si4713_subdev_tuner_ops_group0 = (struct v4l2_frequency *)tmp VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6262] CALL, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6262] RET, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6262] tmp___0 = ldv_zalloc(1736UL) [L6263] si4713_subdev_tuner_ops_group1 = (struct v4l2_subdev *)tmp___0 VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6264] CALL, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6264] RET, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6264] tmp___1 = ldv_zalloc(68UL) [L6265] si4713_subdev_tuner_ops_group2 = (struct v4l2_modulator *)tmp___1 [L6383] ldv_state_variable_4 = 1 [L6120] void *tmp ; [L6121] void *tmp___0 ; [L6122] void *tmp___1 ; VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6124] CALL, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6124] RET, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6124] tmp = ldv_zalloc(32UL) [L6125] si4713_subdev_core_ops_group0 = (struct v4l2_ext_controls *)tmp VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6126] CALL, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6126] RET, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6126] tmp___0 = ldv_zalloc(1736UL) [L6127] si4713_subdev_core_ops_group1 = (struct v4l2_subdev *)tmp___0 VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6128] CALL, EXPR ldv_zalloc(8UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6128] RET, EXPR ldv_zalloc(8UL) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6128] tmp___1 = ldv_zalloc(8UL) [L6129] si4713_subdev_core_ops_group2 = (struct v4l2_control *)tmp___1 VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6387] COND FALSE !(ldv_retval_0 != 0) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6301] tmp___3 = __VERIFIER_nondet_int() [L6303] case 0: VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6304] COND TRUE ldv_state_variable_4 != 0 [L6305] tmp___4 = __VERIFIER_nondet_int() [L6307] case 0: [L6314] case 1: [L6321] case 2: [L6328] case 3: VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6329] COND TRUE ldv_state_variable_4 == 1 [L5502] struct si4713_device *sdev ; [L5503] struct v4l2_subdev const *__mptr ; [L5504] int i ; [L5505] int err ; [L5507] __mptr = (struct v4l2_subdev const *)sd [L5508] sdev = (struct si4713_device *)__mptr [L5509] EXPR ctrls->ctrl_class VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L5509] COND FALSE !(ctrls->ctrl_class != 10158080U) [L5513] i = 0 VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L5536] EXPR ctrls->count VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L5536] COND TRUE (__u32 )i < ctrls->count [L5516] EXPR ctrls->controls [L5516] (ctrls->controls + (unsigned long )i)->id [L5517] case 10160389U: [L5518] case 10160390U: [L5519] ctrls->controls [L4924] struct v4l2_queryctrl vqc ; [L4925] int len ; [L4926] s32 rval ; [L4927] char ps_name[97U] ; [L4928] unsigned long tmp ; [L4929] size_t tmp___0 ; [L4930] char radio_text[385U] ; [L4931] unsigned long tmp___1 ; [L4932] size_t tmp___2 ; [L4934] rval = 0 [L4935] EXPR control->id [L4935] vqc.id = control->id [L4936] CALL, EXPR si4713_queryctrl(& sdev->sd, & vqc) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, qc={20:0}, ref_cnt=0, sd={0:0}, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L5588] int rval ; [L5590] rval = 0 [L5591] qc->id [L5592] case 9963785U: [L5595] case 10160386U: [L5598] case 10160387U: [L5601] case 10160385U: [L5604] case 10160389U: VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, qc={20:0}, qc={20:0}, qc->id=10160389, ref_cnt=0, rval=0, sd={0:0}, sd={0:0}, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L5605] CALL, EXPR v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) VAL [\old(arg1)=0, \old(arg2)=96, \old(arg3)=8, \old(arg4)=0, __mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, arg0={20:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6730] return __VERIFIER_nondet_int(); [L5605] RET, EXPR v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, qc={20:0}, qc={20:0}, qc->id=10160389, ref_cnt=0, rval=0, sd={0:0}, sd={0:0}, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}, v4l2_ctrl_query_fill(qc, 0, 96, 8, 0)=0] [L5605] rval = v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) [L5657] return (rval); [L4936] RET, EXPR si4713_queryctrl(& sdev->sd, & vqc) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L4936] rval = si4713_queryctrl(& sdev->sd, & vqc) [L4937] COND FALSE !(rval < 0) [L4941] control->id [L4942] case 10160389U: [L4943] EXPR control->size [L4943] len = (int )(control->size - 1U) [L4944] COND FALSE !(len > 96) [L4949] EXPR control->ldv_23757.string VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L4949-L4950] CALL ldv_copy_from_user_7((void *)(& ps_name), (void const *)control->ldv_23757.string, (unsigned long )len) VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6524] unsigned long tmp ; VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6526] CALL ldv_check_len((long )n) VAL [\old(n)=-2147483648, __mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6599] COND FALSE !(n >= 0L) VAL [\old(n)=-2147483648, __mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, n=-2147483648, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L6601] CALL ldv_error() VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] [L3957] reach_error() VAL [__mod_i2c_device_table=0, __this_module={135:134}, acomp_rtimes={44:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={27:0}, preemphasis_values={12:0}, ref_cnt=0, si4713_i2c_driver={30:0}, si4713_i2c_driver_group0={0:0}, si4713_id={22:0}, si4713_subdev_core_ops={21:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={26:0}, si4713_subdev_tuner_ops={43:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={51:0}] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26 ms. Allocated memory is still 107.0 MB. Free memory was 84.2 MB in the beginning and 84.2 MB in the end (delta: 59.8 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 1938.71 ms. Allocated memory was 107.0 MB in the beginning and 146.8 MB in the end (delta: 39.8 MB). Free memory was 80.5 MB in the beginning and 78.8 MB in the end (delta: 1.6 MB). Peak memory consumption was 74.2 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 274.03 ms. Allocated memory is still 146.8 MB. Free memory was 78.8 MB in the beginning and 61.4 MB in the end (delta: 17.5 MB). Peak memory consumption was 16.8 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 290.86 ms. Allocated memory is still 146.8 MB. Free memory was 61.4 MB in the beginning and 76.5 MB in the end (delta: -15.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 457780.85 ms. Allocated memory was 146.8 MB in the beginning and 562.0 MB in the end (delta: 415.2 MB). Free memory was 76.5 MB in the beginning and 299.5 MB in the end (delta: -223.0 MB). Peak memory consumption was 345.7 MB. Max. memory is 16.1 GB. * CodeCheck took 95258.91 ms. Allocated memory is still 562.0 MB. Free memory was 299.5 MB in the beginning and 144.1 MB in the end (delta: 155.4 MB). Peak memory consumption was 154.4 MB. Max. memory is 16.1 GB. * Witness Printer took 440.97 ms. Allocated memory is still 562.0 MB. Free memory was 144.1 MB in the beginning and 314.2 MB in the end (delta: -170.1 MB). Peak memory consumption was 15.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. RESULT: Ultimate proved your program to be incorrect! [2021-10-29 03:05:30,616 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7e8178f0-a96d-4e6f-9f12-c283630633fc/bin/ukojak-Rh5K9KB4LI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Ended with exit code 0 Received shutdown request...