./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aef121e0 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/config/KojakReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/config/svcomp-Reach-64bit-Kojak_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Kojak --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 56ff1aa7a746f87b9c1b788d1f6729b885abef13666f4b3b25250b45ff5a6786 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-aef121e [2021-11-23 01:00:12,621 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-23 01:00:12,624 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-23 01:00:12,660 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-23 01:00:12,661 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-23 01:00:12,662 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-23 01:00:12,664 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-23 01:00:12,666 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-23 01:00:12,669 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-23 01:00:12,670 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-23 01:00:12,671 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-23 01:00:12,673 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-23 01:00:12,673 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-23 01:00:12,675 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-23 01:00:12,676 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-23 01:00:12,678 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-23 01:00:12,679 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-23 01:00:12,680 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-23 01:00:12,682 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-23 01:00:12,685 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-23 01:00:12,687 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-23 01:00:12,689 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-23 01:00:12,690 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-23 01:00:12,691 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-23 01:00:12,695 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-23 01:00:12,695 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-23 01:00:12,696 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-23 01:00:12,697 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-23 01:00:12,698 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-23 01:00:12,699 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-23 01:00:12,699 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-23 01:00:12,700 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-23 01:00:12,701 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-23 01:00:12,702 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-23 01:00:12,704 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-23 01:00:12,704 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-23 01:00:12,705 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-23 01:00:12,706 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-23 01:00:12,706 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-23 01:00:12,707 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-23 01:00:12,708 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-23 01:00:12,712 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/config/svcomp-Reach-64bit-Kojak_Default.epf [2021-11-23 01:00:12,735 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-23 01:00:12,736 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-23 01:00:12,737 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-11-23 01:00:12,737 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ALWAYS [2021-11-23 01:00:12,738 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-23 01:00:12,738 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-23 01:00:12,738 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-23 01:00:12,738 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-23 01:00:12,739 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-23 01:00:12,739 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-11-23 01:00:12,739 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-11-23 01:00:12,739 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-11-23 01:00:12,740 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-23 01:00:12,740 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-23 01:00:12,740 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-11-23 01:00:12,740 INFO L136 SettingsManager]: Preferences of CodeCheck differ from their defaults: [2021-11-23 01:00:12,741 INFO L138 SettingsManager]: * Timeout in seconds=1000000 [2021-11-23 01:00:12,741 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-23 01:00:12,741 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2021-11-23 01:00:12,741 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-23 01:00:12,742 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-11-23 01:00:12,742 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-11-23 01:00:12,742 INFO L138 SettingsManager]: * Trace refinement strategy=PENGUIN [2021-11-23 01:00:12,742 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-11-23 01:00:12,742 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-11-23 01:00:12,743 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Kojak Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 56ff1aa7a746f87b9c1b788d1f6729b885abef13666f4b3b25250b45ff5a6786 [2021-11-23 01:00:13,050 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-23 01:00:13,076 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-23 01:00:13,079 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-23 01:00:13,080 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-23 01:00:13,081 INFO L275 PluginConnector]: CDTParser initialized [2021-11-23 01:00:13,083 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i [2021-11-23 01:00:13,153 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/data/1adea5a4b/b6b8a4fe5b3a44ca86181cf02ed3ad63/FLAGe729b79ce [2021-11-23 01:00:14,040 INFO L306 CDTParser]: Found 1 translation units. [2021-11-23 01:00:14,041 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i [2021-11-23 01:00:14,096 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/data/1adea5a4b/b6b8a4fe5b3a44ca86181cf02ed3ad63/FLAGe729b79ce [2021-11-23 01:00:14,532 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/data/1adea5a4b/b6b8a4fe5b3a44ca86181cf02ed3ad63 [2021-11-23 01:00:14,534 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-23 01:00:14,535 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-23 01:00:14,537 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-23 01:00:14,537 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-23 01:00:14,541 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-23 01:00:14,541 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:00:14" (1/1) ... [2021-11-23 01:00:14,543 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ac800f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:14, skipping insertion in model container [2021-11-23 01:00:14,543 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 01:00:14" (1/1) ... [2021-11-23 01:00:14,560 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-23 01:00:14,671 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-23 01:00:15,334 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i[115668,115681] [2021-11-23 01:00:16,251 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 01:00:16,288 INFO L203 MainTranslator]: Completed pre-run [2021-11-23 01:00:16,410 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-064368f-1-111_1a-drivers--media--radio--si4713-i2c.ko-entry_point.cil.out.i[115668,115681] [2021-11-23 01:00:16,589 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-23 01:00:16,708 INFO L208 MainTranslator]: Completed translation [2021-11-23 01:00:16,709 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16 WrapperNode [2021-11-23 01:00:16,709 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-23 01:00:16,710 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-23 01:00:16,710 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-23 01:00:16,711 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-23 01:00:16,719 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:16,816 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:16,988 INFO L137 Inliner]: procedures = 160, calls = 1221, calls flagged for inlining = 70, calls inlined = 70, statements flattened = 3023 [2021-11-23 01:00:16,989 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-23 01:00:16,989 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-23 01:00:16,990 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-23 01:00:16,990 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-23 01:00:16,999 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:16,999 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,021 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,022 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,145 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,162 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,181 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,206 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-23 01:00:17,207 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-23 01:00:17,207 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-23 01:00:17,207 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-23 01:00:17,208 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 01:00:16" (1/1) ... [2021-11-23 01:00:17,223 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 [2021-11-23 01:00:17,234 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/z3 [2021-11-23 01:00:17,261 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (exit command is (exit), workingDir is null) [2021-11-23 01:00:17,292 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Waiting until timeout for monitored process [2021-11-23 01:00:17,306 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_rds_radio_text [2021-11-23 01:00:17,307 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_rds_radio_text [2021-11-23 01:00:17,307 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2021-11-23 01:00:17,307 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~$Pointer$ [2021-11-23 01:00:17,307 INFO L130 BoogieDeclarations]: Found specification of procedure write~unchecked~$Pointer$ [2021-11-23 01:00:17,307 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2021-11-23 01:00:17,308 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2021-11-23 01:00:17,308 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-23 01:00:17,308 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_is_valid [2021-11-23 01:00:17,308 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_is_valid [2021-11-23 01:00:17,308 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_wait_stc [2021-11-23 01:00:17,308 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_wait_stc [2021-11-23 01:00:17,309 INFO L130 BoogieDeclarations]: Found specification of procedure dev_to_usecs [2021-11-23 01:00:17,309 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_to_usecs [2021-11-23 01:00:17,309 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_mute [2021-11-23 01:00:17,309 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_mute [2021-11-23 01:00:17,309 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2021-11-23 01:00:17,309 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2021-11-23 01:00:17,310 INFO L130 BoogieDeclarations]: Found specification of procedure wait_for_completion_timeout [2021-11-23 01:00:17,310 INFO L138 BoogieDeclarations]: Found implementation of procedure wait_for_completion_timeout [2021-11-23 01:00:17,310 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_malloc [2021-11-23 01:00:17,310 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2021-11-23 01:00:17,310 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_power_state [2021-11-23 01:00:17,310 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_power_state [2021-11-23 01:00:17,311 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_choose_econtrol_action [2021-11-23 01:00:17,311 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_choose_econtrol_action [2021-11-23 01:00:17,311 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_len [2021-11-23 01:00:17,311 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_len [2021-11-23 01:00:17,311 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2021-11-23 01:00:17,311 INFO L138 BoogieDeclarations]: Found implementation of procedure kfree [2021-11-23 01:00:17,312 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2021-11-23 01:00:17,312 INFO L138 BoogieDeclarations]: Found implementation of procedure free_irq [2021-11-23 01:00:17,312 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_econtrol_tune [2021-11-23 01:00:17,312 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_econtrol_tune [2021-11-23 01:00:17,312 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-23 01:00:17,312 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_unlock [2021-11-23 01:00:17,313 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_unlock [2021-11-23 01:00:17,313 INFO L130 BoogieDeclarations]: Found specification of procedure copy_to_user [2021-11-23 01:00:17,313 INFO L138 BoogieDeclarations]: Found implementation of procedure copy_to_user [2021-11-23 01:00:17,313 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2021-11-23 01:00:17,313 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2021-11-23 01:00:17,313 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2021-11-23 01:00:17,314 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2021-11-23 01:00:17,314 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__copy_from_user_1 [2021-11-23 01:00:17,314 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__copy_from_user_1 [2021-11-23 01:00:17,314 INFO L130 BoogieDeclarations]: Found specification of procedure ldv__builtin_expect [2021-11-23 01:00:17,314 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv__builtin_expect [2021-11-23 01:00:17,314 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_strlen [2021-11-23 01:00:17,315 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_strlen [2021-11-23 01:00:17,315 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_set_value [2021-11-23 01:00:17,315 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_set_value [2021-11-23 01:00:17,315 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_tx_rds_buff [2021-11-23 01:00:17,315 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_tx_rds_buff [2021-11-23 01:00:17,315 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2021-11-23 01:00:17,316 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2021-11-23 01:00:17,316 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-11-23 01:00:17,316 INFO L130 BoogieDeclarations]: Found specification of procedure v4l2_ctrl_query_fill [2021-11-23 01:00:17,316 INFO L138 BoogieDeclarations]: Found implementation of procedure v4l2_ctrl_query_fill [2021-11-23 01:00:17,316 INFO L130 BoogieDeclarations]: Found specification of procedure validate_range [2021-11-23 01:00:17,316 INFO L138 BoogieDeclarations]: Found implementation of procedure validate_range [2021-11-23 01:00:17,316 INFO L130 BoogieDeclarations]: Found specification of procedure regulator_bulk_free [2021-11-23 01:00:17,317 INFO L138 BoogieDeclarations]: Found implementation of procedure regulator_bulk_free [2021-11-23 01:00:17,317 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_econtrol_integers [2021-11-23 01:00:17,317 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_econtrol_integers [2021-11-23 01:00:17,317 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-23 01:00:17,317 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_undef_int [2021-11-23 01:00:17,317 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_undef_int [2021-11-23 01:00:17,318 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2021-11-23 01:00:17,318 INFO L130 BoogieDeclarations]: Found specification of procedure regulator_bulk_disable [2021-11-23 01:00:17,318 INFO L138 BoogieDeclarations]: Found implementation of procedure regulator_bulk_disable [2021-11-23 01:00:17,318 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-23 01:00:17,318 INFO L130 BoogieDeclarations]: Found specification of procedure gpio_free [2021-11-23 01:00:17,318 INFO L138 BoogieDeclarations]: Found implementation of procedure gpio_free [2021-11-23 01:00:17,319 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2021-11-23 01:00:17,319 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2021-11-23 01:00:17,319 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_send_command [2021-11-23 01:00:17,319 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_send_command [2021-11-23 01:00:17,319 INFO L130 BoogieDeclarations]: Found specification of procedure v4l2_get_subdevdata [2021-11-23 01:00:17,319 INFO L138 BoogieDeclarations]: Found implementation of procedure v4l2_get_subdevdata [2021-11-23 01:00:17,320 INFO L130 BoogieDeclarations]: Found specification of procedure usecs_to_jiffies [2021-11-23 01:00:17,320 INFO L138 BoogieDeclarations]: Found implementation of procedure usecs_to_jiffies [2021-11-23 01:00:17,320 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_write_property [2021-11-23 01:00:17,320 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_write_property [2021-11-23 01:00:17,320 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2021-11-23 01:00:17,320 INFO L130 BoogieDeclarations]: Found specification of procedure strlcpy [2021-11-23 01:00:17,321 INFO L138 BoogieDeclarations]: Found implementation of procedure strlcpy [2021-11-23 01:00:17,321 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-23 01:00:17,321 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2021-11-23 01:00:17,321 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_read_property [2021-11-23 01:00:17,321 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_read_property [2021-11-23 01:00:17,321 INFO L130 BoogieDeclarations]: Found specification of procedure might_fault [2021-11-23 01:00:17,321 INFO L138 BoogieDeclarations]: Found implementation of procedure might_fault [2021-11-23 01:00:17,322 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_s_frequency [2021-11-23 01:00:17,322 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_s_frequency [2021-11-23 01:00:17,322 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_copy_from_user_7 [2021-11-23 01:00:17,322 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_copy_from_user_7 [2021-11-23 01:00:17,322 INFO L130 BoogieDeclarations]: Found specification of procedure kmalloc [2021-11-23 01:00:17,322 INFO L138 BoogieDeclarations]: Found implementation of procedure kmalloc [2021-11-23 01:00:17,322 INFO L130 BoogieDeclarations]: Found specification of procedure mutex_lock_nested [2021-11-23 01:00:17,323 INFO L138 BoogieDeclarations]: Found implementation of procedure mutex_lock_nested [2021-11-23 01:00:17,323 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-23 01:00:17,323 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_tx_tune_status [2021-11-23 01:00:17,323 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_tx_tune_status [2021-11-23 01:00:17,323 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_ret_val [2021-11-23 01:00:17,323 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_check_ret_val [2021-11-23 01:00:17,324 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_update_tune_status [2021-11-23 01:00:17,324 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_update_tune_status [2021-11-23 01:00:17,324 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_set_rds_ps_name [2021-11-23 01:00:17,324 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_set_rds_ps_name [2021-11-23 01:00:17,324 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_queryctrl [2021-11-23 01:00:17,324 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_queryctrl [2021-11-23 01:00:17,325 INFO L130 BoogieDeclarations]: Found specification of procedure si4713_s_modulator [2021-11-23 01:00:17,325 INFO L138 BoogieDeclarations]: Found implementation of procedure si4713_s_modulator [2021-11-23 01:00:17,325 INFO L130 BoogieDeclarations]: Found specification of procedure read~unchecked~int [2021-11-23 01:00:17,325 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2021-11-23 01:00:17,325 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2021-11-23 01:00:17,325 INFO L130 BoogieDeclarations]: Found specification of procedure strncpy [2021-11-23 01:00:17,326 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-23 01:00:17,326 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-23 01:00:17,899 INFO L236 CfgBuilder]: Building ICFG [2021-11-23 01:00:17,901 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-23 01:00:18,209 INFO L768 $ProcedureCfgBuilder]: dead code at ProgramPoint ldv_stopFINAL: assume true; [2021-11-23 01:00:22,765 INFO L277 CfgBuilder]: Performing block encoding [2021-11-23 01:00:23,857 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-23 01:00:23,858 INFO L301 CfgBuilder]: Removed 0 assume(true) statements. [2021-11-23 01:00:23,867 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:00:23 BoogieIcfgContainer [2021-11-23 01:00:23,867 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-23 01:00:23,869 INFO L113 PluginConnector]: ------------------------CodeCheck---------------------------- [2021-11-23 01:00:23,869 INFO L271 PluginConnector]: Initializing CodeCheck... [2021-11-23 01:00:23,879 INFO L275 PluginConnector]: CodeCheck initialized [2021-11-23 01:00:23,879 INFO L185 PluginConnector]: Executing the observer CodeCheckObserver from plugin CodeCheck for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:00:23" (1/1) ... [2021-11-23 01:00:23,892 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-23 01:00:24,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:24,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 808 states and 1185 transitions. [2021-11-23 01:00:24,110 INFO L276 IsEmpty]: Start isEmpty. Operand 808 states and 1185 transitions. [2021-11-23 01:00:24,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2021-11-23 01:00:24,135 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:24,136 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:24,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:24,700 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:24,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:24,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1217 states to 810 states and 1217 transitions. [2021-11-23 01:00:24,984 INFO L276 IsEmpty]: Start isEmpty. Operand 810 states and 1217 transitions. [2021-11-23 01:00:24,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2021-11-23 01:00:24,993 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:24,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:25,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:25,232 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:25,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:25,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1255 states to 814 states and 1255 transitions. [2021-11-23 01:00:25,358 INFO L276 IsEmpty]: Start isEmpty. Operand 814 states and 1255 transitions. [2021-11-23 01:00:25,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2021-11-23 01:00:25,372 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:25,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:25,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:25,523 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:25,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:25,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1294 states to 819 states and 1294 transitions. [2021-11-23 01:00:25,716 INFO L276 IsEmpty]: Start isEmpty. Operand 819 states and 1294 transitions. [2021-11-23 01:00:25,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2021-11-23 01:00:25,719 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:25,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:25,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:25,837 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:25,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:25,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1303 states to 823 states and 1303 transitions. [2021-11-23 01:00:25,938 INFO L276 IsEmpty]: Start isEmpty. Operand 823 states and 1303 transitions. [2021-11-23 01:00:25,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-11-23 01:00:25,942 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:25,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:25,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,048 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:26,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:26,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1303 states to 824 states and 1303 transitions. [2021-11-23 01:00:26,072 INFO L276 IsEmpty]: Start isEmpty. Operand 824 states and 1303 transitions. [2021-11-23 01:00:26,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-11-23 01:00:26,075 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:26,075 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:26,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,261 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:26,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:26,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1308 states to 827 states and 1308 transitions. [2021-11-23 01:00:26,301 INFO L276 IsEmpty]: Start isEmpty. Operand 827 states and 1308 transitions. [2021-11-23 01:00:26,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2021-11-23 01:00:26,304 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:26,304 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:26,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,448 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:26,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:26,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1311 states to 829 states and 1311 transitions. [2021-11-23 01:00:26,472 INFO L276 IsEmpty]: Start isEmpty. Operand 829 states and 1311 transitions. [2021-11-23 01:00:26,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-11-23 01:00:26,475 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:26,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:26,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,608 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:26,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:26,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1311 states to 830 states and 1311 transitions. [2021-11-23 01:00:26,637 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1311 transitions. [2021-11-23 01:00:26,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-11-23 01:00:26,641 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:26,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:26,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,765 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:26,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:26,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1316 states to 833 states and 1316 transitions. [2021-11-23 01:00:26,822 INFO L276 IsEmpty]: Start isEmpty. Operand 833 states and 1316 transitions. [2021-11-23 01:00:26,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-11-23 01:00:26,825 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:26,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:26,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:26,940 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:27,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:27,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1351 states to 839 states and 1351 transitions. [2021-11-23 01:00:27,247 INFO L276 IsEmpty]: Start isEmpty. Operand 839 states and 1351 transitions. [2021-11-23 01:00:27,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2021-11-23 01:00:27,253 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:27,253 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:27,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:27,356 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:27,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:27,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1345 states to 838 states and 1345 transitions. [2021-11-23 01:00:27,403 INFO L276 IsEmpty]: Start isEmpty. Operand 838 states and 1345 transitions. [2021-11-23 01:00:27,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2021-11-23 01:00:27,406 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:27,407 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:27,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:27,565 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:27,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:27,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1339 states to 837 states and 1339 transitions. [2021-11-23 01:00:27,615 INFO L276 IsEmpty]: Start isEmpty. Operand 837 states and 1339 transitions. [2021-11-23 01:00:27,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2021-11-23 01:00:27,618 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:27,618 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:27,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:27,740 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:28,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:28,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1374 states to 844 states and 1374 transitions. [2021-11-23 01:00:28,234 INFO L276 IsEmpty]: Start isEmpty. Operand 844 states and 1374 transitions. [2021-11-23 01:00:28,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-11-23 01:00:28,237 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:28,237 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:28,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:28,349 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:28,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:28,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1375 states to 845 states and 1375 transitions. [2021-11-23 01:00:28,420 INFO L276 IsEmpty]: Start isEmpty. Operand 845 states and 1375 transitions. [2021-11-23 01:00:28,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2021-11-23 01:00:28,423 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:28,424 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:28,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:28,522 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:28,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:28,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1381 states to 848 states and 1381 transitions. [2021-11-23 01:00:28,838 INFO L276 IsEmpty]: Start isEmpty. Operand 848 states and 1381 transitions. [2021-11-23 01:00:28,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-11-23 01:00:28,841 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:28,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:28,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:28,946 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:28,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:28,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1381 states to 849 states and 1381 transitions. [2021-11-23 01:00:28,972 INFO L276 IsEmpty]: Start isEmpty. Operand 849 states and 1381 transitions. [2021-11-23 01:00:28,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-11-23 01:00:28,978 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:28,978 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:29,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:29,162 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:29,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:29,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1428 states to 856 states and 1428 transitions. [2021-11-23 01:00:29,776 INFO L276 IsEmpty]: Start isEmpty. Operand 856 states and 1428 transitions. [2021-11-23 01:00:29,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-11-23 01:00:29,779 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:29,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:29,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:29,874 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:30,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:30,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1431 states to 858 states and 1431 transitions. [2021-11-23 01:00:30,056 INFO L276 IsEmpty]: Start isEmpty. Operand 858 states and 1431 transitions. [2021-11-23 01:00:30,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-11-23 01:00:30,063 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:30,063 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:30,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:30,158 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:30,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:30,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1434 states to 860 states and 1434 transitions. [2021-11-23 01:00:30,333 INFO L276 IsEmpty]: Start isEmpty. Operand 860 states and 1434 transitions. [2021-11-23 01:00:30,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2021-11-23 01:00:30,340 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:30,340 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:30,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:30,472 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:30,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:30,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1432 states to 859 states and 1432 transitions. [2021-11-23 01:00:30,534 INFO L276 IsEmpty]: Start isEmpty. Operand 859 states and 1432 transitions. [2021-11-23 01:00:30,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-11-23 01:00:30,537 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:30,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:30,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:30,630 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:30,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:30,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1432 states to 860 states and 1432 transitions. [2021-11-23 01:00:30,665 INFO L276 IsEmpty]: Start isEmpty. Operand 860 states and 1432 transitions. [2021-11-23 01:00:30,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-11-23 01:00:30,668 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:30,669 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:30,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:30,794 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:31,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:31,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1476 states to 866 states and 1476 transitions. [2021-11-23 01:00:31,465 INFO L276 IsEmpty]: Start isEmpty. Operand 866 states and 1476 transitions. [2021-11-23 01:00:31,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-11-23 01:00:31,483 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:31,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:31,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:31,594 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:31,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:31,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1508 states to 869 states and 1508 transitions. [2021-11-23 01:00:31,980 INFO L276 IsEmpty]: Start isEmpty. Operand 869 states and 1508 transitions. [2021-11-23 01:00:31,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2021-11-23 01:00:31,984 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:31,984 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:32,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:32,077 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:32,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:32,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1511 states to 871 states and 1511 transitions. [2021-11-23 01:00:32,245 INFO L276 IsEmpty]: Start isEmpty. Operand 871 states and 1511 transitions. [2021-11-23 01:00:32,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-11-23 01:00:32,249 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:32,249 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:32,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:32,364 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:32,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:32,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1523 states to 876 states and 1523 transitions. [2021-11-23 01:00:32,445 INFO L276 IsEmpty]: Start isEmpty. Operand 876 states and 1523 transitions. [2021-11-23 01:00:32,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-11-23 01:00:32,448 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:32,449 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:32,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:32,523 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-11-23 01:00:32,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:32,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1527 states to 878 states and 1527 transitions. [2021-11-23 01:00:32,749 INFO L276 IsEmpty]: Start isEmpty. Operand 878 states and 1527 transitions. [2021-11-23 01:00:32,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2021-11-23 01:00:32,752 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:32,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:32,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:32,841 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-11-23 01:00:32,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:32,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1528 states to 879 states and 1528 transitions. [2021-11-23 01:00:32,934 INFO L276 IsEmpty]: Start isEmpty. Operand 879 states and 1528 transitions. [2021-11-23 01:00:32,937 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-11-23 01:00:32,937 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:32,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:32,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,020 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:33,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1532 states to 882 states and 1532 transitions. [2021-11-23 01:00:33,043 INFO L276 IsEmpty]: Start isEmpty. Operand 882 states and 1532 transitions. [2021-11-23 01:00:33,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-11-23 01:00:33,046 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,046 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,125 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:33,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1532 states to 883 states and 1532 transitions. [2021-11-23 01:00:33,171 INFO L276 IsEmpty]: Start isEmpty. Operand 883 states and 1532 transitions. [2021-11-23 01:00:33,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2021-11-23 01:00:33,174 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,249 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2021-11-23 01:00:33,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1532 states to 884 states and 1532 transitions. [2021-11-23 01:00:33,270 INFO L276 IsEmpty]: Start isEmpty. Operand 884 states and 1532 transitions. [2021-11-23 01:00:33,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:33,273 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,353 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:33,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1536 states to 887 states and 1536 transitions. [2021-11-23 01:00:33,373 INFO L276 IsEmpty]: Start isEmpty. Operand 887 states and 1536 transitions. [2021-11-23 01:00:33,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:33,376 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,456 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:33,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1536 states to 888 states and 1536 transitions. [2021-11-23 01:00:33,477 INFO L276 IsEmpty]: Start isEmpty. Operand 888 states and 1536 transitions. [2021-11-23 01:00:33,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:33,481 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,482 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,561 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2021-11-23 01:00:33,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1537 states to 889 states and 1537 transitions. [2021-11-23 01:00:33,684 INFO L276 IsEmpty]: Start isEmpty. Operand 889 states and 1537 transitions. [2021-11-23 01:00:33,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:33,687 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,758 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:33,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:33,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1537 states to 890 states and 1537 transitions. [2021-11-23 01:00:33,782 INFO L276 IsEmpty]: Start isEmpty. Operand 890 states and 1537 transitions. [2021-11-23 01:00:33,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:33,786 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:33,786 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:33,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:33,869 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:34,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:34,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1570 states to 896 states and 1570 transitions. [2021-11-23 01:00:34,273 INFO L276 IsEmpty]: Start isEmpty. Operand 896 states and 1570 transitions. [2021-11-23 01:00:34,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:34,277 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:34,277 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:34,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:34,378 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2021-11-23 01:00:34,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:34,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 899 states and 1596 transitions. [2021-11-23 01:00:34,635 INFO L276 IsEmpty]: Start isEmpty. Operand 899 states and 1596 transitions. [2021-11-23 01:00:34,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:34,639 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:34,639 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:34,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:34,711 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-11-23 01:00:34,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:34,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1596 states to 900 states and 1596 transitions. [2021-11-23 01:00:34,731 INFO L276 IsEmpty]: Start isEmpty. Operand 900 states and 1596 transitions. [2021-11-23 01:00:34,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2021-11-23 01:00:34,734 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:34,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:34,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:34,805 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-11-23 01:00:34,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:34,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1598 states to 902 states and 1598 transitions. [2021-11-23 01:00:34,902 INFO L276 IsEmpty]: Start isEmpty. Operand 902 states and 1598 transitions. [2021-11-23 01:00:34,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-11-23 01:00:34,905 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:34,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:34,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2021-11-23 01:00:34,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:34,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1602 states to 905 states and 1602 transitions. [2021-11-23 01:00:34,995 INFO L276 IsEmpty]: Start isEmpty. Operand 905 states and 1602 transitions. [2021-11-23 01:00:34,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2021-11-23 01:00:34,999 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:34,999 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:35,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:35,073 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:35,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:35,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1631 states to 911 states and 1631 transitions. [2021-11-23 01:00:35,521 INFO L276 IsEmpty]: Start isEmpty. Operand 911 states and 1631 transitions. [2021-11-23 01:00:35,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2021-11-23 01:00:35,524 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:35,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:35,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:35,593 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:35,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:35,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1636 states to 912 states and 1634 transitions. [2021-11-23 01:00:35,619 INFO L276 IsEmpty]: Start isEmpty. Operand 912 states and 1634 transitions. [2021-11-23 01:00:35,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2021-11-23 01:00:35,622 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:35,623 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:35,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:35,704 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:36,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:36,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1643 states to 915 states and 1641 transitions. [2021-11-23 01:00:36,203 INFO L276 IsEmpty]: Start isEmpty. Operand 915 states and 1641 transitions. [2021-11-23 01:00:36,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:36,206 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:36,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:36,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:36,286 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:36,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:36,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 920 states and 1652 transitions. [2021-11-23 01:00:36,328 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1652 transitions. [2021-11-23 01:00:36,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:36,331 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:36,331 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:36,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:36,403 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:36,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:36,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1655 states to 920 states and 1651 transitions. [2021-11-23 01:00:36,427 INFO L276 IsEmpty]: Start isEmpty. Operand 920 states and 1651 transitions. [2021-11-23 01:00:36,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:36,430 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:36,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:36,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:36,499 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-11-23 01:00:36,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:36,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1657 states to 921 states and 1653 transitions. [2021-11-23 01:00:36,724 INFO L276 IsEmpty]: Start isEmpty. Operand 921 states and 1653 transitions. [2021-11-23 01:00:36,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:36,728 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:36,728 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:36,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:36,802 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-11-23 01:00:36,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:36,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1657 states to 922 states and 1653 transitions. [2021-11-23 01:00:36,960 INFO L276 IsEmpty]: Start isEmpty. Operand 922 states and 1653 transitions. [2021-11-23 01:00:36,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:36,965 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:36,965 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:37,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:37,044 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 8 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2021-11-23 01:00:37,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:37,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1659 states to 923 states and 1655 transitions. [2021-11-23 01:00:37,109 INFO L276 IsEmpty]: Start isEmpty. Operand 923 states and 1655 transitions. [2021-11-23 01:00:37,113 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:37,114 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:37,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:37,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:37,181 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:37,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:37,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1662 states to 925 states and 1658 transitions. [2021-11-23 01:00:37,501 INFO L276 IsEmpty]: Start isEmpty. Operand 925 states and 1658 transitions. [2021-11-23 01:00:37,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2021-11-23 01:00:37,505 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:37,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:37,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:37,579 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 7 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:37,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:37,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1665 states to 927 states and 1661 transitions. [2021-11-23 01:00:37,796 INFO L276 IsEmpty]: Start isEmpty. Operand 927 states and 1661 transitions. [2021-11-23 01:00:37,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-23 01:00:37,801 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:37,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:37,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:37,872 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:37,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:37,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1669 states to 930 states and 1665 transitions. [2021-11-23 01:00:37,899 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1665 transitions. [2021-11-23 01:00:37,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-23 01:00:37,903 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:37,903 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:37,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:37,969 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:37,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:37,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 930 states and 1664 transitions. [2021-11-23 01:00:37,992 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1664 transitions. [2021-11-23 01:00:37,995 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-23 01:00:37,996 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:37,996 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,063 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2021-11-23 01:00:38,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:38,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1670 states to 931 states and 1664 transitions. [2021-11-23 01:00:38,085 INFO L276 IsEmpty]: Start isEmpty. Operand 931 states and 1664 transitions. [2021-11-23 01:00:38,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-23 01:00:38,088 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:38,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,156 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-23 01:00:38,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:38,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1673 states to 933 states and 1667 transitions. [2021-11-23 01:00:38,394 INFO L276 IsEmpty]: Start isEmpty. Operand 933 states and 1667 transitions. [2021-11-23 01:00:38,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-11-23 01:00:38,397 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:38,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,467 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2021-11-23 01:00:38,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:38,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1674 states to 934 states and 1668 transitions. [2021-11-23 01:00:38,565 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1668 transitions. [2021-11-23 01:00:38,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-11-23 01:00:38,568 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:38,568 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,655 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:38,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:38,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1678 states to 937 states and 1672 transitions. [2021-11-23 01:00:38,682 INFO L276 IsEmpty]: Start isEmpty. Operand 937 states and 1672 transitions. [2021-11-23 01:00:38,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-11-23 01:00:38,689 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:38,689 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,755 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:38,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:38,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1679 states to 936 states and 1670 transitions. [2021-11-23 01:00:38,779 INFO L276 IsEmpty]: Start isEmpty. Operand 936 states and 1670 transitions. [2021-11-23 01:00:38,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-11-23 01:00:38,782 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:38,782 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:38,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:38,851 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:39,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:39,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 941 states and 1682 transitions. [2021-11-23 01:00:39,111 INFO L276 IsEmpty]: Start isEmpty. Operand 941 states and 1682 transitions. [2021-11-23 01:00:39,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-11-23 01:00:39,114 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:39,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:39,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:39,197 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:39,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:39,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1700 states to 945 states and 1691 transitions. [2021-11-23 01:00:39,417 INFO L276 IsEmpty]: Start isEmpty. Operand 945 states and 1691 transitions. [2021-11-23 01:00:39,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-11-23 01:00:39,420 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:39,421 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:39,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:39,505 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2021-11-23 01:00:39,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:39,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1704 states to 948 states and 1695 transitions. [2021-11-23 01:00:39,537 INFO L276 IsEmpty]: Start isEmpty. Operand 948 states and 1695 transitions. [2021-11-23 01:00:39,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2021-11-23 01:00:39,540 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:39,540 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:39,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:39,624 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-11-23 01:00:39,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:39,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1707 states to 950 states and 1698 transitions. [2021-11-23 01:00:39,788 INFO L276 IsEmpty]: Start isEmpty. Operand 950 states and 1698 transitions. [2021-11-23 01:00:39,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:39,791 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:39,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:39,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:39,872 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:39,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:39,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1717 states to 955 states and 1708 transitions. [2021-11-23 01:00:39,905 INFO L276 IsEmpty]: Start isEmpty. Operand 955 states and 1708 transitions. [2021-11-23 01:00:39,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:39,908 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:39,909 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:39,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:39,977 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:39,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1721 states to 958 states and 1712 transitions. [2021-11-23 01:00:40,003 INFO L276 IsEmpty]: Start isEmpty. Operand 958 states and 1712 transitions. [2021-11-23 01:00:40,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:40,006 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:40,078 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:40,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 961 states and 1716 transitions. [2021-11-23 01:00:40,163 INFO L276 IsEmpty]: Start isEmpty. Operand 961 states and 1716 transitions. [2021-11-23 01:00:40,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:40,170 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,170 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:40,256 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2021-11-23 01:00:40,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 962 states and 1716 transitions. [2021-11-23 01:00:40,298 INFO L276 IsEmpty]: Start isEmpty. Operand 962 states and 1716 transitions. [2021-11-23 01:00:40,300 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:40,300 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:40,392 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-11-23 01:00:40,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 963 states and 1716 transitions. [2021-11-23 01:00:40,414 INFO L276 IsEmpty]: Start isEmpty. Operand 963 states and 1716 transitions. [2021-11-23 01:00:40,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:40,416 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,417 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:40,486 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2021-11-23 01:00:40,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1729 states to 965 states and 1720 transitions. [2021-11-23 01:00:40,741 INFO L276 IsEmpty]: Start isEmpty. Operand 965 states and 1720 transitions. [2021-11-23 01:00:40,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2021-11-23 01:00:40,743 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,744 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:40,812 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2021-11-23 01:00:40,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:40,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1731 states to 967 states and 1722 transitions. [2021-11-23 01:00:40,940 INFO L276 IsEmpty]: Start isEmpty. Operand 967 states and 1722 transitions. [2021-11-23 01:00:40,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-11-23 01:00:40,943 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:40,943 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:40,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,008 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1735 states to 970 states and 1726 transitions. [2021-11-23 01:00:41,034 INFO L276 IsEmpty]: Start isEmpty. Operand 970 states and 1726 transitions. [2021-11-23 01:00:41,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-11-23 01:00:41,037 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,037 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,103 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1741 states to 973 states and 1732 transitions. [2021-11-23 01:00:41,180 INFO L276 IsEmpty]: Start isEmpty. Operand 973 states and 1732 transitions. [2021-11-23 01:00:41,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-11-23 01:00:41,185 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,185 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,250 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1745 states to 976 states and 1736 transitions. [2021-11-23 01:00:41,277 INFO L276 IsEmpty]: Start isEmpty. Operand 976 states and 1736 transitions. [2021-11-23 01:00:41,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2021-11-23 01:00:41,279 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,280 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,385 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2021-11-23 01:00:41,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1745 states to 977 states and 1736 transitions. [2021-11-23 01:00:41,408 INFO L276 IsEmpty]: Start isEmpty. Operand 977 states and 1736 transitions. [2021-11-23 01:00:41,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-11-23 01:00:41,411 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,504 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 980 states and 1740 transitions. [2021-11-23 01:00:41,531 INFO L276 IsEmpty]: Start isEmpty. Operand 980 states and 1740 transitions. [2021-11-23 01:00:41,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-11-23 01:00:41,533 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,534 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,607 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1754 states to 983 states and 1745 transitions. [2021-11-23 01:00:41,685 INFO L276 IsEmpty]: Start isEmpty. Operand 983 states and 1745 transitions. [2021-11-23 01:00:41,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2021-11-23 01:00:41,687 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,688 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,759 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1758 states to 986 states and 1749 transitions. [2021-11-23 01:00:41,793 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 1749 transitions. [2021-11-23 01:00:41,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-11-23 01:00:41,795 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,871 INFO L134 CoverageAnalysis]: Checked inductivity of 29 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:41,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1758 states to 987 states and 1749 transitions. [2021-11-23 01:00:41,897 INFO L276 IsEmpty]: Start isEmpty. Operand 987 states and 1749 transitions. [2021-11-23 01:00:41,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2021-11-23 01:00:41,900 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:41,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:41,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:41,973 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2021-11-23 01:00:41,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:42,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1762 states to 990 states and 1753 transitions. [2021-11-23 01:00:42,008 INFO L276 IsEmpty]: Start isEmpty. Operand 990 states and 1753 transitions. [2021-11-23 01:00:42,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2021-11-23 01:00:42,011 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:42,011 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:42,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:42,083 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2021-11-23 01:00:42,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:42,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1764 states to 991 states and 1755 transitions. [2021-11-23 01:00:42,109 INFO L276 IsEmpty]: Start isEmpty. Operand 991 states and 1755 transitions. [2021-11-23 01:00:42,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2021-11-23 01:00:42,112 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:42,112 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:42,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:42,182 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-11-23 01:00:42,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:42,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1764 states to 992 states and 1755 transitions. [2021-11-23 01:00:42,205 INFO L276 IsEmpty]: Start isEmpty. Operand 992 states and 1755 transitions. [2021-11-23 01:00:42,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2021-11-23 01:00:42,208 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:42,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:42,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:42,279 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2021-11-23 01:00:42,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:42,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1764 states to 993 states and 1755 transitions. [2021-11-23 01:00:42,303 INFO L276 IsEmpty]: Start isEmpty. Operand 993 states and 1755 transitions. [2021-11-23 01:00:42,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2021-11-23 01:00:42,305 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:42,305 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:42,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:42,965 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:43,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:43,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1797 states to 998 states and 1782 transitions. [2021-11-23 01:00:43,536 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1782 transitions. [2021-11-23 01:00:43,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2021-11-23 01:00:43,539 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:43,539 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:43,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:43,834 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:44,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:44,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1799 states to 998 states and 1781 transitions. [2021-11-23 01:00:44,378 INFO L276 IsEmpty]: Start isEmpty. Operand 998 states and 1781 transitions. [2021-11-23 01:00:44,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2021-11-23 01:00:44,381 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:44,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:44,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:45,051 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:46,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:46,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1834 states to 1004 states and 1809 transitions. [2021-11-23 01:00:46,862 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1809 transitions. [2021-11-23 01:00:46,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2021-11-23 01:00:46,865 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:46,865 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:46,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:47,138 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:48,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:48,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1836 states to 1004 states and 1808 transitions. [2021-11-23 01:00:48,149 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1808 transitions. [2021-11-23 01:00:48,152 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2021-11-23 01:00:48,152 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:48,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:48,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:48,333 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:48,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:48,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1838 states to 1004 states and 1807 transitions. [2021-11-23 01:00:48,637 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1807 transitions. [2021-11-23 01:00:48,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2021-11-23 01:00:48,640 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:48,640 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:48,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:48,786 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:48,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:48,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1840 states to 1004 states and 1806 transitions. [2021-11-23 01:00:48,839 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1806 transitions. [2021-11-23 01:00:48,841 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2021-11-23 01:00:48,841 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:48,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:48,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:49,000 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:49,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:49,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1004 states and 1805 transitions. [2021-11-23 01:00:49,046 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1805 transitions. [2021-11-23 01:00:49,049 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2021-11-23 01:00:49,049 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:49,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:49,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-23 01:00:49,211 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2021-11-23 01:00:49,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand no size info available [2021-11-23 01:00:49,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1004 states and 1804 transitions. [2021-11-23 01:00:49,262 INFO L276 IsEmpty]: Start isEmpty. Operand 1004 states and 1804 transitions. [2021-11-23 01:00:49,264 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2021-11-23 01:00:49,265 INFO L422 CodeCheckObserver]: Error Path is FOUND. [2021-11-23 01:00:49,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-23 01:00:49,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 01:00:49,463 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 01:00:49,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 01:00:51,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 01:00:51,827 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-23 01:00:53,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-23 01:00:53,739 WARN L475 CodeCheckObserver]: This program is UNSAFE, Check terminated with 88 iterations. [2021-11-23 01:00:54,100 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck CFG 23.11 01:00:54 ImpRootNode [2021-11-23 01:00:54,101 INFO L132 PluginConnector]: ------------------------ END CodeCheck---------------------------- [2021-11-23 01:00:54,101 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-23 01:00:54,101 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-23 01:00:54,101 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-23 01:00:54,102 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 01:00:23" (3/4) ... [2021-11-23 01:00:54,104 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-11-23 01:00:54,317 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/witness.graphml [2021-11-23 01:00:54,317 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-23 01:00:54,318 INFO L158 Benchmark]: Toolchain (without parser) took 39782.42ms. Allocated memory was 119.5MB in the beginning and 859.8MB in the end (delta: 740.3MB). Free memory was 70.4MB in the beginning and 526.7MB in the end (delta: -456.3MB). Peak memory consumption was 284.1MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,318 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 119.5MB. Free memory is still 95.3MB. There was no memory consumed. Max. memory is 16.1GB. [2021-11-23 01:00:54,319 INFO L158 Benchmark]: CACSL2BoogieTranslator took 2172.59ms. Allocated memory was 119.5MB in the beginning and 144.7MB in the end (delta: 25.2MB). Free memory was 70.2MB in the beginning and 84.2MB in the end (delta: -14.0MB). Peak memory consumption was 56.7MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,320 INFO L158 Benchmark]: Boogie Procedure Inliner took 278.61ms. Allocated memory is still 144.7MB. Free memory was 84.2MB in the beginning and 66.6MB in the end (delta: 17.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,320 INFO L158 Benchmark]: Boogie Preprocessor took 216.55ms. Allocated memory is still 144.7MB. Free memory was 66.6MB in the beginning and 79.7MB in the end (delta: -13.0MB). Peak memory consumption was 25.5MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,320 INFO L158 Benchmark]: RCFGBuilder took 6660.88ms. Allocated memory was 144.7MB in the beginning and 381.7MB in the end (delta: 237.0MB). Free memory was 79.7MB in the beginning and 115.3MB in the end (delta: -35.6MB). Peak memory consumption was 201.3MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,321 INFO L158 Benchmark]: CodeCheck took 30232.09ms. Allocated memory was 381.7MB in the beginning and 859.8MB in the end (delta: 478.2MB). Free memory was 115.3MB in the beginning and 573.9MB in the end (delta: -458.6MB). Peak memory consumption was 19.6MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,321 INFO L158 Benchmark]: Witness Printer took 215.84ms. Allocated memory is still 859.8MB. Free memory was 573.9MB in the beginning and 526.7MB in the end (delta: 47.2MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. [2021-11-23 01:00:54,324 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.codecheck: - StatisticsResult: Ultimate CodeCheck benchmark data CFG has 52 procedures, 809 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 29.7s, OverallIterations: 88, TraceHistogramMax: 0, PathProgramHistogramMax: 0, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 59043 SdHoareTripleChecker+Valid, 67.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 30996 mSDsluCounter, 86618 SdHoareTripleChecker+Invalid, 57.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 70799 mSDsCounter, 6768 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 43620 IncrementalHoareTripleChecker+Invalid, 50388 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 6768 mSolverCounterUnsat, 20447 mSDtfsCounter, 43620 mSolverCounterSat, 1.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 72265 GetRequests, 71899 SyntacticMatches, 100 SemanticMatches, 266 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39679 ImplicationChecksByTransitivity, 12.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=-1occurred in iteration=-1, InterpolantAutomatonStates: 0, traceCheckStatistics: 0.8s SsaConstructionTime, 4.1s SatisfiabilityAnalysisTime, 6.0s InterpolantComputationTime, 6251 NumberOfCodeBlocks, 6251 NumberOfCodeBlocksAsserted, 88 NumberOfCheckSat, 6057 ConstructedInterpolants, 0 QuantifiedInterpolants, 9159 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 87 InterpolantComputations, 78 PerfectInterpolantSequences, 3078/3120 InterpolantCoveringCapability, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: No data available, ReuseStatistics: No data available - CounterExampleResult [Line: 3957]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L3980] struct v4l2_subdev *si4713_subdev_tuner_ops_group1 ; [L3981] int ldv_irq_1_3 = 0; [L3982] void *ldv_irq_data_1_1 ; [L3983] int ldv_irq_1_0 = 0; [L3984] void *ldv_irq_data_1_0 ; [L3985] int ldv_state_variable_0 ; [L3986] struct v4l2_frequency *si4713_subdev_tuner_ops_group0 ; [L3987] struct v4l2_control *si4713_subdev_core_ops_group2 ; [L3988] int ldv_state_variable_2 ; [L3989] void *ldv_irq_data_1_3 ; [L3990] void *ldv_irq_data_1_2 ; [L3991] int ldv_irq_1_2 = 0; [L3992] int LDV_IN_INTERRUPT = 1; [L3993] int ldv_irq_1_1 = 0; [L3994] int ldv_irq_line_1_3 ; [L3995] struct v4l2_subdev *si4713_subdev_core_ops_group1 ; [L3996] struct v4l2_ext_controls *si4713_subdev_core_ops_group0 ; [L3997] int ldv_state_variable_3 ; [L3998] int ldv_irq_line_1_0 ; [L3999] int ref_cnt ; [L4000] struct v4l2_modulator *si4713_subdev_tuner_ops_group2 ; [L4001] int ldv_irq_line_1_1 ; [L4002] struct i2c_client *si4713_i2c_driver_group0 ; [L4003] int ldv_state_variable_1 ; [L4004] int ldv_irq_line_1_2 ; [L4005] int ldv_state_variable_4 ; [L4144] static int debug ; [L4145] static char const *si4713_supply_names[2U] = { "vio", "vdd"}; [L4146-L4156] static long limiter_times[40U] = { 2000L, 250L, 1000L, 500L, 510L, 1000L, 255L, 2000L, 170L, 3000L, 127L, 4020L, 102L, 5010L, 85L, 6020L, 73L, 7010L, 64L, 7990L, 57L, 8970L, 51L, 10030L, 25L, 20470L, 17L, 30110L, 13L, 39380L, 10L, 51190L, 8L, 63690L, 7L, 73140L, 6L, 85330L, 5L, 102390L}; [L4157-L4160] static unsigned long acomp_rtimes[10U] = { 0UL, 100000UL, 1UL, 200000UL, 2UL, 350000UL, 3UL, 525000UL, 4UL, 1000000UL}; [L4161-L4162] static unsigned long preemphasis_values[6U] = { 2UL, 0UL, 1UL, 1UL, 0UL, 2UL}; [L5779-L5781] static struct v4l2_subdev_core_ops const si4713_subdev_core_ops = {0, 0, 0, 0, 0, 0, 0, & si4713_queryctrl, & si4713_g_ctrl, & si4713_s_ctrl, & si4713_g_ext_ctrls, & si4713_s_ext_ctrls, 0, 0, 0, & si4713_ioctl, 0, 0, 0, 0, 0, 0}; [L5949-L5951] static struct v4l2_subdev_tuner_ops const si4713_subdev_tuner_ops = {0, 0, & si4713_s_frequency, & si4713_g_frequency, 0, 0, & si4713_g_modulator, & si4713_s_modulator, 0, 0}; [L5952-L5953] static struct v4l2_subdev_ops const si4713_subdev_ops = {& si4713_subdev_core_ops, & si4713_subdev_tuner_ops, 0, 0, 0, 0, 0, 0}; [L6083] static struct i2c_device_id const si4713_id[2U] = { {{'s', 'i', '4', '7', '1', '3', '\000'}, 0UL}}; [L6084] struct i2c_device_id const __mod_i2c_device_table ; [L6085-L6089] static struct i2c_driver si4713_i2c_driver = {0U, 0, 0, & si4713_probe, & si4713_remove, 0, 0, 0, 0, 0, {"si4713", 0, 0, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, (struct i2c_device_id const *)(& si4713_id), 0, 0, {0, 0}}; [L6105] int ldv_retval_0 ; [L6106] int ldv_retval_1 ; [L6271] unsigned int ldvarg1 ; [L6272] unsigned int tmp ; [L6273] void *ldvarg0 ; [L6274] void *tmp___0 ; [L6275] struct v4l2_queryctrl *ldvarg2 ; [L6276] void *tmp___1 ; [L6277] struct i2c_device_id *ldvarg3 ; [L6278] void *tmp___2 ; [L6279] int tmp___3 ; [L6280] int tmp___4 ; [L6281] int tmp___5 ; [L6282] int tmp___6 ; [L6283] int tmp___7 ; [L6285] tmp = __VERIFIER_nondet_uint() [L6286] ldvarg1 = tmp VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg1=86, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86] [L6287] CALL, EXPR ldv_zalloc(1UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=1, \result={0:0}, __mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=1, tmp___0=-1] [L6287] RET, EXPR ldv_zalloc(1UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldv_zalloc(1UL)={0:0}, ldvarg1=86, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86] [L6287] tmp___0 = ldv_zalloc(1UL) [L6288] ldvarg0 = tmp___0 VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg0={0:0}, ldvarg1=86, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}] [L6289] CALL, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=68, \result={0:0}, __mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=68, tmp___0=-2147483648] [L6289] RET, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldv_zalloc(68UL)={0:0}, ldvarg0={0:0}, ldvarg1=86, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}] [L6289] tmp___1 = ldv_zalloc(68UL) [L6290] ldvarg2 = (struct v4l2_queryctrl *)tmp___1 VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}] [L6291] CALL, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=32, \result={0:0}, __mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=32, tmp___0=1] [L6291] RET, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldv_zalloc(32UL)={0:0}, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}] [L6291] tmp___2 = ldv_zalloc(32UL) [L6292] ldvarg3 = (struct i2c_device_id *)tmp___2 [L6293] FCALL ldv_initialize() [L6294] ldv_state_variable_4 = 0 [L6295] ldv_state_variable_1 = 1 [L6296] ref_cnt = 0 [L6297] ldv_state_variable_0 = 1 [L6298] ldv_state_variable_3 = 0 [L6299] ldv_state_variable_2 = 0 VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}] [L6301] tmp___3 = __VERIFIER_nondet_int() [L6303] case 0: [L6356] case 1: [L6362] case 2: VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}, tmp___3=2] [L6363] COND TRUE ldv_state_variable_0 != 0 [L6364] tmp___5 = __VERIFIER_nondet_int() [L6366] case 0: [L6374] case 1: VAL [__mod_i2c_device_table=0, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_state_variable_4=0, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}, tmp___3=2, tmp___5=1] [L6375] COND TRUE ldv_state_variable_0 == 1 [L6376] CALL, EXPR si4713_module_init() [L6092] int tmp ; [L6094] CALL, EXPR i2c_add_driver(& si4713_i2c_driver) [L4108] int tmp ; [L4110] CALL, EXPR i2c_register_driver(& __this_module, driver) [L6677] return __VERIFIER_nondet_int(); [L4110] RET, EXPR i2c_register_driver(& __this_module, driver) [L4110] tmp = i2c_register_driver(& __this_module, driver) [L4111] return (tmp); [L6094] RET, EXPR i2c_add_driver(& si4713_i2c_driver) [L6094] tmp = i2c_add_driver(& si4713_i2c_driver) [L6095] return (tmp); [L6376] RET, EXPR si4713_module_init() [L6376] ldv_retval_0 = si4713_module_init() [L6377] COND TRUE ldv_retval_0 == 0 [L6378] ldv_state_variable_0 = 3 [L6379] ldv_state_variable_2 = 1 [L6380] CALL ldv_initialize_i2c_driver_2() [L6111] void *tmp ; VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6113] CALL, EXPR ldv_zalloc(1168UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=1168, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=1168, tmp___0=1] [L6113] RET, EXPR ldv_zalloc(1168UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_state_variable_4=0, ldv_zalloc(1168UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6113] tmp = ldv_zalloc(1168UL) [L6114] si4713_i2c_driver_group0 = (struct i2c_client *)tmp [L6380] RET ldv_initialize_i2c_driver_2() [L6381] ldv_state_variable_3 = 1 [L6382] CALL ldv_initialize_v4l2_subdev_tuner_ops_3() [L6256] void *tmp ; [L6257] void *tmp___0 ; [L6258] void *tmp___1 ; VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6260] CALL, EXPR ldv_zalloc(44UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=44, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=44, tmp___0=1] [L6260] RET, EXPR ldv_zalloc(44UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, ldv_zalloc(44UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6260] tmp = ldv_zalloc(44UL) [L6261] si4713_subdev_tuner_ops_group0 = (struct v4l2_frequency *)tmp VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}] [L6262] CALL, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=1736, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=1736, tmp___0=1] [L6262] RET, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, ldv_zalloc(1736UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}] [L6262] tmp___0 = ldv_zalloc(1736UL) [L6263] si4713_subdev_tuner_ops_group1 = (struct v4l2_subdev *)tmp___0 VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}, tmp___0={0:0}] [L6264] CALL, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=68, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=68, tmp___0=-1] [L6264] RET, EXPR ldv_zalloc(68UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=0, ldv_zalloc(68UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}, tmp___0={0:0}] [L6264] tmp___1 = ldv_zalloc(68UL) [L6265] si4713_subdev_tuner_ops_group2 = (struct v4l2_modulator *)tmp___1 [L6382] RET ldv_initialize_v4l2_subdev_tuner_ops_3() [L6383] ldv_state_variable_4 = 1 [L6384] CALL ldv_initialize_v4l2_subdev_core_ops_4() [L6120] void *tmp ; [L6121] void *tmp___0 ; [L6122] void *tmp___1 ; VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6124] CALL, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=32, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=32, tmp___0=-2147483648] [L6124] RET, EXPR ldv_zalloc(32UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldv_zalloc(32UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6124] tmp = ldv_zalloc(32UL) [L6125] si4713_subdev_core_ops_group0 = (struct v4l2_ext_controls *)tmp VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}] [L6126] CALL, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=1736, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=1736, tmp___0=1] [L6126] RET, EXPR ldv_zalloc(1736UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldv_zalloc(1736UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}] [L6126] tmp___0 = ldv_zalloc(1736UL) [L6127] si4713_subdev_core_ops_group1 = (struct v4l2_subdev *)tmp___0 VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}, tmp___0={0:0}] [L6128] CALL, EXPR ldv_zalloc(8UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3922] void *p ; [L3923] void *tmp ; [L3924] int tmp___0 ; [L3926] tmp___0 = __VERIFIER_nondet_int() [L3927] COND TRUE tmp___0 != 0 [L3928] return ((void *)0); VAL [\old(size)=8, \result={0:0}, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, size=8, tmp___0=1] [L6128] RET, EXPR ldv_zalloc(8UL) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldv_zalloc(8UL)={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp={0:0}, tmp___0={0:0}] [L6128] tmp___1 = ldv_zalloc(8UL) [L6129] si4713_subdev_core_ops_group2 = (struct v4l2_control *)tmp___1 [L6384] RET ldv_initialize_v4l2_subdev_core_ops_4() [L6387] COND FALSE !(ldv_retval_0 != 0) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}, tmp___3=2, tmp___5=1] [L6301] tmp___3 = __VERIFIER_nondet_int() [L6303] case 0: VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}, tmp___3=0, tmp___5=1] [L6304] COND TRUE ldv_state_variable_4 != 0 [L6305] tmp___4 = __VERIFIER_nondet_int() [L6307] case 0: [L6314] case 1: [L6321] case 2: [L6328] case 3: VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, ldvarg0={0:0}, ldvarg1=86, ldvarg2={0:0}, ldvarg3={0:0}, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, tmp=86, tmp___0={0:0}, tmp___1={0:0}, tmp___2={0:0}, tmp___3=0, tmp___4=3, tmp___5=1] [L6329] COND TRUE ldv_state_variable_4 == 1 [L6330] CALL si4713_s_ext_ctrls(si4713_subdev_core_ops_group1, si4713_subdev_core_ops_group0) [L5502] struct si4713_device *sdev ; [L5503] struct v4l2_subdev const *__mptr ; [L5504] int i ; [L5505] int err ; [L5507] __mptr = (struct v4l2_subdev const *)sd [L5508] sdev = (struct si4713_device *)__mptr [L5509] EXPR ctrls->ctrl_class VAL [__mod_i2c_device_table=0, __mptr={0:0}, __this_module={114:113}, acomp_rtimes={61:0}, ctrls={0:0}, ctrls={0:0}, ctrls->ctrl_class=10158080, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, sd={0:0}, sd={0:0}, sdev={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L5509] COND FALSE !(ctrls->ctrl_class != 10158080U) [L5513] i = 0 VAL [__mod_i2c_device_table=0, __mptr={0:0}, __this_module={114:113}, acomp_rtimes={61:0}, ctrls={0:0}, ctrls={0:0}, debug=0, i=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, sd={0:0}, sd={0:0}, sdev={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L5536] EXPR ctrls->count VAL [__mod_i2c_device_table=0, __mptr={0:0}, __this_module={114:113}, acomp_rtimes={61:0}, ctrls={0:0}, ctrls={0:0}, ctrls->count=1, debug=0, i=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, sd={0:0}, sd={0:0}, sdev={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L5536] COND TRUE (__u32 )i < ctrls->count [L5516] EXPR ctrls->controls [L5516] (ctrls->controls + (unsigned long )i)->id [L5517] case 10160389U: [L5518] case 10160390U: [L5519] EXPR ctrls->controls [L5519] CALL si4713_write_econtrol_string(sdev, ctrls->controls + (unsigned long )i) [L4924] struct v4l2_queryctrl vqc ; [L4925] int len ; [L4926] s32 rval ; [L4927] char ps_name[97U] ; [L4928] unsigned long tmp ; [L4929] size_t tmp___0 ; [L4930] char radio_text[385U] ; [L4931] unsigned long tmp___1 ; [L4932] size_t tmp___2 ; [L4934] rval = 0 [L4935] EXPR control->id [L4935] vqc.id = control->id [L4936] CALL, EXPR si4713_queryctrl(& sdev->sd, & vqc) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, qc={70:0}, ref_cnt=0, sd={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L5588] int rval ; [L5590] rval = 0 [L5591] qc->id [L5592] case 9963785U: [L5595] case 10160386U: [L5598] case 10160387U: [L5601] case 10160385U: [L5604] case 10160389U: VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, qc={70:0}, qc={70:0}, qc->id=10160389, ref_cnt=0, rval=0, sd={0:0}, sd={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L5605] CALL, EXPR v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) VAL [\old(arg1)=0, \old(arg2)=96, \old(arg3)=8, \old(arg4)=0, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, arg0={70:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6730] return __VERIFIER_nondet_int(); [L5605] RET, EXPR v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, qc={70:0}, qc={70:0}, qc->id=10160389, ref_cnt=0, rval=0, sd={0:0}, sd={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, v4l2_ctrl_query_fill(qc, 0, 96, 8, 0)=0] [L5605] rval = v4l2_ctrl_query_fill(qc, 0, 96, 8, 0) [L5657] return (rval); [L4936] RET, EXPR si4713_queryctrl(& sdev->sd, & vqc) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, control={132:1}, control={132:1}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ps_name={71:0}, radio_text={69:0}, ref_cnt=0, rval=0, sdev={0:0}, sdev={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_queryctrl(& sdev->sd, & vqc)=0, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, vqc={70:0}] [L4936] rval = si4713_queryctrl(& sdev->sd, & vqc) [L4937] COND FALSE !(rval < 0) [L4941] control->id [L4942] case 10160389U: [L4943] EXPR control->size [L4943] len = (int )(control->size - 1U) [L4944] COND FALSE !(len > 96) [L4949] EXPR control->ldv_23757.string VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, control={132:1}, control={132:1}, control->id=10160389, control->ldv_23757.string={142:139}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, len=-1, limiter_times={60:0}, preemphasis_values={62:0}, ps_name={71:0}, radio_text={69:0}, ref_cnt=0, rval=0, sdev={0:0}, sdev={0:0}, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, vqc={70:0}] [L4949-L4950] CALL ldv_copy_from_user_7((void *)(& ps_name), (void const *)control->ldv_23757.string, (unsigned long )len) VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6524] unsigned long tmp ; VAL [\old(n)=-1, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, from={142:139}, from={142:139}, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, n=-1, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}, to={71:0}, to={71:0}] [L6526] CALL ldv_check_len((long )n) VAL [\old(n)=-1, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6599] COND FALSE !(n >= 0L) VAL [\old(n)=-1, __mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, n=-1, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L6601] CALL ldv_error() VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] [L3957] reach_error() VAL [__mod_i2c_device_table=0, __this_module={114:113}, acomp_rtimes={61:0}, debug=0, LDV_IN_INTERRUPT=1, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=1, ldv_state_variable_4=1, limiter_times={60:0}, preemphasis_values={62:0}, ref_cnt=0, si4713_i2c_driver={67:0}, si4713_i2c_driver_group0={0:0}, si4713_id={66:0}, si4713_subdev_core_ops={63:0}, si4713_subdev_core_ops_group0={0:0}, si4713_subdev_core_ops_group1={0:0}, si4713_subdev_core_ops_group2={0:0}, si4713_subdev_ops={65:0}, si4713_subdev_tuner_ops={64:0}, si4713_subdev_tuner_ops_group0={0:0}, si4713_subdev_tuner_ops_group1={0:0}, si4713_subdev_tuner_ops_group2={0:0}, si4713_supply_names={59:0}] * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 119.5MB. Free memory is still 95.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 2172.59ms. Allocated memory was 119.5MB in the beginning and 144.7MB in the end (delta: 25.2MB). Free memory was 70.2MB in the beginning and 84.2MB in the end (delta: -14.0MB). Peak memory consumption was 56.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 278.61ms. Allocated memory is still 144.7MB. Free memory was 84.2MB in the beginning and 66.6MB in the end (delta: 17.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Preprocessor took 216.55ms. Allocated memory is still 144.7MB. Free memory was 66.6MB in the beginning and 79.7MB in the end (delta: -13.0MB). Peak memory consumption was 25.5MB. Max. memory is 16.1GB. * RCFGBuilder took 6660.88ms. Allocated memory was 144.7MB in the beginning and 381.7MB in the end (delta: 237.0MB). Free memory was 79.7MB in the beginning and 115.3MB in the end (delta: -35.6MB). Peak memory consumption was 201.3MB. Max. memory is 16.1GB. * CodeCheck took 30232.09ms. Allocated memory was 381.7MB in the beginning and 859.8MB in the end (delta: 478.2MB). Free memory was 115.3MB in the beginning and 573.9MB in the end (delta: -458.6MB). Peak memory consumption was 19.6MB. Max. memory is 16.1GB. * Witness Printer took 215.84ms. Allocated memory is still 859.8MB. Free memory was 573.9MB in the beginning and 526.7MB in the end (delta: 47.2MB). Peak memory consumption was 48.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. - GenericResult: Unfinished Backtranslation The program execution was not completely translated back. RESULT: Ultimate proved your program to be incorrect! [2021-11-23 01:00:54,401 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9521efdd-2d08-43bb-910f-90992e697e2f/bin/ukojak-LBtLqBUTdQ/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:10000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE