./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/goblint-regression/28-race_reach_37-indirect_racing.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 57096758 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs/config/TaipanReach.xml -i ../../sv-benchmarks/c/goblint-regression/28-race_reach_37-indirect_racing.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4cd03cb6-c4f7-4e77-a5b3-1301e2803206/bin/utaipan-mTDlp9Zugs --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash f9457a2aae94a41bb0750384b4cb2967438b2dd8 ..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................