./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version b2eff8ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG/config/TaipanReach.xml -i ../../sv-benchmarks/c/bitvector-loops/verisec_sendmail_tTflag_arr_one_loop.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9943b074-c652-48dc-8851-c15e8fa861ac/bin/utaipan-SDwSMHVbGG --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bec73cbd355af8995620266d1bb50e13212a1740ed8bd583620b6985b8fd569c .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................