./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-12 23:10:34,846 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-12 23:10:34,875 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-12 23:10:34,918 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-12 23:10:34,919 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-12 23:10:34,920 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-12 23:10:34,922 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-12 23:10:34,925 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-12 23:10:34,927 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-12 23:10:34,929 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-12 23:10:34,930 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-12 23:10:34,932 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-12 23:10:34,933 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-12 23:10:34,934 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-12 23:10:34,936 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-12 23:10:34,938 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-12 23:10:34,939 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-12 23:10:34,941 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-12 23:10:34,943 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-12 23:10:34,946 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-12 23:10:34,949 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-12 23:10:34,950 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-12 23:10:34,952 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-12 23:10:34,953 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-12 23:10:34,958 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-12 23:10:34,958 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-12 23:10:34,959 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-12 23:10:34,960 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-12 23:10:34,961 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-12 23:10:34,962 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-12 23:10:34,963 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-12 23:10:34,964 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-12 23:10:34,965 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-12 23:10:34,966 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-12 23:10:34,967 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-12 23:10:34,968 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-12 23:10:34,969 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-12 23:10:34,969 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-12 23:10:34,970 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-12 23:10:34,971 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-12 23:10:34,972 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-12 23:10:34,973 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/config/svcomp-Reach-32bit-Taipan_Default.epf [2021-11-12 23:10:35,000 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-12 23:10:35,000 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-12 23:10:35,001 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-11-12 23:10:35,002 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-11-12 23:10:35,002 INFO L138 SettingsManager]: * User list type=DISABLED [2021-11-12 23:10:35,003 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2021-11-12 23:10:35,003 INFO L138 SettingsManager]: * Explicit value domain=true [2021-11-12 23:10:35,003 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2021-11-12 23:10:35,004 INFO L138 SettingsManager]: * Octagon Domain=false [2021-11-12 23:10:35,004 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2021-11-12 23:10:35,005 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2021-11-12 23:10:35,005 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2021-11-12 23:10:35,005 INFO L138 SettingsManager]: * Interval Domain=false [2021-11-12 23:10:35,006 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2021-11-12 23:10:35,006 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2021-11-12 23:10:35,007 INFO L138 SettingsManager]: * Simplification Technique=SIMPLIFY_QUICK [2021-11-12 23:10:35,008 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-12 23:10:35,008 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-12 23:10:35,009 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-12 23:10:35,009 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-12 23:10:35,009 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-12 23:10:35,010 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-11-12 23:10:35,010 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-11-12 23:10:35,011 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-11-12 23:10:35,011 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2021-11-12 23:10:35,011 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-12 23:10:35,012 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-12 23:10:35,012 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-12 23:10:35,012 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-11-12 23:10:35,013 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-12 23:10:35,013 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-11-12 23:10:35,013 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-12 23:10:35,013 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-12 23:10:35,014 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-11-12 23:10:35,014 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-11-12 23:10:35,014 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2021-11-12 23:10:35,014 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-11-12 23:10:35,015 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-11-12 23:10:35,015 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-12 23:10:35,015 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2021-11-12 23:10:35,015 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2021-11-12 23:10:35,246 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-12 23:10:35,267 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-12 23:10:35,270 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-12 23:10:35,271 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-12 23:10:35,272 INFO L275 PluginConnector]: CDTParser initialized [2021-11-12 23:10:35,274 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-11-12 23:10:35,346 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/data/72cab2bf8/16e912edd8c0469ead77a4b958d31f79/FLAG4677a356a [2021-11-12 23:10:35,863 INFO L306 CDTParser]: Found 1 translation units. [2021-11-12 23:10:35,867 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/sv-benchmarks/c/systemc/transmitter.16.cil.c [2021-11-12 23:10:35,895 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/data/72cab2bf8/16e912edd8c0469ead77a4b958d31f79/FLAG4677a356a [2021-11-12 23:10:36,182 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/data/72cab2bf8/16e912edd8c0469ead77a4b958d31f79 [2021-11-12 23:10:36,185 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-12 23:10:36,186 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-12 23:10:36,203 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-12 23:10:36,203 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-12 23:10:36,205 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-12 23:10:36,206 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,207 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@249adcfc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36, skipping insertion in model container [2021-11-12 23:10:36,207 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,215 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-12 23:10:36,263 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-12 23:10:36,459 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-11-12 23:10:36,642 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-12 23:10:36,664 INFO L203 MainTranslator]: Completed pre-run [2021-11-12 23:10:36,675 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2021-11-12 23:10:36,778 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-12 23:10:36,810 INFO L208 MainTranslator]: Completed translation [2021-11-12 23:10:36,810 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36 WrapperNode [2021-11-12 23:10:36,810 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-12 23:10:36,812 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-12 23:10:36,812 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-12 23:10:36,812 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-12 23:10:36,820 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,836 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,913 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-12 23:10:36,914 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-12 23:10:36,914 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-12 23:10:36,914 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-12 23:10:36,922 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,923 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,929 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,929 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,948 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,984 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:36,994 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:37,001 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-12 23:10:37,011 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-12 23:10:37,011 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-12 23:10:37,011 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-12 23:10:37,016 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (1/1) ... [2021-11-12 23:10:37,023 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-12 23:10:37,034 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/z3 [2021-11-12 23:10:37,046 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-11-12 23:10:37,061 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-11-12 23:10:37,092 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-12 23:10:37,092 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2021-11-12 23:10:37,092 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2021-11-12 23:10:37,092 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2021-11-12 23:10:37,093 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2021-11-12 23:10:37,093 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2021-11-12 23:10:37,093 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2021-11-12 23:10:37,093 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2021-11-12 23:10:37,093 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2021-11-12 23:10:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2021-11-12 23:10:37,094 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2021-11-12 23:10:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2021-11-12 23:10:37,094 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2021-11-12 23:10:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-12 23:10:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-12 23:10:37,095 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-12 23:10:38,824 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-12 23:10:38,824 INFO L299 CfgBuilder]: Removed 18 assume(true) statements. [2021-11-12 23:10:38,828 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 11:10:38 BoogieIcfgContainer [2021-11-12 23:10:38,828 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-12 23:10:38,831 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-11-12 23:10:38,832 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-11-12 23:10:38,835 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-11-12 23:10:38,836 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.11 11:10:36" (1/3) ... [2021-11-12 23:10:38,837 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2e2c3063 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.11 11:10:38, skipping insertion in model container [2021-11-12 23:10:38,838 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.11 11:10:36" (2/3) ... [2021-11-12 23:10:38,838 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2e2c3063 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.11 11:10:38, skipping insertion in model container [2021-11-12 23:10:38,838 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 11:10:38" (3/3) ... [2021-11-12 23:10:38,840 INFO L111 eAbstractionObserver]: Analyzing ICFG transmitter.16.cil.c [2021-11-12 23:10:38,847 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-11-12 23:10:38,847 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-11-12 23:10:38,927 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-11-12 23:10:38,935 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-11-12 23:10:38,935 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2021-11-12 23:10:38,961 INFO L276 IsEmpty]: Start isEmpty. Operand has 197 states, 163 states have (on average 1.5521472392638036) internal successors, (253), 165 states have internal predecessors, (253), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2021-11-12 23:10:38,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:38,971 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:38,971 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:38,972 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:38,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:38,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1439967137, now seen corresponding path program 1 times [2021-11-12 23:10:38,987 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:38,988 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447932902] [2021-11-12 23:10:38,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:38,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:39,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:39,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:39,415 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:39,415 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447932902] [2021-11-12 23:10:39,416 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447932902] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:39,416 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:39,416 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2021-11-12 23:10:39,418 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482108921] [2021-11-12 23:10:39,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:39,424 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-11-12 23:10:39,424 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:39,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-12 23:10:39,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-12 23:10:39,455 INFO L87 Difference]: Start difference. First operand has 197 states, 163 states have (on average 1.5521472392638036) internal successors, (253), 165 states have internal predecessors, (253), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:40,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:40,043 INFO L93 Difference]: Finished difference Result 574 states and 919 transitions. [2021-11-12 23:10:40,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-12 23:10:40,046 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:40,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:40,072 INFO L225 Difference]: With dead ends: 574 [2021-11-12 23:10:40,073 INFO L226 Difference]: Without dead ends: 378 [2021-11-12 23:10:40,083 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-12 23:10:40,087 INFO L933 BasicCegarLoop]: 470 mSDtfsCounter, 525 mSDsluCounter, 474 mSDsCounter, 0 mSdLazyCounter, 306 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 332.35ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 525 SdHoareTripleChecker+Valid, 846 SdHoareTripleChecker+Invalid, 320 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 20.13ms SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 306 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 408.84ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:40,089 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [525 Valid, 846 Invalid, 320 Unknown, 0 Unchecked, 20.13ms Time], IncrementalHoareTripleChecker [14 Valid, 306 Invalid, 0 Unknown, 0 Unchecked, 408.84ms Time] [2021-11-12 23:10:40,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2021-11-12 23:10:40,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 375. [2021-11-12 23:10:40,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 375 states, 315 states have (on average 1.511111111111111) internal successors, (476), 316 states have internal predecessors, (476), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2021-11-12 23:10:40,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 375 states to 375 states and 570 transitions. [2021-11-12 23:10:40,218 INFO L78 Accepts]: Start accepts. Automaton has 375 states and 570 transitions. Word has length 70 [2021-11-12 23:10:40,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:40,219 INFO L470 AbstractCegarLoop]: Abstraction has 375 states and 570 transitions. [2021-11-12 23:10:40,220 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:40,220 INFO L276 IsEmpty]: Start isEmpty. Operand 375 states and 570 transitions. [2021-11-12 23:10:40,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:40,226 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:40,227 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:40,227 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2021-11-12 23:10:40,228 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:40,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:40,232 INFO L85 PathProgramCache]: Analyzing trace with hash -466517056, now seen corresponding path program 1 times [2021-11-12 23:10:40,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:40,232 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792785622] [2021-11-12 23:10:40,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:40,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:40,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:40,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:40,465 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:40,465 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792785622] [2021-11-12 23:10:40,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792785622] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:40,466 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:40,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:40,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618040249] [2021-11-12 23:10:40,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:40,468 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:40,469 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:40,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:40,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:40,470 INFO L87 Difference]: Start difference. First operand 375 states and 570 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:41,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:41,245 INFO L93 Difference]: Finished difference Result 1287 states and 1981 transitions. [2021-11-12 23:10:41,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:41,246 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:41,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:41,253 INFO L225 Difference]: With dead ends: 1287 [2021-11-12 23:10:41,254 INFO L226 Difference]: Without dead ends: 890 [2021-11-12 23:10:41,256 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:41,258 INFO L933 BasicCegarLoop]: 503 mSDtfsCounter, 1120 mSDsluCounter, 1036 mSDsCounter, 0 mSdLazyCounter, 505 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 530.77ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1350 SdHoareTripleChecker+Invalid, 715 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 15.14ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 505 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 645.85ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:41,258 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1350 Invalid, 715 Unknown, 0 Unchecked, 15.14ms Time], IncrementalHoareTripleChecker [210 Valid, 505 Invalid, 0 Unknown, 0 Unchecked, 645.85ms Time] [2021-11-12 23:10:41,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states. [2021-11-12 23:10:41,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 878. [2021-11-12 23:10:41,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 878 states, 757 states have (on average 1.500660501981506) internal successors, (1136), 746 states have internal predecessors, (1136), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2021-11-12 23:10:41,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 878 states to 878 states and 1334 transitions. [2021-11-12 23:10:41,325 INFO L78 Accepts]: Start accepts. Automaton has 878 states and 1334 transitions. Word has length 70 [2021-11-12 23:10:41,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:41,326 INFO L470 AbstractCegarLoop]: Abstraction has 878 states and 1334 transitions. [2021-11-12 23:10:41,326 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:41,326 INFO L276 IsEmpty]: Start isEmpty. Operand 878 states and 1334 transitions. [2021-11-12 23:10:41,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:41,328 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:41,328 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:41,328 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2021-11-12 23:10:41,328 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:41,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:41,329 INFO L85 PathProgramCache]: Analyzing trace with hash -363715809, now seen corresponding path program 1 times [2021-11-12 23:10:41,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:41,329 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248872588] [2021-11-12 23:10:41,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:41,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:41,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:41,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:41,442 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:41,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248872588] [2021-11-12 23:10:41,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248872588] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:41,443 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:41,443 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:41,444 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786677602] [2021-11-12 23:10:41,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:41,444 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:41,445 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:41,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:41,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:41,446 INFO L87 Difference]: Start difference. First operand 878 states and 1334 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:42,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:42,169 INFO L93 Difference]: Finished difference Result 3089 states and 4760 transitions. [2021-11-12 23:10:42,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:42,170 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:42,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:42,191 INFO L225 Difference]: With dead ends: 3089 [2021-11-12 23:10:42,191 INFO L226 Difference]: Without dead ends: 2165 [2021-11-12 23:10:42,197 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:42,204 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 468.60ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 18.44ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 555.95ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:42,205 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 18.44ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 555.95ms Time] [2021-11-12 23:10:42,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2165 states. [2021-11-12 23:10:42,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2165 to 1689. [2021-11-12 23:10:42,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1689 states, 1460 states have (on average 1.5027397260273974) internal successors, (2194), 1450 states have internal predecessors, (2194), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2021-11-12 23:10:42,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1689 states to 1689 states and 2579 transitions. [2021-11-12 23:10:42,368 INFO L78 Accepts]: Start accepts. Automaton has 1689 states and 2579 transitions. Word has length 70 [2021-11-12 23:10:42,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:42,369 INFO L470 AbstractCegarLoop]: Abstraction has 1689 states and 2579 transitions. [2021-11-12 23:10:42,369 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:42,369 INFO L276 IsEmpty]: Start isEmpty. Operand 1689 states and 2579 transitions. [2021-11-12 23:10:42,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:42,371 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:42,371 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:42,371 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2021-11-12 23:10:42,372 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:42,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:42,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1830410272, now seen corresponding path program 1 times [2021-11-12 23:10:42,372 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:42,373 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945707236] [2021-11-12 23:10:42,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:42,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:42,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:42,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:42,467 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:42,467 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945707236] [2021-11-12 23:10:42,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945707236] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:42,467 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:42,467 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:42,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170569201] [2021-11-12 23:10:42,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:42,468 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:42,468 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:42,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:42,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:42,469 INFO L87 Difference]: Start difference. First operand 1689 states and 2579 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:43,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:43,312 INFO L93 Difference]: Finished difference Result 5878 states and 9131 transitions. [2021-11-12 23:10:43,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:43,312 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:43,313 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:43,350 INFO L225 Difference]: With dead ends: 5878 [2021-11-12 23:10:43,350 INFO L226 Difference]: Without dead ends: 4096 [2021-11-12 23:10:43,362 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:43,363 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 498.02ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 9.70ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 588.26ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:43,364 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 9.70ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 588.26ms Time] [2021-11-12 23:10:43,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4096 states. [2021-11-12 23:10:43,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4096 to 3285. [2021-11-12 23:10:43,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3285 states, 2844 states have (on average 1.5028129395218002) internal successors, (4274), 2838 states have internal predecessors, (4274), 328 states have call successors, (328), 98 states have call predecessors, (328), 112 states have return successors, (421), 349 states have call predecessors, (421), 328 states have call successors, (421) [2021-11-12 23:10:43,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3285 states to 3285 states and 5023 transitions. [2021-11-12 23:10:43,584 INFO L78 Accepts]: Start accepts. Automaton has 3285 states and 5023 transitions. Word has length 70 [2021-11-12 23:10:43,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:43,588 INFO L470 AbstractCegarLoop]: Abstraction has 3285 states and 5023 transitions. [2021-11-12 23:10:43,588 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:43,588 INFO L276 IsEmpty]: Start isEmpty. Operand 3285 states and 5023 transitions. [2021-11-12 23:10:43,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:43,592 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:43,592 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:43,593 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2021-11-12 23:10:43,593 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:43,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:43,594 INFO L85 PathProgramCache]: Analyzing trace with hash 956932577, now seen corresponding path program 1 times [2021-11-12 23:10:43,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:43,594 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440365231] [2021-11-12 23:10:43,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:43,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:43,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:43,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:43,714 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:43,714 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440365231] [2021-11-12 23:10:43,715 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440365231] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:43,715 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:43,715 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:43,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67140742] [2021-11-12 23:10:43,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:43,718 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:43,718 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:43,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:43,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:43,719 INFO L87 Difference]: Start difference. First operand 3285 states and 5023 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:44,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:44,696 INFO L93 Difference]: Finished difference Result 11298 states and 17607 transitions. [2021-11-12 23:10:44,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:44,697 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:44,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:44,775 INFO L225 Difference]: With dead ends: 11298 [2021-11-12 23:10:44,775 INFO L226 Difference]: Without dead ends: 7828 [2021-11-12 23:10:44,797 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:44,803 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 467.62ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 9.48ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 559.37ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:44,804 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 9.48ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 559.37ms Time] [2021-11-12 23:10:44,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7828 states. [2021-11-12 23:10:45,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7828 to 6437. [2021-11-12 23:10:45,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6437 states, 5580 states have (on average 1.5014336917562725) internal successors, (8378), 5582 states have internal predecessors, (8378), 632 states have call successors, (632), 194 states have call predecessors, (632), 224 states have return successors, (825), 661 states have call predecessors, (825), 632 states have call successors, (825) [2021-11-12 23:10:45,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6437 states to 6437 states and 9835 transitions. [2021-11-12 23:10:45,251 INFO L78 Accepts]: Start accepts. Automaton has 6437 states and 9835 transitions. Word has length 70 [2021-11-12 23:10:45,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:45,251 INFO L470 AbstractCegarLoop]: Abstraction has 6437 states and 9835 transitions. [2021-11-12 23:10:45,252 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:45,252 INFO L276 IsEmpty]: Start isEmpty. Operand 6437 states and 9835 transitions. [2021-11-12 23:10:45,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:45,258 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:45,258 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:45,258 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-11-12 23:10:45,259 INFO L402 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:45,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:45,260 INFO L85 PathProgramCache]: Analyzing trace with hash 4194, now seen corresponding path program 1 times [2021-11-12 23:10:45,260 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:45,260 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800681948] [2021-11-12 23:10:45,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:45,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:45,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:45,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:45,369 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:45,370 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800681948] [2021-11-12 23:10:45,370 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800681948] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:45,370 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:45,370 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:45,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218856365] [2021-11-12 23:10:45,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:45,372 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:45,373 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:45,373 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:45,373 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:45,374 INFO L87 Difference]: Start difference. First operand 6437 states and 9835 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:46,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:46,631 INFO L93 Difference]: Finished difference Result 21870 states and 34091 transitions. [2021-11-12 23:10:46,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:46,631 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:46,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:46,764 INFO L225 Difference]: With dead ends: 21870 [2021-11-12 23:10:46,764 INFO L226 Difference]: Without dead ends: 15068 [2021-11-12 23:10:46,806 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:46,808 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 571.18ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 12.26ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 660.61ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:46,809 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 12.26ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 660.61ms Time] [2021-11-12 23:10:46,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15068 states. [2021-11-12 23:10:47,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15068 to 12669. [2021-11-12 23:10:47,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12669 states, 10996 states have (on average 1.4992724627137142) internal successors, (16486), 11014 states have internal predecessors, (16486), 1224 states have call successors, (1224), 386 states have call predecessors, (1224), 448 states have return successors, (1609), 1269 states have call predecessors, (1609), 1224 states have call successors, (1609) [2021-11-12 23:10:47,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12669 states to 12669 states and 19319 transitions. [2021-11-12 23:10:47,703 INFO L78 Accepts]: Start accepts. Automaton has 12669 states and 19319 transitions. Word has length 70 [2021-11-12 23:10:47,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:47,704 INFO L470 AbstractCegarLoop]: Abstraction has 12669 states and 19319 transitions. [2021-11-12 23:10:47,705 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:47,705 INFO L276 IsEmpty]: Start isEmpty. Operand 12669 states and 19319 transitions. [2021-11-12 23:10:47,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:47,707 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:47,707 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:47,708 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2021-11-12 23:10:47,708 INFO L402 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:47,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:47,709 INFO L85 PathProgramCache]: Analyzing trace with hash -1576553565, now seen corresponding path program 1 times [2021-11-12 23:10:47,709 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:47,709 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880125473] [2021-11-12 23:10:47,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:47,710 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:47,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:47,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:47,802 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:47,802 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880125473] [2021-11-12 23:10:47,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880125473] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:47,804 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:47,804 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:47,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945266094] [2021-11-12 23:10:47,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:47,805 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:47,805 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:47,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:47,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:47,806 INFO L87 Difference]: Start difference. First operand 12669 states and 19319 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:49,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:49,461 INFO L93 Difference]: Finished difference Result 42510 states and 66171 transitions. [2021-11-12 23:10:49,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:49,462 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:49,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:49,708 INFO L225 Difference]: With dead ends: 42510 [2021-11-12 23:10:49,709 INFO L226 Difference]: Without dead ends: 29124 [2021-11-12 23:10:49,855 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:49,857 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 545.12ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 11.87ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 633.78ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:49,857 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 11.87ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 633.78ms Time] [2021-11-12 23:10:49,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29124 states. [2021-11-12 23:10:51,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29124 to 24997. [2021-11-12 23:10:51,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24997 states, 21724 states have (on average 1.4966856932424968) internal successors, (32514), 21774 states have internal predecessors, (32514), 2376 states have call successors, (2376), 770 states have call predecessors, (2376), 896 states have return successors, (3129), 2453 states have call predecessors, (3129), 2376 states have call successors, (3129) [2021-11-12 23:10:51,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24997 states to 24997 states and 38019 transitions. [2021-11-12 23:10:51,243 INFO L78 Accepts]: Start accepts. Automaton has 24997 states and 38019 transitions. Word has length 70 [2021-11-12 23:10:51,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:51,244 INFO L470 AbstractCegarLoop]: Abstraction has 24997 states and 38019 transitions. [2021-11-12 23:10:51,244 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:51,244 INFO L276 IsEmpty]: Start isEmpty. Operand 24997 states and 38019 transitions. [2021-11-12 23:10:51,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:51,245 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:51,245 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:51,245 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2021-11-12 23:10:51,245 INFO L402 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:51,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:51,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1045896100, now seen corresponding path program 1 times [2021-11-12 23:10:51,246 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:51,246 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051277915] [2021-11-12 23:10:51,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:51,247 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:51,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:51,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:51,342 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:51,342 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051277915] [2021-11-12 23:10:51,342 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051277915] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:51,342 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:51,342 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:51,342 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975867491] [2021-11-12 23:10:51,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:51,343 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:51,343 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:51,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:51,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:51,346 INFO L87 Difference]: Start difference. First operand 24997 states and 38019 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:53,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:10:53,879 INFO L93 Difference]: Finished difference Result 83322 states and 129365 transitions. [2021-11-12 23:10:53,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-12 23:10:53,880 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:10:53,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:10:54,149 INFO L225 Difference]: With dead ends: 83322 [2021-11-12 23:10:54,149 INFO L226 Difference]: Without dead ends: 56920 [2021-11-12 23:10:54,238 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:10:54,241 INFO L933 BasicCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 757 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 422.53ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 15.77ms SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 527.42ms IncrementalHoareTripleChecker+Time [2021-11-12 23:10:54,241 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 15.77ms Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 527.42ms Time] [2021-11-12 23:10:54,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56920 states. [2021-11-12 23:10:56,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56920 to 49393. [2021-11-12 23:10:56,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49393 states, 42984 states have (on average 1.493858179787828) internal successors, (64212), 43098 states have internal predecessors, (64212), 4616 states have call successors, (4616), 1538 states have call predecessors, (4616), 1792 states have return successors, (6073), 4757 states have call predecessors, (6073), 4616 states have call successors, (6073) [2021-11-12 23:10:57,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49393 states to 49393 states and 74901 transitions. [2021-11-12 23:10:57,173 INFO L78 Accepts]: Start accepts. Automaton has 49393 states and 74901 transitions. Word has length 70 [2021-11-12 23:10:57,176 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:10:57,176 INFO L470 AbstractCegarLoop]: Abstraction has 49393 states and 74901 transitions. [2021-11-12 23:10:57,176 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:10:57,176 INFO L276 IsEmpty]: Start isEmpty. Operand 49393 states and 74901 transitions. [2021-11-12 23:10:57,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:10:57,177 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:10:57,178 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:10:57,178 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2021-11-12 23:10:57,178 INFO L402 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:10:57,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:10:57,179 INFO L85 PathProgramCache]: Analyzing trace with hash -544498877, now seen corresponding path program 1 times [2021-11-12 23:10:57,179 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:10:57,179 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165774630] [2021-11-12 23:10:57,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:10:57,179 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:10:57,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:10:57,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:10:57,287 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:10:57,287 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165774630] [2021-11-12 23:10:57,287 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165774630] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:10:57,287 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:10:57,288 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-12 23:10:57,288 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777500889] [2021-11-12 23:10:57,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:10:57,289 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2021-11-12 23:10:57,289 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:10:57,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-12 23:10:57,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-12 23:10:57,290 INFO L87 Difference]: Start difference. First operand 49393 states and 74901 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:11:00,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:11:00,665 INFO L93 Difference]: Finished difference Result 139717 states and 215087 transitions. [2021-11-12 23:11:00,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-12 23:11:00,670 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:11:00,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:11:01,449 INFO L225 Difference]: With dead ends: 139717 [2021-11-12 23:11:01,449 INFO L226 Difference]: Without dead ends: 87703 [2021-11-12 23:11:01,623 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2021-11-12 23:11:01,625 INFO L933 BasicCegarLoop]: 510 mSDtfsCounter, 1077 mSDsluCounter, 1200 mSDsCounter, 0 mSdLazyCounter, 538 mSolverCounterSat, 168 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 471.09ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1099 SdHoareTripleChecker+Valid, 1492 SdHoareTripleChecker+Invalid, 706 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 12.47ms SdHoareTripleChecker+Time, 168 IncrementalHoareTripleChecker+Valid, 538 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 609.95ms IncrementalHoareTripleChecker+Time [2021-11-12 23:11:01,626 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1099 Valid, 1492 Invalid, 706 Unknown, 0 Unchecked, 12.47ms Time], IncrementalHoareTripleChecker [168 Valid, 538 Invalid, 0 Unknown, 0 Unchecked, 609.95ms Time] [2021-11-12 23:11:01,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87703 states. [2021-11-12 23:11:04,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87703 to 56019. [2021-11-12 23:11:04,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56019 states, 49153 states have (on average 1.4871930502716009) internal successors, (73100), 49390 states have internal predecessors, (73100), 4812 states have call successors, (4812), 1671 states have call predecessors, (4812), 2053 states have return successors, (6455), 4958 states have call predecessors, (6455), 4812 states have call successors, (6455) [2021-11-12 23:11:04,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56019 states to 56019 states and 84367 transitions. [2021-11-12 23:11:04,488 INFO L78 Accepts]: Start accepts. Automaton has 56019 states and 84367 transitions. Word has length 70 [2021-11-12 23:11:04,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:11:04,489 INFO L470 AbstractCegarLoop]: Abstraction has 56019 states and 84367 transitions. [2021-11-12 23:11:04,489 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:11:04,489 INFO L276 IsEmpty]: Start isEmpty. Operand 56019 states and 84367 transitions. [2021-11-12 23:11:04,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2021-11-12 23:11:04,490 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:11:04,490 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:11:04,491 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2021-11-12 23:11:04,491 INFO L402 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:11:04,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:11:04,496 INFO L85 PathProgramCache]: Analyzing trace with hash 595852834, now seen corresponding path program 1 times [2021-11-12 23:11:04,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:11:04,496 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947958417] [2021-11-12 23:11:04,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:11:04,496 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:11:04,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-12 23:11:04,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-12 23:11:04,626 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-12 23:11:04,626 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947958417] [2021-11-12 23:11:04,626 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947958417] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-12 23:11:04,626 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-12 23:11:04,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2021-11-12 23:11:04,627 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001855032] [2021-11-12 23:11:04,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-12 23:11:04,627 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2021-11-12 23:11:04,628 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-12 23:11:04,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-11-12 23:11:04,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2021-11-12 23:11:04,629 INFO L87 Difference]: Start difference. First operand 56019 states and 84367 transitions. Second operand has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:11:08,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-12 23:11:08,856 INFO L93 Difference]: Finished difference Result 172811 states and 261460 transitions. [2021-11-12 23:11:08,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-11-12 23:11:08,857 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2021-11-12 23:11:08,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-12 23:11:09,930 INFO L225 Difference]: With dead ends: 172811 [2021-11-12 23:11:09,931 INFO L226 Difference]: Without dead ends: 120965 [2021-11-12 23:11:10,093 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2021-11-12 23:11:10,094 INFO L933 BasicCegarLoop]: 268 mSDtfsCounter, 1185 mSDsluCounter, 601 mSDsCounter, 0 mSdLazyCounter, 301 mSolverCounterSat, 161 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 358.23ms Time, 0 mProtectedPredicate, 0 mProtectedAction, 1192 SdHoareTripleChecker+Valid, 767 SdHoareTripleChecker+Invalid, 462 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 9.91ms SdHoareTripleChecker+Time, 161 IncrementalHoareTripleChecker+Valid, 301 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 430.09ms IncrementalHoareTripleChecker+Time [2021-11-12 23:11:10,096 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [1192 Valid, 767 Invalid, 462 Unknown, 0 Unchecked, 9.91ms Time], IncrementalHoareTripleChecker [161 Valid, 301 Invalid, 0 Unknown, 0 Unchecked, 430.09ms Time] [2021-11-12 23:11:10,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120965 states. [2021-11-12 23:11:14,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120965 to 91253. [2021-11-12 23:11:14,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91253 states, 80730 states have (on average 1.4784962219744828) internal successors, (119359), 81080 states have internal predecessors, (119359), 7186 states have call successors, (7186), 2700 states have call predecessors, (7186), 3336 states have return successors, (10286), 7473 states have call predecessors, (10286), 7186 states have call successors, (10286) [2021-11-12 23:11:15,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91253 states to 91253 states and 136831 transitions. [2021-11-12 23:11:15,016 INFO L78 Accepts]: Start accepts. Automaton has 91253 states and 136831 transitions. Word has length 70 [2021-11-12 23:11:15,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-12 23:11:15,017 INFO L470 AbstractCegarLoop]: Abstraction has 91253 states and 136831 transitions. [2021-11-12 23:11:15,017 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2021-11-12 23:11:15,017 INFO L276 IsEmpty]: Start isEmpty. Operand 91253 states and 136831 transitions. [2021-11-12 23:11:15,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2021-11-12 23:11:15,018 INFO L506 BasicCegarLoop]: Found error trace [2021-11-12 23:11:15,018 INFO L514 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:11:15,018 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2021-11-12 23:11:15,019 INFO L402 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-12 23:11:15,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-12 23:11:15,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1244227868, now seen corresponding path program 1 times [2021-11-12 23:11:15,019 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-12 23:11:15,020 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734108839] [2021-11-12 23:11:15,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-12 23:11:15,020 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-12 23:11:15,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-12 23:11:15,098 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-12 23:11:15,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-12 23:11:15,265 INFO L133 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2021-11-12 23:11:15,265 INFO L628 BasicCegarLoop]: Counterexample is feasible [2021-11-12 23:11:15,266 INFO L764 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2021-11-12 23:11:15,268 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2021-11-12 23:11:15,276 INFO L732 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-12 23:11:15,279 INFO L179 ceAbstractionStarter]: Computing trace abstraction results [2021-11-12 23:11:15,543 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.11 11:11:15 BoogieIcfgContainer [2021-11-12 23:11:15,544 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-11-12 23:11:15,544 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-12 23:11:15,545 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-12 23:11:15,552 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-12 23:11:15,553 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.11 11:10:38" (3/4) ... [2021-11-12 23:11:15,555 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-11-12 23:11:15,753 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/witness.graphml [2021-11-12 23:11:15,754 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-12 23:11:15,755 INFO L158 Benchmark]: Toolchain (without parser) took 39568.22ms. Allocated memory was 98.6MB in the beginning and 12.1GB in the end (delta: 12.0GB). Free memory was 65.5MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2021-11-12 23:11:15,755 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 98.6MB. Free memory is still 54.9MB. There was no memory consumed. Max. memory is 16.1GB. [2021-11-12 23:11:15,755 INFO L158 Benchmark]: CACSL2BoogieTranslator took 607.92ms. Allocated memory was 98.6MB in the beginning and 119.5MB in the end (delta: 21.0MB). Free memory was 65.3MB in the beginning and 83.1MB in the end (delta: -17.8MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2021-11-12 23:11:15,756 INFO L158 Benchmark]: Boogie Procedure Inliner took 101.36ms. Allocated memory is still 119.5MB. Free memory was 83.1MB in the beginning and 78.7MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-11-12 23:11:15,756 INFO L158 Benchmark]: Boogie Preprocessor took 96.58ms. Allocated memory is still 119.5MB. Free memory was 78.7MB in the beginning and 74.8MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-11-12 23:11:15,757 INFO L158 Benchmark]: RCFGBuilder took 1817.60ms. Allocated memory was 119.5MB in the beginning and 144.7MB in the end (delta: 25.2MB). Free memory was 74.8MB in the beginning and 96.8MB in the end (delta: -22.1MB). Peak memory consumption was 48.5MB. Max. memory is 16.1GB. [2021-11-12 23:11:15,757 INFO L158 Benchmark]: TraceAbstraction took 36712.31ms. Allocated memory was 144.7MB in the beginning and 12.1GB in the end (delta: 11.9GB). Free memory was 96.8MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2021-11-12 23:11:15,758 INFO L158 Benchmark]: Witness Printer took 209.39ms. Allocated memory is still 12.1GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 34.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2021-11-12 23:11:15,760 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 98.6MB. Free memory is still 54.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 607.92ms. Allocated memory was 98.6MB in the beginning and 119.5MB in the end (delta: 21.0MB). Free memory was 65.3MB in the beginning and 83.1MB in the end (delta: -17.8MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 101.36ms. Allocated memory is still 119.5MB. Free memory was 83.1MB in the beginning and 78.7MB in the end (delta: 4.5MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 96.58ms. Allocated memory is still 119.5MB. Free memory was 78.7MB in the beginning and 74.8MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1817.60ms. Allocated memory was 119.5MB in the beginning and 144.7MB in the end (delta: 25.2MB). Free memory was 74.8MB in the beginning and 96.8MB in the end (delta: -22.1MB). Peak memory consumption was 48.5MB. Max. memory is 16.1GB. * TraceAbstraction took 36712.31ms. Allocated memory was 144.7MB in the beginning and 12.1GB in the end (delta: 11.9GB). Free memory was 96.8MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 209.39ms. Allocated memory is still 12.1GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 34.6MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int t14_pc = 0; [L40] int m_st ; [L41] int t1_st ; [L42] int t2_st ; [L43] int t3_st ; [L44] int t4_st ; [L45] int t5_st ; [L46] int t6_st ; [L47] int t7_st ; [L48] int t8_st ; [L49] int t9_st ; [L50] int t10_st ; [L51] int t11_st ; [L52] int t12_st ; [L53] int t13_st ; [L54] int t14_st ; [L55] int m_i ; [L56] int t1_i ; [L57] int t2_i ; [L58] int t3_i ; [L59] int t4_i ; [L60] int t5_i ; [L61] int t6_i ; [L62] int t7_i ; [L63] int t8_i ; [L64] int t9_i ; [L65] int t10_i ; [L66] int t11_i ; [L67] int t12_i ; [L68] int t13_i ; [L69] int t14_i ; [L70] int M_E = 2; [L71] int T1_E = 2; [L72] int T2_E = 2; [L73] int T3_E = 2; [L74] int T4_E = 2; [L75] int T5_E = 2; [L76] int T6_E = 2; [L77] int T7_E = 2; [L78] int T8_E = 2; [L79] int T9_E = 2; [L80] int T10_E = 2; [L81] int T11_E = 2; [L82] int T12_E = 2; [L83] int T13_E = 2; [L84] int T14_E = 2; [L85] int E_1 = 2; [L86] int E_2 = 2; [L87] int E_3 = 2; [L88] int E_4 = 2; [L89] int E_5 = 2; [L90] int E_6 = 2; [L91] int E_7 = 2; [L92] int E_8 = 2; [L93] int E_9 = 2; [L94] int E_10 = 2; [L95] int E_11 = 2; [L96] int E_12 = 2; [L97] int E_13 = 2; [L98] int E_14 = 2; [L2062] int __retres1 ; [L2066] CALL init_model() [L1964] m_i = 1 [L1965] t1_i = 1 [L1966] t2_i = 1 [L1967] t3_i = 1 [L1968] t4_i = 1 [L1969] t5_i = 1 [L1970] t6_i = 1 [L1971] t7_i = 1 [L1972] t8_i = 1 [L1973] t9_i = 1 [L1974] t10_i = 1 [L1975] t11_i = 1 [L1976] t12_i = 1 [L1977] t13_i = 1 [L1978] t14_i = 1 [L2066] RET init_model() [L2067] CALL start_simulation() [L2003] int kernel_st ; [L2004] int tmp ; [L2005] int tmp___0 ; [L2009] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2010] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2011] CALL init_threads() [L939] COND TRUE m_i == 1 [L940] m_st = 0 [L944] COND TRUE t1_i == 1 [L945] t1_st = 0 [L949] COND TRUE t2_i == 1 [L950] t2_st = 0 [L954] COND TRUE t3_i == 1 [L955] t3_st = 0 [L959] COND TRUE t4_i == 1 [L960] t4_st = 0 [L964] COND TRUE t5_i == 1 [L965] t5_st = 0 [L969] COND TRUE t6_i == 1 [L970] t6_st = 0 [L974] COND TRUE t7_i == 1 [L975] t7_st = 0 [L979] COND TRUE t8_i == 1 [L980] t8_st = 0 [L984] COND TRUE t9_i == 1 [L985] t9_st = 0 [L989] COND TRUE t10_i == 1 [L990] t10_st = 0 [L994] COND TRUE t11_i == 1 [L995] t11_st = 0 [L999] COND TRUE t12_i == 1 [L1000] t12_st = 0 [L1004] COND TRUE t13_i == 1 [L1005] t13_st = 0 [L1009] COND TRUE t14_i == 1 [L1010] t14_st = 0 [L2011] RET init_threads() [L2012] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(M_E == 0) [L1347] COND FALSE !(T1_E == 0) [L1352] COND FALSE !(T2_E == 0) [L1357] COND FALSE !(T3_E == 0) [L1362] COND FALSE !(T4_E == 0) [L1367] COND FALSE !(T5_E == 0) [L1372] COND FALSE !(T6_E == 0) [L1377] COND FALSE !(T7_E == 0) [L1382] COND FALSE !(T8_E == 0) [L1387] COND FALSE !(T9_E == 0) [L1392] COND FALSE !(T10_E == 0) [L1397] COND FALSE !(T11_E == 0) [L1402] COND FALSE !(T12_E == 0) [L1407] COND FALSE !(T13_E == 0) [L1412] COND FALSE !(T14_E == 0) [L1417] COND FALSE !(E_1 == 0) [L1422] COND FALSE !(E_2 == 0) [L1427] COND FALSE !(E_3 == 0) [L1432] COND FALSE !(E_4 == 0) [L1437] COND FALSE !(E_5 == 0) [L1442] COND FALSE !(E_6 == 0) [L1447] COND FALSE !(E_7 == 0) [L1452] COND FALSE !(E_8 == 0) [L1457] COND FALSE !(E_9 == 0) [L1462] COND FALSE !(E_10 == 0) [L1467] COND FALSE !(E_11 == 0) [L1472] COND FALSE !(E_12 == 0) [L1477] COND FALSE !(E_13 == 0) [L1482] COND FALSE !(E_14 == 0) [L2012] RET fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2013] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1645] int tmp ; [L1646] int tmp___0 ; [L1647] int tmp___1 ; [L1648] int tmp___2 ; [L1649] int tmp___3 ; [L1650] int tmp___4 ; [L1651] int tmp___5 ; [L1652] int tmp___6 ; [L1653] int tmp___7 ; [L1654] int tmp___8 ; [L1655] int tmp___9 ; [L1656] int tmp___10 ; [L1657] int tmp___11 ; [L1658] int tmp___12 ; [L1659] int tmp___13 ; [L1664] CALL, EXPR is_master_triggered() [L643] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L656] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L658] return (__retres1); [L1664] RET, EXPR is_master_triggered() [L1664] tmp = is_master_triggered() [L1666] COND FALSE !(\read(tmp)) [L1672] CALL, EXPR is_transmit1_triggered() [L662] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L675] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L677] return (__retres1); [L1672] RET, EXPR is_transmit1_triggered() [L1672] tmp___0 = is_transmit1_triggered() [L1674] COND FALSE !(\read(tmp___0)) [L1680] CALL, EXPR is_transmit2_triggered() [L681] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L694] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L696] return (__retres1); [L1680] RET, EXPR is_transmit2_triggered() [L1680] tmp___1 = is_transmit2_triggered() [L1682] COND FALSE !(\read(tmp___1)) [L1688] CALL, EXPR is_transmit3_triggered() [L700] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L713] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L715] return (__retres1); [L1688] RET, EXPR is_transmit3_triggered() [L1688] tmp___2 = is_transmit3_triggered() [L1690] COND FALSE !(\read(tmp___2)) [L1696] CALL, EXPR is_transmit4_triggered() [L719] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L732] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L734] return (__retres1); [L1696] RET, EXPR is_transmit4_triggered() [L1696] tmp___3 = is_transmit4_triggered() [L1698] COND FALSE !(\read(tmp___3)) [L1704] CALL, EXPR is_transmit5_triggered() [L738] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L751] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L753] return (__retres1); [L1704] RET, EXPR is_transmit5_triggered() [L1704] tmp___4 = is_transmit5_triggered() [L1706] COND FALSE !(\read(tmp___4)) [L1712] CALL, EXPR is_transmit6_triggered() [L757] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L770] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L772] return (__retres1); [L1712] RET, EXPR is_transmit6_triggered() [L1712] tmp___5 = is_transmit6_triggered() [L1714] COND FALSE !(\read(tmp___5)) [L1720] CALL, EXPR is_transmit7_triggered() [L776] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L789] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L791] return (__retres1); [L1720] RET, EXPR is_transmit7_triggered() [L1720] tmp___6 = is_transmit7_triggered() [L1722] COND FALSE !(\read(tmp___6)) [L1728] CALL, EXPR is_transmit8_triggered() [L795] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L808] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L810] return (__retres1); [L1728] RET, EXPR is_transmit8_triggered() [L1728] tmp___7 = is_transmit8_triggered() [L1730] COND FALSE !(\read(tmp___7)) [L1736] CALL, EXPR is_transmit9_triggered() [L814] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L827] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L829] return (__retres1); [L1736] RET, EXPR is_transmit9_triggered() [L1736] tmp___8 = is_transmit9_triggered() [L1738] COND FALSE !(\read(tmp___8)) [L1744] CALL, EXPR is_transmit10_triggered() [L833] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L846] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L848] return (__retres1); [L1744] RET, EXPR is_transmit10_triggered() [L1744] tmp___9 = is_transmit10_triggered() [L1746] COND FALSE !(\read(tmp___9)) [L1752] CALL, EXPR is_transmit11_triggered() [L852] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L865] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L867] return (__retres1); [L1752] RET, EXPR is_transmit11_triggered() [L1752] tmp___10 = is_transmit11_triggered() [L1754] COND FALSE !(\read(tmp___10)) [L1760] CALL, EXPR is_transmit12_triggered() [L871] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L884] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L886] return (__retres1); [L1760] RET, EXPR is_transmit12_triggered() [L1760] tmp___11 = is_transmit12_triggered() [L1762] COND FALSE !(\read(tmp___11)) [L1768] CALL, EXPR is_transmit13_triggered() [L890] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L903] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L905] return (__retres1); [L1768] RET, EXPR is_transmit13_triggered() [L1768] tmp___12 = is_transmit13_triggered() [L1770] COND FALSE !(\read(tmp___12)) [L1776] CALL, EXPR is_transmit14_triggered() [L909] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] COND FALSE !(t14_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L922] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L924] return (__retres1); [L1776] RET, EXPR is_transmit14_triggered() [L1776] tmp___13 = is_transmit14_triggered() [L1778] COND FALSE !(\read(tmp___13)) [L2013] RET activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2014] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(M_E == 1) [L1500] COND FALSE !(T1_E == 1) [L1505] COND FALSE !(T2_E == 1) [L1510] COND FALSE !(T3_E == 1) [L1515] COND FALSE !(T4_E == 1) [L1520] COND FALSE !(T5_E == 1) [L1525] COND FALSE !(T6_E == 1) [L1530] COND FALSE !(T7_E == 1) [L1535] COND FALSE !(T8_E == 1) [L1540] COND FALSE !(T9_E == 1) [L1545] COND FALSE !(T10_E == 1) [L1550] COND FALSE !(T11_E == 1) [L1555] COND FALSE !(T12_E == 1) [L1560] COND FALSE !(T13_E == 1) [L1565] COND FALSE !(T14_E == 1) [L1570] COND FALSE !(E_1 == 1) [L1575] COND FALSE !(E_2 == 1) [L1580] COND FALSE !(E_3 == 1) [L1585] COND FALSE !(E_4 == 1) [L1590] COND FALSE !(E_5 == 1) [L1595] COND FALSE !(E_6 == 1) [L1600] COND FALSE !(E_7 == 1) [L1605] COND FALSE !(E_8 == 1) [L1610] COND FALSE !(E_9 == 1) [L1615] COND FALSE !(E_10 == 1) [L1620] COND FALSE !(E_11 == 1) [L1625] COND FALSE !(E_12 == 1) [L1630] COND FALSE !(E_13 == 1) [L1635] COND FALSE !(E_14 == 1) [L2014] RET reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2017] COND TRUE 1 [L2020] kernel_st = 1 [L2021] CALL eval() [L1106] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1113] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1019] int __retres1 ; [L1022] COND TRUE m_st == 0 [L1023] __retres1 = 1 [L1101] return (__retres1); [L1113] RET, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1113] tmp = exists_runnable_thread() [L1115] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1120] COND TRUE m_st == 0 [L1121] int tmp_ndt_1; [L1122] tmp_ndt_1 = __VERIFIER_nondet_int() [L1123] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1, tmp_ndt_1=0] [L1134] COND TRUE t1_st == 0 [L1135] int tmp_ndt_2; [L1136] tmp_ndt_2 = __VERIFIER_nondet_int() [L1137] COND FALSE !(\read(tmp_ndt_2)) [L1143] CALL error() [L21] reach_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 197 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 36.4s, OverallIterations: 11, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 20.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 10754 SdHoareTripleChecker+Valid, 5620.15ms IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 10627 mSDsluCounter, 11139 SdHoareTripleChecker+Invalid, 4665.52ms Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7853 mSDsCounter, 1813 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 4344 IncrementalHoareTripleChecker+Invalid, 6157 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1813 mSolverCounterUnsat, 4733 mSDtfsCounter, 4344 mSolverCounterSat, 135.17ms SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 91 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=91253occurred in iteration=10, InterpolantAutomatonStates: 53, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 14.0s AutomataMinimizationTime, 10 MinimizatonAttempts, 78142 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 0.9s InterpolantComputationTime, 771 NumberOfCodeBlocks, 771 NumberOfCodeBlocksAsserted, 11 NumberOfCheckSat, 690 ConstructedInterpolants, 0 QuantifiedInterpolants, 2052 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 10 InterpolantComputations, 10 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2021-11-12 23:11:15,840 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_46573368-3c24-449a-8ae9-55d7af774cf7/bin/utaipan-vmNK8stdcF/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE