./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/pipeline.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 53f42b1a Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/pipeline.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-53f42b1 [2021-11-21 00:54:54,372 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-21 00:54:54,375 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-21 00:54:54,413 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-21 00:54:54,414 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-21 00:54:54,415 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-21 00:54:54,417 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-21 00:54:54,420 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-21 00:54:54,422 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-21 00:54:54,423 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-21 00:54:54,424 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-21 00:54:54,426 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-21 00:54:54,426 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-21 00:54:54,428 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-21 00:54:54,429 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-21 00:54:54,431 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-21 00:54:54,432 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-21 00:54:54,433 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-21 00:54:54,436 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-21 00:54:54,438 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-21 00:54:54,440 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-21 00:54:54,442 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-21 00:54:54,444 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-21 00:54:54,445 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-21 00:54:54,448 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-21 00:54:54,449 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-21 00:54:54,452 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-21 00:54:54,453 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-21 00:54:54,453 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-21 00:54:54,455 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-21 00:54:54,455 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-21 00:54:54,455 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-21 00:54:54,456 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-21 00:54:54,457 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-21 00:54:54,458 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-21 00:54:54,458 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-21 00:54:54,459 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-21 00:54:54,459 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-21 00:54:54,459 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-21 00:54:54,460 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-21 00:54:54,460 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-21 00:54:54,461 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/config/svcomp-Reach-32bit-Taipan_Default.epf [2021-11-21 00:54:54,487 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-21 00:54:54,487 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-21 00:54:54,488 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-21 00:54:54,488 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-21 00:54:54,489 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2021-11-21 00:54:54,489 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2021-11-21 00:54:54,489 INFO L138 SettingsManager]: * User list type=DISABLED [2021-11-21 00:54:54,489 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2021-11-21 00:54:54,489 INFO L138 SettingsManager]: * Explicit value domain=true [2021-11-21 00:54:54,490 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2021-11-21 00:54:54,490 INFO L138 SettingsManager]: * Octagon Domain=false [2021-11-21 00:54:54,490 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2021-11-21 00:54:54,490 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2021-11-21 00:54:54,490 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2021-11-21 00:54:54,491 INFO L138 SettingsManager]: * Interval Domain=false [2021-11-21 00:54:54,491 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2021-11-21 00:54:54,491 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2021-11-21 00:54:54,491 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2021-11-21 00:54:54,493 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-21 00:54:54,493 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-21 00:54:54,494 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-21 00:54:54,494 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-21 00:54:54,494 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-21 00:54:54,494 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2021-11-21 00:54:54,494 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2021-11-21 00:54:54,495 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2021-11-21 00:54:54,495 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-21 00:54:54,495 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-21 00:54:54,495 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-21 00:54:54,495 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2021-11-21 00:54:54,496 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-21 00:54:54,496 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2021-11-21 00:54:54,496 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-21 00:54:54,496 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-21 00:54:54,497 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2021-11-21 00:54:54,497 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2021-11-21 00:54:54,497 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2021-11-21 00:54:54,497 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2021-11-21 00:54:54,497 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2021-11-21 00:54:54,498 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-21 00:54:54,498 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2021-11-21 00:54:54,498 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79bbe68806c3ba3852cd8c209d4ce80dca551636a131cc65daaf97524d927c63 [2021-11-21 00:54:54,779 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-21 00:54:54,806 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-21 00:54:54,808 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-21 00:54:54,810 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-21 00:54:54,811 INFO L275 PluginConnector]: CDTParser initialized [2021-11-21 00:54:54,812 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/../../sv-benchmarks/c/systemc/pipeline.cil-1.c [2021-11-21 00:54:54,873 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/data/226f5a28b/e687d8baa280434b8098a8288e37fe94/FLAG9a83d0f1e [2021-11-21 00:54:55,344 INFO L306 CDTParser]: Found 1 translation units. [2021-11-21 00:54:55,344 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/sv-benchmarks/c/systemc/pipeline.cil-1.c [2021-11-21 00:54:55,355 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/data/226f5a28b/e687d8baa280434b8098a8288e37fe94/FLAG9a83d0f1e [2021-11-21 00:54:55,371 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/data/226f5a28b/e687d8baa280434b8098a8288e37fe94 [2021-11-21 00:54:55,374 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-21 00:54:55,375 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-21 00:54:55,377 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-21 00:54:55,377 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-21 00:54:55,381 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-21 00:54:55,382 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,384 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@402c63e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55, skipping insertion in model container [2021-11-21 00:54:55,384 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,391 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-21 00:54:55,445 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-21 00:54:55,605 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2021-11-21 00:54:55,676 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-21 00:54:55,686 INFO L203 MainTranslator]: Completed pre-run [2021-11-21 00:54:55,698 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/sv-benchmarks/c/systemc/pipeline.cil-1.c[640,653] [2021-11-21 00:54:55,745 INFO L209 PostProcessor]: Analyzing one entry point: main [2021-11-21 00:54:55,760 INFO L208 MainTranslator]: Completed translation [2021-11-21 00:54:55,761 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55 WrapperNode [2021-11-21 00:54:55,761 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-21 00:54:55,762 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-21 00:54:55,762 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-21 00:54:55,762 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-21 00:54:55,770 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,781 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,818 INFO L137 Inliner]: procedures = 20, calls = 17, calls flagged for inlining = 9, calls inlined = 9, statements flattened = 422 [2021-11-21 00:54:55,819 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-21 00:54:55,820 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-21 00:54:55,820 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-21 00:54:55,820 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-21 00:54:55,829 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,829 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,834 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,834 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,843 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,853 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,857 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,862 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-21 00:54:55,864 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-21 00:54:55,864 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-21 00:54:55,864 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-21 00:54:55,865 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (1/1) ... [2021-11-21 00:54:55,874 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2021-11-21 00:54:55,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 [2021-11-21 00:54:55,911 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2021-11-21 00:54:55,936 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2021-11-21 00:54:55,968 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2021-11-21 00:54:55,968 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-21 00:54:55,968 INFO L130 BoogieDeclarations]: Found specification of procedure start_simulation [2021-11-21 00:54:55,968 INFO L138 BoogieDeclarations]: Found implementation of procedure start_simulation [2021-11-21 00:54:55,968 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-21 00:54:55,969 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-21 00:54:56,051 INFO L236 CfgBuilder]: Building ICFG [2021-11-21 00:54:56,053 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2021-11-21 00:54:56,573 INFO L277 CfgBuilder]: Performing block encoding [2021-11-21 00:54:57,026 INFO L296 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-21 00:54:57,027 INFO L301 CfgBuilder]: Removed 3 assume(true) statements. [2021-11-21 00:54:57,031 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 12:54:57 BoogieIcfgContainer [2021-11-21 00:54:57,032 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-21 00:54:57,034 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2021-11-21 00:54:57,034 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2021-11-21 00:54:57,037 INFO L275 PluginConnector]: TraceAbstraction initialized [2021-11-21 00:54:57,038 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 21.11 12:54:55" (1/3) ... [2021-11-21 00:54:57,038 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@744846fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 21.11 12:54:57, skipping insertion in model container [2021-11-21 00:54:57,039 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.11 12:54:55" (2/3) ... [2021-11-21 00:54:57,039 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@744846fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 21.11 12:54:57, skipping insertion in model container [2021-11-21 00:54:57,039 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 12:54:57" (3/3) ... [2021-11-21 00:54:57,041 INFO L111 eAbstractionObserver]: Analyzing ICFG pipeline.cil-1.c [2021-11-21 00:54:57,049 INFO L204 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2021-11-21 00:54:57,050 INFO L163 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2021-11-21 00:54:57,113 INFO L338 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2021-11-21 00:54:57,123 INFO L339 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mLoopAccelerationTechnique=FAST_UPR [2021-11-21 00:54:57,123 INFO L340 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2021-11-21 00:54:57,141 INFO L276 IsEmpty]: Start isEmpty. Operand has 30 states, 24 states have (on average 1.6666666666666667) internal successors, (40), 26 states have internal predecessors, (40), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-21 00:54:57,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2021-11-21 00:54:57,148 INFO L506 BasicCegarLoop]: Found error trace [2021-11-21 00:54:57,148 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-21 00:54:57,149 INFO L402 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-21 00:54:57,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-21 00:54:57,154 INFO L85 PathProgramCache]: Analyzing trace with hash 1030469667, now seen corresponding path program 1 times [2021-11-21 00:54:57,164 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-21 00:54:57,164 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713690573] [2021-11-21 00:54:57,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:57,166 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-21 00:54:57,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:57,414 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-11-21 00:54:57,414 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-21 00:54:57,415 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713690573] [2021-11-21 00:54:57,415 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713690573] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-21 00:54:57,416 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [325743125] [2021-11-21 00:54:57,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:57,416 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:54:57,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 [2021-11-21 00:54:57,421 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-21 00:54:57,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-11-21 00:54:57,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:57,634 INFO L263 TraceCheckSpWp]: Trace formula consists of 528 conjuncts, 1 conjunts are in the unsatisfiable core [2021-11-21 00:54:57,640 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-21 00:54:57,697 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2021-11-21 00:54:57,697 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-21 00:54:57,698 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [325743125] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-21 00:54:57,698 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-11-21 00:54:57,698 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2021-11-21 00:54:57,701 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689886661] [2021-11-21 00:54:57,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-21 00:54:57,706 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2021-11-21 00:54:57,707 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-21 00:54:57,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-21 00:54:57,741 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-21 00:54:57,744 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.6666666666666667) internal successors, (40), 26 states have internal predecessors, (40), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2021-11-21 00:54:57,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-21 00:54:57,831 INFO L93 Difference]: Finished difference Result 57 states and 92 transitions. [2021-11-21 00:54:57,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-21 00:54:57,834 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 16 [2021-11-21 00:54:57,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-21 00:54:57,843 INFO L225 Difference]: With dead ends: 57 [2021-11-21 00:54:57,843 INFO L226 Difference]: Without dead ends: 29 [2021-11-21 00:54:57,852 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 17 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-21 00:54:57,856 INFO L933 BasicCegarLoop]: 36 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 36 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-11-21 00:54:57,858 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [0 Valid, 36 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-11-21 00:54:57,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2021-11-21 00:54:57,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2021-11-21 00:54:57,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 25 states have internal predecessors, (36), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2021-11-21 00:54:57,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2021-11-21 00:54:57,912 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 42 transitions. Word has length 16 [2021-11-21 00:54:57,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-21 00:54:57,912 INFO L470 AbstractCegarLoop]: Abstraction has 29 states and 42 transitions. [2021-11-21 00:54:57,914 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 5.5) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2021-11-21 00:54:57,914 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 42 transitions. [2021-11-21 00:54:57,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2021-11-21 00:54:57,917 INFO L506 BasicCegarLoop]: Found error trace [2021-11-21 00:54:57,918 INFO L514 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-21 00:54:57,955 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2021-11-21 00:54:58,138 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:54:58,139 INFO L402 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-21 00:54:58,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-21 00:54:58,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1095063889, now seen corresponding path program 1 times [2021-11-21 00:54:58,140 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-21 00:54:58,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526618454] [2021-11-21 00:54:58,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:58,140 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-21 00:54:58,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:58,494 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2021-11-21 00:54:58,494 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-21 00:54:58,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [526618454] [2021-11-21 00:54:58,495 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [526618454] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-21 00:54:58,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1709338753] [2021-11-21 00:54:58,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:58,496 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:54:58,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 [2021-11-21 00:54:58,498 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-21 00:54:58,502 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-11-21 00:54:58,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:58,688 INFO L263 TraceCheckSpWp]: Trace formula consists of 622 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-21 00:54:58,692 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-21 00:54:58,806 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2021-11-21 00:54:58,806 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2021-11-21 00:54:58,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1709338753] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-21 00:54:58,807 INFO L186 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2021-11-21 00:54:58,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [10] total 13 [2021-11-21 00:54:58,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [189098936] [2021-11-21 00:54:58,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-21 00:54:58,808 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2021-11-21 00:54:58,808 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-21 00:54:58,809 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-21 00:54:58,809 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2021-11-21 00:54:58,809 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. Second operand has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2021-11-21 00:54:58,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-21 00:54:58,905 INFO L93 Difference]: Finished difference Result 67 states and 97 transitions. [2021-11-21 00:54:58,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-21 00:54:58,907 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 40 [2021-11-21 00:54:58,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-21 00:54:58,910 INFO L225 Difference]: With dead ends: 67 [2021-11-21 00:54:58,911 INFO L226 Difference]: Without dead ends: 40 [2021-11-21 00:54:58,912 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2021-11-21 00:54:58,914 INFO L933 BasicCegarLoop]: 40 mSDtfsCounter, 5 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 73 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2021-11-21 00:54:58,915 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [8 Valid, 73 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2021-11-21 00:54:58,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2021-11-21 00:54:58,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 35. [2021-11-21 00:54:58,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 28 states have (on average 1.4285714285714286) internal successors, (40), 29 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 4 states have call predecessors, (5), 5 states have call successors, (5) [2021-11-21 00:54:58,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 50 transitions. [2021-11-21 00:54:58,939 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 50 transitions. Word has length 40 [2021-11-21 00:54:58,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-21 00:54:58,939 INFO L470 AbstractCegarLoop]: Abstraction has 35 states and 50 transitions. [2021-11-21 00:54:58,940 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2021-11-21 00:54:58,940 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 50 transitions. [2021-11-21 00:54:58,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2021-11-21 00:54:58,948 INFO L506 BasicCegarLoop]: Found error trace [2021-11-21 00:54:58,948 INFO L514 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-21 00:54:58,989 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2021-11-21 00:54:59,161 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:54:59,162 INFO L402 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-21 00:54:59,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-21 00:54:59,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1023532891, now seen corresponding path program 1 times [2021-11-21 00:54:59,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-21 00:54:59,163 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919504821] [2021-11-21 00:54:59,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:59,163 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-21 00:54:59,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:59,613 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 79 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2021-11-21 00:54:59,613 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-21 00:54:59,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919504821] [2021-11-21 00:54:59,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919504821] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-21 00:54:59,614 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1462081732] [2021-11-21 00:54:59,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:54:59,615 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:54:59,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 [2021-11-21 00:54:59,616 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-21 00:54:59,636 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-11-21 00:54:59,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:54:59,900 INFO L263 TraceCheckSpWp]: Trace formula consists of 1127 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-21 00:54:59,906 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-21 00:55:00,097 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2021-11-21 00:55:00,097 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-21 00:55:00,316 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2021-11-21 00:55:00,317 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1462081732] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-21 00:55:00,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1763892156] [2021-11-21 00:55:00,342 INFO L159 IcfgInterpreter]: Started Sifa with 27 locations of interest [2021-11-21 00:55:00,342 INFO L166 IcfgInterpreter]: Building call graph [2021-11-21 00:55:00,347 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2021-11-21 00:55:00,353 INFO L176 IcfgInterpreter]: Starting interpretation [2021-11-21 00:55:00,354 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2021-11-21 00:55:35,107 INFO L197 IcfgInterpreter]: Interpreting procedure start_simulation with input of size 66 for LOIs [2021-11-21 00:55:42,344 INFO L180 IcfgInterpreter]: Interpretation finished [2021-11-21 00:55:44,868 WARN L312 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2021-11-21 00:55:44,869 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-21 00:55:44,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5] total 16 [2021-11-21 00:55:44,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416086517] [2021-11-21 00:55:44,869 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-21 00:55:44,870 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2021-11-21 00:55:44,870 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-21 00:55:44,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-21 00:55:44,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=770, Unknown=0, NotChecked=0, Total=870 [2021-11-21 00:55:44,872 INFO L87 Difference]: Start difference. First operand 35 states and 50 transitions. Second operand has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) [2021-11-21 00:55:45,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-21 00:55:45,508 INFO L93 Difference]: Finished difference Result 131 states and 204 transitions. [2021-11-21 00:55:45,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-21 00:55:45,518 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) Word has length 78 [2021-11-21 00:55:45,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-21 00:55:45,521 INFO L225 Difference]: With dead ends: 131 [2021-11-21 00:55:45,521 INFO L226 Difference]: Without dead ends: 98 [2021-11-21 00:55:45,523 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 218 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 411 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=226, Invalid=1496, Unknown=0, NotChecked=0, Total=1722 [2021-11-21 00:55:45,525 INFO L933 BasicCegarLoop]: 41 mSDtfsCounter, 219 mSDsluCounter, 324 mSDsCounter, 0 mSdLazyCounter, 261 mSolverCounterSat, 101 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 223 SdHoareTripleChecker+Valid, 337 SdHoareTripleChecker+Invalid, 362 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 101 IncrementalHoareTripleChecker+Valid, 261 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2021-11-21 00:55:45,525 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [223 Valid, 337 Invalid, 362 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [101 Valid, 261 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2021-11-21 00:55:45,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2021-11-21 00:55:45,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 91. [2021-11-21 00:55:45,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 75 states have (on average 1.44) internal successors, (108), 77 states have internal predecessors, (108), 12 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (22), 11 states have call predecessors, (22), 12 states have call successors, (22) [2021-11-21 00:55:45,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 142 transitions. [2021-11-21 00:55:45,565 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 142 transitions. Word has length 78 [2021-11-21 00:55:45,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-21 00:55:45,566 INFO L470 AbstractCegarLoop]: Abstraction has 91 states and 142 transitions. [2021-11-21 00:55:45,569 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 14 states have (on average 5.0) internal successors, (70), 14 states have internal predecessors, (70), 7 states have call successors, (12), 2 states have call predecessors, (12), 3 states have return successors, (12), 6 states have call predecessors, (12), 7 states have call successors, (12) [2021-11-21 00:55:45,569 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 142 transitions. [2021-11-21 00:55:45,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2021-11-21 00:55:45,579 INFO L506 BasicCegarLoop]: Found error trace [2021-11-21 00:55:45,579 INFO L514 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-21 00:55:45,623 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2021-11-21 00:55:45,801 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:55:45,802 INFO L402 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-21 00:55:45,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-21 00:55:45,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1830493759, now seen corresponding path program 1 times [2021-11-21 00:55:45,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-21 00:55:45,803 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673561651] [2021-11-21 00:55:45,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:55:45,803 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-21 00:55:45,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:55:46,368 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 27 proven. 475 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2021-11-21 00:55:46,369 INFO L139 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2021-11-21 00:55:46,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673561651] [2021-11-21 00:55:46,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673561651] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-21 00:55:46,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [222215838] [2021-11-21 00:55:46,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:55:46,369 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:55:46,370 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 [2021-11-21 00:55:46,373 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-21 00:55:46,382 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-11-21 00:55:46,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-21 00:55:46,908 INFO L263 TraceCheckSpWp]: Trace formula consists of 2650 conjuncts, 63 conjunts are in the unsatisfiable core [2021-11-21 00:55:46,929 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-21 00:55:48,963 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 457 proven. 66 refuted. 0 times theorem prover too weak. 269 trivial. 0 not checked. [2021-11-21 00:55:48,963 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2021-11-21 00:55:55,986 INFO L134 CoverageAnalysis]: Checked inductivity of 792 backedges. 96 proven. 208 refuted. 0 times theorem prover too weak. 488 trivial. 0 not checked. [2021-11-21 00:55:55,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [222215838] provided 0 perfect and 2 imperfect interpolant sequences [2021-11-21 00:55:55,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1876998245] [2021-11-21 00:55:55,990 INFO L159 IcfgInterpreter]: Started Sifa with 28 locations of interest [2021-11-21 00:55:55,990 INFO L166 IcfgInterpreter]: Building call graph [2021-11-21 00:55:55,990 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2021-11-21 00:55:55,991 INFO L176 IcfgInterpreter]: Starting interpretation [2021-11-21 00:55:55,991 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2021-11-21 00:57:21,421 INFO L197 IcfgInterpreter]: Interpreting procedure start_simulation with input of size 66 for LOIs [2021-11-21 00:57:37,285 INFO L180 IcfgInterpreter]: Interpretation finished [2021-11-21 00:57:41,080 WARN L312 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2021-11-21 00:57:41,081 INFO L186 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2021-11-21 00:57:41,081 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 12] total 34 [2021-11-21 00:57:41,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884522919] [2021-11-21 00:57:41,082 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2021-11-21 00:57:41,083 INFO L546 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2021-11-21 00:57:41,084 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2021-11-21 00:57:41,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-21 00:57:41,086 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=2590, Unknown=0, NotChecked=0, Total=2862 [2021-11-21 00:57:41,086 INFO L87 Difference]: Start difference. First operand 91 states and 142 transitions. Second operand has 34 states, 26 states have (on average 6.923076923076923) internal successors, (180), 27 states have internal predecessors, (180), 10 states have call successors, (15), 7 states have call predecessors, (15), 10 states have return successors, (15), 6 states have call predecessors, (15), 10 states have call successors, (15) [2021-11-21 00:57:42,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-21 00:57:42,019 INFO L93 Difference]: Finished difference Result 199 states and 309 transitions. [2021-11-21 00:57:42,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-21 00:57:42,021 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 26 states have (on average 6.923076923076923) internal successors, (180), 27 states have internal predecessors, (180), 10 states have call successors, (15), 7 states have call predecessors, (15), 10 states have return successors, (15), 6 states have call predecessors, (15), 10 states have call successors, (15) Word has length 195 [2021-11-21 00:57:42,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2021-11-21 00:57:42,029 INFO L225 Difference]: With dead ends: 199 [2021-11-21 00:57:42,030 INFO L226 Difference]: Without dead ends: 113 [2021-11-21 00:57:42,038 INFO L932 BasicCegarLoop]: 0 DeclaredPredicates, 626 GetRequests, 561 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1423 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=491, Invalid=3931, Unknown=0, NotChecked=0, Total=4422 [2021-11-21 00:57:42,041 INFO L933 BasicCegarLoop]: 79 mSDtfsCounter, 902 mSDsluCounter, 941 mSDsCounter, 0 mSdLazyCounter, 341 mSolverCounterSat, 124 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 902 SdHoareTripleChecker+Valid, 944 SdHoareTripleChecker+Invalid, 465 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 124 IncrementalHoareTripleChecker+Valid, 341 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2021-11-21 00:57:42,043 INFO L934 BasicCegarLoop]: SdHoareTripleChecker [902 Valid, 944 Invalid, 465 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [124 Valid, 341 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2021-11-21 00:57:42,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2021-11-21 00:57:42,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 90. [2021-11-21 00:57:42,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 75 states have (on average 1.4266666666666667) internal successors, (107), 76 states have internal predecessors, (107), 11 states have call successors, (11), 3 states have call predecessors, (11), 3 states have return successors, (11), 10 states have call predecessors, (11), 11 states have call successors, (11) [2021-11-21 00:57:42,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 129 transitions. [2021-11-21 00:57:42,068 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 129 transitions. Word has length 195 [2021-11-21 00:57:42,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2021-11-21 00:57:42,069 INFO L470 AbstractCegarLoop]: Abstraction has 90 states and 129 transitions. [2021-11-21 00:57:42,070 INFO L471 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 26 states have (on average 6.923076923076923) internal successors, (180), 27 states have internal predecessors, (180), 10 states have call successors, (15), 7 states have call predecessors, (15), 10 states have return successors, (15), 6 states have call predecessors, (15), 10 states have call successors, (15) [2021-11-21 00:57:42,070 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 129 transitions. [2021-11-21 00:57:42,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 208 [2021-11-21 00:57:42,078 INFO L506 BasicCegarLoop]: Found error trace [2021-11-21 00:57:42,079 INFO L514 BasicCegarLoop]: trace histogram [15, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2021-11-21 00:57:42,123 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2021-11-21 00:57:42,293 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-21 00:57:42,293 INFO L402 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2021-11-21 00:57:42,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-21 00:57:42,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1741877527, now seen corresponding path program 2 times [2021-11-21 00:57:42,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2021-11-21 00:57:42,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9176746] [2021-11-21 00:57:42,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-21 00:57:42,294 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-21 00:57:42,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-21 00:57:42,827 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-21 00:57:43,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-21 00:57:43,402 INFO L133 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2021-11-21 00:57:43,402 INFO L628 BasicCegarLoop]: Counterexample is feasible [2021-11-21 00:57:43,403 INFO L764 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2021-11-21 00:57:43,405 WARN L452 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2021-11-21 00:57:43,408 INFO L732 BasicCegarLoop]: Path program histogram: [2, 1, 1, 1] [2021-11-21 00:57:43,412 INFO L179 ceAbstractionStarter]: Computing trace abstraction results [2021-11-21 00:57:43,873 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 21.11 12:57:43 BoogieIcfgContainer [2021-11-21 00:57:43,874 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2021-11-21 00:57:43,874 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-21 00:57:43,874 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-21 00:57:43,875 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-21 00:57:43,875 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.11 12:54:57" (3/4) ... [2021-11-21 00:57:43,877 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2021-11-21 00:57:44,342 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/witness.graphml [2021-11-21 00:57:44,342 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-21 00:57:44,343 INFO L158 Benchmark]: Toolchain (without parser) took 168967.78ms. Allocated memory was 90.2MB in the beginning and 813.7MB in the end (delta: 723.5MB). Free memory was 51.7MB in the beginning and 482.0MB in the end (delta: -430.3MB). Peak memory consumption was 289.4MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,343 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 90.2MB. Free memory is still 68.9MB. There was no memory consumed. Max. memory is 16.1GB. [2021-11-21 00:57:44,343 INFO L158 Benchmark]: CACSL2BoogieTranslator took 384.69ms. Allocated memory was 90.2MB in the beginning and 136.3MB in the end (delta: 46.1MB). Free memory was 51.5MB in the beginning and 106.6MB in the end (delta: -55.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,344 INFO L158 Benchmark]: Boogie Procedure Inliner took 56.95ms. Allocated memory is still 136.3MB. Free memory was 106.6MB in the beginning and 104.5MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,344 INFO L158 Benchmark]: Boogie Preprocessor took 43.21ms. Allocated memory is still 136.3MB. Free memory was 104.0MB in the beginning and 101.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,344 INFO L158 Benchmark]: RCFGBuilder took 1168.41ms. Allocated memory is still 136.3MB. Free memory was 101.9MB in the beginning and 85.0MB in the end (delta: 16.9MB). Peak memory consumption was 62.6MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,345 INFO L158 Benchmark]: TraceAbstraction took 166840.02ms. Allocated memory was 136.3MB in the beginning and 813.7MB in the end (delta: 677.4MB). Free memory was 84.3MB in the beginning and 595.0MB in the end (delta: -510.7MB). Peak memory consumption was 166.7MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,345 INFO L158 Benchmark]: Witness Printer took 467.81ms. Allocated memory is still 813.7MB. Free memory was 595.0MB in the beginning and 482.0MB in the end (delta: 113.0MB). Peak memory consumption was 111.1MB. Max. memory is 16.1GB. [2021-11-21 00:57:44,348 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 90.2MB. Free memory is still 68.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 384.69ms. Allocated memory was 90.2MB in the beginning and 136.3MB in the end (delta: 46.1MB). Free memory was 51.5MB in the beginning and 106.6MB in the end (delta: -55.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 56.95ms. Allocated memory is still 136.3MB. Free memory was 106.6MB in the beginning and 104.5MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.21ms. Allocated memory is still 136.3MB. Free memory was 104.0MB in the beginning and 101.9MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1168.41ms. Allocated memory is still 136.3MB. Free memory was 101.9MB in the beginning and 85.0MB in the end (delta: 16.9MB). Peak memory consumption was 62.6MB. Max. memory is 16.1GB. * TraceAbstraction took 166840.02ms. Allocated memory was 136.3MB in the beginning and 813.7MB in the end (delta: 677.4MB). Free memory was 84.3MB in the beginning and 595.0MB in the end (delta: -510.7MB). Peak memory consumption was 166.7MB. Max. memory is 16.1GB. * Witness Printer took 467.81ms. Allocated memory is still 813.7MB. Free memory was 595.0MB in the beginning and 482.0MB in the end (delta: 113.0MB). Peak memory consumption was 111.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 19]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L23] int main_in1_val ; [L24] int main_in1_val_t ; [L25] int main_in1_ev ; [L26] int main_in1_req_up ; [L27] int main_in2_val ; [L28] int main_in2_val_t ; [L29] int main_in2_ev ; [L30] int main_in2_req_up ; [L31] int main_diff_val ; [L32] int main_diff_val_t ; [L33] int main_diff_ev ; [L34] int main_diff_req_up ; [L35] int main_sum_val ; [L36] int main_sum_val_t ; [L37] int main_sum_ev ; [L38] int main_sum_req_up ; [L39] int main_pres_val ; [L40] int main_pres_val_t ; [L41] int main_pres_ev ; [L42] int main_pres_req_up ; [L43] int main_dbl_val ; [L44] int main_dbl_val_t ; [L45] int main_dbl_ev ; [L46] int main_dbl_req_up ; [L47] int main_zero_val ; [L48] int main_zero_val_t ; [L49] int main_zero_ev ; [L50] int main_zero_req_up ; [L51] int main_clk_val ; [L52] int main_clk_val_t ; [L53] int main_clk_ev ; [L54] int main_clk_req_up ; [L55] int main_clk_pos_edge ; [L56] int main_clk_neg_edge ; [L57] int N_generate_st ; [L58] int N_generate_i ; [L59] int S1_addsub_st ; [L60] int S1_addsub_i ; [L61] int S2_presdbl_st ; [L62] int S2_presdbl_i ; [L63] int S3_zero_st ; [L64] int S3_zero_i ; [L65] int D_z ; [L66] int D_print_st ; [L67] int D_print_i ; [L759] int count ; [L760] int __retres2 ; [L765] main_in1_ev = 2 [L766] main_in1_req_up = 0 [L767] main_in2_ev = 2 [L768] main_in2_req_up = 0 [L769] main_diff_ev = 2 [L770] main_diff_req_up = 0 [L771] main_sum_ev = 2 [L772] main_sum_req_up = 0 [L773] main_pres_ev = 2 [L774] main_pres_req_up = 0 [L775] main_dbl_ev = 2 [L776] main_dbl_req_up = 0 [L777] main_zero_ev = 2 [L778] main_zero_req_up = 0 [L779] main_clk_val = 0 [L780] main_clk_ev = 2 [L781] main_clk_req_up = 0 [L782] main_clk_pos_edge = 2 [L783] main_clk_neg_edge = 2 [L786] count = 0 [L787] N_generate_i = 0 [L788] S1_addsub_i = 0 [L789] S2_presdbl_i = 0 [L790] S3_zero_i = 0 [L791] D_print_i = 0 VAL [count=0, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L792] CALL start_simulation() VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND FALSE !((int )main_clk_req_up == 1) [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND FALSE !((int )main_clk_ev == 0) [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND FALSE !((int )main_clk_ev == 1) [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L146] COND TRUE 1 VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=0, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=0, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=0, \old(S1_addsub_st)=0, \old(S2_presdbl_st)=0, \old(S3_zero_st)=0, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L792] RET start_simulation() VAL [count=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [count=0, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L800] CALL start_simulation() VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=4, __VERIFIER_nondet_int()=-1, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-3, __VERIFIER_nondet_int()=-2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=-2, tmp___0=1, tmp___1=4, tmp___2=-3, tmp___3=-1] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L800] RET start_simulation() VAL [count=0, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L801] count += 1 VAL [count=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L803] COND FALSE !(count == 5) VAL [count=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [count=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L818] CALL start_simulation() VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L146] COND TRUE 1 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L818] RET start_simulation() VAL [count=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [count=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L800] CALL start_simulation() VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=6, __VERIFIER_nondet_int()=-4, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-5, __VERIFIER_nondet_int()=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=5, tmp___0=1, tmp___1=6, tmp___2=-5, tmp___3=-4] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L800] RET start_simulation() VAL [count=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L801] count += 1 VAL [count=2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L803] COND FALSE !(count == 5) VAL [count=2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [count=2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L818] CALL start_simulation() VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L146] COND TRUE 1 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L818] RET start_simulation() VAL [count=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [count=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L800] CALL start_simulation() VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=8, __VERIFIER_nondet_int()=-6, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-7, __VERIFIER_nondet_int()=7, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=7, tmp___0=1, tmp___1=8, tmp___2=-7, tmp___3=-6] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND FALSE !(main_in2_val != main_in2_val_t) [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L800] RET start_simulation() VAL [count=2, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L801] count += 1 VAL [count=3, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L803] COND FALSE !(count == 5) VAL [count=3, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [count=3, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L818] CALL start_simulation() VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L146] COND TRUE 1 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L818] RET start_simulation() VAL [count=3, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [count=3, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L800] CALL start_simulation() VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=0, main_in1_val_t=0, main_in2_ev=2, main_in2_req_up=0, main_in2_val=0, main_in2_val_t=0, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=10, __VERIFIER_nondet_int()=-8, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-9, __VERIFIER_nondet_int()=9, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=0, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=0, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=9, tmp___0=1, tmp___1=10, tmp___2=-9, tmp___3=-8] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND TRUE main_in1_val != main_in1_val_t [L511] main_in1_val = main_in1_val_t [L512] main_in1_ev = 0 [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND TRUE main_in2_val != main_in2_val_t [L522] main_in2_val = main_in2_val_t [L523] main_in2_ev = 0 [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND FALSE !(main_sum_val != main_sum_val_t) [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND TRUE (int )main_in1_ev == 0 [L606] main_in1_ev = 1 [L610] COND TRUE (int )main_in2_ev == 0 [L611] main_in2_ev = 1 [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND TRUE (int )main_in1_ev == 1 [L681] main_in1_ev = 2 [L685] COND TRUE (int )main_in2_ev == 1 [L686] main_in2_ev = 2 [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=0, \old(main_in1_val_t)=0, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=0, \old(main_in2_val_t)=0, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L800] RET start_simulation() VAL [count=3, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L801] count += 1 VAL [count=4, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L803] COND FALSE !(count == 5) VAL [count=4, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L816] main_clk_val_t = 0 [L817] main_clk_req_up = 1 VAL [count=4, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L818] CALL start_simulation() VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=1, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND FALSE !((int )main_clk_val == 1) [L341] main_clk_neg_edge = 0 [L342] main_clk_pos_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND FALSE !((int )main_clk_pos_edge == 0) [L421] COND TRUE (int )main_clk_neg_edge == 0 [L422] main_clk_neg_edge = 1 [L426] COND FALSE !((int )main_clk_pos_edge == 1) [L431] COND FALSE !((int )main_clk_pos_edge == 1) [L436] COND FALSE !((int )main_clk_pos_edge == 1) [L441] COND FALSE !((int )main_clk_pos_edge == 1) [L446] COND FALSE !((int )main_clk_pos_edge == 1) [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND FALSE !((int )main_clk_pos_edge == 1) [L496] COND TRUE (int )main_clk_neg_edge == 1 [L497] main_clk_neg_edge = 2 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L146] COND TRUE 1 VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L506] RET eval() [L508] kernel_st = 2 [L509] COND FALSE !((int )main_in1_req_up == 1) [L520] COND FALSE !((int )main_in2_req_up == 1) [L531] COND FALSE !((int )main_sum_req_up == 1) [L542] COND FALSE !((int )main_diff_req_up == 1) [L553] COND FALSE !((int )main_pres_req_up == 1) [L564] COND FALSE !((int )main_dbl_req_up == 1) [L575] COND FALSE !((int )main_zero_req_up == 1) [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND FALSE !((int )main_in2_ev == 0) [L615] COND FALSE !((int )main_sum_ev == 0) [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND FALSE !((int )main_in2_ev == 1) [L690] COND FALSE !((int )main_sum_ev == 1) [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=1, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=1, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=1, \old(S1_addsub_st)=1, \old(S2_presdbl_st)=1, \old(S3_zero_st)=1, D_print_i=0, D_print_st=2, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L818] RET start_simulation() VAL [count=4, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=0, main_clk_val_t=0, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L795] COND TRUE 1 [L798] main_clk_val_t = 1 [L799] main_clk_req_up = 1 VAL [count=4, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L800] CALL start_simulation() VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=2, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=1, main_clk_val=0, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=2, S1_addsub_i=0, S1_addsub_st=2, S2_presdbl_i=0, S2_presdbl_st=2, S3_zero_i=0, S3_zero_st=2] [L252] int kernel_st ; [L255] kernel_st = 0 [L256] COND FALSE !((int )main_in1_req_up == 1) [L267] COND FALSE !((int )main_in2_req_up == 1) [L278] COND FALSE !((int )main_sum_req_up == 1) [L289] COND FALSE !((int )main_diff_req_up == 1) [L300] COND FALSE !((int )main_pres_req_up == 1) [L311] COND FALSE !((int )main_dbl_req_up == 1) [L322] COND FALSE !((int )main_zero_req_up == 1) [L333] COND TRUE (int )main_clk_req_up == 1 [L334] COND TRUE (int )main_clk_val != (int )main_clk_val_t [L335] main_clk_val = main_clk_val_t [L336] main_clk_ev = 0 [L337] COND TRUE (int )main_clk_val == 1 [L338] main_clk_pos_edge = 0 [L339] main_clk_neg_edge = 2 [L347] main_clk_req_up = 0 [L351] COND FALSE !((int )N_generate_i == 1) [L354] N_generate_st = 2 [L356] COND FALSE !((int )S1_addsub_i == 1) [L359] S1_addsub_st = 2 [L361] COND FALSE !((int )S2_presdbl_i == 1) [L364] S2_presdbl_st = 2 [L366] COND FALSE !((int )S3_zero_i == 1) [L369] S3_zero_st = 2 [L371] COND FALSE !((int )D_print_i == 1) [L374] D_print_st = 2 [L376] COND FALSE !((int )main_in1_ev == 0) [L381] COND FALSE !((int )main_in2_ev == 0) [L386] COND FALSE !((int )main_sum_ev == 0) [L391] COND FALSE !((int )main_diff_ev == 0) [L396] COND FALSE !((int )main_pres_ev == 0) [L401] COND FALSE !((int )main_dbl_ev == 0) [L406] COND FALSE !((int )main_zero_ev == 0) [L411] COND TRUE (int )main_clk_ev == 0 [L412] main_clk_ev = 1 [L416] COND TRUE (int )main_clk_pos_edge == 0 [L417] main_clk_pos_edge = 1 [L421] COND FALSE !((int )main_clk_neg_edge == 0) [L426] COND TRUE (int )main_clk_pos_edge == 1 [L427] N_generate_st = 0 [L431] COND TRUE (int )main_clk_pos_edge == 1 [L432] S1_addsub_st = 0 [L436] COND TRUE (int )main_clk_pos_edge == 1 [L437] S2_presdbl_st = 0 [L441] COND TRUE (int )main_clk_pos_edge == 1 [L442] S3_zero_st = 0 [L446] COND TRUE (int )main_clk_pos_edge == 1 [L447] D_print_st = 0 [L451] COND FALSE !((int )main_in1_ev == 1) [L456] COND FALSE !((int )main_in2_ev == 1) [L461] COND FALSE !((int )main_sum_ev == 1) [L466] COND FALSE !((int )main_diff_ev == 1) [L471] COND FALSE !((int )main_pres_ev == 1) [L476] COND FALSE !((int )main_dbl_ev == 1) [L481] COND FALSE !((int )main_zero_ev == 1) [L486] COND TRUE (int )main_clk_ev == 1 [L487] main_clk_ev = 2 [L491] COND TRUE (int )main_clk_pos_edge == 1 [L492] main_clk_pos_edge = 2 [L496] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, kernel_st=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L502] COND TRUE 1 [L505] kernel_st = 1 [L506] CALL eval() [L138] int tmp ; [L139] int tmp___0 ; [L140] int tmp___1 ; [L141] int tmp___2 ; [L142] int tmp___3 ; VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L148] COND TRUE (int )N_generate_st == 0 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=0, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=13, main_in2_val_t=13, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=0, main_sum_val_t=0, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=0, S1_addsub_i=0, S1_addsub_st=0, S2_presdbl_i=0, S2_presdbl_st=0, S3_zero_i=0, S3_zero_st=0] [L169] COND TRUE (int )N_generate_st == 0 [L171] tmp = __VERIFIER_nondet_int() [L173] COND TRUE \read(tmp) [L175] N_generate_st = 1 [L176] CALL N_generate() [L69] int a ; [L70] int b ; [L73] main_in1_val_t = a [L74] main_in1_req_up = 1 [L75] main_in2_val_t = b [L76] main_in2_req_up = 1 [L176] RET N_generate() [L184] COND TRUE (int )S1_addsub_st == 0 [L186] tmp___0 = __VERIFIER_nondet_int() [L188] COND TRUE \read(tmp___0) [L190] S1_addsub_st = 1 [L191] CALL S1_addsub() [L82] int a ; [L83] int b ; [L86] a = main_in1_val [L87] b = main_in2_val [L88] main_sum_val_t = a + b [L89] main_sum_req_up = 1 [L90] main_diff_val_t = a - b [L91] main_diff_req_up = 1 [L191] RET S1_addsub() [L199] COND TRUE (int )S2_presdbl_st == 0 [L201] tmp___1 = __VERIFIER_nondet_int() [L203] COND TRUE \read(tmp___1) [L205] S2_presdbl_st = 1 [L206] CALL S2_presdbl() [L97] int a ; [L98] int b ; [L99] int c ; [L100] int d ; [L103] a = main_sum_val [L104] b = main_diff_val [L105] main_pres_val_t = a [L106] main_pres_req_up = 1 [L107] c = a + b [L108] d = a - b [L109] main_dbl_val_t = c + d [L110] main_dbl_req_up = 1 [L206] RET S2_presdbl() [L214] COND TRUE (int )S3_zero_st == 0 [L216] tmp___2 = __VERIFIER_nondet_int() [L218] COND TRUE \read(tmp___2) [L220] S3_zero_st = 1 [L221] CALL S3_zero() [L116] int a ; [L117] int b ; [L120] a = main_pres_val [L121] b = main_dbl_val [L122] main_zero_val_t = b - (a + a) [L123] main_zero_req_up = 1 [L221] RET S3_zero() [L229] COND TRUE (int )D_print_st == 0 [L231] tmp___3 = __VERIFIER_nondet_int() [L233] COND TRUE \read(tmp___3) [L235] D_print_st = 1 [L236] CALL D_print() [L132] D_z = main_zero_val [L236] RET D_print() [L146] COND TRUE 1 VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L148] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L151] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L154] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L157] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L160] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, __VERIFIER_nondet_int()=-12, __VERIFIER_nondet_int()=-10, __VERIFIER_nondet_int()=1, __VERIFIER_nondet_int()=-11, __VERIFIER_nondet_int()=11, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=1, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=1, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=1, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=1, main_in2_val=13, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=1, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=1, main_sum_val=0, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=1, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1, tmp=11, tmp___0=1, tmp___1=-12, tmp___2=-11, tmp___3=-10] [L506] RET eval() [L508] kernel_st = 2 [L509] COND TRUE (int )main_in1_req_up == 1 [L510] COND FALSE !(main_in1_val != main_in1_val_t) [L516] main_in1_req_up = 0 [L520] COND TRUE (int )main_in2_req_up == 1 [L521] COND TRUE main_in2_val != main_in2_val_t [L522] main_in2_val = main_in2_val_t [L523] main_in2_ev = 0 [L527] main_in2_req_up = 0 [L531] COND TRUE (int )main_sum_req_up == 1 [L532] COND TRUE main_sum_val != main_sum_val_t [L533] main_sum_val = main_sum_val_t [L534] main_sum_ev = 0 [L538] main_sum_req_up = 0 [L542] COND TRUE (int )main_diff_req_up == 1 [L543] COND FALSE !(main_diff_val != main_diff_val_t) [L549] main_diff_req_up = 0 [L553] COND TRUE (int )main_pres_req_up == 1 [L554] COND FALSE !(main_pres_val != main_pres_val_t) [L560] main_pres_req_up = 0 [L564] COND TRUE (int )main_dbl_req_up == 1 [L565] COND FALSE !(main_dbl_val != main_dbl_val_t) [L571] main_dbl_req_up = 0 [L575] COND TRUE (int )main_zero_req_up == 1 [L576] COND FALSE !(main_zero_val != main_zero_val_t) [L582] main_zero_req_up = 0 [L586] COND FALSE !((int )main_clk_req_up == 1) [L604] kernel_st = 3 [L605] COND FALSE !((int )main_in1_ev == 0) [L610] COND TRUE (int )main_in2_ev == 0 [L611] main_in2_ev = 1 [L615] COND TRUE (int )main_sum_ev == 0 [L616] main_sum_ev = 1 [L620] COND FALSE !((int )main_diff_ev == 0) [L625] COND FALSE !((int )main_pres_ev == 0) [L630] COND FALSE !((int )main_dbl_ev == 0) [L635] COND FALSE !((int )main_zero_ev == 0) [L640] COND FALSE !((int )main_clk_ev == 0) [L645] COND FALSE !((int )main_clk_pos_edge == 0) [L650] COND FALSE !((int )main_clk_neg_edge == 0) [L655] COND FALSE !((int )main_clk_pos_edge == 1) [L660] COND FALSE !((int )main_clk_pos_edge == 1) [L665] COND FALSE !((int )main_clk_pos_edge == 1) [L670] COND FALSE !((int )main_clk_pos_edge == 1) [L675] COND FALSE !((int )main_clk_pos_edge == 1) [L680] COND FALSE !((int )main_in1_ev == 1) [L685] COND TRUE (int )main_in2_ev == 1 [L686] main_in2_ev = 2 [L690] COND TRUE (int )main_sum_ev == 1 [L691] main_sum_ev = 2 [L695] COND FALSE !((int )main_diff_ev == 1) [L700] COND FALSE !((int )main_pres_ev == 1) [L705] COND FALSE !((int )main_dbl_ev == 1) [L710] COND FALSE !((int )main_zero_ev == 1) [L715] COND FALSE !((int )main_clk_ev == 1) [L720] COND FALSE !((int )main_clk_pos_edge == 1) [L725] COND FALSE !((int )main_clk_neg_edge == 1) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L730] COND FALSE !((int )N_generate_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L733] COND FALSE !((int )S1_addsub_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L736] COND FALSE !((int )S2_presdbl_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L739] COND FALSE !((int )S3_zero_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L742] COND FALSE !((int )D_print_st == 0) VAL [\old(D_print_st)=2, \old(D_z)=0, \old(main_clk_ev)=2, \old(main_clk_neg_edge)=2, \old(main_clk_pos_edge)=2, \old(main_clk_req_up)=1, \old(main_clk_val)=0, \old(main_dbl_ev)=2, \old(main_dbl_req_up)=0, \old(main_dbl_val)=0, \old(main_dbl_val_t)=0, \old(main_diff_ev)=2, \old(main_diff_req_up)=0, \old(main_diff_val)=0, \old(main_diff_val_t)=0, \old(main_in1_ev)=2, \old(main_in1_req_up)=0, \old(main_in1_val)=13, \old(main_in1_val_t)=13, \old(main_in2_ev)=2, \old(main_in2_req_up)=0, \old(main_in2_val)=13, \old(main_in2_val_t)=13, \old(main_pres_ev)=2, \old(main_pres_req_up)=0, \old(main_pres_val)=0, \old(main_pres_val_t)=0, \old(main_sum_ev)=2, \old(main_sum_req_up)=0, \old(main_sum_val)=0, \old(main_sum_val_t)=0, \old(main_zero_ev)=2, \old(main_zero_req_up)=0, \old(main_zero_val)=0, \old(main_zero_val_t)=0, \old(N_generate_st)=2, \old(S1_addsub_st)=2, \old(S2_presdbl_st)=2, \old(S3_zero_st)=2, D_print_i=0, D_print_st=1, D_z=0, kernel_st=3, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L800] RET start_simulation() VAL [count=4, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L801] count += 1 VAL [count=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L803] COND TRUE count == 5 VAL [count=5, D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] [L804] COND TRUE (D_z == 0) [L806] CALL error() [L19] reach_error() VAL [D_print_i=0, D_print_st=1, D_z=0, main_clk_ev=2, main_clk_neg_edge=2, main_clk_pos_edge=2, main_clk_req_up=0, main_clk_val=1, main_clk_val_t=1, main_dbl_ev=2, main_dbl_req_up=0, main_dbl_val=0, main_dbl_val_t=0, main_diff_ev=2, main_diff_req_up=0, main_diff_val=0, main_diff_val_t=0, main_in1_ev=2, main_in1_req_up=0, main_in1_val=13, main_in1_val_t=13, main_in2_ev=2, main_in2_req_up=0, main_in2_val=49, main_in2_val_t=49, main_pres_ev=2, main_pres_req_up=0, main_pres_val=0, main_pres_val_t=0, main_sum_ev=2, main_sum_req_up=0, main_sum_val=26, main_sum_val_t=26, main_zero_ev=2, main_zero_req_up=0, main_zero_val=0, main_zero_val_t=0, N_generate_i=0, N_generate_st=1, S1_addsub_i=0, S1_addsub_st=1, S2_presdbl_i=0, S2_presdbl_st=1, S3_zero_i=0, S3_zero_st=1] - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 30 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 166.3s, OverallIterations: 5, TraceHistogramMax: 15, PathProgramHistogramMax: 2, EmptinessCheckTime: 0.0s, AutomataDifference: 1.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, PartialOrderReductionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1133 SdHoareTripleChecker+Valid, 0.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1126 mSDsluCounter, 1390 SdHoareTripleChecker+Invalid, 0.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1304 mSDsCounter, 232 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 629 IncrementalHoareTripleChecker+Invalid, 861 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 232 mSolverCounterUnsat, 196 mSDtfsCounter, 629 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 952 GetRequests, 835 SyntacticMatches, 1 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1853 ImplicationChecksByTransitivity, 7.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=91occurred in iteration=3, InterpolantAutomatonStates: 44, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 4 MinimizatonAttempts, 35 StatesRemovedByMinimization, 3 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 1.5s SatisfiabilityAnalysisTime, 10.9s InterpolantComputationTime, 865 NumberOfCodeBlocks, 865 NumberOfCodeBlocksAsserted, 9 NumberOfCheckSat, 921 ConstructedInterpolants, 0 QuantifiedInterpolants, 4683 SizeOfPredicates, 16 NumberOfNonLiveVariables, 4927 ConjunctsInSsa, 71 ConjunctsInUnsatCore, 10 InterpolantComputations, 2 PerfectInterpolantSequences, 1863/2716 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2021-11-21 00:57:44,436 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a89671d0-8ce9-4c20-85de-442ac405d787/bin/utaipan-TEXQjIfE4P/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE