./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c --full-output --architecture 32bit
--------------------------------------------------------------------------------
Checking for termination
Using default analysis
Version 63182f13
Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )
--witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9
--- Real Ultimate output ---
This is Ultimate 0.2.1-dev-63182f1
[2021-11-13 17:47:30,233 INFO L177 SettingsManager]: Resetting all preferences to default values...
[2021-11-13 17:47:30,236 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values
[2021-11-13 17:47:30,281 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring...
[2021-11-13 17:47:30,281 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values
[2021-11-13 17:47:30,283 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values
[2021-11-13 17:47:30,285 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values
[2021-11-13 17:47:30,288 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values
[2021-11-13 17:47:30,291 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values
[2021-11-13 17:47:30,292 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values
[2021-11-13 17:47:30,293 INFO L181 SettingsManager]: Resetting Sifa preferences to default values
[2021-11-13 17:47:30,295 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring...
[2021-11-13 17:47:30,295 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values
[2021-11-13 17:47:30,297 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values
[2021-11-13 17:47:30,299 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values
[2021-11-13 17:47:30,300 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values
[2021-11-13 17:47:30,302 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values
[2021-11-13 17:47:30,303 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values
[2021-11-13 17:47:30,305 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values
[2021-11-13 17:47:30,308 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values
[2021-11-13 17:47:30,310 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values
[2021-11-13 17:47:30,312 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values
[2021-11-13 17:47:30,314 INFO L181 SettingsManager]: Resetting Referee preferences to default values
[2021-11-13 17:47:30,315 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values
[2021-11-13 17:47:30,320 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring...
[2021-11-13 17:47:30,320 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring...
[2021-11-13 17:47:30,321 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values
[2021-11-13 17:47:30,322 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values
[2021-11-13 17:47:30,323 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values
[2021-11-13 17:47:30,324 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring...
[2021-11-13 17:47:30,325 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values
[2021-11-13 17:47:30,326 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values
[2021-11-13 17:47:30,327 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values
[2021-11-13 17:47:30,332 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values
[2021-11-13 17:47:30,333 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring...
[2021-11-13 17:47:30,333 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values
[2021-11-13 17:47:30,334 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring...
[2021-11-13 17:47:30,335 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring...
[2021-11-13 17:47:30,335 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values
[2021-11-13 17:47:30,336 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values
[2021-11-13 17:47:30,337 INFO L188 SettingsManager]: Finished resetting all preferences to default values...
[2021-11-13 17:47:30,340 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf
[2021-11-13 17:47:30,385 INFO L113 SettingsManager]: Loading preferences was successful
[2021-11-13 17:47:30,385 INFO L115 SettingsManager]: Preferences different from defaults after loading the file:
[2021-11-13 17:47:30,386 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2021-11-13 17:47:30,386 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2021-11-13 17:47:30,388 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2021-11-13 17:47:30,388 INFO L138 SettingsManager]: * Create parallel compositions if possible=false
[2021-11-13 17:47:30,389 INFO L138 SettingsManager]: * Use SBE=true
[2021-11-13 17:47:30,389 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2021-11-13 17:47:30,389 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3
[2021-11-13 17:47:30,389 INFO L138 SettingsManager]: * Use old map elimination=false
[2021-11-13 17:47:30,390 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false
[2021-11-13 17:47:30,390 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES
[2021-11-13 17:47:30,391 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * sizeof long=4
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * sizeof POINTER=4
[2021-11-13 17:47:30,391 INFO L138 SettingsManager]: * Check division by zero=IGNORE
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * sizeof long double=12
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * Check if freed pointer was valid=false
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false
[2021-11-13 17:47:30,392 INFO L138 SettingsManager]: * Use constant arrays=true
[2021-11-13 17:47:30,393 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME
[2021-11-13 17:47:30,393 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2021-11-13 17:47:30,393 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements
[2021-11-13 17:47:30,393 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2021-11-13 17:47:30,393 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL
[2021-11-13 17:47:30,394 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE
[2021-11-13 17:47:30,394 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2021-11-13 17:47:30,395 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int)
WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ae06fa96255229a08f1e8c01eaa7f353b1ba462dacd64e058a3c6957598773d9
[2021-11-13 17:47:30,655 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2021-11-13 17:47:30,682 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2021-11-13 17:47:30,684 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2021-11-13 17:47:30,685 INFO L271 PluginConnector]: Initializing CDTParser...
[2021-11-13 17:47:30,687 INFO L275 PluginConnector]: CDTParser initialized
[2021-11-13 17:47:30,688 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/token_ring.09.cil-2.c
[2021-11-13 17:47:30,753 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/data/d443a763c/c0deafcf176a417f9f0382ca851d2f16/FLAGebf3d1bfa
[2021-11-13 17:47:31,318 INFO L306 CDTParser]: Found 1 translation units.
[2021-11-13 17:47:31,319 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/sv-benchmarks/c/systemc/token_ring.09.cil-2.c
[2021-11-13 17:47:31,337 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/data/d443a763c/c0deafcf176a417f9f0382ca851d2f16/FLAGebf3d1bfa
[2021-11-13 17:47:31,766 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/data/d443a763c/c0deafcf176a417f9f0382ca851d2f16
[2021-11-13 17:47:31,769 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2021-11-13 17:47:31,770 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements.
[2021-11-13 17:47:31,772 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2021-11-13 17:47:31,772 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2021-11-13 17:47:31,776 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized
[2021-11-13 17:47:31,778 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 05:47:31" (1/1) ...
[2021-11-13 17:47:31,779 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24b23ae2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:31, skipping insertion in model container
[2021-11-13 17:47:31,780 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 05:47:31" (1/1) ...
[2021-11-13 17:47:31,806 INFO L145 MainTranslator]: Starting translation in SV-COMP mode
[2021-11-13 17:47:31,861 INFO L178 MainTranslator]: Built tables and reachable declarations
[2021-11-13 17:47:32,041 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684]
[2021-11-13 17:47:32,156 INFO L206 PostProcessor]: Analyzing one entry point: main
[2021-11-13 17:47:32,168 INFO L203 MainTranslator]: Completed pre-run
[2021-11-13 17:47:32,181 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/sv-benchmarks/c/systemc/token_ring.09.cil-2.c[671,684]
[2021-11-13 17:47:32,286 INFO L206 PostProcessor]: Analyzing one entry point: main
[2021-11-13 17:47:32,308 INFO L208 MainTranslator]: Completed translation
[2021-11-13 17:47:32,308 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32 WrapperNode
[2021-11-13 17:47:32,309 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2021-11-13 17:47:32,310 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2021-11-13 17:47:32,310 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner...
[2021-11-13 17:47:32,310 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized
[2021-11-13 17:47:32,318 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,333 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,451 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2021-11-13 17:47:32,452 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2021-11-13 17:47:32,452 INFO L271 PluginConnector]: Initializing Boogie Preprocessor...
[2021-11-13 17:47:32,452 INFO L275 PluginConnector]: Boogie Preprocessor initialized
[2021-11-13 17:47:32,461 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,462 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,492 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,493 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,548 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,613 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,622 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,639 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2021-11-13 17:47:32,641 INFO L113 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2021-11-13 17:47:32,642 INFO L271 PluginConnector]: Initializing RCFGBuilder...
[2021-11-13 17:47:32,642 INFO L275 PluginConnector]: RCFGBuilder initialized
[2021-11-13 17:47:32,644 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (1/1) ...
[2021-11-13 17:47:32,652 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2021-11-13 17:47:32,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/z3
[2021-11-13 17:47:32,683 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2021-11-13 17:47:32,697 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b6e05f48-08a9-4ffc-aeca-2116cdc7728f/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2021-11-13 17:47:32,730 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack
[2021-11-13 17:47:32,731 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int
[2021-11-13 17:47:32,731 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2021-11-13 17:47:32,731 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2021-11-13 17:47:34,891 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2021-11-13 17:47:34,892 INFO L299 CfgBuilder]: Removed 12 assume(true) statements.
[2021-11-13 17:47:34,896 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 05:47:34 BoogieIcfgContainer
[2021-11-13 17:47:34,897 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2021-11-13 17:47:34,898 INFO L113 PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2021-11-13 17:47:34,898 INFO L271 PluginConnector]: Initializing BuchiAutomizer...
[2021-11-13 17:47:34,928 INFO L275 PluginConnector]: BuchiAutomizer initialized
[2021-11-13 17:47:34,929 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2021-11-13 17:47:34,929 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 05:47:31" (1/3) ...
[2021-11-13 17:47:34,930 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7ad32808 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 05:47:34, skipping insertion in model container
[2021-11-13 17:47:34,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2021-11-13 17:47:34,930 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:47:32" (2/3) ...
[2021-11-13 17:47:34,931 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7ad32808 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 05:47:34, skipping insertion in model container
[2021-11-13 17:47:34,931 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2021-11-13 17:47:34,931 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 05:47:34" (3/3) ...
[2021-11-13 17:47:34,933 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-2.c
[2021-11-13 17:47:34,990 INFO L359 BuchiCegarLoop]: Interprodecural is true
[2021-11-13 17:47:34,991 INFO L360 BuchiCegarLoop]: Hoare is false
[2021-11-13 17:47:34,991 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2021-11-13 17:47:34,991 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2021-11-13 17:47:34,991 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2021-11-13 17:47:34,991 INFO L364 BuchiCegarLoop]: Difference is false
[2021-11-13 17:47:34,991 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2021-11-13 17:47:34,992 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop========
[2021-11-13 17:47:35,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:35,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052
[2021-11-13 17:47:35,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:35,145 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:35,164 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:35,164 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:35,165 INFO L425 BuchiCegarLoop]: ======== Iteration 1============
[2021-11-13 17:47:35,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:35,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1052
[2021-11-13 17:47:35,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:35,192 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:35,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:35,199 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:35,210 INFO L791 eck$LassoCheckResult]: Stem: 562#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1076#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1021#L1403true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 588#L663true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 494#L670true assume !(1 == ~m_i~0);~m_st~0 := 2; 301#L670-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 814#L675-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 898#L680-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1012#L685-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 876#L690-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1164#L695-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 378#L700-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 370#L705-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 511#L710-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 254#L715-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 755#L951true assume !(0 == ~M_E~0); 109#L951-2true assume !(0 == ~T1_E~0); 196#L956-1true assume !(0 == ~T2_E~0); 1133#L961-1true assume !(0 == ~T3_E~0); 509#L966-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 637#L971-1true assume !(0 == ~T5_E~0); 1065#L976-1true assume !(0 == ~T6_E~0); 610#L981-1true assume !(0 == ~T7_E~0); 403#L986-1true assume !(0 == ~T8_E~0); 225#L991-1true assume !(0 == ~T9_E~0); 1106#L996-1true assume !(0 == ~E_M~0); 985#L1001-1true assume !(0 == ~E_1~0); 561#L1006-1true assume 0 == ~E_2~0;~E_2~0 := 1; 899#L1011-1true assume !(0 == ~E_3~0); 937#L1016-1true assume !(0 == ~E_4~0); 1078#L1021-1true assume !(0 == ~E_5~0); 22#L1026-1true assume !(0 == ~E_6~0); 1142#L1031-1true assume !(0 == ~E_7~0); 520#L1036-1true assume !(0 == ~E_8~0); 517#L1041-1true assume !(0 == ~E_9~0); 825#L1046-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1068#L472true assume 1 == ~m_pc~0; 1020#L473true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 543#L483true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1018#L484true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 553#L1179true assume !(0 != activate_threads_~tmp~1#1); 26#L1179-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 870#L491true assume 1 == ~t1_pc~0; 559#L492true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 621#L502true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514#L503true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12#L1187true assume !(0 != activate_threads_~tmp___0~0#1); 23#L1187-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 808#L510true assume !(1 == ~t2_pc~0); 7#L510-2true is_transmit2_triggered_~__retres1~2#1 := 0; 979#L521true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 828#L522true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1141#L1195true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136#L1195-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 407#L529true assume 1 == ~t3_pc~0; 347#L530true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 747#L540true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 958#L541true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1056#L1203true assume !(0 != activate_threads_~tmp___2~0#1); 98#L1203-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1107#L548true assume !(1 == ~t4_pc~0); 308#L548-2true is_transmit4_triggered_~__retres1~4#1 := 0; 201#L559true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 894#L560true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69#L1211true assume !(0 != activate_threads_~tmp___3~0#1); 619#L1211-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47#L567true assume 1 == ~t5_pc~0; 866#L568true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1082#L578true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160#L579true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1010#L1219true assume !(0 != activate_threads_~tmp___4~0#1); 805#L1219-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103#L586true assume !(1 == ~t6_pc~0); 139#L586-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1006#L597true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1168#L598true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1172#L1227true assume !(0 != activate_threads_~tmp___5~0#1); 799#L1227-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1104#L605true assume 1 == ~t7_pc~0; 737#L606true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 545#L616true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 512#L617true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1089#L1235true assume !(0 != activate_threads_~tmp___6~0#1); 1077#L1235-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488#L624true assume !(1 == ~t8_pc~0); 1042#L624-2true is_transmit8_triggered_~__retres1~8#1 := 0; 597#L635true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 537#L636true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 768#L1243true assume !(0 != activate_threads_~tmp___7~0#1); 1148#L1243-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33#L643true assume 1 == ~t9_pc~0; 833#L644true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 692#L654true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 612#L655true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 228#L1251true assume !(0 != activate_threads_~tmp___8~0#1); 1103#L1251-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124#L1059true assume !(1 == ~M_E~0); 1176#L1059-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 212#L1064-1true assume !(1 == ~T2_E~0); 700#L1069-1true assume !(1 == ~T3_E~0); 1064#L1074-1true assume !(1 == ~T4_E~0); 763#L1079-1true assume !(1 == ~T5_E~0); 736#L1084-1true assume !(1 == ~T6_E~0); 909#L1089-1true assume !(1 == ~T7_E~0); 790#L1094-1true assume !(1 == ~T8_E~0); 427#L1099-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 925#L1104-1true assume !(1 == ~E_M~0); 601#L1109-1true assume !(1 == ~E_1~0); 295#L1114-1true assume !(1 == ~E_2~0); 1112#L1119-1true assume !(1 == ~E_3~0); 331#L1124-1true assume !(1 == ~E_4~0); 31#L1129-1true assume !(1 == ~E_5~0); 497#L1134-1true assume !(1 == ~E_6~0); 194#L1139-1true assume 1 == ~E_7~0;~E_7~0 := 2; 306#L1144-1true assume !(1 == ~E_8~0); 1153#L1149-1true assume !(1 == ~E_9~0); 106#L1154-1true assume { :end_inline_reset_delta_events } true; 174#L1440-2true
[2021-11-13 17:47:35,214 INFO L793 eck$LassoCheckResult]: Loop: 174#L1440-2true assume !false; 964#L1441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 826#L926true assume false; 423#L941true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 765#L663-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245#L951-3true assume !(0 == ~M_E~0); 1143#L951-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 651#L956-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 491#L961-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 320#L966-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 918#L971-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 538#L976-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 41#L981-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 238#L986-3true assume !(0 == ~T8_E~0); 32#L991-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L996-3true assume 0 == ~E_M~0;~E_M~0 := 1; 762#L1001-3true assume 0 == ~E_1~0;~E_1~0 := 1; 305#L1006-3true assume 0 == ~E_2~0;~E_2~0 := 1; 658#L1011-3true assume 0 == ~E_3~0;~E_3~0 := 1; 896#L1016-3true assume 0 == ~E_4~0;~E_4~0 := 1; 709#L1021-3true assume 0 == ~E_5~0;~E_5~0 := 1; 440#L1026-3true assume !(0 == ~E_6~0); 1059#L1031-3true assume 0 == ~E_7~0;~E_7~0 := 1; 627#L1036-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1118#L1041-3true assume 0 == ~E_9~0;~E_9~0 := 1; 695#L1046-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650#L472-33true assume 1 == ~m_pc~0; 771#L473-11true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 904#L483-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11#L484-11true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 655#L1179-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 325#L1179-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1045#L491-33true assume 1 == ~t1_pc~0; 554#L492-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 956#L502-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1184#L503-11true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1001#L1187-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1063#L1187-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 605#L510-33true assume !(1 == ~t2_pc~0); 603#L510-35true is_transmit2_triggered_~__retres1~2#1 := 0; 987#L521-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 510#L522-11true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 716#L1195-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4#L1195-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 152#L529-33true assume !(1 == ~t3_pc~0); 208#L529-35true is_transmit3_triggered_~__retres1~3#1 := 0; 143#L540-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 947#L541-11true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1007#L1203-33true assume !(0 != activate_threads_~tmp___2~0#1); 61#L1203-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183#L548-33true assume !(1 == ~t4_pc~0); 1163#L548-35true is_transmit4_triggered_~__retres1~4#1 := 0; 570#L559-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 278#L560-11true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 281#L1211-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148#L1211-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 911#L567-33true assume 1 == ~t5_pc~0; 414#L568-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 353#L578-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 957#L579-11true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1030#L1219-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1119#L1219-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 508#L586-33true assume 1 == ~t6_pc~0; 478#L587-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 546#L597-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 436#L598-11true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1138#L1227-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 157#L1227-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 261#L605-33true assume 1 == ~t7_pc~0; 1177#L606-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 120#L616-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 357#L617-11true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1108#L1235-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66#L1235-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 142#L624-33true assume !(1 == ~t8_pc~0); 146#L624-35true is_transmit8_triggered_~__retres1~8#1 := 0; 1039#L635-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130#L636-11true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 270#L1243-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1154#L1243-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121#L643-33true assume 1 == ~t9_pc~0; 513#L644-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 459#L654-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1099#L655-11true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 425#L1251-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 785#L1251-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62#L1059-3true assume 1 == ~M_E~0;~M_E~0 := 2; 339#L1059-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1170#L1064-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 376#L1069-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 611#L1074-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 859#L1079-3true assume !(1 == ~T5_E~0); 522#L1084-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 458#L1089-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 572#L1094-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 396#L1099-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 631#L1104-3true assume 1 == ~E_M~0;~E_M~0 := 2; 932#L1109-3true assume 1 == ~E_1~0;~E_1~0 := 2; 618#L1114-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1031#L1119-3true assume !(1 == ~E_3~0); 1167#L1124-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1061#L1129-3true assume 1 == ~E_5~0;~E_5~0 := 2; 216#L1134-3true assume 1 == ~E_6~0;~E_6~0 := 2; 472#L1139-3true assume 1 == ~E_7~0;~E_7~0 := 2; 317#L1144-3true assume 1 == ~E_8~0;~E_8~0 := 2; 428#L1149-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1159#L1154-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1095#L728-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 729#L780-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13#L781-1true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16#L1459true assume !(0 == start_simulation_~tmp~3#1); 712#L1459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 891#L728-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 527#L780-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1134#L781-2true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 243#L1414true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 342#L1421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 482#L1422true start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 708#L1472true assume !(0 != start_simulation_~tmp___0~1#1); 174#L1440-2true
[2021-11-13 17:47:35,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:35,224 INFO L85 PathProgramCache]: Analyzing trace with hash -986421749, now seen corresponding path program 1 times
[2021-11-13 17:47:35,234 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:35,235 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734072109]
[2021-11-13 17:47:35,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:35,237 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:35,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:35,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:35,549 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:35,550 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734072109]
[2021-11-13 17:47:35,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734072109] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:35,551 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:35,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:35,554 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615358408]
[2021-11-13 17:47:35,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:35,569 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:35,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:35,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1822815513, now seen corresponding path program 1 times
[2021-11-13 17:47:35,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:35,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047856920]
[2021-11-13 17:47:35,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:35,571 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:35,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:35,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:35,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:35,643 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047856920]
[2021-11-13 17:47:35,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047856920] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:35,643 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:35,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:35,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65551498]
[2021-11-13 17:47:35,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:35,646 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:35,647 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:35,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:35,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:35,689 INFO L87 Difference]: Start difference. First operand has 1183 states, 1182 states have (on average 1.5109983079526226) internal successors, (1786), 1182 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:35,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:35,799 INFO L93 Difference]: Finished difference Result 1181 states and 1757 transitions.
[2021-11-13 17:47:35,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:35,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1757 transitions.
[2021-11-13 17:47:35,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:35,849 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1175 states and 1751 transitions.
[2021-11-13 17:47:35,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:35,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:35,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1751 transitions.
[2021-11-13 17:47:35,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:35,867 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions.
[2021-11-13 17:47:35,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1751 transitions.
[2021-11-13 17:47:35,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:35,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.490212765957447) internal successors, (1751), 1174 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:35,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1751 transitions.
[2021-11-13 17:47:35,984 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions.
[2021-11-13 17:47:35,984 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1751 transitions.
[2021-11-13 17:47:35,984 INFO L425 BuchiCegarLoop]: ======== Iteration 2============
[2021-11-13 17:47:35,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1751 transitions.
[2021-11-13 17:47:35,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:35,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:35,995 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:36,000 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,000 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,001 INFO L791 eck$LassoCheckResult]: Stem: 3275#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 3276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3535#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3294#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 2945#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2946#L675-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3453#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3485#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3477#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3478#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3058#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3048#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3049#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2869#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2870#L951 assume !(0 == ~M_E~0); 2608#L951-2 assume !(0 == ~T1_E~0); 2609#L956-1 assume !(0 == ~T2_E~0); 2769#L961-1 assume !(0 == ~T3_E~0); 3210#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3211#L971-1 assume !(0 == ~T5_E~0); 3350#L976-1 assume !(0 == ~T6_E~0); 3321#L981-1 assume !(0 == ~T7_E~0); 3094#L986-1 assume !(0 == ~T8_E~0); 2822#L991-1 assume !(0 == ~T9_E~0); 2823#L996-1 assume !(0 == ~E_M~0); 3516#L1001-1 assume !(0 == ~E_1~0); 3273#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3274#L1011-1 assume !(0 == ~E_3~0); 3487#L1016-1 assume !(0 == ~E_4~0); 3499#L1021-1 assume !(0 == ~E_5~0); 2415#L1026-1 assume !(0 == ~E_6~0); 2416#L1031-1 assume !(0 == ~E_7~0); 3222#L1036-1 assume !(0 == ~E_8~0); 3218#L1041-1 assume !(0 == ~E_9~0); 3219#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3460#L472 assume 1 == ~m_pc~0; 3534#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3253#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3261#L1179 assume !(0 != activate_threads_~tmp~1#1); 2423#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2424#L491 assume 1 == ~t1_pc~0; 3270#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2920#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2395#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 2396#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2419#L510 assume !(1 == ~t2_pc~0); 2382#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2383#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3463#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3464#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2664#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2665#L529 assume 1 == ~t3_pc~0; 3015#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3016#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3427#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3509#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 2585#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2586#L548 assume !(1 == ~t4_pc~0); 2483#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2482#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2527#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 2528#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2470#L567 assume 1 == ~t5_pc~0; 2471#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2529#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2710#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2711#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 3448#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2596#L586 assume !(1 == ~t6_pc~0); 2597#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2670#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3531#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3547#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 3444#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3445#L605 assume 1 == ~t7_pc~0; 3424#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3075#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3214#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3215#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 3543#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3190#L624 assume !(1 == ~t8_pc~0); 2658#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2657#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3246#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3247#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 3432#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2438#L643 assume 1 == ~t9_pc~0; 2439#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3389#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3323#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2829#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 2830#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2640#L1059 assume !(1 == ~M_E~0); 2641#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2797#L1064-1 assume !(1 == ~T2_E~0); 2798#L1069-1 assume !(1 == ~T3_E~0); 3396#L1074-1 assume !(1 == ~T4_E~0); 3430#L1079-1 assume !(1 == ~T5_E~0); 3422#L1084-1 assume !(1 == ~T6_E~0); 3423#L1089-1 assume !(1 == ~T7_E~0); 3440#L1094-1 assume !(1 == ~T8_E~0); 3123#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3124#L1104-1 assume !(1 == ~E_M~0); 3309#L1109-1 assume !(1 == ~E_1~0); 2938#L1114-1 assume !(1 == ~E_2~0); 2939#L1119-1 assume !(1 == ~E_3~0); 2991#L1124-1 assume !(1 == ~E_4~0); 2434#L1129-1 assume !(1 == ~E_5~0); 2435#L1134-1 assume !(1 == ~E_6~0); 2765#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2766#L1144-1 assume !(1 == ~E_8~0); 2953#L1149-1 assume !(1 == ~E_9~0); 2602#L1154-1 assume { :end_inline_reset_delta_events } true; 2603#L1440-2
[2021-11-13 17:47:36,002 INFO L793 eck$LassoCheckResult]: Loop: 2603#L1440-2 assume !false; 2732#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2374#L926 assume !false; 2993#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2994#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2692#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2693#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2698#L795 assume !(0 != eval_~tmp~0#1); 2699#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3118#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2854#L951-3 assume !(0 == ~M_E~0); 2855#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3358#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3194#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2977#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2978#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3248#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2456#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2457#L986-3 assume !(0 == ~T8_E~0); 2436#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2437#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3344#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3366#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3401#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3141#L1026-3 assume !(0 == ~E_6~0); 3142#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3338#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3339#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3394#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3356#L472-33 assume !(1 == ~m_pc~0); 2555#L472-35 is_master_triggered_~__retres1~0#1 := 0; 2556#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2391#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2392#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2982#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2983#L491-33 assume !(1 == ~t1_pc~0); 2489#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2490#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3507#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3526#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3527#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3315#L510-33 assume 1 == ~t2_pc~0; 3316#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3311#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3212#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3213#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2375#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2376#L529-33 assume 1 == ~t3_pc~0; 2403#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2404#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2677#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3503#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 2506#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2507#L548-33 assume 1 == ~t4_pc~0; 2750#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2871#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2911#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2912#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2687#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2688#L567-33 assume 1 == ~t5_pc~0; 3108#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2793#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3026#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3508#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3539#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3209#L586-33 assume !(1 == ~t6_pc~0); 2810#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2811#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3135#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3136#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2702#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2703#L605-33 assume !(1 == ~t7_pc~0); 2878#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2625#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2626#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3030#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2518#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2519#L624-33 assume 1 == ~t8_pc~0; 2673#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2681#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2652#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2653#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2894#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2627#L643-33 assume 1 == ~t9_pc~0; 2628#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2720#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3166#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3119#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3120#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2508#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2509#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3005#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3055#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3056#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3322#L1079-3 assume !(1 == ~T5_E~0); 3225#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3164#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3165#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3087#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3088#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3345#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3326#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3327#L1119-3 assume !(1 == ~E_3~0); 3538#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3542#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2805#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2806#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2964#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2965#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3125#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3545#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2511#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2393#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 2394#L1459 assume !(0 == start_simulation_~tmp~3#1); 2402#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3402#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2690#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3233#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 2852#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2853#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3006#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3186#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 2603#L1440-2
[2021-11-13 17:47:36,003 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,003 INFO L85 PathProgramCache]: Analyzing trace with hash 1581400585, now seen corresponding path program 1 times
[2021-11-13 17:47:36,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,004 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759792745]
[2021-11-13 17:47:36,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,004 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,118 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,118 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759792745]
[2021-11-13 17:47:36,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759792745] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,119 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,119 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,119 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835683534]
[2021-11-13 17:47:36,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,120 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:36,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,121 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 1 times
[2021-11-13 17:47:36,121 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,121 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570031592]
[2021-11-13 17:47:36,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,122 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,245 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570031592]
[2021-11-13 17:47:36,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570031592] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,246 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,247 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725640275]
[2021-11-13 17:47:36,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,247 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:36,248 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:36,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:36,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:36,249 INFO L87 Difference]: Start difference. First operand 1175 states and 1751 transitions. cyclomatic complexity: 577 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:36,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:36,294 INFO L93 Difference]: Finished difference Result 1175 states and 1750 transitions.
[2021-11-13 17:47:36,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:36,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1750 transitions.
[2021-11-13 17:47:36,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:36,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1750 transitions.
[2021-11-13 17:47:36,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:36,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:36,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1750 transitions.
[2021-11-13 17:47:36,329 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:36,329 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions.
[2021-11-13 17:47:36,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1750 transitions.
[2021-11-13 17:47:36,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:36,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4893617021276595) internal successors, (1750), 1174 states have internal predecessors, (1750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:36,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1750 transitions.
[2021-11-13 17:47:36,365 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions.
[2021-11-13 17:47:36,365 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1750 transitions.
[2021-11-13 17:47:36,365 INFO L425 BuchiCegarLoop]: ======== Iteration 3============
[2021-11-13 17:47:36,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1750 transitions.
[2021-11-13 17:47:36,376 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:36,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:36,376 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:36,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,380 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,380 INFO L791 eck$LassoCheckResult]: Stem: 5632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 5633#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5892#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5651#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5552#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 5302#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5303#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5810#L680-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5842#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5834#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5835#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5415#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5405#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5406#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5227#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5228#L951 assume !(0 == ~M_E~0); 4967#L951-2 assume !(0 == ~T1_E~0); 4968#L956-1 assume !(0 == ~T2_E~0); 5126#L961-1 assume !(0 == ~T3_E~0); 5567#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5568#L971-1 assume !(0 == ~T5_E~0); 5707#L976-1 assume !(0 == ~T6_E~0); 5678#L981-1 assume !(0 == ~T7_E~0); 5454#L986-1 assume !(0 == ~T8_E~0); 5179#L991-1 assume !(0 == ~T9_E~0); 5180#L996-1 assume !(0 == ~E_M~0); 5874#L1001-1 assume !(0 == ~E_1~0); 5630#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5631#L1011-1 assume !(0 == ~E_3~0); 5844#L1016-1 assume !(0 == ~E_4~0); 5856#L1021-1 assume !(0 == ~E_5~0); 4772#L1026-1 assume !(0 == ~E_6~0); 4773#L1031-1 assume !(0 == ~E_7~0); 5581#L1036-1 assume !(0 == ~E_8~0); 5577#L1041-1 assume !(0 == ~E_9~0); 5578#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5817#L472 assume 1 == ~m_pc~0; 5891#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5610#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5611#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5618#L1179 assume !(0 != activate_threads_~tmp~1#1); 4780#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4781#L491 assume 1 == ~t1_pc~0; 5627#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5277#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5573#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4752#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 4753#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4776#L510 assume !(1 == ~t2_pc~0); 4739#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4740#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5820#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5821#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5021#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5022#L529 assume 1 == ~t3_pc~0; 5372#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5373#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5784#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5866#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 4942#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4943#L548 assume !(1 == ~t4_pc~0); 4840#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4839#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5136#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4884#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 4885#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4829#L567 assume 1 == ~t5_pc~0; 4830#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4886#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5067#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5068#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 5805#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4953#L586 assume !(1 == ~t6_pc~0); 4954#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5029#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5888#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5904#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 5801#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5802#L605 assume 1 == ~t7_pc~0; 5781#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5436#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5571#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5572#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 5900#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5547#L624 assume !(1 == ~t8_pc~0); 5015#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5014#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5603#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5604#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 5789#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4795#L643 assume 1 == ~t9_pc~0; 4796#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5746#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5680#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5186#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 5187#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4997#L1059 assume !(1 == ~M_E~0); 4998#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5154#L1064-1 assume !(1 == ~T2_E~0); 5155#L1069-1 assume !(1 == ~T3_E~0); 5753#L1074-1 assume !(1 == ~T4_E~0); 5788#L1079-1 assume !(1 == ~T5_E~0); 5779#L1084-1 assume !(1 == ~T6_E~0); 5780#L1089-1 assume !(1 == ~T7_E~0); 5797#L1094-1 assume !(1 == ~T8_E~0); 5480#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5481#L1104-1 assume !(1 == ~E_M~0); 5668#L1109-1 assume !(1 == ~E_1~0); 5295#L1114-1 assume !(1 == ~E_2~0); 5296#L1119-1 assume !(1 == ~E_3~0); 5348#L1124-1 assume !(1 == ~E_4~0); 4791#L1129-1 assume !(1 == ~E_5~0); 4792#L1134-1 assume !(1 == ~E_6~0); 5122#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 5123#L1144-1 assume !(1 == ~E_8~0); 5310#L1149-1 assume !(1 == ~E_9~0); 4959#L1154-1 assume { :end_inline_reset_delta_events } true; 4960#L1440-2
[2021-11-13 17:47:36,381 INFO L793 eck$LassoCheckResult]: Loop: 4960#L1440-2 assume !false; 5091#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4731#L926 assume !false; 5350#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5351#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5049#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5050#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5055#L795 assume !(0 != eval_~tmp~0#1); 5056#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5475#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5211#L951-3 assume !(0 == ~M_E~0); 5212#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5715#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5551#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5335#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5336#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4813#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4814#L986-3 assume !(0 == ~T8_E~0); 4793#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4794#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5701#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5306#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5307#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5723#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5758#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5499#L1026-3 assume !(0 == ~E_6~0); 5500#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5695#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5696#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5751#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L472-33 assume !(1 == ~m_pc~0); 4912#L472-35 is_master_triggered_~__retres1~0#1 := 0; 4913#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4748#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4749#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5339#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5340#L491-33 assume 1 == ~t1_pc~0; 5619#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4847#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5865#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5883#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5884#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5669#L510-33 assume !(1 == ~t2_pc~0); 5666#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5667#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5569#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5570#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4732#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4733#L529-33 assume 1 == ~t3_pc~0; 4760#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4761#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5034#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5860#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 4863#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4864#L548-33 assume 1 == ~t4_pc~0; 5104#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5226#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5266#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5267#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5044#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5045#L567-33 assume 1 == ~t5_pc~0; 5464#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5150#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5382#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5864#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5895#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5566#L586-33 assume !(1 == ~t6_pc~0); 5168#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5169#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5492#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5493#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5061#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5062#L605-33 assume !(1 == ~t7_pc~0); 5238#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4982#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4983#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5387#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4875#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4876#L624-33 assume 1 == ~t8_pc~0; 5032#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5041#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5009#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5010#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5251#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4984#L643-33 assume 1 == ~t9_pc~0; 4985#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5077#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5523#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5476#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5477#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4865#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4866#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5362#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5412#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5413#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5679#L1079-3 assume !(1 == ~T5_E~0); 5582#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5521#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5522#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5444#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5445#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5702#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5683#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5684#L1119-3 assume !(1 == ~E_3~0); 5896#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5899#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5162#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5163#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5324#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5325#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5482#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5902#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4868#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4750#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 4751#L1459 assume !(0 == start_simulation_~tmp~3#1); 4759#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5759#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5047#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5590#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 5209#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5210#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5364#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 5543#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 4960#L1440-2
[2021-11-13 17:47:36,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1066203769, now seen corresponding path program 1 times
[2021-11-13 17:47:36,382 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,383 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401830242]
[2021-11-13 17:47:36,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,383 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,494 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,494 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1401830242]
[2021-11-13 17:47:36,494 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1401830242] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,494 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,495 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,495 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20364955]
[2021-11-13 17:47:36,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,496 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:36,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,496 INFO L85 PathProgramCache]: Analyzing trace with hash -714854010, now seen corresponding path program 1 times
[2021-11-13 17:47:36,497 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,497 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061380381]
[2021-11-13 17:47:36,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,609 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061380381]
[2021-11-13 17:47:36,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061380381] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,610 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1098639969]
[2021-11-13 17:47:36,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,611 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:36,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:36,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:36,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:36,613 INFO L87 Difference]: Start difference. First operand 1175 states and 1750 transitions. cyclomatic complexity: 576 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:36,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:36,661 INFO L93 Difference]: Finished difference Result 1175 states and 1749 transitions.
[2021-11-13 17:47:36,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:36,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1749 transitions.
[2021-11-13 17:47:36,678 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:36,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1749 transitions.
[2021-11-13 17:47:36,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:36,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:36,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1749 transitions.
[2021-11-13 17:47:36,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:36,697 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions.
[2021-11-13 17:47:36,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1749 transitions.
[2021-11-13 17:47:36,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:36,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4885106382978723) internal successors, (1749), 1174 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:36,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1749 transitions.
[2021-11-13 17:47:36,736 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions.
[2021-11-13 17:47:36,736 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1749 transitions.
[2021-11-13 17:47:36,736 INFO L425 BuchiCegarLoop]: ======== Iteration 4============
[2021-11-13 17:47:36,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1749 transitions.
[2021-11-13 17:47:36,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:36,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:36,748 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:36,751 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:36,754 INFO L791 eck$LassoCheckResult]: Stem: 7989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 8250#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8010#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7909#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 7661#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7662#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8167#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8199#L685-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8191#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8192#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7772#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7762#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7763#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7584#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7585#L951 assume !(0 == ~M_E~0); 7326#L951-2 assume !(0 == ~T1_E~0); 7327#L956-1 assume !(0 == ~T2_E~0); 7483#L961-1 assume !(0 == ~T3_E~0); 7924#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7925#L971-1 assume !(0 == ~T5_E~0); 8064#L976-1 assume !(0 == ~T6_E~0); 8035#L981-1 assume !(0 == ~T7_E~0); 7811#L986-1 assume !(0 == ~T8_E~0); 7536#L991-1 assume !(0 == ~T9_E~0); 7537#L996-1 assume !(0 == ~E_M~0); 8231#L1001-1 assume !(0 == ~E_1~0); 7987#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7988#L1011-1 assume !(0 == ~E_3~0); 8202#L1016-1 assume !(0 == ~E_4~0); 8213#L1021-1 assume !(0 == ~E_5~0); 7129#L1026-1 assume !(0 == ~E_6~0); 7130#L1031-1 assume !(0 == ~E_7~0); 7938#L1036-1 assume !(0 == ~E_8~0); 7934#L1041-1 assume !(0 == ~E_9~0); 7935#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8174#L472 assume 1 == ~m_pc~0; 8248#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7967#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7968#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7975#L1179 assume !(0 != activate_threads_~tmp~1#1); 7137#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7138#L491 assume 1 == ~t1_pc~0; 7986#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7636#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7930#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7109#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 7110#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7133#L510 assume !(1 == ~t2_pc~0); 7096#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7097#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8177#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8178#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7378#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7379#L529 assume 1 == ~t3_pc~0; 7729#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7730#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8141#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8223#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 7299#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7300#L548 assume !(1 == ~t4_pc~0); 7197#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7196#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7493#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7241#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 7242#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7189#L567 assume 1 == ~t5_pc~0; 7190#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7243#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7427#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7428#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 8162#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7310#L586 assume !(1 == ~t6_pc~0); 7311#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7386#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8245#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8261#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 8158#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8159#L605 assume 1 == ~t7_pc~0; 8139#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7796#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7928#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7929#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 8257#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7904#L624 assume !(1 == ~t8_pc~0); 7372#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7371#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7960#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7961#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 8146#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7154#L643 assume 1 == ~t9_pc~0; 7155#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8104#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8038#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7543#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 7544#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7354#L1059 assume !(1 == ~M_E~0); 7355#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7511#L1064-1 assume !(1 == ~T2_E~0); 7512#L1069-1 assume !(1 == ~T3_E~0); 8110#L1074-1 assume !(1 == ~T4_E~0); 8145#L1079-1 assume !(1 == ~T5_E~0); 8136#L1084-1 assume !(1 == ~T6_E~0); 8137#L1089-1 assume !(1 == ~T7_E~0); 8154#L1094-1 assume !(1 == ~T8_E~0); 7837#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7838#L1104-1 assume !(1 == ~E_M~0); 8025#L1109-1 assume !(1 == ~E_1~0); 7652#L1114-1 assume !(1 == ~E_2~0); 7653#L1119-1 assume !(1 == ~E_3~0); 7706#L1124-1 assume !(1 == ~E_4~0); 7150#L1129-1 assume !(1 == ~E_5~0); 7151#L1134-1 assume !(1 == ~E_6~0); 7481#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7482#L1144-1 assume !(1 == ~E_8~0); 7667#L1149-1 assume !(1 == ~E_9~0); 7316#L1154-1 assume { :end_inline_reset_delta_events } true; 7317#L1440-2
[2021-11-13 17:47:36,755 INFO L793 eck$LassoCheckResult]: Loop: 7317#L1440-2 assume !false; 7448#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7088#L926 assume !false; 7707#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7708#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7406#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7407#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 7412#L795 assume !(0 != eval_~tmp~0#1); 7413#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7832#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7570#L951-3 assume !(0 == ~M_E~0); 7571#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8073#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7908#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7692#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7693#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7962#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7176#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7177#L986-3 assume !(0 == ~T8_E~0); 7148#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7149#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8058#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7663#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7664#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8080#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8115#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7855#L1026-3 assume !(0 == ~E_6~0); 7856#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8052#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8053#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8108#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8069#L472-33 assume !(1 == ~m_pc~0); 7266#L472-35 is_master_triggered_~__retres1~0#1 := 0; 7267#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7105#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7106#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7696#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7697#L491-33 assume !(1 == ~t1_pc~0); 7203#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7204#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8221#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8240#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8241#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8029#L510-33 assume !(1 == ~t2_pc~0); 8023#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8024#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7926#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7927#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7089#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7090#L529-33 assume 1 == ~t3_pc~0; 7117#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7118#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7391#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8217#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 7220#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7221#L548-33 assume 1 == ~t4_pc~0; 7462#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7583#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7623#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7624#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7401#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7402#L567-33 assume !(1 == ~t5_pc~0); 7506#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7739#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8222#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8252#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7923#L586-33 assume !(1 == ~t6_pc~0); 7525#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7526#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7849#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7850#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7418#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7419#L605-33 assume !(1 == ~t7_pc~0); 7595#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7346#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7347#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7744#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7232#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7233#L624-33 assume 1 == ~t8_pc~0; 7389#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7398#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7366#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7367#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7608#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7348#L643-33 assume 1 == ~t9_pc~0; 7349#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7434#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7880#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7833#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7834#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7222#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7223#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7719#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7769#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7770#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8036#L1079-3 assume !(1 == ~T5_E~0); 7939#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7878#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7879#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7801#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7802#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8059#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8041#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8042#L1119-3 assume !(1 == ~E_3~0); 8253#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8256#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7519#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7520#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7683#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7684#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7839#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8259#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7225#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7107#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 7108#L1459 assume !(0 == start_simulation_~tmp~3#1); 7116#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8117#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7404#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7947#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 7566#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7567#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7721#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7900#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 7317#L1440-2
[2021-11-13 17:47:36,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1065146953, now seen corresponding path program 1 times
[2021-11-13 17:47:36,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134113773]
[2021-11-13 17:47:36,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,761 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,849 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,850 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134113773]
[2021-11-13 17:47:36,851 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134113773] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,851 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,852 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [527122647]
[2021-11-13 17:47:36,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,853 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:36,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:36,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 1 times
[2021-11-13 17:47:36,857 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:36,860 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781586550]
[2021-11-13 17:47:36,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:36,860 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:36,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:36,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:36,930 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:36,930 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781586550]
[2021-11-13 17:47:36,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1781586550] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:36,937 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:36,937 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:36,937 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238883183]
[2021-11-13 17:47:36,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:36,938 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:36,938 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:36,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:36,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:36,940 INFO L87 Difference]: Start difference. First operand 1175 states and 1749 transitions. cyclomatic complexity: 575 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:36,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:36,993 INFO L93 Difference]: Finished difference Result 1175 states and 1748 transitions.
[2021-11-13 17:47:36,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:36,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1748 transitions.
[2021-11-13 17:47:37,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1748 transitions.
[2021-11-13 17:47:37,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:37,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:37,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1748 transitions.
[2021-11-13 17:47:37,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:37,020 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions.
[2021-11-13 17:47:37,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1748 transitions.
[2021-11-13 17:47:37,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:37,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4876595744680852) internal successors, (1748), 1174 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1748 transitions.
[2021-11-13 17:47:37,050 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions.
[2021-11-13 17:47:37,050 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1748 transitions.
[2021-11-13 17:47:37,051 INFO L425 BuchiCegarLoop]: ======== Iteration 5============
[2021-11-13 17:47:37,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1748 transitions.
[2021-11-13 17:47:37,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:37,061 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:37,063 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,063 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,064 INFO L791 eck$LassoCheckResult]: Stem: 10346#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 10347#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 10606#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10365#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10266#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 10016#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10017#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10524#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10556#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10548#L690-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10549#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10129#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10119#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10120#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9940#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9941#L951 assume !(0 == ~M_E~0); 9679#L951-2 assume !(0 == ~T1_E~0); 9680#L956-1 assume !(0 == ~T2_E~0); 9840#L961-1 assume !(0 == ~T3_E~0); 10281#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10282#L971-1 assume !(0 == ~T5_E~0); 10421#L976-1 assume !(0 == ~T6_E~0); 10392#L981-1 assume !(0 == ~T7_E~0); 10165#L986-1 assume !(0 == ~T8_E~0); 9893#L991-1 assume !(0 == ~T9_E~0); 9894#L996-1 assume !(0 == ~E_M~0); 10587#L1001-1 assume !(0 == ~E_1~0); 10344#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 10345#L1011-1 assume !(0 == ~E_3~0); 10557#L1016-1 assume !(0 == ~E_4~0); 10570#L1021-1 assume !(0 == ~E_5~0); 9486#L1026-1 assume !(0 == ~E_6~0); 9487#L1031-1 assume !(0 == ~E_7~0); 10293#L1036-1 assume !(0 == ~E_8~0); 10289#L1041-1 assume !(0 == ~E_9~0); 10290#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10531#L472 assume 1 == ~m_pc~0; 10605#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10325#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10332#L1179 assume !(0 != activate_threads_~tmp~1#1); 9494#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9495#L491 assume 1 == ~t1_pc~0; 10341#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9991#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10287#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9464#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 9465#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9488#L510 assume !(1 == ~t2_pc~0); 9453#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9454#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10533#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10534#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9735#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9736#L529 assume 1 == ~t3_pc~0; 10086#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10087#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10498#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10580#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 9656#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9657#L548 assume !(1 == ~t4_pc~0); 9554#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9553#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9848#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9596#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 9597#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9541#L567 assume 1 == ~t5_pc~0; 9542#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9598#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9781#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9782#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 10519#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9667#L586 assume !(1 == ~t6_pc~0); 9668#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9741#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10602#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10618#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 10515#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10516#L605 assume 1 == ~t7_pc~0; 10495#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10145#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10285#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10286#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 10614#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10261#L624 assume !(1 == ~t8_pc~0); 9729#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9728#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10317#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10318#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 10503#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9509#L643 assume 1 == ~t9_pc~0; 9510#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10460#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10394#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9898#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 9899#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9711#L1059 assume !(1 == ~M_E~0); 9712#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9868#L1064-1 assume !(1 == ~T2_E~0); 9869#L1069-1 assume !(1 == ~T3_E~0); 10467#L1074-1 assume !(1 == ~T4_E~0); 10501#L1079-1 assume !(1 == ~T5_E~0); 10493#L1084-1 assume !(1 == ~T6_E~0); 10494#L1089-1 assume !(1 == ~T7_E~0); 10511#L1094-1 assume !(1 == ~T8_E~0); 10194#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10195#L1104-1 assume !(1 == ~E_M~0); 10380#L1109-1 assume !(1 == ~E_1~0); 10009#L1114-1 assume !(1 == ~E_2~0); 10010#L1119-1 assume !(1 == ~E_3~0); 10062#L1124-1 assume !(1 == ~E_4~0); 9505#L1129-1 assume !(1 == ~E_5~0); 9506#L1134-1 assume !(1 == ~E_6~0); 9836#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 9837#L1144-1 assume !(1 == ~E_8~0); 10022#L1149-1 assume !(1 == ~E_9~0); 9673#L1154-1 assume { :end_inline_reset_delta_events } true; 9674#L1440-2
[2021-11-13 17:47:37,064 INFO L793 eck$LassoCheckResult]: Loop: 9674#L1440-2 assume !false; 9803#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9445#L926 assume !false; 10064#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10065#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9760#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9761#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9768#L795 assume !(0 != eval_~tmp~0#1); 9769#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10189#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9925#L951-3 assume !(0 == ~M_E~0); 9926#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10429#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10265#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10045#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10046#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10319#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9525#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9526#L986-3 assume !(0 == ~T8_E~0); 9507#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9508#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10415#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10020#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10021#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10437#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10472#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10212#L1026-3 assume !(0 == ~E_6~0); 10213#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10409#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10410#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10465#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10427#L472-33 assume !(1 == ~m_pc~0); 9626#L472-35 is_master_triggered_~__retres1~0#1 := 0; 9627#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9462#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9463#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10053#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10054#L491-33 assume !(1 == ~t1_pc~0); 9560#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9561#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10578#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10597#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10598#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L510-33 assume 1 == ~t2_pc~0; 10387#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10382#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10283#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10284#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9446#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9447#L529-33 assume 1 == ~t3_pc~0; 9474#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9475#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9748#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10574#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 9577#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9578#L548-33 assume 1 == ~t4_pc~0; 9819#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9942#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9980#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9981#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9758#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9759#L567-33 assume 1 == ~t5_pc~0; 10179#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9864#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10096#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10579#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10609#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10280#L586-33 assume !(1 == ~t6_pc~0); 9882#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9883#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10208#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10209#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9775#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9776#L605-33 assume !(1 == ~t7_pc~0); 9952#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9703#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9704#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10101#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9589#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9590#L624-33 assume 1 == ~t8_pc~0; 9746#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9755#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9723#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9724#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9965#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9705#L643-33 assume 1 == ~t9_pc~0; 9706#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9791#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10237#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10190#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10191#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9579#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9580#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10076#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10127#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10128#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10393#L1079-3 assume !(1 == ~T5_E~0); 10296#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10235#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10236#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10158#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10159#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10416#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10398#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10399#L1119-3 assume !(1 == ~E_3~0); 10610#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10613#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9876#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9877#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10040#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10041#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10196#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10616#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9584#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9466#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9467#L1459 assume !(0 == start_simulation_~tmp~3#1); 9473#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10474#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9763#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10304#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 9923#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9924#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10080#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10257#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 9674#L1440-2
[2021-11-13 17:47:37,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,065 INFO L85 PathProgramCache]: Analyzing trace with hash 2103731527, now seen corresponding path program 1 times
[2021-11-13 17:47:37,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,065 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022798974]
[2021-11-13 17:47:37,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,114 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,115 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022798974]
[2021-11-13 17:47:37,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022798974] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,115 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238230371]
[2021-11-13 17:47:37,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,116 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:37,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,117 INFO L85 PathProgramCache]: Analyzing trace with hash 634879174, now seen corresponding path program 2 times
[2021-11-13 17:47:37,117 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,118 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889042093]
[2021-11-13 17:47:37,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,118 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,178 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,179 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889042093]
[2021-11-13 17:47:37,179 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889042093] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,179 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,179 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,179 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99988284]
[2021-11-13 17:47:37,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,180 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:37,180 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:37,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:37,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:37,181 INFO L87 Difference]: Start difference. First operand 1175 states and 1748 transitions. cyclomatic complexity: 574 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:37,221 INFO L93 Difference]: Finished difference Result 1175 states and 1747 transitions.
[2021-11-13 17:47:37,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:37,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1747 transitions.
[2021-11-13 17:47:37,240 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1747 transitions.
[2021-11-13 17:47:37,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:37,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:37,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1747 transitions.
[2021-11-13 17:47:37,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:37,258 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions.
[2021-11-13 17:47:37,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1747 transitions.
[2021-11-13 17:47:37,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:37,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4868085106382978) internal successors, (1747), 1174 states have internal predecessors, (1747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1747 transitions.
[2021-11-13 17:47:37,326 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions.
[2021-11-13 17:47:37,326 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1747 transitions.
[2021-11-13 17:47:37,326 INFO L425 BuchiCegarLoop]: ======== Iteration 6============
[2021-11-13 17:47:37,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1747 transitions.
[2021-11-13 17:47:37,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:37,338 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:37,340 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,341 INFO L791 eck$LassoCheckResult]: Stem: 12703#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12963#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12722#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12623#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 12373#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12374#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12881#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12913#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12905#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12906#L695-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12486#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12476#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12477#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12297#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12298#L951 assume !(0 == ~M_E~0); 12036#L951-2 assume !(0 == ~T1_E~0); 12037#L956-1 assume !(0 == ~T2_E~0); 12197#L961-1 assume !(0 == ~T3_E~0); 12638#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12639#L971-1 assume !(0 == ~T5_E~0); 12778#L976-1 assume !(0 == ~T6_E~0); 12749#L981-1 assume !(0 == ~T7_E~0); 12522#L986-1 assume !(0 == ~T8_E~0); 12250#L991-1 assume !(0 == ~T9_E~0); 12251#L996-1 assume !(0 == ~E_M~0); 12944#L1001-1 assume !(0 == ~E_1~0); 12701#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12702#L1011-1 assume !(0 == ~E_3~0); 12914#L1016-1 assume !(0 == ~E_4~0); 12927#L1021-1 assume !(0 == ~E_5~0); 11843#L1026-1 assume !(0 == ~E_6~0); 11844#L1031-1 assume !(0 == ~E_7~0); 12650#L1036-1 assume !(0 == ~E_8~0); 12646#L1041-1 assume !(0 == ~E_9~0); 12647#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12888#L472 assume 1 == ~m_pc~0; 12962#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12681#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12682#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12689#L1179 assume !(0 != activate_threads_~tmp~1#1); 11851#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11852#L491 assume 1 == ~t1_pc~0; 12698#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12348#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12644#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11821#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 11822#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11845#L510 assume !(1 == ~t2_pc~0); 11810#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11811#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12890#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12891#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12092#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12093#L529 assume 1 == ~t3_pc~0; 12443#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12444#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12855#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12937#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 12013#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12014#L548 assume !(1 == ~t4_pc~0); 11911#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11910#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12205#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11953#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 11954#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11898#L567 assume 1 == ~t5_pc~0; 11899#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11955#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12138#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12139#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 12876#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12024#L586 assume !(1 == ~t6_pc~0); 12025#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12098#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12959#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12975#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 12872#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12873#L605 assume 1 == ~t7_pc~0; 12852#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12502#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12642#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12643#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 12971#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12618#L624 assume !(1 == ~t8_pc~0); 12086#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12085#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12674#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12675#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 12860#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11866#L643 assume 1 == ~t9_pc~0; 11867#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12817#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12751#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12255#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 12256#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12068#L1059 assume !(1 == ~M_E~0); 12069#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12225#L1064-1 assume !(1 == ~T2_E~0); 12226#L1069-1 assume !(1 == ~T3_E~0); 12824#L1074-1 assume !(1 == ~T4_E~0); 12858#L1079-1 assume !(1 == ~T5_E~0); 12850#L1084-1 assume !(1 == ~T6_E~0); 12851#L1089-1 assume !(1 == ~T7_E~0); 12868#L1094-1 assume !(1 == ~T8_E~0); 12551#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12552#L1104-1 assume !(1 == ~E_M~0); 12737#L1109-1 assume !(1 == ~E_1~0); 12366#L1114-1 assume !(1 == ~E_2~0); 12367#L1119-1 assume !(1 == ~E_3~0); 12419#L1124-1 assume !(1 == ~E_4~0); 11862#L1129-1 assume !(1 == ~E_5~0); 11863#L1134-1 assume !(1 == ~E_6~0); 12193#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 12194#L1144-1 assume !(1 == ~E_8~0); 12379#L1149-1 assume !(1 == ~E_9~0); 12030#L1154-1 assume { :end_inline_reset_delta_events } true; 12031#L1440-2
[2021-11-13 17:47:37,342 INFO L793 eck$LassoCheckResult]: Loop: 12031#L1440-2 assume !false; 12160#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11802#L926 assume !false; 12421#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12422#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12117#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12118#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12125#L795 assume !(0 != eval_~tmp~0#1); 12126#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12546#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12282#L951-3 assume !(0 == ~M_E~0); 12283#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12786#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12622#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12402#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12403#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12676#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11882#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11883#L986-3 assume !(0 == ~T8_E~0); 11864#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11865#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12772#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12377#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12378#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12794#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12829#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12569#L1026-3 assume !(0 == ~E_6~0); 12570#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12766#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12767#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12822#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12784#L472-33 assume 1 == ~m_pc~0; 12785#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11984#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11819#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11820#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12410#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12411#L491-33 assume 1 == ~t1_pc~0; 12690#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11918#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12935#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12954#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12955#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12743#L510-33 assume !(1 == ~t2_pc~0); 12738#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 12739#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12640#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12641#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11803#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11804#L529-33 assume 1 == ~t3_pc~0; 11831#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11832#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12105#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12931#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 11934#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11935#L548-33 assume 1 == ~t4_pc~0; 12176#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12299#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12337#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12338#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12115#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12116#L567-33 assume 1 == ~t5_pc~0; 12536#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12221#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12453#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12936#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12966#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12637#L586-33 assume 1 == ~t6_pc~0; 12610#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12240#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12565#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12566#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12132#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12133#L605-33 assume !(1 == ~t7_pc~0); 12309#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 12060#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12061#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12458#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11946#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11947#L624-33 assume 1 == ~t8_pc~0; 12103#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12112#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12080#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12081#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12322#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12062#L643-33 assume !(1 == ~t9_pc~0); 12064#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 12148#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12594#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12547#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12548#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11936#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11937#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12433#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12484#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12485#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12750#L1079-3 assume !(1 == ~T5_E~0); 12653#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12592#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12593#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12515#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12516#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12773#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12755#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12756#L1119-3 assume !(1 == ~E_3~0); 12967#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12970#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12233#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12234#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12397#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12398#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12553#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12973#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11941#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11823#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 11824#L1459 assume !(0 == start_simulation_~tmp~3#1); 11830#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12831#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12120#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 12661#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 12280#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12281#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12437#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 12614#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 12031#L1440-2
[2021-11-13 17:47:37,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,343 INFO L85 PathProgramCache]: Analyzing trace with hash -218070391, now seen corresponding path program 1 times
[2021-11-13 17:47:37,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317669175]
[2021-11-13 17:47:37,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,399 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317669175]
[2021-11-13 17:47:37,400 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317669175] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879981917]
[2021-11-13 17:47:37,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,401 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:37,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,402 INFO L85 PathProgramCache]: Analyzing trace with hash 1265732613, now seen corresponding path program 1 times
[2021-11-13 17:47:37,403 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,409 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405437265]
[2021-11-13 17:47:37,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,476 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,476 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405437265]
[2021-11-13 17:47:37,477 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405437265] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,477 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701529299]
[2021-11-13 17:47:37,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,480 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:37,480 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:37,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:37,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:37,482 INFO L87 Difference]: Start difference. First operand 1175 states and 1747 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:37,523 INFO L93 Difference]: Finished difference Result 1175 states and 1746 transitions.
[2021-11-13 17:47:37,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:37,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1746 transitions.
[2021-11-13 17:47:37,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,549 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1746 transitions.
[2021-11-13 17:47:37,549 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:37,550 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:37,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1746 transitions.
[2021-11-13 17:47:37,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:37,553 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions.
[2021-11-13 17:47:37,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1746 transitions.
[2021-11-13 17:47:37,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:37,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4859574468085106) internal successors, (1746), 1174 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1746 transitions.
[2021-11-13 17:47:37,589 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions.
[2021-11-13 17:47:37,589 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1746 transitions.
[2021-11-13 17:47:37,589 INFO L425 BuchiCegarLoop]: ======== Iteration 7============
[2021-11-13 17:47:37,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1746 transitions.
[2021-11-13 17:47:37,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:37,599 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:37,601 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,601 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,602 INFO L791 eck$LassoCheckResult]: Stem: 15060#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 15061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15320#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15079#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14980#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 14730#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14731#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15238#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15270#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15262#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15263#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14843#L700-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14833#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14834#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14654#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14655#L951 assume !(0 == ~M_E~0); 14393#L951-2 assume !(0 == ~T1_E~0); 14394#L956-1 assume !(0 == ~T2_E~0); 14554#L961-1 assume !(0 == ~T3_E~0); 14995#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14996#L971-1 assume !(0 == ~T5_E~0); 15135#L976-1 assume !(0 == ~T6_E~0); 15106#L981-1 assume !(0 == ~T7_E~0); 14879#L986-1 assume !(0 == ~T8_E~0); 14607#L991-1 assume !(0 == ~T9_E~0); 14608#L996-1 assume !(0 == ~E_M~0); 15301#L1001-1 assume !(0 == ~E_1~0); 15058#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15059#L1011-1 assume !(0 == ~E_3~0); 15271#L1016-1 assume !(0 == ~E_4~0); 15284#L1021-1 assume !(0 == ~E_5~0); 14200#L1026-1 assume !(0 == ~E_6~0); 14201#L1031-1 assume !(0 == ~E_7~0); 15007#L1036-1 assume !(0 == ~E_8~0); 15003#L1041-1 assume !(0 == ~E_9~0); 15004#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15245#L472 assume 1 == ~m_pc~0; 15319#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15038#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15039#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15046#L1179 assume !(0 != activate_threads_~tmp~1#1); 14208#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14209#L491 assume 1 == ~t1_pc~0; 15055#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14705#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15001#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14178#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 14179#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14202#L510 assume !(1 == ~t2_pc~0); 14167#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14168#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15247#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15248#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14449#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14450#L529 assume 1 == ~t3_pc~0; 14800#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14801#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15212#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15294#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 14370#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14371#L548 assume !(1 == ~t4_pc~0); 14268#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14267#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14562#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14310#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 14311#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14255#L567 assume 1 == ~t5_pc~0; 14256#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14312#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14495#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14496#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 15233#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14381#L586 assume !(1 == ~t6_pc~0); 14382#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14455#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15316#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15332#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 15229#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15230#L605 assume 1 == ~t7_pc~0; 15209#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14859#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14999#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15000#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 15328#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14975#L624 assume !(1 == ~t8_pc~0); 14443#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 14442#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15031#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15032#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 15217#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14223#L643 assume 1 == ~t9_pc~0; 14224#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15174#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15108#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14612#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 14613#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14425#L1059 assume !(1 == ~M_E~0); 14426#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14582#L1064-1 assume !(1 == ~T2_E~0); 14583#L1069-1 assume !(1 == ~T3_E~0); 15181#L1074-1 assume !(1 == ~T4_E~0); 15215#L1079-1 assume !(1 == ~T5_E~0); 15207#L1084-1 assume !(1 == ~T6_E~0); 15208#L1089-1 assume !(1 == ~T7_E~0); 15225#L1094-1 assume !(1 == ~T8_E~0); 14908#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14909#L1104-1 assume !(1 == ~E_M~0); 15094#L1109-1 assume !(1 == ~E_1~0); 14723#L1114-1 assume !(1 == ~E_2~0); 14724#L1119-1 assume !(1 == ~E_3~0); 14776#L1124-1 assume !(1 == ~E_4~0); 14219#L1129-1 assume !(1 == ~E_5~0); 14220#L1134-1 assume !(1 == ~E_6~0); 14550#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14551#L1144-1 assume !(1 == ~E_8~0); 14736#L1149-1 assume !(1 == ~E_9~0); 14387#L1154-1 assume { :end_inline_reset_delta_events } true; 14388#L1440-2
[2021-11-13 17:47:37,602 INFO L793 eck$LassoCheckResult]: Loop: 14388#L1440-2 assume !false; 14517#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14159#L926 assume !false; 14778#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14779#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14474#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14475#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 14482#L795 assume !(0 != eval_~tmp~0#1); 14483#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14903#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14639#L951-3 assume !(0 == ~M_E~0); 14640#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15143#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14979#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14759#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14760#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15033#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14239#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14240#L986-3 assume !(0 == ~T8_E~0); 14221#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14222#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15129#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14734#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14735#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15151#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15186#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14926#L1026-3 assume !(0 == ~E_6~0); 14927#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15123#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15124#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15179#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15141#L472-33 assume !(1 == ~m_pc~0); 14340#L472-35 is_master_triggered_~__retres1~0#1 := 0; 14341#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14176#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14177#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14767#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14768#L491-33 assume !(1 == ~t1_pc~0); 14274#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 14275#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15292#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15311#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15312#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15100#L510-33 assume !(1 == ~t2_pc~0); 15095#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15096#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14997#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14998#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14160#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14161#L529-33 assume 1 == ~t3_pc~0; 14188#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14189#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14462#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15288#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 14291#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14292#L548-33 assume 1 == ~t4_pc~0; 14533#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14656#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14694#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14695#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14472#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14473#L567-33 assume !(1 == ~t5_pc~0); 14577#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 14578#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15293#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15323#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14994#L586-33 assume !(1 == ~t6_pc~0); 14596#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 14597#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14922#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14923#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14489#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14490#L605-33 assume !(1 == ~t7_pc~0); 14666#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 14417#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14418#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14815#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14303#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14304#L624-33 assume 1 == ~t8_pc~0; 14460#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14469#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14437#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14438#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14679#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14419#L643-33 assume 1 == ~t9_pc~0; 14420#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14505#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14951#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14904#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14905#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14293#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14294#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14790#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14841#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14842#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15107#L1079-3 assume !(1 == ~T5_E~0); 15010#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14949#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14950#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14872#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14873#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15130#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15112#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15113#L1119-3 assume !(1 == ~E_3~0); 15324#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15327#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14590#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14591#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14754#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14755#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14910#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15330#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14298#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 14180#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14181#L1459 assume !(0 == start_simulation_~tmp~3#1); 14187#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15188#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14477#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15018#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 14637#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14638#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14794#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14971#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 14388#L1440-2
[2021-11-13 17:47:37,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1923790087, now seen corresponding path program 1 times
[2021-11-13 17:47:37,603 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,603 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515827194]
[2021-11-13 17:47:37,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,604 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,635 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,636 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515827194]
[2021-11-13 17:47:37,636 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515827194] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,636 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,636 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,636 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738180979]
[2021-11-13 17:47:37,637 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,637 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:37,638 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,638 INFO L85 PathProgramCache]: Analyzing trace with hash -1623165560, now seen corresponding path program 2 times
[2021-11-13 17:47:37,638 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,638 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522570653]
[2021-11-13 17:47:37,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,639 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,691 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522570653]
[2021-11-13 17:47:37,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522570653] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,692 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [611333711]
[2021-11-13 17:47:37,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,693 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:37,693 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:37,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:37,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:37,694 INFO L87 Difference]: Start difference. First operand 1175 states and 1746 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:37,730 INFO L93 Difference]: Finished difference Result 1175 states and 1745 transitions.
[2021-11-13 17:47:37,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:37,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1745 transitions.
[2021-11-13 17:47:37,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1745 transitions.
[2021-11-13 17:47:37,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:37,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:37,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1745 transitions.
[2021-11-13 17:47:37,759 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:37,759 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions.
[2021-11-13 17:47:37,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1745 transitions.
[2021-11-13 17:47:37,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:37,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4851063829787234) internal successors, (1745), 1174 states have internal predecessors, (1745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1745 transitions.
[2021-11-13 17:47:37,791 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions.
[2021-11-13 17:47:37,791 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1745 transitions.
[2021-11-13 17:47:37,791 INFO L425 BuchiCegarLoop]: ======== Iteration 8============
[2021-11-13 17:47:37,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1745 transitions.
[2021-11-13 17:47:37,801 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:37,801 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:37,803 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,804 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:37,804 INFO L791 eck$LassoCheckResult]: Stem: 17417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17418#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17677#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17436#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17337#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 17087#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17088#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17595#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17627#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17619#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17620#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17200#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17190#L705-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17191#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17011#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17012#L951 assume !(0 == ~M_E~0); 16750#L951-2 assume !(0 == ~T1_E~0); 16751#L956-1 assume !(0 == ~T2_E~0); 16911#L961-1 assume !(0 == ~T3_E~0); 17352#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17353#L971-1 assume !(0 == ~T5_E~0); 17492#L976-1 assume !(0 == ~T6_E~0); 17463#L981-1 assume !(0 == ~T7_E~0); 17236#L986-1 assume !(0 == ~T8_E~0); 16964#L991-1 assume !(0 == ~T9_E~0); 16965#L996-1 assume !(0 == ~E_M~0); 17658#L1001-1 assume !(0 == ~E_1~0); 17415#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17416#L1011-1 assume !(0 == ~E_3~0); 17628#L1016-1 assume !(0 == ~E_4~0); 17641#L1021-1 assume !(0 == ~E_5~0); 16557#L1026-1 assume !(0 == ~E_6~0); 16558#L1031-1 assume !(0 == ~E_7~0); 17364#L1036-1 assume !(0 == ~E_8~0); 17360#L1041-1 assume !(0 == ~E_9~0); 17361#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17602#L472 assume 1 == ~m_pc~0; 17676#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17395#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17396#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17403#L1179 assume !(0 != activate_threads_~tmp~1#1); 16565#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16566#L491 assume 1 == ~t1_pc~0; 17412#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17062#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17358#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16537#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 16538#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16559#L510 assume !(1 == ~t2_pc~0); 16524#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16525#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17605#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17606#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16806#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16807#L529 assume 1 == ~t3_pc~0; 17157#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17158#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17569#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17651#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 16727#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16728#L548 assume !(1 == ~t4_pc~0); 16625#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16624#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16919#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16667#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 16668#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16612#L567 assume 1 == ~t5_pc~0; 16613#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16669#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16852#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16853#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 17590#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16738#L586 assume !(1 == ~t6_pc~0); 16739#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16812#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17673#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17689#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 17586#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17587#L605 assume 1 == ~t7_pc~0; 17566#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17216#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17356#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17357#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 17685#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17332#L624 assume !(1 == ~t8_pc~0); 16800#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16799#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17388#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17389#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 17574#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16580#L643 assume 1 == ~t9_pc~0; 16581#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17531#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17465#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16971#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 16972#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1059 assume !(1 == ~M_E~0); 16783#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16939#L1064-1 assume !(1 == ~T2_E~0); 16940#L1069-1 assume !(1 == ~T3_E~0); 17538#L1074-1 assume !(1 == ~T4_E~0); 17572#L1079-1 assume !(1 == ~T5_E~0); 17564#L1084-1 assume !(1 == ~T6_E~0); 17565#L1089-1 assume !(1 == ~T7_E~0); 17582#L1094-1 assume !(1 == ~T8_E~0); 17265#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17266#L1104-1 assume !(1 == ~E_M~0); 17451#L1109-1 assume !(1 == ~E_1~0); 17080#L1114-1 assume !(1 == ~E_2~0); 17081#L1119-1 assume !(1 == ~E_3~0); 17133#L1124-1 assume !(1 == ~E_4~0); 16576#L1129-1 assume !(1 == ~E_5~0); 16577#L1134-1 assume !(1 == ~E_6~0); 16907#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 16908#L1144-1 assume !(1 == ~E_8~0); 17095#L1149-1 assume !(1 == ~E_9~0); 16744#L1154-1 assume { :end_inline_reset_delta_events } true; 16745#L1440-2
[2021-11-13 17:47:37,804 INFO L793 eck$LassoCheckResult]: Loop: 16745#L1440-2 assume !false; 16874#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16516#L926 assume !false; 17135#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17136#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16834#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16835#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16840#L795 assume !(0 != eval_~tmp~0#1); 16841#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17260#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16996#L951-3 assume !(0 == ~M_E~0); 16997#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17500#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17336#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17117#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17118#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17390#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16598#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16599#L986-3 assume !(0 == ~T8_E~0); 16578#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16579#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17486#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17091#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17092#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17508#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17543#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17283#L1026-3 assume !(0 == ~E_6~0); 17284#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17480#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17481#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17536#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17498#L472-33 assume !(1 == ~m_pc~0); 16697#L472-35 is_master_triggered_~__retres1~0#1 := 0; 16698#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16533#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16534#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17124#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17125#L491-33 assume !(1 == ~t1_pc~0); 16631#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16632#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17649#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17668#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17669#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17457#L510-33 assume 1 == ~t2_pc~0; 17458#L511-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17453#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17354#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17355#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16517#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16518#L529-33 assume 1 == ~t3_pc~0; 16545#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16546#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16819#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17645#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 16648#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16649#L548-33 assume 1 == ~t4_pc~0; 16892#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17013#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17052#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16829#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16830#L567-33 assume 1 == ~t5_pc~0; 17250#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16935#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17168#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17650#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17681#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17351#L586-33 assume !(1 == ~t6_pc~0); 16953#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16954#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17279#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17280#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16846#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16847#L605-33 assume 1 == ~t7_pc~0; 17024#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16774#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16775#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17173#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16660#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16661#L624-33 assume 1 == ~t8_pc~0; 16817#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16826#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16794#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16795#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17036#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16776#L643-33 assume 1 == ~t9_pc~0; 16777#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16862#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17261#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17262#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16650#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16651#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17147#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17198#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17199#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17464#L1079-3 assume !(1 == ~T5_E~0); 17367#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17306#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17307#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17229#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17230#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17487#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17468#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17469#L1119-3 assume !(1 == ~E_3~0); 17680#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17684#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16947#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16948#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17106#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17107#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17267#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17687#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16653#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16535#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16536#L1459 assume !(0 == start_simulation_~tmp~3#1); 16544#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17544#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 16832#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17375#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 16994#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16995#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17148#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17327#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 16745#L1440-2
[2021-11-13 17:47:37,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1747895607, now seen corresponding path program 1 times
[2021-11-13 17:47:37,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,805 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317265373]
[2021-11-13 17:47:37,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,867 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,867 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317265373]
[2021-11-13 17:47:37,867 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317265373] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,868 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,869 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,869 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776370288]
[2021-11-13 17:47:37,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,870 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:37,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:37,870 INFO L85 PathProgramCache]: Analyzing trace with hash -1559246907, now seen corresponding path program 1 times
[2021-11-13 17:47:37,870 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:37,872 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264898938]
[2021-11-13 17:47:37,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:37,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:37,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:37,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:37,911 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:37,911 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264898938]
[2021-11-13 17:47:37,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264898938] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:37,912 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:37,912 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:37,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217395409]
[2021-11-13 17:47:37,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:37,913 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:37,913 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:37,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:37,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:37,914 INFO L87 Difference]: Start difference. First operand 1175 states and 1745 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:37,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:37,946 INFO L93 Difference]: Finished difference Result 1175 states and 1744 transitions.
[2021-11-13 17:47:37,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:37,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1744 transitions.
[2021-11-13 17:47:37,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:37,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1744 transitions.
[2021-11-13 17:47:37,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:37,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:37,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1744 transitions.
[2021-11-13 17:47:37,972 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:37,972 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions.
[2021-11-13 17:47:37,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1744 transitions.
[2021-11-13 17:47:37,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:37,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.4842553191489363) internal successors, (1744), 1174 states have internal predecessors, (1744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1744 transitions.
[2021-11-13 17:47:38,002 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions.
[2021-11-13 17:47:38,002 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1744 transitions.
[2021-11-13 17:47:38,002 INFO L425 BuchiCegarLoop]: ======== Iteration 9============
[2021-11-13 17:47:38,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1744 transitions.
[2021-11-13 17:47:38,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:38,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:38,008 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:38,010 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,011 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,011 INFO L791 eck$LassoCheckResult]: Stem: 19774#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20034#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19793#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19694#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 19444#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19445#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19952#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19984#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19976#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19977#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19557#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19547#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19548#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19368#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19369#L951 assume !(0 == ~M_E~0); 19107#L951-2 assume !(0 == ~T1_E~0); 19108#L956-1 assume !(0 == ~T2_E~0); 19268#L961-1 assume !(0 == ~T3_E~0); 19709#L966-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19710#L971-1 assume !(0 == ~T5_E~0); 19849#L976-1 assume !(0 == ~T6_E~0); 19820#L981-1 assume !(0 == ~T7_E~0); 19593#L986-1 assume !(0 == ~T8_E~0); 19321#L991-1 assume !(0 == ~T9_E~0); 19322#L996-1 assume !(0 == ~E_M~0); 20016#L1001-1 assume !(0 == ~E_1~0); 19772#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 19773#L1011-1 assume !(0 == ~E_3~0); 19986#L1016-1 assume !(0 == ~E_4~0); 19998#L1021-1 assume !(0 == ~E_5~0); 18914#L1026-1 assume !(0 == ~E_6~0); 18915#L1031-1 assume !(0 == ~E_7~0); 19723#L1036-1 assume !(0 == ~E_8~0); 19717#L1041-1 assume !(0 == ~E_9~0); 19718#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19959#L472 assume 1 == ~m_pc~0; 20033#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19752#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19753#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19760#L1179 assume !(0 != activate_threads_~tmp~1#1); 18922#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18923#L491 assume 1 == ~t1_pc~0; 19769#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19419#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19715#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18894#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 18895#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18918#L510 assume !(1 == ~t2_pc~0); 18881#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18882#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19962#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19963#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19163#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19164#L529 assume 1 == ~t3_pc~0; 19514#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19515#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19926#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20008#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 19084#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19085#L548 assume !(1 == ~t4_pc~0); 18982#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18981#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19276#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19026#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 19027#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18969#L567 assume 1 == ~t5_pc~0; 18970#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19028#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19209#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19210#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 19947#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19095#L586 assume !(1 == ~t6_pc~0); 19096#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19169#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20030#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20046#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 19943#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19944#L605 assume 1 == ~t7_pc~0; 19923#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19577#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19713#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19714#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 20042#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19689#L624 assume !(1 == ~t8_pc~0); 19157#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19156#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19745#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19746#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 19931#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18937#L643 assume 1 == ~t9_pc~0; 18938#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19888#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19822#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19328#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 19329#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19139#L1059 assume !(1 == ~M_E~0); 19140#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19296#L1064-1 assume !(1 == ~T2_E~0); 19297#L1069-1 assume !(1 == ~T3_E~0); 19895#L1074-1 assume !(1 == ~T4_E~0); 19929#L1079-1 assume !(1 == ~T5_E~0); 19921#L1084-1 assume !(1 == ~T6_E~0); 19922#L1089-1 assume !(1 == ~T7_E~0); 19939#L1094-1 assume !(1 == ~T8_E~0); 19622#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19623#L1104-1 assume !(1 == ~E_M~0); 19808#L1109-1 assume !(1 == ~E_1~0); 19437#L1114-1 assume !(1 == ~E_2~0); 19438#L1119-1 assume !(1 == ~E_3~0); 19490#L1124-1 assume !(1 == ~E_4~0); 18933#L1129-1 assume !(1 == ~E_5~0); 18934#L1134-1 assume !(1 == ~E_6~0); 19264#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19265#L1144-1 assume !(1 == ~E_8~0); 19452#L1149-1 assume !(1 == ~E_9~0); 19101#L1154-1 assume { :end_inline_reset_delta_events } true; 19102#L1440-2
[2021-11-13 17:47:38,011 INFO L793 eck$LassoCheckResult]: Loop: 19102#L1440-2 assume !false; 19231#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18873#L926 assume !false; 19492#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19493#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19191#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19192#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 19197#L795 assume !(0 != eval_~tmp~0#1); 19198#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19617#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19353#L951-3 assume !(0 == ~M_E~0); 19354#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19857#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19693#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19477#L966-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19478#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19747#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18955#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18956#L986-3 assume !(0 == ~T8_E~0); 18935#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18936#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19843#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19448#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19449#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19865#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19900#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19641#L1026-3 assume !(0 == ~E_6~0); 19642#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19837#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19838#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19893#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19855#L472-33 assume 1 == ~m_pc~0; 19856#L473-11 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19055#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18890#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18891#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19481#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19482#L491-33 assume 1 == ~t1_pc~0; 19761#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18989#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20007#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20025#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20026#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19814#L510-33 assume !(1 == ~t2_pc~0); 19809#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 19810#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19711#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19712#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18874#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18875#L529-33 assume 1 == ~t3_pc~0; 18902#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18903#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19176#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20002#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 19005#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19006#L548-33 assume 1 == ~t4_pc~0; 19249#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19370#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19408#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19409#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19186#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19187#L567-33 assume 1 == ~t5_pc~0; 19606#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19289#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19524#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20006#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20037#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19708#L586-33 assume 1 == ~t6_pc~0; 19681#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19310#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19634#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19635#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19203#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19204#L605-33 assume !(1 == ~t7_pc~0); 19380#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 19124#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19125#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19529#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19017#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19018#L624-33 assume 1 == ~t8_pc~0; 19174#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19183#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19151#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19152#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19393#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19126#L643-33 assume 1 == ~t9_pc~0; 19127#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19219#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19665#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19618#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19619#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19007#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19008#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19504#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19554#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19555#L1074-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19821#L1079-3 assume !(1 == ~T5_E~0); 19724#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19663#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19664#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19586#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19587#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19844#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19825#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19826#L1119-3 assume !(1 == ~E_3~0); 20038#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20041#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19304#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19305#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19463#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19464#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19624#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20044#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19010#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18892#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 18893#L1459 assume !(0 == start_simulation_~tmp~3#1); 18901#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19901#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19189#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19732#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19351#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19352#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19505#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 19685#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 19102#L1440-2
[2021-11-13 17:47:38,012 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,012 INFO L85 PathProgramCache]: Analyzing trace with hash -1866337081, now seen corresponding path program 1 times
[2021-11-13 17:47:38,012 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,012 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588260680]
[2021-11-13 17:47:38,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,013 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,057 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,057 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1588260680]
[2021-11-13 17:47:38,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1588260680] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,057 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:38,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583078589]
[2021-11-13 17:47:38,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,058 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:38,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,058 INFO L85 PathProgramCache]: Analyzing trace with hash -2072306300, now seen corresponding path program 1 times
[2021-11-13 17:47:38,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,059 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648293830]
[2021-11-13 17:47:38,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,101 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648293830]
[2021-11-13 17:47:38,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648293830] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,101 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:38,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663911588]
[2021-11-13 17:47:38,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,102 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:38,102 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:38,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:38,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:38,103 INFO L87 Difference]: Start difference. First operand 1175 states and 1744 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:38,140 INFO L93 Difference]: Finished difference Result 1175 states and 1739 transitions.
[2021-11-13 17:47:38,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:38,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1739 transitions.
[2021-11-13 17:47:38,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:38,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1739 transitions.
[2021-11-13 17:47:38,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:38,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:38,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1739 transitions.
[2021-11-13 17:47:38,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:38,164 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1739 transitions.
[2021-11-13 17:47:38,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1739 transitions.
[2021-11-13 17:47:38,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:38,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.48) internal successors, (1739), 1174 states have internal predecessors, (1739), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1739 transitions.
[2021-11-13 17:47:38,192 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1739 transitions.
[2021-11-13 17:47:38,192 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1739 transitions.
[2021-11-13 17:47:38,192 INFO L425 BuchiCegarLoop]: ======== Iteration 10============
[2021-11-13 17:47:38,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1739 transitions.
[2021-11-13 17:47:38,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:38,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:38,198 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:38,200 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,200 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,201 INFO L791 eck$LassoCheckResult]: Stem: 22131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22391#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22152#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22051#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 21801#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21802#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22309#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22341#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22333#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22334#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21914#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21904#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21905#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21726#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21727#L951 assume !(0 == ~M_E~0); 21468#L951-2 assume !(0 == ~T1_E~0); 21469#L956-1 assume !(0 == ~T2_E~0); 21625#L961-1 assume !(0 == ~T3_E~0); 22066#L966-1 assume !(0 == ~T4_E~0); 22067#L971-1 assume !(0 == ~T5_E~0); 22206#L976-1 assume !(0 == ~T6_E~0); 22177#L981-1 assume !(0 == ~T7_E~0); 21953#L986-1 assume !(0 == ~T8_E~0); 21678#L991-1 assume !(0 == ~T9_E~0); 21679#L996-1 assume !(0 == ~E_M~0); 22373#L1001-1 assume !(0 == ~E_1~0); 22129#L1006-1 assume 0 == ~E_2~0;~E_2~0 := 1; 22130#L1011-1 assume !(0 == ~E_3~0); 22343#L1016-1 assume !(0 == ~E_4~0); 22355#L1021-1 assume !(0 == ~E_5~0); 21271#L1026-1 assume !(0 == ~E_6~0); 21272#L1031-1 assume !(0 == ~E_7~0); 22080#L1036-1 assume !(0 == ~E_8~0); 22076#L1041-1 assume !(0 == ~E_9~0); 22077#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22316#L472 assume 1 == ~m_pc~0; 22390#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22109#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22110#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22117#L1179 assume !(0 != activate_threads_~tmp~1#1); 21279#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21280#L491 assume 1 == ~t1_pc~0; 22126#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21778#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22072#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21251#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 21252#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21275#L510 assume !(1 == ~t2_pc~0); 21238#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21239#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22319#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22320#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21520#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21521#L529 assume 1 == ~t3_pc~0; 21871#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21872#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22283#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22365#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 21441#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21442#L548 assume !(1 == ~t4_pc~0); 21339#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21338#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21635#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21383#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 21384#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21331#L567 assume 1 == ~t5_pc~0; 21332#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21385#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21569#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21570#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 22304#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21452#L586 assume !(1 == ~t6_pc~0); 21453#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21528#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22387#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22403#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 22300#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22301#L605 assume 1 == ~t7_pc~0; 22280#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21935#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22070#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22071#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 22399#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22046#L624 assume !(1 == ~t8_pc~0); 21514#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 21513#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22102#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22103#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 22288#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21296#L643 assume 1 == ~t9_pc~0; 21297#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22245#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22180#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21685#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 21686#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21496#L1059 assume !(1 == ~M_E~0); 21497#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21653#L1064-1 assume !(1 == ~T2_E~0); 21654#L1069-1 assume !(1 == ~T3_E~0); 22252#L1074-1 assume !(1 == ~T4_E~0); 22287#L1079-1 assume !(1 == ~T5_E~0); 22278#L1084-1 assume !(1 == ~T6_E~0); 22279#L1089-1 assume !(1 == ~T7_E~0); 22296#L1094-1 assume !(1 == ~T8_E~0); 21979#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21980#L1104-1 assume !(1 == ~E_M~0); 22167#L1109-1 assume !(1 == ~E_1~0); 21794#L1114-1 assume !(1 == ~E_2~0); 21795#L1119-1 assume !(1 == ~E_3~0); 21848#L1124-1 assume !(1 == ~E_4~0); 21290#L1129-1 assume !(1 == ~E_5~0); 21291#L1134-1 assume !(1 == ~E_6~0); 21621#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21622#L1144-1 assume !(1 == ~E_8~0); 21809#L1149-1 assume !(1 == ~E_9~0); 21458#L1154-1 assume { :end_inline_reset_delta_events } true; 21459#L1440-2
[2021-11-13 17:47:38,201 INFO L793 eck$LassoCheckResult]: Loop: 21459#L1440-2 assume !false; 21590#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21230#L926 assume !false; 21849#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 21850#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21548#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21549#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 21554#L795 assume !(0 != eval_~tmp~0#1); 21555#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21974#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21712#L951-3 assume !(0 == ~M_E~0); 21713#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22214#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22050#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21834#L966-3 assume !(0 == ~T4_E~0); 21835#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22104#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21312#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21313#L986-3 assume !(0 == ~T8_E~0); 21292#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21293#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22200#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21805#L1006-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21806#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22222#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22257#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21998#L1026-3 assume !(0 == ~E_6~0); 21999#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22194#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22195#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22250#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22212#L472-33 assume !(1 == ~m_pc~0); 21411#L472-35 is_master_triggered_~__retres1~0#1 := 0; 21412#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21242#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21243#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21838#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21839#L491-33 assume 1 == ~t1_pc~0; 22118#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21343#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22363#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22382#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22383#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22168#L510-33 assume !(1 == ~t2_pc~0); 22165#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 22166#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22068#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22069#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21231#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21232#L529-33 assume 1 == ~t3_pc~0; 21259#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21260#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21533#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22359#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 21362#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21363#L548-33 assume 1 == ~t4_pc~0; 21604#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21725#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21765#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21766#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21543#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21544#L567-33 assume !(1 == ~t5_pc~0); 21648#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 21649#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21881#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22364#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22394#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22065#L586-33 assume !(1 == ~t6_pc~0); 21667#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21668#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21991#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21992#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21560#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21561#L605-33 assume !(1 == ~t7_pc~0); 21737#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 21484#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21485#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21886#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21374#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21375#L624-33 assume 1 == ~t8_pc~0; 21531#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21540#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21508#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21509#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21750#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21486#L643-33 assume !(1 == ~t9_pc~0); 21488#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 21576#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22022#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21975#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21976#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21364#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21365#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21861#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21911#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21912#L1074-3 assume !(1 == ~T4_E~0); 22178#L1079-3 assume !(1 == ~T5_E~0); 22081#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22020#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22021#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21943#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21944#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22201#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22182#L1114-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22183#L1119-3 assume !(1 == ~E_3~0); 22395#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22398#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21661#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21662#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21823#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21824#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21981#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22401#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21367#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21249#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 21250#L1459 assume !(0 == start_simulation_~tmp~3#1); 21258#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22258#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21546#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22089#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 21708#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21709#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21863#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 22042#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 21459#L1440-2
[2021-11-13 17:47:38,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,202 INFO L85 PathProgramCache]: Analyzing trace with hash 522226949, now seen corresponding path program 1 times
[2021-11-13 17:47:38,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,202 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989472592]
[2021-11-13 17:47:38,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,203 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,235 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,235 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989472592]
[2021-11-13 17:47:38,236 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1989472592] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,236 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,236 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:38,236 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634585638]
[2021-11-13 17:47:38,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,237 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:38,237 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1840001080, now seen corresponding path program 1 times
[2021-11-13 17:47:38,237 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,237 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008124276]
[2021-11-13 17:47:38,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,238 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,280 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008124276]
[2021-11-13 17:47:38,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008124276] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,280 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,280 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:38,281 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65623187]
[2021-11-13 17:47:38,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,281 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:38,281 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:38,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:38,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:38,282 INFO L87 Difference]: Start difference. First operand 1175 states and 1739 transitions. cyclomatic complexity: 565 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:38,377 INFO L93 Difference]: Finished difference Result 1175 states and 1722 transitions.
[2021-11-13 17:47:38,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:38,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1722 transitions.
[2021-11-13 17:47:38,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:38,397 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1722 transitions.
[2021-11-13 17:47:38,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175
[2021-11-13 17:47:38,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175
[2021-11-13 17:47:38,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1722 transitions.
[2021-11-13 17:47:38,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:38,401 INFO L681 BuchiCegarLoop]: Abstraction has 1175 states and 1722 transitions.
[2021-11-13 17:47:38,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1722 transitions.
[2021-11-13 17:47:38,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175.
[2021-11-13 17:47:38,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.465531914893617) internal successors, (1722), 1174 states have internal predecessors, (1722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1722 transitions.
[2021-11-13 17:47:38,427 INFO L704 BuchiCegarLoop]: Abstraction has 1175 states and 1722 transitions.
[2021-11-13 17:47:38,427 INFO L587 BuchiCegarLoop]: Abstraction has 1175 states and 1722 transitions.
[2021-11-13 17:47:38,427 INFO L425 BuchiCegarLoop]: ======== Iteration 11============
[2021-11-13 17:47:38,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1722 transitions.
[2021-11-13 17:47:38,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1048
[2021-11-13 17:47:38,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:38,433 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:38,435 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,435 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,435 INFO L791 eck$LassoCheckResult]: Stem: 24487#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 24488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 24749#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24508#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24407#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 24159#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24160#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24666#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24698#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24690#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24691#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24270#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24260#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24261#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24082#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24083#L951 assume !(0 == ~M_E~0); 23824#L951-2 assume !(0 == ~T1_E~0); 23825#L956-1 assume !(0 == ~T2_E~0); 23981#L961-1 assume !(0 == ~T3_E~0); 24422#L966-1 assume !(0 == ~T4_E~0); 24423#L971-1 assume !(0 == ~T5_E~0); 24562#L976-1 assume !(0 == ~T6_E~0); 24533#L981-1 assume !(0 == ~T7_E~0); 24310#L986-1 assume !(0 == ~T8_E~0); 24034#L991-1 assume !(0 == ~T9_E~0); 24035#L996-1 assume !(0 == ~E_M~0); 24730#L1001-1 assume !(0 == ~E_1~0); 24485#L1006-1 assume !(0 == ~E_2~0); 24486#L1011-1 assume !(0 == ~E_3~0); 24701#L1016-1 assume !(0 == ~E_4~0); 24712#L1021-1 assume !(0 == ~E_5~0); 23627#L1026-1 assume !(0 == ~E_6~0); 23628#L1031-1 assume !(0 == ~E_7~0); 24436#L1036-1 assume !(0 == ~E_8~0); 24432#L1041-1 assume !(0 == ~E_9~0); 24433#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24673#L472 assume 1 == ~m_pc~0; 24747#L473 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 24465#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24466#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24473#L1179 assume !(0 != activate_threads_~tmp~1#1); 23635#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23636#L491 assume 1 == ~t1_pc~0; 24484#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24134#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24428#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23608#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 23609#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23631#L510 assume !(1 == ~t2_pc~0); 23595#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23596#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24676#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24677#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23876#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23877#L529 assume 1 == ~t3_pc~0; 24227#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24228#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24640#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24722#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 23797#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23798#L548 assume !(1 == ~t4_pc~0); 23696#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23695#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23991#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23740#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 23741#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23688#L567 assume 1 == ~t5_pc~0; 23689#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23742#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23925#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23926#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 24661#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23808#L586 assume !(1 == ~t6_pc~0); 23809#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23884#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24744#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24760#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 24657#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24658#L605 assume 1 == ~t7_pc~0; 24638#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24294#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24426#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24427#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 24756#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24402#L624 assume !(1 == ~t8_pc~0); 23870#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23869#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24459#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24460#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 24645#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23652#L643 assume 1 == ~t9_pc~0; 23653#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24603#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24536#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24041#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 24042#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23852#L1059 assume !(1 == ~M_E~0); 23853#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24009#L1064-1 assume !(1 == ~T2_E~0); 24010#L1069-1 assume !(1 == ~T3_E~0); 24609#L1074-1 assume !(1 == ~T4_E~0); 24644#L1079-1 assume !(1 == ~T5_E~0); 24635#L1084-1 assume !(1 == ~T6_E~0); 24636#L1089-1 assume !(1 == ~T7_E~0); 24653#L1094-1 assume !(1 == ~T8_E~0); 24335#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24336#L1104-1 assume !(1 == ~E_M~0); 24521#L1109-1 assume !(1 == ~E_1~0); 24150#L1114-1 assume !(1 == ~E_2~0); 24151#L1119-1 assume !(1 == ~E_3~0); 24203#L1124-1 assume !(1 == ~E_4~0); 23646#L1129-1 assume !(1 == ~E_5~0); 23647#L1134-1 assume !(1 == ~E_6~0); 23977#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23978#L1144-1 assume !(1 == ~E_8~0); 24163#L1149-1 assume !(1 == ~E_9~0); 23814#L1154-1 assume { :end_inline_reset_delta_events } true; 23815#L1440-2
[2021-11-13 17:47:38,436 INFO L793 eck$LassoCheckResult]: Loop: 23815#L1440-2 assume !false; 23944#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23587#L926 assume !false; 24205#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 24206#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23901#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23902#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 23909#L795 assume !(0 != eval_~tmp~0#1); 23910#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24330#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24066#L951-3 assume !(0 == ~M_E~0); 24067#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24571#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24406#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24186#L966-3 assume !(0 == ~T4_E~0); 24187#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24458#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23667#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23668#L986-3 assume !(0 == ~T8_E~0); 23648#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23649#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24556#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24161#L1006-3 assume !(0 == ~E_2~0); 24162#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24579#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24614#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24353#L1026-3 assume !(0 == ~E_6~0); 24354#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24550#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24551#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24607#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24569#L472-33 assume !(1 == ~m_pc~0); 23768#L472-35 is_master_triggered_~__retres1~0#1 := 0; 23769#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23604#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23605#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24194#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24195#L491-33 assume !(1 == ~t1_pc~0); 23702#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 23703#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24720#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24739#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24740#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24527#L510-33 assume !(1 == ~t2_pc~0); 24522#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 24523#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24424#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24425#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23588#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23589#L529-33 assume 1 == ~t3_pc~0; 23616#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23617#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23889#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24716#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 23719#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23720#L548-33 assume 1 == ~t4_pc~0; 23960#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24081#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24121#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24122#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23899#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23900#L567-33 assume 1 == ~t5_pc~0; 24321#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24005#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24237#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24721#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24751#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24421#L586-33 assume !(1 == ~t6_pc~0); 24023#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 24024#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24349#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24350#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23916#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23917#L605-33 assume !(1 == ~t7_pc~0); 24093#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 23843#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23844#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24242#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23731#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23732#L624-33 assume !(1 == ~t8_pc~0); 23888#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 23896#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23864#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23865#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24106#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23845#L643-33 assume 1 == ~t9_pc~0; 23846#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23932#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24378#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24331#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24332#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23721#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23722#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24217#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24268#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24269#L1074-3 assume !(1 == ~T4_E~0); 24534#L1079-3 assume !(1 == ~T5_E~0); 24437#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24376#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24377#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24299#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24300#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24557#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24539#L1114-3 assume !(1 == ~E_2~0); 24540#L1119-3 assume !(1 == ~E_3~0); 24752#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24755#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24017#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24018#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24181#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24182#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24337#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 24758#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23726#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23606#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23607#L1459 assume !(0 == start_simulation_~tmp~3#1); 23615#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 24616#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 23904#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24445#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 24064#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24065#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24221#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24398#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 23815#L1440-2
[2021-11-13 17:47:38,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,436 INFO L85 PathProgramCache]: Analyzing trace with hash -1895677117, now seen corresponding path program 1 times
[2021-11-13 17:47:38,436 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,437 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254793553]
[2021-11-13 17:47:38,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,437 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,479 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,479 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254793553]
[2021-11-13 17:47:38,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254793553] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,479 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:38,480 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674702561]
[2021-11-13 17:47:38,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,480 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:38,480 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,481 INFO L85 PathProgramCache]: Analyzing trace with hash -967758776, now seen corresponding path program 1 times
[2021-11-13 17:47:38,481 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,481 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063272259]
[2021-11-13 17:47:38,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,481 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,525 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063272259]
[2021-11-13 17:47:38,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063272259] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,525 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,525 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:38,526 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411303906]
[2021-11-13 17:47:38,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,526 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:38,526 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:38,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:38,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:38,527 INFO L87 Difference]: Start difference. First operand 1175 states and 1722 transitions. cyclomatic complexity: 548 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:38,639 INFO L93 Difference]: Finished difference Result 2202 states and 3197 transitions.
[2021-11-13 17:47:38,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:38,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2202 states and 3197 transitions.
[2021-11-13 17:47:38,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2075
[2021-11-13 17:47:38,675 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2202 states to 2202 states and 3197 transitions.
[2021-11-13 17:47:38,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2202
[2021-11-13 17:47:38,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2202
[2021-11-13 17:47:38,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2202 states and 3197 transitions.
[2021-11-13 17:47:38,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:38,682 INFO L681 BuchiCegarLoop]: Abstraction has 2202 states and 3197 transitions.
[2021-11-13 17:47:38,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2202 states and 3197 transitions.
[2021-11-13 17:47:38,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2202 to 2133.
[2021-11-13 17:47:38,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2133 states, 2133 states have (on average 1.453820909517112) internal successors, (3101), 2132 states have internal predecessors, (3101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:38,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2133 states to 2133 states and 3101 transitions.
[2021-11-13 17:47:38,736 INFO L704 BuchiCegarLoop]: Abstraction has 2133 states and 3101 transitions.
[2021-11-13 17:47:38,736 INFO L587 BuchiCegarLoop]: Abstraction has 2133 states and 3101 transitions.
[2021-11-13 17:47:38,736 INFO L425 BuchiCegarLoop]: ======== Iteration 12============
[2021-11-13 17:47:38,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2133 states and 3101 transitions.
[2021-11-13 17:47:38,747 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2006
[2021-11-13 17:47:38,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:38,747 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:38,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:38,749 INFO L791 eck$LassoCheckResult]: Stem: 27886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 27887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28162#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27906#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27805#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 27552#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27553#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28076#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28109#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28101#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28102#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27668#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27657#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27658#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27471#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27472#L951 assume !(0 == ~M_E~0); 27204#L951-2 assume !(0 == ~T1_E~0); 27205#L956-1 assume !(0 == ~T2_E~0); 27368#L961-1 assume !(0 == ~T3_E~0); 27820#L966-1 assume !(0 == ~T4_E~0); 27821#L971-1 assume !(0 == ~T5_E~0); 27962#L976-1 assume !(0 == ~T6_E~0); 27933#L981-1 assume !(0 == ~T7_E~0); 27705#L986-1 assume !(0 == ~T8_E~0); 27421#L991-1 assume !(0 == ~T9_E~0); 27422#L996-1 assume !(0 == ~E_M~0); 28144#L1001-1 assume !(0 == ~E_1~0); 27884#L1006-1 assume !(0 == ~E_2~0); 27885#L1011-1 assume !(0 == ~E_3~0); 28110#L1016-1 assume !(0 == ~E_4~0); 28124#L1021-1 assume !(0 == ~E_5~0); 27011#L1026-1 assume !(0 == ~E_6~0); 27012#L1031-1 assume !(0 == ~E_7~0); 27832#L1036-1 assume !(0 == ~E_8~0); 27828#L1041-1 assume !(0 == ~E_9~0); 27829#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28083#L472 assume !(1 == ~m_pc~0); 28049#L472-2 is_master_triggered_~__retres1~0#1 := 0; 27863#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27864#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27872#L1179 assume !(0 != activate_threads_~tmp~1#1); 27019#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27020#L491 assume 1 == ~t1_pc~0; 27881#L492 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27524#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27826#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26990#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 26991#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27013#L510 assume !(1 == ~t2_pc~0); 26979#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26980#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28085#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28086#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27259#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27260#L529 assume 1 == ~t3_pc~0; 27624#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27625#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28044#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28135#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 27181#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27182#L548 assume !(1 == ~t4_pc~0); 27079#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27078#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27376#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27121#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 27122#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27066#L567 assume 1 == ~t5_pc~0; 27067#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27123#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27305#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27306#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 28071#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27192#L586 assume !(1 == ~t6_pc~0); 27193#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27265#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28159#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28182#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 28067#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28068#L605 assume 1 == ~t7_pc~0; 28039#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27684#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27824#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27825#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 28172#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27800#L624 assume !(1 == ~t8_pc~0); 27253#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27252#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27856#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27857#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 28052#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27034#L643 assume 1 == ~t9_pc~0; 27035#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28003#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27935#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27426#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 27427#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27236#L1059 assume !(1 == ~M_E~0); 27237#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27396#L1064-1 assume !(1 == ~T2_E~0); 27397#L1069-1 assume !(1 == ~T3_E~0); 28011#L1074-1 assume !(1 == ~T4_E~0); 28050#L1079-1 assume !(1 == ~T5_E~0); 28037#L1084-1 assume !(1 == ~T6_E~0); 28038#L1089-1 assume !(1 == ~T7_E~0); 28063#L1094-1 assume !(1 == ~T8_E~0); 27734#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27735#L1104-1 assume !(1 == ~E_M~0); 27921#L1109-1 assume !(1 == ~E_1~0); 27542#L1114-1 assume !(1 == ~E_2~0); 27543#L1119-1 assume !(1 == ~E_3~0); 27600#L1124-1 assume !(1 == ~E_4~0); 27030#L1129-1 assume !(1 == ~E_5~0); 27031#L1134-1 assume !(1 == ~E_6~0); 27364#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27365#L1144-1 assume !(1 == ~E_8~0); 27559#L1149-1 assume !(1 == ~E_9~0); 27198#L1154-1 assume { :end_inline_reset_delta_events } true; 27199#L1440-2
[2021-11-13 17:47:38,750 INFO L793 eck$LassoCheckResult]: Loop: 27199#L1440-2 assume !false; 27329#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26971#L926 assume !false; 27602#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 27603#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27284#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27285#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 27292#L795 assume !(0 != eval_~tmp~0#1); 27293#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27728#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27455#L951-3 assume !(0 == ~M_E~0); 27456#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27972#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27804#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27583#L966-3 assume !(0 == ~T4_E~0); 27584#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27858#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27051#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27052#L986-3 assume !(0 == ~T8_E~0); 27032#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27033#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27956#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27557#L1006-3 assume !(0 == ~E_2~0); 27558#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27980#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28016#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27752#L1026-3 assume !(0 == ~E_6~0); 27753#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27951#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27952#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28008#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27970#L472-33 assume !(1 == ~m_pc~0); 27149#L472-35 is_master_triggered_~__retres1~0#1 := 0; 27150#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26988#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26989#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27591#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27592#L491-33 assume 1 == ~t1_pc~0; 27873#L492-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27086#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28133#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28154#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28155#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27927#L510-33 assume !(1 == ~t2_pc~0); 27922#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 27923#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27822#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27823#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26972#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26973#L529-33 assume 1 == ~t3_pc~0; 27000#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27001#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27272#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28128#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 27102#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27103#L548-33 assume 1 == ~t4_pc~0; 27345#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27473#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27513#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27514#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27282#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27283#L567-33 assume 1 == ~t5_pc~0; 27719#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27392#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27634#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28134#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28166#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27819#L586-33 assume 1 == ~t6_pc~0; 27792#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27411#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27748#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27749#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27299#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27300#L605-33 assume !(1 == ~t7_pc~0); 27485#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 27227#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27228#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27639#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27114#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27115#L624-33 assume 1 == ~t8_pc~0; 27270#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27279#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27247#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27248#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27498#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27229#L643-33 assume 1 == ~t9_pc~0; 27230#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27317#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27776#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27730#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27731#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27104#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27105#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27614#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27666#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27667#L1074-3 assume !(1 == ~T4_E~0); 27934#L1079-3 assume !(1 == ~T5_E~0); 27835#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27774#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27775#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28293#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28291#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28289#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28287#L1114-3 assume !(1 == ~E_2~0); 28276#L1119-3 assume !(1 == ~E_3~0); 28274#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28272#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28256#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28244#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28234#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28227#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28181#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28174#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27109#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26992#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 26993#L1459 assume !(0 == start_simulation_~tmp~3#1); 26999#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28018#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 27287#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 27843#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 27451#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27452#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27618#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 27796#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 27199#L1440-2
[2021-11-13 17:47:38,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,751 INFO L85 PathProgramCache]: Analyzing trace with hash -435683196, now seen corresponding path program 1 times
[2021-11-13 17:47:38,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,751 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367161714]
[2021-11-13 17:47:38,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,797 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,797 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367161714]
[2021-11-13 17:47:38,797 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367161714] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:38,801 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [152486245]
[2021-11-13 17:47:38,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,802 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:38,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:38,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1150691781, now seen corresponding path program 1 times
[2021-11-13 17:47:38,802 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:38,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159702605]
[2021-11-13 17:47:38,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:38,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:38,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:38,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:38,844 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:38,845 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159702605]
[2021-11-13 17:47:38,845 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159702605] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:38,845 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:38,845 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:38,845 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499892648]
[2021-11-13 17:47:38,845 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:38,846 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:38,846 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:38,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2021-11-13 17:47:38,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2021-11-13 17:47:38,847 INFO L87 Difference]: Start difference. First operand 2133 states and 3101 transitions. cyclomatic complexity: 970 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:39,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:39,152 INFO L93 Difference]: Finished difference Result 5042 states and 7258 transitions.
[2021-11-13 17:47:39,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2021-11-13 17:47:39,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5042 states and 7258 transitions.
[2021-11-13 17:47:39,190 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4839
[2021-11-13 17:47:39,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5042 states to 5042 states and 7258 transitions.
[2021-11-13 17:47:39,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5042
[2021-11-13 17:47:39,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5042
[2021-11-13 17:47:39,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5042 states and 7258 transitions.
[2021-11-13 17:47:39,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:39,254 INFO L681 BuchiCegarLoop]: Abstraction has 5042 states and 7258 transitions.
[2021-11-13 17:47:39,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5042 states and 7258 transitions.
[2021-11-13 17:47:39,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5042 to 3969.
[2021-11-13 17:47:39,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3969 states, 3969 states have (on average 1.4452003023431594) internal successors, (5736), 3968 states have internal predecessors, (5736), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:39,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3969 states to 3969 states and 5736 transitions.
[2021-11-13 17:47:39,347 INFO L704 BuchiCegarLoop]: Abstraction has 3969 states and 5736 transitions.
[2021-11-13 17:47:39,347 INFO L587 BuchiCegarLoop]: Abstraction has 3969 states and 5736 transitions.
[2021-11-13 17:47:39,347 INFO L425 BuchiCegarLoop]: ======== Iteration 13============
[2021-11-13 17:47:39,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3969 states and 5736 transitions.
[2021-11-13 17:47:39,367 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3842
[2021-11-13 17:47:39,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:39,368 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:39,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:39,370 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:39,370 INFO L791 eck$LassoCheckResult]: Stem: 35069#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 35070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 35361#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35088#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34989#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 34736#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34737#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35266#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35306#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35295#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35296#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34851#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34840#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34841#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34656#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34657#L951 assume !(0 == ~M_E~0); 34388#L951-2 assume !(0 == ~T1_E~0); 34389#L956-1 assume !(0 == ~T2_E~0); 34553#L961-1 assume !(0 == ~T3_E~0); 35004#L966-1 assume !(0 == ~T4_E~0); 35005#L971-1 assume !(0 == ~T5_E~0); 35144#L976-1 assume !(0 == ~T6_E~0); 35115#L981-1 assume !(0 == ~T7_E~0); 34888#L986-1 assume !(0 == ~T8_E~0); 34606#L991-1 assume !(0 == ~T9_E~0); 34607#L996-1 assume !(0 == ~E_M~0); 35343#L1001-1 assume !(0 == ~E_1~0); 35067#L1006-1 assume !(0 == ~E_2~0); 35068#L1011-1 assume !(0 == ~E_3~0); 35308#L1016-1 assume !(0 == ~E_4~0); 35323#L1021-1 assume !(0 == ~E_5~0); 34196#L1026-1 assume !(0 == ~E_6~0); 34197#L1031-1 assume !(0 == ~E_7~0); 35018#L1036-1 assume !(0 == ~E_8~0); 35014#L1041-1 assume !(0 == ~E_9~0); 35015#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35275#L472 assume !(1 == ~m_pc~0); 35234#L472-2 is_master_triggered_~__retres1~0#1 := 0; 35046#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35047#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35054#L1179 assume !(0 != activate_threads_~tmp~1#1); 34204#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34205#L491 assume !(1 == ~t1_pc~0); 34705#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34706#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35010#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34177#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 34178#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34200#L510 assume !(1 == ~t2_pc~0); 34164#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34165#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35278#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35279#L1195 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34444#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34445#L529 assume 1 == ~t3_pc~0; 34807#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34808#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35231#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35333#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 34365#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34366#L548 assume !(1 == ~t4_pc~0); 34264#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34263#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34563#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34308#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 34309#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34251#L567 assume 1 == ~t5_pc~0; 34252#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34310#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34490#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34491#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 35261#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34376#L586 assume !(1 == ~t6_pc~0); 34377#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34452#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35358#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35377#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 35254#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35255#L605 assume 1 == ~t7_pc~0; 35228#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34871#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35008#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35009#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 35370#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34984#L624 assume !(1 == ~t8_pc~0); 34438#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34437#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35040#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35041#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 35237#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34219#L643 assume 1 == ~t9_pc~0; 34220#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35188#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35117#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34613#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 34614#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34420#L1059 assume !(1 == ~M_E~0); 34421#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34581#L1064-1 assume !(1 == ~T2_E~0); 34582#L1069-1 assume !(1 == ~T3_E~0); 35197#L1074-1 assume !(1 == ~T4_E~0); 35235#L1079-1 assume !(1 == ~T5_E~0); 35226#L1084-1 assume !(1 == ~T6_E~0); 35227#L1089-1 assume !(1 == ~T7_E~0); 35250#L1094-1 assume !(1 == ~T8_E~0); 34917#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34918#L1104-1 assume !(1 == ~E_M~0); 35105#L1109-1 assume !(1 == ~E_1~0); 34727#L1114-1 assume !(1 == ~E_2~0); 34728#L1119-1 assume !(1 == ~E_3~0); 34782#L1124-1 assume !(1 == ~E_4~0); 34215#L1129-1 assume !(1 == ~E_5~0); 34216#L1134-1 assume !(1 == ~E_6~0); 34549#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34550#L1144-1 assume !(1 == ~E_8~0); 34744#L1149-1 assume !(1 == ~E_9~0); 34382#L1154-1 assume { :end_inline_reset_delta_events } true; 34383#L1440-2
[2021-11-13 17:47:39,371 INFO L793 eck$LassoCheckResult]: Loop: 34383#L1440-2 assume !false; 34514#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34156#L926 assume !false; 34784#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 34785#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34472#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34473#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 34478#L795 assume !(0 != eval_~tmp~0#1); 34479#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34911#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34640#L951-3 assume !(0 == ~M_E~0); 34641#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35155#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34988#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34769#L966-3 assume !(0 == ~T4_E~0); 34770#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35042#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34237#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34238#L986-3 assume !(0 == ~T8_E~0); 34217#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34218#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35138#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34740#L1006-3 assume !(0 == ~E_2~0); 34741#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35163#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35202#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34936#L1026-3 assume !(0 == ~E_6~0); 34937#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35133#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35134#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35194#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35153#L472-33 assume !(1 == ~m_pc~0); 34332#L472-35 is_master_triggered_~__retres1~0#1 := 0; 34333#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34168#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34169#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34773#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34774#L491-33 assume !(1 == ~t1_pc~0); 34267#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 34268#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35331#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35353#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35354#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35106#L510-33 assume !(1 == ~t2_pc~0); 35103#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 35104#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35006#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35007#L1195-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34157#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34158#L529-33 assume 1 == ~t3_pc~0; 34185#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34186#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34457#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35327#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 34287#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34288#L548-33 assume 1 == ~t4_pc~0; 34532#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34655#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34697#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34698#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34467#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34468#L567-33 assume 1 == ~t5_pc~0; 34901#L568-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34574#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34817#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35332#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35365#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35003#L586-33 assume 1 == ~t6_pc~0; 34976#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34596#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34929#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34930#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34484#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34485#L605-33 assume !(1 == ~t7_pc~0); 34667#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 34405#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34406#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34822#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34299#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34300#L624-33 assume 1 == ~t8_pc~0; 34455#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34464#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34432#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34433#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 34680#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34407#L643-33 assume 1 == ~t9_pc~0; 34408#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34502#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34960#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34913#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34914#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34289#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34290#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34796#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34847#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34848#L1074-3 assume !(1 == ~T4_E~0); 35116#L1079-3 assume !(1 == ~T5_E~0); 35019#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34958#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34959#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34880#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34881#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35139#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35121#L1114-3 assume !(1 == ~E_2~0); 35122#L1119-3 assume !(1 == ~E_3~0); 35364#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35369#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34589#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34590#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34755#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34756#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34919#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35372#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34292#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 34175#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 34176#L1459 assume !(0 == start_simulation_~tmp~3#1); 34184#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 35203#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 34470#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 35027#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 34636#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34637#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34797#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34979#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 34383#L1440-2
[2021-11-13 17:47:39,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:39,372 INFO L85 PathProgramCache]: Analyzing trace with hash -294583675, now seen corresponding path program 1 times
[2021-11-13 17:47:39,372 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:39,372 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150624024]
[2021-11-13 17:47:39,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:39,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:39,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:39,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:39,422 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:39,422 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150624024]
[2021-11-13 17:47:39,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150624024] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:39,422 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:39,422 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2021-11-13 17:47:39,423 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103437269]
[2021-11-13 17:47:39,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:39,424 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:39,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:39,425 INFO L85 PathProgramCache]: Analyzing trace with hash -334548410, now seen corresponding path program 1 times
[2021-11-13 17:47:39,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:39,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466766807]
[2021-11-13 17:47:39,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:39,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:39,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:39,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:39,467 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:39,467 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466766807]
[2021-11-13 17:47:39,467 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466766807] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:39,467 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:39,467 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:39,468 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598191342]
[2021-11-13 17:47:39,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:39,468 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:39,469 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:39,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2021-11-13 17:47:39,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2021-11-13 17:47:39,469 INFO L87 Difference]: Start difference. First operand 3969 states and 5736 transitions. cyclomatic complexity: 1769 Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:39,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:39,723 INFO L93 Difference]: Finished difference Result 5033 states and 7246 transitions.
[2021-11-13 17:47:39,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states.
[2021-11-13 17:47:39,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5033 states and 7246 transitions.
[2021-11-13 17:47:39,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4904
[2021-11-13 17:47:39,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5033 states to 5033 states and 7246 transitions.
[2021-11-13 17:47:39,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5033
[2021-11-13 17:47:39,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5033
[2021-11-13 17:47:39,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5033 states and 7246 transitions.
[2021-11-13 17:47:39,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:39,808 INFO L681 BuchiCegarLoop]: Abstraction has 5033 states and 7246 transitions.
[2021-11-13 17:47:39,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5033 states and 7246 transitions.
[2021-11-13 17:47:39,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5033 to 3975.
[2021-11-13 17:47:39,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3975 states, 3975 states have (on average 1.4337106918238993) internal successors, (5699), 3974 states have internal predecessors, (5699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:39,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3975 states to 3975 states and 5699 transitions.
[2021-11-13 17:47:39,933 INFO L704 BuchiCegarLoop]: Abstraction has 3975 states and 5699 transitions.
[2021-11-13 17:47:39,933 INFO L587 BuchiCegarLoop]: Abstraction has 3975 states and 5699 transitions.
[2021-11-13 17:47:39,933 INFO L425 BuchiCegarLoop]: ======== Iteration 14============
[2021-11-13 17:47:39,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3975 states and 5699 transitions.
[2021-11-13 17:47:39,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3848
[2021-11-13 17:47:39,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:39,955 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:39,957 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:39,958 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:39,958 INFO L791 eck$LassoCheckResult]: Stem: 44216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 44217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 44797#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44247#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44110#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 43780#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43781#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44560#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44656#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44633#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44634#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43930#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43914#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43915#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43691#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43692#L951 assume !(0 == ~M_E~0); 43407#L951-2 assume !(0 == ~T1_E~0); 43408#L956-1 assume !(0 == ~T2_E~0); 43580#L961-1 assume !(0 == ~T3_E~0); 44132#L966-1 assume !(0 == ~T4_E~0); 44133#L971-1 assume !(0 == ~T5_E~0); 44323#L976-1 assume !(0 == ~T6_E~0); 44286#L981-1 assume !(0 == ~T7_E~0); 43981#L986-1 assume !(0 == ~T8_E~0); 43638#L991-1 assume !(0 == ~T9_E~0); 43639#L996-1 assume !(0 == ~E_M~0); 44761#L1001-1 assume !(0 == ~E_1~0); 44214#L1006-1 assume !(0 == ~E_2~0); 44215#L1011-1 assume !(0 == ~E_3~0); 44659#L1016-1 assume !(0 == ~E_4~0); 44701#L1021-1 assume !(0 == ~E_5~0); 43211#L1026-1 assume !(0 == ~E_6~0); 43212#L1031-1 assume !(0 == ~E_7~0); 44150#L1036-1 assume !(0 == ~E_8~0); 44146#L1041-1 assume !(0 == ~E_9~0); 44147#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44574#L472 assume !(1 == ~m_pc~0); 44489#L472-2 is_master_triggered_~__retres1~0#1 := 0; 44190#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44191#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44200#L1179 assume !(0 != activate_threads_~tmp~1#1); 43219#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43220#L491 assume !(1 == ~t1_pc~0); 43746#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43747#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44138#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43192#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 43193#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43215#L510 assume !(1 == ~t2_pc~0); 43179#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43180#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44578#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44579#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 43462#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43463#L529 assume 1 == ~t3_pc~0; 43867#L530 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43868#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44476#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44727#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 43382#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43383#L548 assume !(1 == ~t4_pc~0); 43279#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43278#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43592#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43323#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 43324#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43268#L567 assume 1 == ~t5_pc~0; 43269#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43325#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43510#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43511#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 44549#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43393#L586 assume !(1 == ~t6_pc~0); 43394#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 43470#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44787#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44957#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 44541#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44542#L605 assume 1 == ~t7_pc~0; 44467#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43957#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44136#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44137#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 44868#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44104#L624 assume !(1 == ~t8_pc~0); 43454#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43453#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44181#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44182#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 44499#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43234#L643 assume 1 == ~t9_pc~0; 43235#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44398#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44290#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43645#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 43646#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43437#L1059 assume !(1 == ~M_E~0); 43438#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43612#L1064-1 assume !(1 == ~T2_E~0); 43613#L1069-1 assume !(1 == ~T3_E~0); 44408#L1074-1 assume !(1 == ~T4_E~0); 44494#L1079-1 assume !(1 == ~T5_E~0); 44463#L1084-1 assume !(1 == ~T6_E~0); 44464#L1089-1 assume !(1 == ~T7_E~0); 44526#L1094-1 assume !(1 == ~T8_E~0); 44010#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44011#L1104-1 assume !(1 == ~E_M~0); 44273#L1109-1 assume !(1 == ~E_1~0); 43769#L1114-1 assume !(1 == ~E_2~0); 43770#L1119-1 assume !(1 == ~E_3~0); 43838#L1124-1 assume !(1 == ~E_4~0); 43232#L1129-1 assume !(1 == ~E_5~0); 43233#L1134-1 assume !(1 == ~E_6~0); 43578#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 43579#L1144-1 assume !(1 == ~E_8~0); 43793#L1149-1 assume !(1 == ~E_9~0); 43399#L1154-1 assume { :end_inline_reset_delta_events } true; 43400#L1440-2
[2021-11-13 17:47:39,959 INFO L793 eck$LassoCheckResult]: Loop: 43400#L1440-2 assume !false; 45989#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45983#L926 assume !false; 45981#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 45056#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 45046#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 45044#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 45040#L795 assume !(0 != eval_~tmp~0#1); 45041#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46718#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46717#L951-3 assume !(0 == ~M_E~0); 46716#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46715#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46714#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46713#L966-3 assume !(0 == ~T4_E~0); 46712#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46711#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46710#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46709#L986-3 assume !(0 == ~T8_E~0); 46708#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46707#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46706#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46705#L1006-3 assume !(0 == ~E_2~0); 46704#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46703#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46702#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46701#L1026-3 assume !(0 == ~E_6~0); 46700#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46699#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46698#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 46697#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46696#L472-33 assume !(1 == ~m_pc~0); 46695#L472-35 is_master_triggered_~__retres1~0#1 := 0; 46694#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46693#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46692#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46691#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44824#L491-33 assume !(1 == ~t1_pc~0); 43285#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 43286#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44725#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44780#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44781#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46005#L510-33 assume !(1 == ~t2_pc~0); 46002#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 46000#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45999#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45995#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 45993#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45991#L529-33 assume 1 == ~t3_pc~0; 45984#L530-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45982#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45980#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45979#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 45978#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45977#L548-33 assume 1 == ~t4_pc~0; 45975#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45974#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45973#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45972#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45971#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45970#L567-33 assume !(1 == ~t5_pc~0); 45968#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 45967#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45966#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45964#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45961#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45959#L586-33 assume 1 == ~t6_pc~0; 45956#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45954#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45952#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45950#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45948#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45945#L605-33 assume !(1 == ~t7_pc~0); 45942#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 45940#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45938#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45936#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45934#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45931#L624-33 assume 1 == ~t8_pc~0; 45928#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45919#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43448#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43449#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43721#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43426#L643-33 assume 1 == ~t9_pc~0; 43427#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43524#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44063#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44006#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44007#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43304#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43305#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43852#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43923#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43924#L1074-3 assume !(1 == ~T4_E~0); 44287#L1079-3 assume !(1 == ~T5_E~0); 44151#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44061#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44062#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43965#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43966#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44315#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44292#L1114-3 assume !(1 == ~E_2~0); 44293#L1119-3 assume !(1 == ~E_3~0); 44810#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44846#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43620#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43621#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43810#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43811#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44012#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 44888#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 43307#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 43190#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 43191#L1459 assume !(0 == start_simulation_~tmp~3#1); 43199#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 46035#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 46025#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 46023#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 46021#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46019#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46016#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 46014#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 43400#L1440-2
[2021-11-13 17:47:39,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:39,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1980763513, now seen corresponding path program 1 times
[2021-11-13 17:47:39,960 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:39,960 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167963791]
[2021-11-13 17:47:39,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:39,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:39,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:40,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:40,002 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:40,002 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [167963791]
[2021-11-13 17:47:40,002 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [167963791] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:40,002 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:40,003 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:40,003 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1607286265]
[2021-11-13 17:47:40,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:40,006 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:40,006 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:40,006 INFO L85 PathProgramCache]: Analyzing trace with hash 269445833, now seen corresponding path program 1 times
[2021-11-13 17:47:40,007 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:40,007 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143108412]
[2021-11-13 17:47:40,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:40,008 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:40,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:40,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:40,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:40,047 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143108412]
[2021-11-13 17:47:40,047 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143108412] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:40,047 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:40,047 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:40,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031978138]
[2021-11-13 17:47:40,048 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:40,048 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:40,048 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:40,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2021-11-13 17:47:40,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2021-11-13 17:47:40,049 INFO L87 Difference]: Start difference. First operand 3975 states and 5699 transitions. cyclomatic complexity: 1726 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:40,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:40,335 INFO L93 Difference]: Finished difference Result 9498 states and 13503 transitions.
[2021-11-13 17:47:40,335 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2021-11-13 17:47:40,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9498 states and 13503 transitions.
[2021-11-13 17:47:40,391 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9219
[2021-11-13 17:47:40,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9498 states to 9498 states and 13503 transitions.
[2021-11-13 17:47:40,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9498
[2021-11-13 17:47:40,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9498
[2021-11-13 17:47:40,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9498 states and 13503 transitions.
[2021-11-13 17:47:40,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:40,466 INFO L681 BuchiCegarLoop]: Abstraction has 9498 states and 13503 transitions.
[2021-11-13 17:47:40,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9498 states and 13503 transitions.
[2021-11-13 17:47:40,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9498 to 7488.
[2021-11-13 17:47:40,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7488 states, 7488 states have (on average 1.4268162393162394) internal successors, (10684), 7487 states have internal predecessors, (10684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:40,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7488 states to 7488 states and 10684 transitions.
[2021-11-13 17:47:40,685 INFO L704 BuchiCegarLoop]: Abstraction has 7488 states and 10684 transitions.
[2021-11-13 17:47:40,686 INFO L587 BuchiCegarLoop]: Abstraction has 7488 states and 10684 transitions.
[2021-11-13 17:47:40,686 INFO L425 BuchiCegarLoop]: ======== Iteration 15============
[2021-11-13 17:47:40,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7488 states and 10684 transitions.
[2021-11-13 17:47:40,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7360
[2021-11-13 17:47:40,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:40,717 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:40,720 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:40,720 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:40,721 INFO L791 eck$LassoCheckResult]: Stem: 57578#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 57579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 57891#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57601#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57496#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 57238#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57239#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57786#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57833#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57823#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57824#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57353#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57342#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 57343#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 57155#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57156#L951 assume !(0 == ~M_E~0); 56890#L951-2 assume !(0 == ~T1_E~0); 56891#L956-1 assume !(0 == ~T2_E~0); 57051#L961-1 assume !(0 == ~T3_E~0); 57511#L966-1 assume !(0 == ~T4_E~0); 57512#L971-1 assume !(0 == ~T5_E~0); 57653#L976-1 assume !(0 == ~T6_E~0); 57625#L981-1 assume !(0 == ~T7_E~0); 57393#L986-1 assume !(0 == ~T8_E~0); 57106#L991-1 assume !(0 == ~T9_E~0); 57107#L996-1 assume !(0 == ~E_M~0); 57872#L1001-1 assume !(0 == ~E_1~0); 57576#L1006-1 assume !(0 == ~E_2~0); 57577#L1011-1 assume !(0 == ~E_3~0); 57836#L1016-1 assume !(0 == ~E_4~0); 57850#L1021-1 assume !(0 == ~E_5~0); 56695#L1026-1 assume !(0 == ~E_6~0); 56696#L1031-1 assume !(0 == ~E_7~0); 57525#L1036-1 assume !(0 == ~E_8~0); 57521#L1041-1 assume !(0 == ~E_9~0); 57522#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57796#L472 assume !(1 == ~m_pc~0); 57753#L472-2 is_master_triggered_~__retres1~0#1 := 0; 57555#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57556#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57563#L1179 assume !(0 != activate_threads_~tmp~1#1); 56703#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56704#L491 assume !(1 == ~t1_pc~0); 57207#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 57208#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57517#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56675#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 56676#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56699#L510 assume !(1 == ~t2_pc~0); 56662#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56663#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57799#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57800#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 56941#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56942#L529 assume !(1 == ~t3_pc~0); 57396#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 57678#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57748#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57861#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 56863#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56864#L548 assume !(1 == ~t4_pc~0); 56763#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56762#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57061#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56806#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 56807#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56755#L567 assume 1 == ~t5_pc~0; 56756#L568 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56808#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56991#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56992#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 57780#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56874#L586 assume !(1 == ~t6_pc~0); 56875#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 56949#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57887#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57922#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 57774#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57775#L605 assume 1 == ~t7_pc~0; 57745#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57377#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57515#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57516#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 57913#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57489#L624 assume !(1 == ~t8_pc~0); 56935#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56934#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57549#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57550#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 57756#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56720#L643 assume 1 == ~t9_pc~0; 56721#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57705#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57628#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57113#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 57114#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56918#L1059 assume !(1 == ~M_E~0); 56919#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57081#L1064-1 assume !(1 == ~T2_E~0); 57082#L1069-1 assume !(1 == ~T3_E~0); 57713#L1074-1 assume !(1 == ~T4_E~0); 57755#L1079-1 assume !(1 == ~T5_E~0); 57742#L1084-1 assume !(1 == ~T6_E~0); 57743#L1089-1 assume !(1 == ~T7_E~0); 57770#L1094-1 assume !(1 == ~T8_E~0); 57420#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57421#L1104-1 assume !(1 == ~E_M~0); 57615#L1109-1 assume !(1 == ~E_1~0); 57227#L1114-1 assume !(1 == ~E_2~0); 57228#L1119-1 assume !(1 == ~E_3~0); 57288#L1124-1 assume !(1 == ~E_4~0); 56716#L1129-1 assume !(1 == ~E_5~0); 56717#L1134-1 assume !(1 == ~E_6~0); 57049#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 57050#L1144-1 assume !(1 == ~E_8~0); 57247#L1149-1 assume !(1 == ~E_9~0); 56880#L1154-1 assume { :end_inline_reset_delta_events } true; 56881#L1440-2
[2021-11-13 17:47:40,721 INFO L793 eck$LassoCheckResult]: Loop: 56881#L1440-2 assume !false; 57013#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56654#L926 assume !false; 57289#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 57290#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 56967#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 56968#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 56976#L795 assume !(0 != eval_~tmp~0#1); 56977#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57414#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57140#L951-3 assume !(0 == ~M_E~0); 57141#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57667#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57494#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57271#L966-3 assume !(0 == ~T4_E~0); 57272#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57548#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56741#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56742#L986-3 assume !(0 == ~T8_E~0); 56714#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 56715#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57647#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57243#L1006-3 assume !(0 == ~E_2~0); 57244#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57674#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57718#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57439#L1026-3 assume !(0 == ~E_6~0); 57440#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57642#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57643#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57709#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57662#L472-33 assume !(1 == ~m_pc~0); 56830#L472-35 is_master_triggered_~__retres1~0#1 := 0; 56831#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56666#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56667#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57276#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57277#L491-33 assume !(1 == ~t1_pc~0); 56766#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 56767#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57859#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57882#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57883#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57616#L510-33 assume !(1 == ~t2_pc~0); 57613#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 57614#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57513#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57514#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 63840#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63824#L529-33 assume !(1 == ~t3_pc~0); 57070#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 56954#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56955#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57855#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 56786#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56787#L548-33 assume 1 == ~t4_pc~0; 57027#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57154#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57195#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57196#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56965#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56966#L567-33 assume !(1 == ~t5_pc~0); 57073#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 57074#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57319#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57860#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57894#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57510#L586-33 assume !(1 == ~t6_pc~0); 57094#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 57095#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57432#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57433#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56981#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56982#L605-33 assume !(1 == ~t7_pc~0); 57163#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 56900#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56901#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57324#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56798#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56799#L624-33 assume 1 == ~t8_pc~0; 56950#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56959#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56929#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56930#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57180#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56902#L643-33 assume 1 == ~t9_pc~0; 56903#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56997#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57465#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57416#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57417#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56788#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56789#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57301#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57349#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57350#L1074-3 assume !(1 == ~T4_E~0); 57626#L1079-3 assume !(1 == ~T5_E~0); 57526#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57463#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57464#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57382#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57383#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57648#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57631#L1114-3 assume !(1 == ~E_2~0); 57632#L1119-3 assume !(1 == ~E_3~0); 57895#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57909#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57089#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57090#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57263#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57264#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57422#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 57916#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 56793#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 56673#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 56674#L1459 assume !(0 == start_simulation_~tmp~3#1); 56682#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 57720#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 56970#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 57534#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 57136#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57137#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57305#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 57485#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 56881#L1440-2
[2021-11-13 17:47:40,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:40,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1403834872, now seen corresponding path program 1 times
[2021-11-13 17:47:40,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:40,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788642295]
[2021-11-13 17:47:40,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:40,723 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:40,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:40,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:40,761 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:40,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788642295]
[2021-11-13 17:47:40,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788642295] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:40,762 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:40,762 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:40,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898941527]
[2021-11-13 17:47:40,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:40,763 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:40,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:40,764 INFO L85 PathProgramCache]: Analyzing trace with hash 650812683, now seen corresponding path program 1 times
[2021-11-13 17:47:40,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:40,764 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [59647318]
[2021-11-13 17:47:40,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:40,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:40,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:40,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:40,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:40,798 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [59647318]
[2021-11-13 17:47:40,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [59647318] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:40,799 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:40,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:40,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022445233]
[2021-11-13 17:47:40,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:40,800 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:40,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:40,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2021-11-13 17:47:40,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2021-11-13 17:47:40,801 INFO L87 Difference]: Start difference. First operand 7488 states and 10684 transitions. cyclomatic complexity: 3198 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:41,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:41,100 INFO L93 Difference]: Finished difference Result 17931 states and 25385 transitions.
[2021-11-13 17:47:41,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2021-11-13 17:47:41,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17931 states and 25385 transitions.
[2021-11-13 17:47:41,323 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17500
[2021-11-13 17:47:41,383 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17931 states to 17931 states and 25385 transitions.
[2021-11-13 17:47:41,383 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17931
[2021-11-13 17:47:41,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17931
[2021-11-13 17:47:41,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17931 states and 25385 transitions.
[2021-11-13 17:47:41,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:41,420 INFO L681 BuchiCegarLoop]: Abstraction has 17931 states and 25385 transitions.
[2021-11-13 17:47:41,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17931 states and 25385 transitions.
[2021-11-13 17:47:41,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17931 to 14187.
[2021-11-13 17:47:41,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14187 states, 14187 states have (on average 1.4208077817720448) internal successors, (20157), 14186 states have internal predecessors, (20157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:41,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14187 states to 14187 states and 20157 transitions.
[2021-11-13 17:47:41,775 INFO L704 BuchiCegarLoop]: Abstraction has 14187 states and 20157 transitions.
[2021-11-13 17:47:41,775 INFO L587 BuchiCegarLoop]: Abstraction has 14187 states and 20157 transitions.
[2021-11-13 17:47:41,775 INFO L425 BuchiCegarLoop]: ======== Iteration 16============
[2021-11-13 17:47:41,775 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14187 states and 20157 transitions.
[2021-11-13 17:47:41,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14056
[2021-11-13 17:47:41,827 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:41,827 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:41,830 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:41,831 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:41,831 INFO L791 eck$LassoCheckResult]: Stem: 83012#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 83013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 83364#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 83036#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82934#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 82665#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82666#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83239#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83295#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83285#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 83286#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82783#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 82772#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 82773#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82583#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82584#L951 assume !(0 == ~M_E~0); 82318#L951-2 assume !(0 == ~T1_E~0); 82319#L956-1 assume !(0 == ~T2_E~0); 82481#L961-1 assume !(0 == ~T3_E~0); 82949#L966-1 assume !(0 == ~T4_E~0); 82950#L971-1 assume !(0 == ~T5_E~0); 83091#L976-1 assume !(0 == ~T6_E~0); 83062#L981-1 assume !(0 == ~T7_E~0); 82822#L986-1 assume !(0 == ~T8_E~0); 82534#L991-1 assume !(0 == ~T9_E~0); 82535#L996-1 assume !(0 == ~E_M~0); 83343#L1001-1 assume !(0 == ~E_1~0); 83010#L1006-1 assume !(0 == ~E_2~0); 83011#L1011-1 assume !(0 == ~E_3~0); 83298#L1016-1 assume !(0 == ~E_4~0); 83320#L1021-1 assume !(0 == ~E_5~0); 82123#L1026-1 assume !(0 == ~E_6~0); 82124#L1031-1 assume !(0 == ~E_7~0); 82964#L1036-1 assume !(0 == ~E_8~0); 82960#L1041-1 assume !(0 == ~E_9~0); 82961#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83257#L472 assume !(1 == ~m_pc~0); 83196#L472-2 is_master_triggered_~__retres1~0#1 := 0; 82991#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82992#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82999#L1179 assume !(0 != activate_threads_~tmp~1#1); 82131#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82132#L491 assume !(1 == ~t1_pc~0); 82634#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82635#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82955#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82104#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 82105#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82127#L510 assume !(1 == ~t2_pc~0); 82091#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82092#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83261#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83262#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 82370#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82371#L529 assume !(1 == ~t3_pc~0); 82825#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 83119#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83190#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83330#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 82291#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82292#L548 assume !(1 == ~t4_pc~0); 82188#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 82187#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82491#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82231#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 82232#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82181#L567 assume !(1 == ~t5_pc~0); 82182#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 82233#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82421#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82422#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 83233#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82302#L586 assume !(1 == ~t6_pc~0); 82303#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 82378#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83358#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83403#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 83225#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83226#L605 assume 1 == ~t7_pc~0; 83187#L606 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82806#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82953#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82954#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 83384#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82927#L624 assume !(1 == ~t8_pc~0); 82363#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82362#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82986#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82987#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 83203#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82147#L643 assume 1 == ~t9_pc~0; 82148#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83150#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83065#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82541#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 82542#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82346#L1059 assume !(1 == ~M_E~0); 82347#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82509#L1064-1 assume !(1 == ~T2_E~0); 82510#L1069-1 assume !(1 == ~T3_E~0); 83158#L1074-1 assume !(1 == ~T4_E~0); 83201#L1079-1 assume !(1 == ~T5_E~0); 83184#L1084-1 assume !(1 == ~T6_E~0); 83185#L1089-1 assume !(1 == ~T7_E~0); 83218#L1094-1 assume !(1 == ~T8_E~0); 82852#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82853#L1104-1 assume !(1 == ~E_M~0); 83052#L1109-1 assume !(1 == ~E_1~0); 82654#L1114-1 assume !(1 == ~E_2~0); 82655#L1119-1 assume !(1 == ~E_3~0); 82717#L1124-1 assume !(1 == ~E_4~0); 82143#L1129-1 assume !(1 == ~E_5~0); 82144#L1134-1 assume !(1 == ~E_6~0); 82479#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 82480#L1144-1 assume !(1 == ~E_8~0); 82674#L1149-1 assume !(1 == ~E_9~0); 82308#L1154-1 assume { :end_inline_reset_delta_events } true; 82309#L1440-2
[2021-11-13 17:47:41,831 INFO L793 eck$LassoCheckResult]: Loop: 82309#L1440-2 assume !false; 82444#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82083#L926 assume !false; 82718#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 82719#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82396#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82397#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 82406#L795 assume !(0 != eval_~tmp~0#1); 82407#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82846#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96268#L951-3 assume !(0 == ~M_E~0); 83400#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83105#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82931#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82932#L966-3 assume !(0 == ~T4_E~0); 83307#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82985#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82162#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 82163#L986-3 assume !(0 == ~T8_E~0); 82141#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82142#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83083#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 82670#L1006-3 assume !(0 == ~E_2~0); 82671#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96227#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96226#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96225#L1026-3 assume !(0 == ~E_6~0); 96223#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 96221#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 96219#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 96217#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96215#L472-33 assume !(1 == ~m_pc~0); 96212#L472-35 is_master_triggered_~__retres1~0#1 := 0; 96209#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96207#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83109#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83110#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83370#L491-33 assume !(1 == ~t1_pc~0); 83371#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 95802#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95801#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95799#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95797#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95795#L510-33 assume !(1 == ~t2_pc~0); 95792#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 95789#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95787#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95785#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 95783#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82401#L529-33 assume !(1 == ~t3_pc~0); 82402#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 82383#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82384#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83324#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 82211#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82212#L548-33 assume 1 == ~t4_pc~0; 82457#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82582#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82622#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82623#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82394#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82395#L567-33 assume !(1 == ~t5_pc~0); 82501#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 82502#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82748#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83329#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 83366#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82948#L586-33 assume 1 == ~t6_pc~0; 82918#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82523#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82866#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82867#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82411#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82412#L605-33 assume 1 == ~t7_pc~0; 82592#L606-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82334#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82335#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82753#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82223#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82224#L624-33 assume 1 == ~t8_pc~0; 82379#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82388#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82357#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82358#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82607#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82336#L643-33 assume 1 == ~t9_pc~0; 82337#L644-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82427#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82901#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82848#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 82849#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82213#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82214#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82730#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82781#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82782#L1074-3 assume !(1 == ~T4_E~0); 83063#L1079-3 assume !(1 == ~T5_E~0); 82965#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 82899#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82900#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 82811#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82812#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83086#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83069#L1114-3 assume !(1 == ~E_2~0); 83070#L1119-3 assume !(1 == ~E_3~0); 83367#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83380#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82517#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 82518#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82691#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82692#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82854#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83389#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82218#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82102#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 82103#L1459 assume !(0 == start_simulation_~tmp~3#1); 82111#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 83165#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 82399#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 82973#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 82564#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82565#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82734#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 82923#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 82309#L1440-2
[2021-11-13 17:47:41,832 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:41,832 INFO L85 PathProgramCache]: Analyzing trace with hash 790291209, now seen corresponding path program 1 times
[2021-11-13 17:47:41,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:41,833 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917463363]
[2021-11-13 17:47:41,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:41,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:41,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:41,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:41,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:41,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917463363]
[2021-11-13 17:47:41,875 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917463363] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:41,875 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:41,876 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:41,876 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190763640]
[2021-11-13 17:47:41,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:41,876 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:41,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:41,877 INFO L85 PathProgramCache]: Analyzing trace with hash -1783580727, now seen corresponding path program 1 times
[2021-11-13 17:47:41,877 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:41,877 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373398637]
[2021-11-13 17:47:41,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:41,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:41,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:41,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:41,920 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:41,921 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373398637]
[2021-11-13 17:47:41,921 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373398637] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:41,921 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:41,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:41,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705920092]
[2021-11-13 17:47:41,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:41,922 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:41,923 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:41,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2021-11-13 17:47:41,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2021-11-13 17:47:41,924 INFO L87 Difference]: Start difference. First operand 14187 states and 20157 transitions. cyclomatic complexity: 5972 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:42,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:42,447 INFO L93 Difference]: Finished difference Result 33878 states and 47778 transitions.
[2021-11-13 17:47:42,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2021-11-13 17:47:42,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33878 states and 47778 transitions.
[2021-11-13 17:47:42,646 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 33144
[2021-11-13 17:47:42,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33878 states to 33878 states and 47778 transitions.
[2021-11-13 17:47:42,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33878
[2021-11-13 17:47:43,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33878
[2021-11-13 17:47:43,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33878 states and 47778 transitions.
[2021-11-13 17:47:43,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:43,060 INFO L681 BuchiCegarLoop]: Abstraction has 33878 states and 47778 transitions.
[2021-11-13 17:47:43,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33878 states and 47778 transitions.
[2021-11-13 17:47:43,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33878 to 26938.
[2021-11-13 17:47:43,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26938 states, 26938 states have (on average 1.415472566634494) internal successors, (38130), 26937 states have internal predecessors, (38130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:43,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26938 states to 26938 states and 38130 transitions.
[2021-11-13 17:47:43,617 INFO L704 BuchiCegarLoop]: Abstraction has 26938 states and 38130 transitions.
[2021-11-13 17:47:43,617 INFO L587 BuchiCegarLoop]: Abstraction has 26938 states and 38130 transitions.
[2021-11-13 17:47:43,617 INFO L425 BuchiCegarLoop]: ======== Iteration 17============
[2021-11-13 17:47:43,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26938 states and 38130 transitions.
[2021-11-13 17:47:43,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26800
[2021-11-13 17:47:43,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:43,717 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:43,722 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:43,722 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:43,723 INFO L791 eck$LassoCheckResult]: Stem: 131092#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 131093#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 131444#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131116#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131012#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 130737#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130738#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131315#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131376#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131364#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131365#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 130858#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 130847#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 130848#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 130656#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 130657#L951 assume !(0 == ~M_E~0); 130387#L951-2 assume !(0 == ~T1_E~0); 130388#L956-1 assume !(0 == ~T2_E~0); 130554#L961-1 assume !(0 == ~T3_E~0); 131027#L966-1 assume !(0 == ~T4_E~0); 131028#L971-1 assume !(0 == ~T5_E~0); 131172#L976-1 assume !(0 == ~T6_E~0); 131144#L981-1 assume !(0 == ~T7_E~0); 130895#L986-1 assume !(0 == ~T8_E~0); 130609#L991-1 assume !(0 == ~T9_E~0); 130610#L996-1 assume !(0 == ~E_M~0); 131422#L1001-1 assume !(0 == ~E_1~0); 131090#L1006-1 assume !(0 == ~E_2~0); 131091#L1011-1 assume !(0 == ~E_3~0); 131377#L1016-1 assume !(0 == ~E_4~0); 131400#L1021-1 assume !(0 == ~E_5~0); 130199#L1026-1 assume !(0 == ~E_6~0); 130200#L1031-1 assume !(0 == ~E_7~0); 131039#L1036-1 assume !(0 == ~E_8~0); 131035#L1041-1 assume !(0 == ~E_9~0); 131036#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131330#L472 assume !(1 == ~m_pc~0); 131276#L472-2 is_master_triggered_~__retres1~0#1 := 0; 131070#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131071#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131079#L1179 assume !(0 != activate_threads_~tmp~1#1); 130207#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130208#L491 assume !(1 == ~t1_pc~0); 130706#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 130707#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131033#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 130177#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 130178#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 130201#L510 assume !(1 == ~t2_pc~0); 130166#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130167#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131332#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131333#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 130442#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130443#L529 assume !(1 == ~t3_pc~0); 130900#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 131196#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131272#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 131410#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 130364#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130365#L548 assume !(1 == ~t4_pc~0); 130264#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 130263#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130563#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130304#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 130305#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130252#L567 assume !(1 == ~t5_pc~0); 130253#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 130306#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130490#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130491#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 131309#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130375#L586 assume !(1 == ~t6_pc~0); 130376#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130448#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 131441#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 131489#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 131302#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131303#L605 assume !(1 == ~t7_pc~0); 130872#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 130873#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131031#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 131032#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 131471#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 131006#L624 assume !(1 == ~t8_pc~0); 130436#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 130435#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 131064#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 131065#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 131279#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130221#L643 assume 1 == ~t9_pc~0; 130222#L644 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 131223#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 131146#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 130614#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 130615#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130419#L1059 assume !(1 == ~M_E~0); 130420#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130584#L1064-1 assume !(1 == ~T2_E~0); 130585#L1069-1 assume !(1 == ~T3_E~0); 131233#L1074-1 assume !(1 == ~T4_E~0); 131277#L1079-1 assume !(1 == ~T5_E~0); 131267#L1084-1 assume !(1 == ~T6_E~0); 131268#L1089-1 assume !(1 == ~T7_E~0); 131295#L1094-1 assume !(1 == ~T8_E~0); 130930#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 130931#L1104-1 assume !(1 == ~E_M~0); 131132#L1109-1 assume !(1 == ~E_1~0); 130725#L1114-1 assume !(1 == ~E_2~0); 130726#L1119-1 assume !(1 == ~E_3~0); 130790#L1124-1 assume !(1 == ~E_4~0); 130217#L1129-1 assume !(1 == ~E_5~0); 130218#L1134-1 assume !(1 == ~E_6~0); 130550#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 130551#L1144-1 assume !(1 == ~E_8~0); 130746#L1149-1 assume !(1 == ~E_9~0); 130381#L1154-1 assume { :end_inline_reset_delta_events } true; 130382#L1440-2
[2021-11-13 17:47:43,723 INFO L793 eck$LassoCheckResult]: Loop: 130382#L1440-2 assume !false; 130513#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130158#L926 assume !false; 130793#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 130794#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130468#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130469#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 130477#L795 assume !(0 != eval_~tmp~0#1); 130478#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 157071#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 157070#L951-3 assume !(0 == ~M_E~0); 131486#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 131184#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 131010#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 130769#L966-3 assume !(0 == ~T4_E~0); 130770#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131066#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 130238#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 130239#L986-3 assume !(0 == ~T8_E~0); 130219#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 130220#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 131164#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 130744#L1006-3 assume !(0 == ~E_2~0); 130745#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 131192#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 131240#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 130948#L1026-3 assume !(0 == ~E_6~0); 130949#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 131161#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 131162#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 131229#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131180#L472-33 assume !(1 == ~m_pc~0); 130329#L472-35 is_master_triggered_~__retres1~0#1 := 0; 130330#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 130172#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 130173#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 130780#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 130781#L491-33 assume !(1 == ~t1_pc~0); 156706#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 156705#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 156704#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 156703#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 156702#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156701#L510-33 assume !(1 == ~t2_pc~0); 156699#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 156698#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156697#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 156696#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 156695#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156694#L529-33 assume !(1 == ~t3_pc~0); 155177#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 156693#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 156692#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 156691#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 156690#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156446#L548-33 assume !(1 == ~t4_pc~0); 156448#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 156684#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 156683#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 156682#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 156681#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131384#L567-33 assume !(1 == ~t5_pc~0); 130576#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 130577#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130823#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 131409#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 131450#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 131026#L586-33 assume !(1 == ~t6_pc~0); 130594#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 130595#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130944#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130945#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 130482#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130483#L605-33 assume !(1 == ~t7_pc~0); 130666#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 130407#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130408#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 130828#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 130298#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130299#L624-33 assume 1 == ~t8_pc~0; 130451#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 130460#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130430#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 130431#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 130681#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130409#L643-33 assume !(1 == ~t9_pc~0); 130411#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 130498#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130981#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 130926#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 130927#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130288#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 130289#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130805#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 130856#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 130857#L1074-3 assume !(1 == ~T4_E~0); 131145#L1079-3 assume !(1 == ~T5_E~0); 131042#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 130979#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 130980#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 130887#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 130888#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 131167#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 131150#L1114-3 assume !(1 == ~E_2~0); 131151#L1119-3 assume !(1 == ~E_3~0); 131451#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131463#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 130592#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 130593#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 130763#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 130764#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 130932#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131473#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130293#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 130179#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 130180#L1459 assume !(0 == start_simulation_~tmp~3#1); 130186#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 131242#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 130471#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 131050#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 130638#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130639#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130809#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 131002#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 130382#L1440-2
[2021-11-13 17:47:43,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:43,724 INFO L85 PathProgramCache]: Analyzing trace with hash -166637174, now seen corresponding path program 1 times
[2021-11-13 17:47:43,724 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:43,724 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654528790]
[2021-11-13 17:47:43,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:43,725 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:43,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:43,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:43,903 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:43,903 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654528790]
[2021-11-13 17:47:43,903 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654528790] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:43,903 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:43,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:43,908 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46453619]
[2021-11-13 17:47:43,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:43,909 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:43,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:43,909 INFO L85 PathProgramCache]: Analyzing trace with hash 831513165, now seen corresponding path program 1 times
[2021-11-13 17:47:43,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:43,910 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315586549]
[2021-11-13 17:47:43,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:43,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:43,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:43,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:43,941 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:43,941 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315586549]
[2021-11-13 17:47:43,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315586549] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:43,941 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:43,941 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:43,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [214452236]
[2021-11-13 17:47:43,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:43,942 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:43,942 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:43,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2021-11-13 17:47:43,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2021-11-13 17:47:43,943 INFO L87 Difference]: Start difference. First operand 26938 states and 38130 transitions. cyclomatic complexity: 11194 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:44,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:44,665 INFO L93 Difference]: Finished difference Result 63953 states and 89879 transitions.
[2021-11-13 17:47:44,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2021-11-13 17:47:44,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63953 states and 89879 transitions.
[2021-11-13 17:47:45,218 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 62616
[2021-11-13 17:47:45,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63953 states to 63953 states and 89879 transitions.
[2021-11-13 17:47:45,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63953
[2021-11-13 17:47:45,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63953
[2021-11-13 17:47:45,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63953 states and 89879 transitions.
[2021-11-13 17:47:45,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:45,733 INFO L681 BuchiCegarLoop]: Abstraction has 63953 states and 89879 transitions.
[2021-11-13 17:47:45,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63953 states and 89879 transitions.
[2021-11-13 17:47:46,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63953 to 51161.
[2021-11-13 17:47:46,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51161 states, 51161 states have (on average 1.410742557807705) internal successors, (72175), 51160 states have internal predecessors, (72175), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:46,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51161 states to 51161 states and 72175 transitions.
[2021-11-13 17:47:46,998 INFO L704 BuchiCegarLoop]: Abstraction has 51161 states and 72175 transitions.
[2021-11-13 17:47:46,998 INFO L587 BuchiCegarLoop]: Abstraction has 51161 states and 72175 transitions.
[2021-11-13 17:47:46,998 INFO L425 BuchiCegarLoop]: ======== Iteration 18============
[2021-11-13 17:47:46,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51161 states and 72175 transitions.
[2021-11-13 17:47:47,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:47,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:47,218 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:47,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:47,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:47,227 INFO L791 eck$LassoCheckResult]: Stem: 222004#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 222005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 222375#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 222028#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221916#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 221636#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221637#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222232#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222298#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222282#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222283#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221755#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 221744#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 221745#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 221555#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221556#L951 assume !(0 == ~M_E~0); 221286#L951-2 assume !(0 == ~T1_E~0); 221287#L956-1 assume !(0 == ~T2_E~0); 221452#L961-1 assume !(0 == ~T3_E~0); 221931#L966-1 assume !(0 == ~T4_E~0); 221932#L971-1 assume !(0 == ~T5_E~0); 222084#L976-1 assume !(0 == ~T6_E~0); 222056#L981-1 assume !(0 == ~T7_E~0); 221793#L986-1 assume !(0 == ~T8_E~0); 221505#L991-1 assume !(0 == ~T9_E~0); 221506#L996-1 assume !(0 == ~E_M~0); 222350#L1001-1 assume !(0 == ~E_1~0); 222002#L1006-1 assume !(0 == ~E_2~0); 222003#L1011-1 assume !(0 == ~E_3~0); 222299#L1016-1 assume !(0 == ~E_4~0); 222326#L1021-1 assume !(0 == ~E_5~0); 221099#L1026-1 assume !(0 == ~E_6~0); 221100#L1031-1 assume !(0 == ~E_7~0); 221946#L1036-1 assume !(0 == ~E_8~0); 221942#L1041-1 assume !(0 == ~E_9~0); 221943#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222247#L472 assume !(1 == ~m_pc~0); 222195#L472-2 is_master_triggered_~__retres1~0#1 := 0; 221982#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221983#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 221991#L1179 assume !(0 != activate_threads_~tmp~1#1); 221107#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 221108#L491 assume !(1 == ~t1_pc~0); 221605#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 221606#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221940#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 221078#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 221079#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221101#L510 assume !(1 == ~t2_pc~0); 221067#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 221068#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222249#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 222250#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 221340#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221341#L529 assume !(1 == ~t3_pc~0); 221798#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 222111#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222190#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222338#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 221263#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221264#L548 assume !(1 == ~t4_pc~0); 221163#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 221162#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221460#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221203#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 221204#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221151#L567 assume !(1 == ~t5_pc~0); 221152#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 221205#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221389#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 221390#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 222226#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221274#L586 assume !(1 == ~t6_pc~0); 221275#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 221346#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222367#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 222413#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 222221#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 222222#L605 assume !(1 == ~t7_pc~0); 221769#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 221770#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221935#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 221936#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 222396#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221909#L624 assume !(1 == ~t8_pc~0); 221334#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 221333#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221973#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221974#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 222200#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221121#L643 assume !(1 == ~t9_pc~0); 221122#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 222141#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 222058#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 221510#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 221511#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221317#L1059 assume !(1 == ~M_E~0); 221318#L1059-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221481#L1064-1 assume !(1 == ~T2_E~0); 221482#L1069-1 assume !(1 == ~T3_E~0); 222151#L1074-1 assume !(1 == ~T4_E~0); 222197#L1079-1 assume !(1 == ~T5_E~0); 222184#L1084-1 assume !(1 == ~T6_E~0); 222185#L1089-1 assume !(1 == ~T7_E~0); 222215#L1094-1 assume !(1 == ~T8_E~0); 221826#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 221827#L1104-1 assume !(1 == ~E_M~0); 222043#L1109-1 assume !(1 == ~E_1~0); 221624#L1114-1 assume !(1 == ~E_2~0); 221625#L1119-1 assume !(1 == ~E_3~0); 221687#L1124-1 assume !(1 == ~E_4~0); 221117#L1129-1 assume !(1 == ~E_5~0); 221118#L1134-1 assume !(1 == ~E_6~0); 221448#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 221449#L1144-1 assume !(1 == ~E_8~0); 221645#L1149-1 assume !(1 == ~E_9~0); 221280#L1154-1 assume { :end_inline_reset_delta_events } true; 221281#L1440-2
[2021-11-13 17:47:47,227 INFO L793 eck$LassoCheckResult]: Loop: 221281#L1440-2 assume !false; 221412#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 221523#L926 assume !false; 221690#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 221691#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 221366#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 221367#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 221375#L795 assume !(0 != eval_~tmp~0#1); 221376#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 222199#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 221540#L951-3 assume !(0 == ~M_E~0); 221541#L951-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 222098#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 222099#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 221667#L966-3 assume !(0 == ~T4_E~0); 221668#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 222313#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 272141#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 272140#L986-3 assume !(0 == ~T8_E~0); 272139#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 272138#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 222196#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 221643#L1006-3 assume !(0 == ~E_2~0); 221644#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 222107#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 272122#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 272116#L1026-3 assume !(0 == ~E_6~0); 272114#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 272110#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 272109#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 272108#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272107#L472-33 assume !(1 == ~m_pc~0); 221228#L472-35 is_master_triggered_~__retres1~0#1 := 0; 221229#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222303#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 271778#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 271777#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222383#L491-33 assume !(1 == ~t1_pc~0); 222384#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 272077#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222420#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 222360#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 222361#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222046#L510-33 assume !(1 == ~t2_pc~0); 222044#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 222045#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 221933#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 221934#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 221060#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221061#L529-33 assume !(1 == ~t3_pc~0); 221371#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 221353#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221354#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 222332#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 222368#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 271997#L548-33 assume 1 == ~t4_pc~0; 271993#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 271992#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221594#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 221595#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 221598#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270602#L567-33 assume !(1 == ~t5_pc~0); 270601#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 270600#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 270599#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 270598#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270597#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270596#L586-33 assume 1 == ~t6_pc~0; 270593#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 270591#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270589#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 270587#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 270585#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270545#L605-33 assume !(1 == ~t7_pc~0); 221962#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 221306#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221307#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 221725#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 221197#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 221198#L624-33 assume !(1 == ~t8_pc~0); 221350#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 221358#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 221326#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 221327#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 221579#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 221308#L643-33 assume !(1 == ~t9_pc~0); 221309#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 221397#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 221878#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 221822#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 221823#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221187#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 221188#L1059-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221702#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 221753#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 221754#L1074-3 assume !(1 == ~T4_E~0); 222057#L1079-3 assume !(1 == ~T5_E~0); 221949#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 221876#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 221877#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 221783#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 221784#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 222079#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 222062#L1114-3 assume !(1 == ~E_2~0); 222063#L1119-3 assume !(1 == ~E_3~0); 222380#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 222392#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 221489#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 221490#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 221662#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 221663#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 221828#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 222401#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 221192#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 221080#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 221081#L1459 assume !(0 == start_simulation_~tmp~3#1); 221087#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 222160#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 221369#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 221957#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 221536#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 221537#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 221706#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 221901#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 221281#L1440-2
[2021-11-13 17:47:47,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:47,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1839154805, now seen corresponding path program 1 times
[2021-11-13 17:47:47,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:47,229 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257904568]
[2021-11-13 17:47:47,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:47,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:47,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:47,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:47,289 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:47,289 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257904568]
[2021-11-13 17:47:47,289 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257904568] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:47,289 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:47,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:47,290 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724816333]
[2021-11-13 17:47:47,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:47,290 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:47,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:47,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1419860724, now seen corresponding path program 1 times
[2021-11-13 17:47:47,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:47,291 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050416070]
[2021-11-13 17:47:47,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:47,292 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:47,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:47,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:47,329 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:47,329 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050416070]
[2021-11-13 17:47:47,329 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050416070] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:47,329 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:47,329 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:47,330 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887533282]
[2021-11-13 17:47:47,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:47,331 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:47,331 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:47,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:47,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:47,332 INFO L87 Difference]: Start difference. First operand 51161 states and 72175 transitions. cyclomatic complexity: 21016 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:47,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:47,811 INFO L93 Difference]: Finished difference Result 51161 states and 71981 transitions.
[2021-11-13 17:47:47,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:47,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51161 states and 71981 transitions.
[2021-11-13 17:47:48,061 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:48,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51161 states to 51161 states and 71981 transitions.
[2021-11-13 17:47:48,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51161
[2021-11-13 17:47:48,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51161
[2021-11-13 17:47:48,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51161 states and 71981 transitions.
[2021-11-13 17:47:48,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:48,514 INFO L681 BuchiCegarLoop]: Abstraction has 51161 states and 71981 transitions.
[2021-11-13 17:47:48,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51161 states and 71981 transitions.
[2021-11-13 17:47:49,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51161 to 51161.
[2021-11-13 17:47:49,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51161 states, 51161 states have (on average 1.4069506069076054) internal successors, (71981), 51160 states have internal predecessors, (71981), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:49,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51161 states to 51161 states and 71981 transitions.
[2021-11-13 17:47:49,486 INFO L704 BuchiCegarLoop]: Abstraction has 51161 states and 71981 transitions.
[2021-11-13 17:47:49,486 INFO L587 BuchiCegarLoop]: Abstraction has 51161 states and 71981 transitions.
[2021-11-13 17:47:49,486 INFO L425 BuchiCegarLoop]: ======== Iteration 19============
[2021-11-13 17:47:49,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51161 states and 71981 transitions.
[2021-11-13 17:47:49,736 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:49,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:49,737 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:49,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:49,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:49,750 INFO L791 eck$LassoCheckResult]: Stem: 324339#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 324340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 324726#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 324363#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 324245#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 323965#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 323966#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 324585#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 324644#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 324625#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 324626#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 324087#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 324074#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 324075#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 323883#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 323884#L951 assume !(0 == ~M_E~0); 323618#L951-2 assume !(0 == ~T1_E~0); 323619#L956-1 assume !(0 == ~T2_E~0); 323785#L961-1 assume !(0 == ~T3_E~0); 324262#L966-1 assume !(0 == ~T4_E~0); 324263#L971-1 assume !(0 == ~T5_E~0); 324421#L976-1 assume !(0 == ~T6_E~0); 324391#L981-1 assume !(0 == ~T7_E~0); 324124#L986-1 assume !(0 == ~T8_E~0); 323837#L991-1 assume !(0 == ~T9_E~0); 323838#L996-1 assume !(0 == ~E_M~0); 324703#L1001-1 assume !(0 == ~E_1~0); 324337#L1006-1 assume !(0 == ~E_2~0); 324338#L1011-1 assume !(0 == ~E_3~0); 324645#L1016-1 assume !(0 == ~E_4~0); 324674#L1021-1 assume !(0 == ~E_5~0); 323429#L1026-1 assume !(0 == ~E_6~0); 323430#L1031-1 assume !(0 == ~E_7~0); 324277#L1036-1 assume !(0 == ~E_8~0); 324273#L1041-1 assume !(0 == ~E_9~0); 324274#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 324598#L472 assume !(1 == ~m_pc~0); 324545#L472-2 is_master_triggered_~__retres1~0#1 := 0; 324312#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 324313#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 324324#L1179 assume !(0 != activate_threads_~tmp~1#1); 323437#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323438#L491 assume !(1 == ~t1_pc~0); 323933#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 323934#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 324271#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 323407#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 323408#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323431#L510 assume !(1 == ~t2_pc~0); 323396#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 323397#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 324601#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 324602#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 323672#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323673#L529 assume !(1 == ~t3_pc~0); 324129#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 324448#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 324540#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 324689#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 323594#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323595#L548 assume !(1 == ~t4_pc~0); 323493#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 323492#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323793#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 323533#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 323534#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323481#L567 assume !(1 == ~t5_pc~0); 323482#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 323535#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323721#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 323722#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 324578#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323605#L586 assume !(1 == ~t6_pc~0); 323606#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 323678#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 324720#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 324787#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 324572#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 324573#L605 assume !(1 == ~t7_pc~0); 324101#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 324102#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 324266#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 324267#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 324749#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 324239#L624 assume !(1 == ~t8_pc~0); 323666#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 323665#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 324304#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 324305#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 324549#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 323451#L643 assume !(1 == ~t9_pc~0); 323452#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 324480#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 324393#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 323842#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 323843#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323649#L1059 assume !(1 == ~M_E~0); 323650#L1059-2 assume !(1 == ~T1_E~0); 323813#L1064-1 assume !(1 == ~T2_E~0); 323814#L1069-1 assume !(1 == ~T3_E~0); 324492#L1074-1 assume !(1 == ~T4_E~0); 324547#L1079-1 assume !(1 == ~T5_E~0); 324532#L1084-1 assume !(1 == ~T6_E~0); 324533#L1089-1 assume !(1 == ~T7_E~0); 324565#L1094-1 assume !(1 == ~T8_E~0); 324158#L1099-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 324159#L1104-1 assume !(1 == ~E_M~0); 324378#L1109-1 assume !(1 == ~E_1~0); 323953#L1114-1 assume !(1 == ~E_2~0); 323954#L1119-1 assume !(1 == ~E_3~0); 324016#L1124-1 assume !(1 == ~E_4~0); 323447#L1129-1 assume !(1 == ~E_5~0); 323448#L1134-1 assume !(1 == ~E_6~0); 323781#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 323782#L1144-1 assume !(1 == ~E_8~0); 323973#L1149-1 assume !(1 == ~E_9~0); 323612#L1154-1 assume { :end_inline_reset_delta_events } true; 323613#L1440-2
[2021-11-13 17:47:49,751 INFO L793 eck$LassoCheckResult]: Loop: 323613#L1440-2 assume !false; 355512#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 355508#L926 assume !false; 355506#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 355498#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 355488#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 355487#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 355485#L795 assume !(0 != eval_~tmp~0#1); 355486#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 374270#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 374268#L951-3 assume !(0 == ~M_E~0); 374266#L951-5 assume !(0 == ~T1_E~0); 374264#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 374262#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 374260#L966-3 assume !(0 == ~T4_E~0); 374258#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 374256#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 374254#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 374252#L986-3 assume !(0 == ~T8_E~0); 374250#L991-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 374248#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 374246#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 374244#L1006-3 assume !(0 == ~E_2~0); 374242#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 374240#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 374238#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 374236#L1026-3 assume !(0 == ~E_6~0); 374234#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 374232#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 374230#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 374228#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 374226#L472-33 assume !(1 == ~m_pc~0); 374224#L472-35 is_master_triggered_~__retres1~0#1 := 0; 374222#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 374220#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 374218#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 374216#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 373987#L491-33 assume !(1 == ~t1_pc~0); 373985#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 373983#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 373980#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 373978#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 373976#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 373974#L510-33 assume !(1 == ~t2_pc~0); 373971#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 373968#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 373966#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 373964#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 373962#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 373960#L529-33 assume !(1 == ~t3_pc~0); 358040#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 373956#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 373954#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 373952#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 373950#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 373948#L548-33 assume 1 == ~t4_pc~0; 373945#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 373942#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 373940#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 373938#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 373936#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 373935#L567-33 assume !(1 == ~t5_pc~0); 351346#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 373933#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 324687#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 324688#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 324730#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 372953#L586-33 assume 1 == ~t6_pc~0; 372951#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 372950#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 372939#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 372741#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 372740#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 355641#L605-33 assume !(1 == ~t7_pc~0); 355639#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 355636#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 355634#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 355632#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 355630#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 355628#L624-33 assume 1 == ~t8_pc~0; 355625#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 355623#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 355621#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 355619#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 355617#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 355615#L643-33 assume !(1 == ~t9_pc~0); 349402#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 355611#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 355609#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 355607#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 355605#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 355603#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 355602#L1059-5 assume !(1 == ~T1_E~0); 355600#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 355598#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 355596#L1074-3 assume !(1 == ~T4_E~0); 355594#L1079-3 assume !(1 == ~T5_E~0); 355592#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 355590#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 355588#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 355586#L1099-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 355584#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 355582#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 355580#L1114-3 assume !(1 == ~E_2~0); 355578#L1119-3 assume !(1 == ~E_3~0); 355576#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 355574#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 355572#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 355570#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 355568#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 355566#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 355564#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 355558#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 355548#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 355547#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 355544#L1459 assume !(0 == start_simulation_~tmp~3#1); 355541#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 355535#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 355525#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 355522#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 355520#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355518#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 355516#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 355514#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 323613#L1440-2
[2021-11-13 17:47:49,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:49,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1638164041, now seen corresponding path program 1 times
[2021-11-13 17:47:49,752 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:49,752 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834812817]
[2021-11-13 17:47:49,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:49,753 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:49,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:49,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:49,811 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:49,811 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834812817]
[2021-11-13 17:47:49,811 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834812817] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:49,811 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:49,812 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:49,812 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579682333]
[2021-11-13 17:47:49,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:49,813 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:49,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:49,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1455521547, now seen corresponding path program 1 times
[2021-11-13 17:47:49,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:49,816 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142899534]
[2021-11-13 17:47:49,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:49,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:49,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:49,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:49,856 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:49,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [142899534]
[2021-11-13 17:47:49,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [142899534] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:49,856 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:49,857 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:49,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606901647]
[2021-11-13 17:47:49,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:49,858 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:49,858 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:49,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:49,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:49,859 INFO L87 Difference]: Start difference. First operand 51161 states and 71981 transitions. cyclomatic complexity: 20822 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:50,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:50,090 INFO L93 Difference]: Finished difference Result 51161 states and 71787 transitions.
[2021-11-13 17:47:50,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:50,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51161 states and 71787 transitions.
[2021-11-13 17:47:50,386 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:50,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51161 states to 51161 states and 71787 transitions.
[2021-11-13 17:47:50,612 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51161
[2021-11-13 17:47:50,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51161
[2021-11-13 17:47:50,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51161 states and 71787 transitions.
[2021-11-13 17:47:50,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:50,688 INFO L681 BuchiCegarLoop]: Abstraction has 51161 states and 71787 transitions.
[2021-11-13 17:47:50,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51161 states and 71787 transitions.
[2021-11-13 17:47:51,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51161 to 51161.
[2021-11-13 17:47:51,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51161 states, 51161 states have (on average 1.4031586560075058) internal successors, (71787), 51160 states have internal predecessors, (71787), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:51,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51161 states to 51161 states and 71787 transitions.
[2021-11-13 17:47:51,852 INFO L704 BuchiCegarLoop]: Abstraction has 51161 states and 71787 transitions.
[2021-11-13 17:47:51,852 INFO L587 BuchiCegarLoop]: Abstraction has 51161 states and 71787 transitions.
[2021-11-13 17:47:51,852 INFO L425 BuchiCegarLoop]: ======== Iteration 20============
[2021-11-13 17:47:51,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51161 states and 71787 transitions.
[2021-11-13 17:47:52,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:52,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:52,020 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:52,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:52,031 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:52,031 INFO L791 eck$LassoCheckResult]: Stem: 426661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 426662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 427039#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 426688#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 426571#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 426295#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 426296#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 426893#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 426957#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 426945#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 426946#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 426417#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 426405#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 426406#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 426216#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 426217#L951 assume !(0 == ~M_E~0); 425949#L951-2 assume !(0 == ~T1_E~0); 425950#L956-1 assume !(0 == ~T2_E~0); 426113#L961-1 assume !(0 == ~T3_E~0); 426588#L966-1 assume !(0 == ~T4_E~0); 426589#L971-1 assume !(0 == ~T5_E~0); 426745#L976-1 assume !(0 == ~T6_E~0); 426715#L981-1 assume !(0 == ~T7_E~0); 426457#L986-1 assume !(0 == ~T8_E~0); 426167#L991-1 assume !(0 == ~T9_E~0); 426168#L996-1 assume !(0 == ~E_M~0); 427012#L1001-1 assume !(0 == ~E_1~0); 426659#L1006-1 assume !(0 == ~E_2~0); 426660#L1011-1 assume !(0 == ~E_3~0); 426960#L1016-1 assume !(0 == ~E_4~0); 426985#L1021-1 assume !(0 == ~E_5~0); 425758#L1026-1 assume !(0 == ~E_6~0); 425759#L1031-1 assume !(0 == ~E_7~0); 426604#L1036-1 assume !(0 == ~E_8~0); 426600#L1041-1 assume !(0 == ~E_9~0); 426601#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 426909#L472 assume !(1 == ~m_pc~0); 426855#L472-2 is_master_triggered_~__retres1~0#1 := 0; 426636#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426637#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426646#L1179 assume !(0 != activate_threads_~tmp~1#1); 425766#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425767#L491 assume !(1 == ~t1_pc~0); 426266#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 426267#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 426595#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 425738#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 425739#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425762#L510 assume !(1 == ~t2_pc~0); 425725#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 425726#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426912#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 426913#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 425999#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 426000#L529 assume !(1 == ~t3_pc~0); 426460#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 426773#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 426851#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 427000#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 425922#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425923#L548 assume !(1 == ~t4_pc~0); 425822#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 425821#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 426123#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 425864#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 425865#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 425812#L567 assume !(1 == ~t5_pc~0); 425813#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 425866#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426050#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 426051#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 426887#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425933#L586 assume !(1 == ~t6_pc~0); 425934#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 426007#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 427031#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 427096#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 426880#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 426881#L605 assume !(1 == ~t7_pc~0); 426435#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 426436#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 426592#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 426593#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 427065#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 426565#L624 assume !(1 == ~t8_pc~0); 425993#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 425992#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 426628#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 426629#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 426860#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 425782#L643 assume !(1 == ~t9_pc~0); 425783#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 426801#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 426718#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 426174#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 426175#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425976#L1059 assume !(1 == ~M_E~0); 425977#L1059-2 assume !(1 == ~T1_E~0); 426143#L1064-1 assume !(1 == ~T2_E~0); 426144#L1069-1 assume !(1 == ~T3_E~0); 426809#L1074-1 assume !(1 == ~T4_E~0); 426858#L1079-1 assume !(1 == ~T5_E~0); 426845#L1084-1 assume !(1 == ~T6_E~0); 426846#L1089-1 assume !(1 == ~T7_E~0); 426873#L1094-1 assume !(1 == ~T8_E~0); 426486#L1099-1 assume !(1 == ~T9_E~0); 426487#L1104-1 assume !(1 == ~E_M~0); 426705#L1109-1 assume !(1 == ~E_1~0); 426286#L1114-1 assume !(1 == ~E_2~0); 426287#L1119-1 assume !(1 == ~E_3~0); 426350#L1124-1 assume !(1 == ~E_4~0); 425778#L1129-1 assume !(1 == ~E_5~0); 425779#L1134-1 assume !(1 == ~E_6~0); 426111#L1139-1 assume 1 == ~E_7~0;~E_7~0 := 2; 426112#L1144-1 assume !(1 == ~E_8~0); 426307#L1149-1 assume !(1 == ~E_9~0); 425939#L1154-1 assume { :end_inline_reset_delta_events } true; 425940#L1440-2
[2021-11-13 17:47:52,032 INFO L793 eck$LassoCheckResult]: Loop: 425940#L1440-2 assume !false; 461944#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 461940#L926 assume !false; 461939#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 461937#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 461928#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 461927#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 461925#L795 assume !(0 != eval_~tmp~0#1); 461926#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 476759#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 476757#L951-3 assume !(0 == ~M_E~0); 476754#L951-5 assume !(0 == ~T1_E~0); 476751#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 476748#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 476746#L966-3 assume !(0 == ~T4_E~0); 476743#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 476740#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 476738#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 476735#L986-3 assume !(0 == ~T8_E~0); 476731#L991-3 assume !(0 == ~T9_E~0); 476726#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 476722#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 476718#L1006-3 assume !(0 == ~E_2~0); 476714#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 476710#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 476706#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 476703#L1026-3 assume !(0 == ~E_6~0); 476699#L1031-3 assume 0 == ~E_7~0;~E_7~0 := 1; 476696#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 427078#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 427079#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476692#L472-33 assume !(1 == ~m_pc~0); 425890#L472-35 is_master_triggered_~__retres1~0#1 := 0; 425891#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 426962#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 426763#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 426338#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 426339#L491-33 assume !(1 == ~t1_pc~0); 425828#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 425829#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 426999#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 427024#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 427025#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426709#L510-33 assume !(1 == ~t2_pc~0); 426703#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 426704#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426590#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 426591#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 425718#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 425719#L529-33 assume !(1 == ~t3_pc~0); 426132#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 426012#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 426013#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 426993#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 425844#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425845#L548-33 assume 1 == ~t4_pc~0; 426087#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 426215#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 426256#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 426257#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 426023#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 426024#L567-33 assume !(1 == ~t5_pc~0); 473734#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 473732#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 473729#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 473730#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 475739#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 475737#L586-33 assume 1 == ~t6_pc~0; 473719#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 473717#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 473715#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 473713#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 473711#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 467057#L605-33 assume !(1 == ~t7_pc~0); 467054#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 466989#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 462113#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 462112#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 462111#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 462110#L624-33 assume !(1 == ~t8_pc~0); 462108#L624-35 is_transmit8_triggered_~__retres1~8#1 := 0; 462105#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 462103#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 462101#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 462099#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 462097#L643-33 assume !(1 == ~t9_pc~0); 462096#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 462094#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 462092#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 462090#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 462088#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462086#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 462084#L1059-5 assume !(1 == ~T1_E~0); 462082#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 462080#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 462078#L1074-3 assume !(1 == ~T4_E~0); 462076#L1079-3 assume !(1 == ~T5_E~0); 462074#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 462072#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 462070#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 462068#L1099-3 assume !(1 == ~T9_E~0); 462066#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 462064#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 462062#L1114-3 assume !(1 == ~E_2~0); 462060#L1119-3 assume !(1 == ~E_3~0); 462058#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 462056#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 462054#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 462052#L1139-3 assume 1 == ~E_7~0;~E_7~0 := 2; 462049#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 462046#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 462043#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 462026#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 462017#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 462013#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 462010#L1459 assume !(0 == start_simulation_~tmp~3#1); 462008#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 462005#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 461990#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 461983#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 461974#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 461967#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 461959#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 461953#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 425940#L1440-2
[2021-11-13 17:47:52,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:52,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1896329479, now seen corresponding path program 1 times
[2021-11-13 17:47:52,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:52,033 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325928405]
[2021-11-13 17:47:52,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:52,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:52,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:52,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:52,071 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:52,071 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325928405]
[2021-11-13 17:47:52,072 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325928405] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:52,072 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:52,072 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:52,072 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131279455]
[2021-11-13 17:47:52,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:52,073 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:52,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:52,073 INFO L85 PathProgramCache]: Analyzing trace with hash 566471820, now seen corresponding path program 1 times
[2021-11-13 17:47:52,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:52,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842782719]
[2021-11-13 17:47:52,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:52,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:52,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:52,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:52,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:52,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842782719]
[2021-11-13 17:47:52,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842782719] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:52,105 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:52,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:52,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462334780]
[2021-11-13 17:47:52,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:52,106 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:52,106 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:52,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:52,106 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:52,107 INFO L87 Difference]: Start difference. First operand 51161 states and 71787 transitions. cyclomatic complexity: 20628 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:52,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:52,807 INFO L93 Difference]: Finished difference Result 51161 states and 71321 transitions.
[2021-11-13 17:47:52,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:52,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51161 states and 71321 transitions.
[2021-11-13 17:47:52,995 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:53,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51161 states to 51161 states and 71321 transitions.
[2021-11-13 17:47:53,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51161
[2021-11-13 17:47:53,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51161
[2021-11-13 17:47:53,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51161 states and 71321 transitions.
[2021-11-13 17:47:53,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:53,222 INFO L681 BuchiCegarLoop]: Abstraction has 51161 states and 71321 transitions.
[2021-11-13 17:47:53,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51161 states and 71321 transitions.
[2021-11-13 17:47:53,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51161 to 51161.
[2021-11-13 17:47:54,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51161 states, 51161 states have (on average 1.3940501553918023) internal successors, (71321), 51160 states have internal predecessors, (71321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:54,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51161 states to 51161 states and 71321 transitions.
[2021-11-13 17:47:54,175 INFO L704 BuchiCegarLoop]: Abstraction has 51161 states and 71321 transitions.
[2021-11-13 17:47:54,175 INFO L587 BuchiCegarLoop]: Abstraction has 51161 states and 71321 transitions.
[2021-11-13 17:47:54,175 INFO L425 BuchiCegarLoop]: ======== Iteration 21============
[2021-11-13 17:47:54,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51161 states and 71321 transitions.
[2021-11-13 17:47:54,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:54,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:54,337 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:54,345 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:54,345 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:54,345 INFO L791 eck$LassoCheckResult]: Stem: 528986#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 528987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 529361#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 529011#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 528898#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 528618#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 528619#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 529222#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 529285#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 529268#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 529269#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 528738#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 528727#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 528728#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 528539#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 528540#L951 assume !(0 == ~M_E~0); 528275#L951-2 assume !(0 == ~T1_E~0); 528276#L956-1 assume !(0 == ~T2_E~0); 528440#L961-1 assume !(0 == ~T3_E~0); 528913#L966-1 assume !(0 == ~T4_E~0); 528914#L971-1 assume !(0 == ~T5_E~0); 529070#L976-1 assume !(0 == ~T6_E~0); 529039#L981-1 assume !(0 == ~T7_E~0); 528777#L986-1 assume !(0 == ~T8_E~0); 528493#L991-1 assume !(0 == ~T9_E~0); 528494#L996-1 assume !(0 == ~E_M~0); 529335#L1001-1 assume !(0 == ~E_1~0); 528984#L1006-1 assume !(0 == ~E_2~0); 528985#L1011-1 assume !(0 == ~E_3~0); 529286#L1016-1 assume !(0 == ~E_4~0); 529309#L1021-1 assume !(0 == ~E_5~0); 528087#L1026-1 assume !(0 == ~E_6~0); 528088#L1031-1 assume !(0 == ~E_7~0); 528928#L1036-1 assume !(0 == ~E_8~0); 528924#L1041-1 assume !(0 == ~E_9~0); 528925#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 529234#L472 assume !(1 == ~m_pc~0); 529181#L472-2 is_master_triggered_~__retres1~0#1 := 0; 528961#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 528962#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 528972#L1179 assume !(0 != activate_threads_~tmp~1#1); 528095#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 528096#L491 assume !(1 == ~t1_pc~0); 528589#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 528590#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 528922#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 528067#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 528068#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 528089#L510 assume !(1 == ~t2_pc~0); 528054#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 528055#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 529237#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 529238#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 528329#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 528330#L529 assume !(1 == ~t3_pc~0); 528783#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 529094#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 529175#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 529320#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 528251#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 528252#L548 assume !(1 == ~t4_pc~0); 528151#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 528150#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 528448#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 528191#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 528192#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 528139#L567 assume !(1 == ~t5_pc~0); 528140#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 528193#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 528379#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 528380#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 529214#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528262#L586 assume !(1 == ~t6_pc~0); 528263#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 528335#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 529353#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 529417#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 529206#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 529207#L605 assume !(1 == ~t7_pc~0); 528752#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 528753#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 528917#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 528918#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 529384#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 528892#L624 assume !(1 == ~t8_pc~0); 528323#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 528322#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 528953#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 528954#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 529184#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 528109#L643 assume !(1 == ~t9_pc~0); 528110#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 529124#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 529041#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 528500#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 528501#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 528306#L1059 assume !(1 == ~M_E~0); 528307#L1059-2 assume !(1 == ~T1_E~0); 528470#L1064-1 assume !(1 == ~T2_E~0); 528471#L1069-1 assume !(1 == ~T3_E~0); 529134#L1074-1 assume !(1 == ~T4_E~0); 529182#L1079-1 assume !(1 == ~T5_E~0); 529169#L1084-1 assume !(1 == ~T6_E~0); 529170#L1089-1 assume !(1 == ~T7_E~0); 529199#L1094-1 assume !(1 == ~T8_E~0); 528810#L1099-1 assume !(1 == ~T9_E~0); 528811#L1104-1 assume !(1 == ~E_M~0); 529026#L1109-1 assume !(1 == ~E_1~0); 528609#L1114-1 assume !(1 == ~E_2~0); 528610#L1119-1 assume !(1 == ~E_3~0); 528667#L1124-1 assume !(1 == ~E_4~0); 528105#L1129-1 assume !(1 == ~E_5~0); 528106#L1134-1 assume !(1 == ~E_6~0); 528436#L1139-1 assume !(1 == ~E_7~0); 528437#L1144-1 assume !(1 == ~E_8~0); 528628#L1149-1 assume !(1 == ~E_9~0); 528269#L1154-1 assume { :end_inline_reset_delta_events } true; 528270#L1440-2
[2021-11-13 17:47:54,346 INFO L793 eck$LassoCheckResult]: Loop: 528270#L1440-2 assume !false; 565577#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 565568#L926 assume !false; 565564#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 565374#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 565359#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 565351#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 565344#L795 assume !(0 != eval_~tmp~0#1); 565345#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 577720#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 577718#L951-3 assume !(0 == ~M_E~0); 577716#L951-5 assume !(0 == ~T1_E~0); 577713#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 577711#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 577709#L966-3 assume !(0 == ~T4_E~0); 577707#L971-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 577705#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 577703#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 577701#L986-3 assume !(0 == ~T8_E~0); 577700#L991-3 assume !(0 == ~T9_E~0); 577698#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 576565#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 576562#L1006-3 assume !(0 == ~E_2~0); 576560#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 576558#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 576556#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 576554#L1026-3 assume !(0 == ~E_6~0); 576552#L1031-3 assume !(0 == ~E_7~0); 576550#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 576549#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 576548#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 576547#L472-33 assume !(1 == ~m_pc~0); 576546#L472-35 is_master_triggered_~__retres1~0#1 := 0; 576545#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 576543#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 576517#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 576516#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 576515#L491-33 assume !(1 == ~t1_pc~0); 575774#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 570639#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 570640#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 570634#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 570635#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 570629#L510-33 assume !(1 == ~t2_pc~0); 570628#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 570620#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570621#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 570614#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 570615#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 568188#L529-33 assume !(1 == ~t3_pc~0); 568187#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 568186#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 568185#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 568182#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 568179#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 568176#L548-33 assume 1 == ~t4_pc~0; 568172#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 568169#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 568166#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 568163#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 568162#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 566055#L567-33 assume !(1 == ~t5_pc~0); 566042#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 565983#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 565979#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 565904#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 565898#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565878#L586-33 assume 1 == ~t6_pc~0; 565871#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 565786#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 565783#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 565781#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 565779#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 565777#L605-33 assume !(1 == ~t7_pc~0); 562090#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 565774#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 565773#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 565771#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 565769#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 565767#L624-33 assume 1 == ~t8_pc~0; 565764#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 565761#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 565759#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 565757#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 565755#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 565753#L643-33 assume !(1 == ~t9_pc~0); 554087#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 565749#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 565748#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 565745#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 565743#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 565741#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 565739#L1059-5 assume !(1 == ~T1_E~0); 565737#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 565735#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 565732#L1074-3 assume !(1 == ~T4_E~0); 565730#L1079-3 assume !(1 == ~T5_E~0); 565728#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 565726#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 565724#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 565722#L1099-3 assume !(1 == ~T9_E~0); 565721#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 565719#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 565717#L1114-3 assume !(1 == ~E_2~0); 565715#L1119-3 assume !(1 == ~E_3~0); 565713#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 565711#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 565708#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 565706#L1139-3 assume !(1 == ~E_7~0); 565704#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 565702#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 565700#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 565693#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 565683#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 565681#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 565678#L1459 assume !(0 == start_simulation_~tmp~3#1); 565675#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 565610#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 565600#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 565598#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 565596#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 565594#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 565592#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 565590#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 528270#L1440-2
[2021-11-13 17:47:54,347 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:54,347 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 1 times
[2021-11-13 17:47:54,347 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:54,347 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653139084]
[2021-11-13 17:47:54,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:54,348 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:54,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:47:54,360 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:47:54,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:47:54,450 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:47:54,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:54,451 INFO L85 PathProgramCache]: Analyzing trace with hash 2019952267, now seen corresponding path program 1 times
[2021-11-13 17:47:54,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:54,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246802002]
[2021-11-13 17:47:54,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:54,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:54,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:54,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:54,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:54,482 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246802002]
[2021-11-13 17:47:54,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246802002] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:54,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:54,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:54,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [713758905]
[2021-11-13 17:47:54,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:54,483 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:54,483 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:54,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:54,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:54,484 INFO L87 Difference]: Start difference. First operand 51161 states and 71321 transitions. cyclomatic complexity: 20162 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:54,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:54,685 INFO L93 Difference]: Finished difference Result 56878 states and 79340 transitions.
[2021-11-13 17:47:54,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:54,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56878 states and 79340 transitions.
[2021-11-13 17:47:54,888 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640
[2021-11-13 17:47:55,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56878 states to 56878 states and 79340 transitions.
[2021-11-13 17:47:55,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56878
[2021-11-13 17:47:55,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56878
[2021-11-13 17:47:55,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56878 states and 79340 transitions.
[2021-11-13 17:47:55,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:55,485 INFO L681 BuchiCegarLoop]: Abstraction has 56878 states and 79340 transitions.
[2021-11-13 17:47:55,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56878 states and 79340 transitions.
[2021-11-13 17:47:55,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56878 to 56878.
[2021-11-13 17:47:55,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56878 states, 56878 states have (on average 1.3949154330321039) internal successors, (79340), 56877 states have internal predecessors, (79340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:56,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56878 states to 56878 states and 79340 transitions.
[2021-11-13 17:47:56,107 INFO L704 BuchiCegarLoop]: Abstraction has 56878 states and 79340 transitions.
[2021-11-13 17:47:56,107 INFO L587 BuchiCegarLoop]: Abstraction has 56878 states and 79340 transitions.
[2021-11-13 17:47:56,107 INFO L425 BuchiCegarLoop]: ======== Iteration 22============
[2021-11-13 17:47:56,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56878 states and 79340 transitions.
[2021-11-13 17:47:56,275 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640
[2021-11-13 17:47:56,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:56,275 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:56,282 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:56,283 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:56,283 INFO L791 eck$LassoCheckResult]: Stem: 637033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 637034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 637444#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 637061#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 636944#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 636671#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 636672#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 637288#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 637353#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 637337#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 637338#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 636793#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 636782#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 636783#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 636589#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 636590#L951 assume !(0 == ~M_E~0); 636320#L951-2 assume !(0 == ~T1_E~0); 636321#L956-1 assume !(0 == ~T2_E~0); 636487#L961-1 assume !(0 == ~T3_E~0); 636959#L966-1 assume !(0 == ~T4_E~0); 636960#L971-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 637124#L976-1 assume !(0 == ~T6_E~0); 637469#L981-1 assume !(0 == ~T7_E~0); 637575#L986-1 assume !(0 == ~T8_E~0); 637574#L991-1 assume !(0 == ~T9_E~0); 637490#L996-1 assume !(0 == ~E_M~0); 637415#L1001-1 assume !(0 == ~E_1~0); 637416#L1006-1 assume !(0 == ~E_2~0); 637572#L1011-1 assume !(0 == ~E_3~0); 637571#L1016-1 assume !(0 == ~E_4~0); 637476#L1021-1 assume !(0 == ~E_5~0); 636132#L1026-1 assume !(0 == ~E_6~0); 636133#L1031-1 assume !(0 == ~E_7~0); 636975#L1036-1 assume !(0 == ~E_8~0); 636971#L1041-1 assume !(0 == ~E_9~0); 636972#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 637303#L472 assume !(1 == ~m_pc~0); 637567#L472-2 is_master_triggered_~__retres1~0#1 := 0; 637009#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 637010#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 637443#L1179 assume !(0 != activate_threads_~tmp~1#1); 637565#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 637564#L491 assume !(1 == ~t1_pc~0); 636640#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 636641#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 636968#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 636110#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 636111#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 636134#L510 assume !(1 == ~t2_pc~0); 636099#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 636100#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 637306#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 637307#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 636376#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 636377#L529 assume !(1 == ~t3_pc~0); 636835#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 637153#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 637237#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 637401#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 637550#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 637491#L548 assume !(1 == ~t4_pc~0); 636196#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 636195#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 636495#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 636236#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 636237#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 636184#L567 assume !(1 == ~t5_pc~0); 636185#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 637480#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 636426#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 636427#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 637281#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 636308#L586 assume !(1 == ~t6_pc~0); 636309#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 637538#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 637537#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 637536#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 637535#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 637489#L605 assume !(1 == ~t7_pc~0); 636806#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 636807#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 637533#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 637482#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 637483#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 637532#L624 assume !(1 == ~t8_pc~0); 636369#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 636368#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 637074#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 637530#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 637529#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 637528#L643 assume !(1 == ~t9_pc~0); 637527#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 637526#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 637525#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 637524#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 637523#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 637522#L1059 assume !(1 == ~M_E~0); 637521#L1059-2 assume !(1 == ~T1_E~0); 637520#L1064-1 assume !(1 == ~T2_E~0); 637519#L1069-1 assume !(1 == ~T3_E~0); 637468#L1074-1 assume !(1 == ~T4_E~0); 637246#L1079-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 637230#L1084-1 assume !(1 == ~T6_E~0); 637231#L1089-1 assume !(1 == ~T7_E~0); 637266#L1094-1 assume !(1 == ~T8_E~0); 636859#L1099-1 assume !(1 == ~T9_E~0); 636860#L1104-1 assume !(1 == ~E_M~0); 637079#L1109-1 assume !(1 == ~E_1~0); 636659#L1114-1 assume !(1 == ~E_2~0); 636660#L1119-1 assume !(1 == ~E_3~0); 636721#L1124-1 assume !(1 == ~E_4~0); 636150#L1129-1 assume !(1 == ~E_5~0); 636151#L1134-1 assume !(1 == ~E_6~0); 636483#L1139-1 assume !(1 == ~E_7~0); 636484#L1144-1 assume !(1 == ~E_8~0); 636679#L1149-1 assume !(1 == ~E_9~0); 636314#L1154-1 assume { :end_inline_reset_delta_events } true; 636315#L1440-2
[2021-11-13 17:47:56,284 INFO L793 eck$LassoCheckResult]: Loop: 636315#L1440-2 assume !false; 670722#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 670719#L926 assume !false; 670717#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 670709#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 670699#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 670697#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 670695#L795 assume !(0 != eval_~tmp~0#1); 670696#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 692670#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 692668#L951-3 assume !(0 == ~M_E~0); 692666#L951-5 assume !(0 == ~T1_E~0); 692664#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 692662#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 692659#L966-3 assume !(0 == ~T4_E~0); 692656#L971-3 assume !(0 == ~T5_E~0); 692654#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 692652#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 692650#L986-3 assume !(0 == ~T8_E~0); 692648#L991-3 assume !(0 == ~T9_E~0); 692646#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 692644#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 692642#L1006-3 assume !(0 == ~E_2~0); 692640#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 692638#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 692636#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 692634#L1026-3 assume !(0 == ~E_6~0); 692632#L1031-3 assume !(0 == ~E_7~0); 692630#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 692628#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 692626#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 692624#L472-33 assume !(1 == ~m_pc~0); 692622#L472-35 is_master_triggered_~__retres1~0#1 := 0; 692620#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 692618#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 692616#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 692614#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 692613#L491-33 assume !(1 == ~t1_pc~0); 691999#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 692610#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 692608#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 692606#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 692603#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 692601#L510-33 assume !(1 == ~t2_pc~0); 692599#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 692598#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 692597#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 692596#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 692595#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 692594#L529-33 assume !(1 == ~t3_pc~0); 692530#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 692593#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 692592#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 692591#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 692590#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 692589#L548-33 assume 1 == ~t4_pc~0; 690808#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 690806#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690804#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 690505#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 690504#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 677357#L567-33 assume !(1 == ~t5_pc~0); 677356#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 677355#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 677301#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 677297#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 677292#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 677287#L586-33 assume 1 == ~t6_pc~0; 677283#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 677281#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 677279#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 677277#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 677275#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 677273#L605-33 assume !(1 == ~t7_pc~0); 670179#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 677270#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 677267#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 677265#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 677263#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 677261#L624-33 assume 1 == ~t8_pc~0; 677258#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 677256#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 677253#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 677251#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 677249#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 677247#L643-33 assume !(1 == ~t9_pc~0); 676285#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 677244#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 677243#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 677241#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 677239#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 677237#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 677235#L1059-5 assume !(1 == ~T1_E~0); 677233#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 677230#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 677228#L1074-3 assume !(1 == ~T4_E~0); 677041#L1079-3 assume !(1 == ~T5_E~0); 677039#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 677037#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 677035#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 677032#L1099-3 assume !(1 == ~T9_E~0); 677030#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 677028#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 677026#L1114-3 assume !(1 == ~E_2~0); 677022#L1119-3 assume !(1 == ~E_3~0); 677011#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 677009#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 677007#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 677005#L1139-3 assume !(1 == ~E_7~0); 677003#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 677001#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 676999#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 670768#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 670759#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 670756#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 670754#L1459 assume !(0 == start_simulation_~tmp~3#1); 670751#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 670746#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 670736#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 670734#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 670731#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 670729#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 670727#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 670725#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 636315#L1440-2
[2021-11-13 17:47:56,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:56,285 INFO L85 PathProgramCache]: Analyzing trace with hash 1316386309, now seen corresponding path program 1 times
[2021-11-13 17:47:56,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:56,285 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483896914]
[2021-11-13 17:47:56,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:56,286 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:56,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:56,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:56,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:56,315 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483896914]
[2021-11-13 17:47:56,315 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483896914] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:56,315 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:56,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:47:56,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871863611]
[2021-11-13 17:47:56,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:56,316 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:47:56,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:56,317 INFO L85 PathProgramCache]: Analyzing trace with hash 981367693, now seen corresponding path program 1 times
[2021-11-13 17:47:56,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:56,317 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895966529]
[2021-11-13 17:47:56,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:56,318 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:56,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:56,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:56,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:56,354 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895966529]
[2021-11-13 17:47:56,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895966529] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:56,355 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:56,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:56,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351814040]
[2021-11-13 17:47:56,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:56,356 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:56,356 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:56,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:56,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:56,357 INFO L87 Difference]: Start difference. First operand 56878 states and 79340 transitions. cyclomatic complexity: 22464 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:56,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:56,594 INFO L93 Difference]: Finished difference Result 51161 states and 71127 transitions.
[2021-11-13 17:47:56,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:56,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51161 states and 71127 transitions.
[2021-11-13 17:47:57,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:57,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51161 states to 51161 states and 71127 transitions.
[2021-11-13 17:47:57,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51161
[2021-11-13 17:47:57,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51161
[2021-11-13 17:47:57,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51161 states and 71127 transitions.
[2021-11-13 17:47:57,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:57,459 INFO L681 BuchiCegarLoop]: Abstraction has 51161 states and 71127 transitions.
[2021-11-13 17:47:57,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51161 states and 71127 transitions.
[2021-11-13 17:47:57,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51161 to 51161.
[2021-11-13 17:47:57,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51161 states, 51161 states have (on average 1.3902582044917027) internal successors, (71127), 51160 states have internal predecessors, (71127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:57,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51161 states to 51161 states and 71127 transitions.
[2021-11-13 17:47:57,942 INFO L704 BuchiCegarLoop]: Abstraction has 51161 states and 71127 transitions.
[2021-11-13 17:47:57,942 INFO L587 BuchiCegarLoop]: Abstraction has 51161 states and 71127 transitions.
[2021-11-13 17:47:57,942 INFO L425 BuchiCegarLoop]: ======== Iteration 23============
[2021-11-13 17:47:57,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51161 states and 71127 transitions.
[2021-11-13 17:47:58,078 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51008
[2021-11-13 17:47:58,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:47:58,078 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:47:58,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:58,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:47:58,085 INFO L791 eck$LassoCheckResult]: Stem: 745071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 745072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 745455#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 745095#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 744988#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 744710#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 744711#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 745316#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 745378#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 745362#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 745363#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 744833#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 744822#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 744823#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 744631#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 744632#L951 assume !(0 == ~M_E~0); 744367#L951-2 assume !(0 == ~T1_E~0); 744368#L956-1 assume !(0 == ~T2_E~0); 744530#L961-1 assume !(0 == ~T3_E~0); 745003#L966-1 assume !(0 == ~T4_E~0); 745004#L971-1 assume !(0 == ~T5_E~0); 745152#L976-1 assume !(0 == ~T6_E~0); 745122#L981-1 assume !(0 == ~T7_E~0); 744871#L986-1 assume !(0 == ~T8_E~0); 744582#L991-1 assume !(0 == ~T9_E~0); 744583#L996-1 assume !(0 == ~E_M~0); 745428#L1001-1 assume !(0 == ~E_1~0); 745069#L1006-1 assume !(0 == ~E_2~0); 745070#L1011-1 assume !(0 == ~E_3~0); 745379#L1016-1 assume !(0 == ~E_4~0); 745402#L1021-1 assume !(0 == ~E_5~0); 744178#L1026-1 assume !(0 == ~E_6~0); 744179#L1031-1 assume !(0 == ~E_7~0); 745018#L1036-1 assume !(0 == ~E_8~0); 745014#L1041-1 assume !(0 == ~E_9~0); 745015#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745332#L472 assume !(1 == ~m_pc~0); 745271#L472-2 is_master_triggered_~__retres1~0#1 := 0; 745048#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 745049#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 745058#L1179 assume !(0 != activate_threads_~tmp~1#1); 744186#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 744187#L491 assume !(1 == ~t1_pc~0); 744682#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 744683#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745012#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 744156#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 744157#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 744180#L510 assume !(1 == ~t2_pc~0); 744145#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 744146#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 745335#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 745336#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 744421#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 744422#L529 assume !(1 == ~t3_pc~0); 744876#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 745179#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 745266#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 745416#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 744344#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 744345#L548 assume !(1 == ~t4_pc~0); 744244#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 744243#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 744538#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 744284#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 744285#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 744232#L567 assume !(1 == ~t5_pc~0); 744233#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 744286#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 744469#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 744470#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 745310#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 744355#L586 assume !(1 == ~t6_pc~0); 744356#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 744427#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 745446#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 745512#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 745301#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 745302#L605 assume !(1 == ~t7_pc~0); 744847#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 744848#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 745007#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 745008#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 745478#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 744982#L624 assume !(1 == ~t8_pc~0); 744415#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 744414#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 745042#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 745043#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 745275#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 744200#L643 assume !(1 == ~t9_pc~0); 744201#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 745210#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 745124#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 744587#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 744588#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 744398#L1059 assume !(1 == ~M_E~0); 744399#L1059-2 assume !(1 == ~T1_E~0); 744559#L1064-1 assume !(1 == ~T2_E~0); 744560#L1069-1 assume !(1 == ~T3_E~0); 745221#L1074-1 assume !(1 == ~T4_E~0); 745272#L1079-1 assume !(1 == ~T5_E~0); 745259#L1084-1 assume !(1 == ~T6_E~0); 745260#L1089-1 assume !(1 == ~T7_E~0); 745292#L1094-1 assume !(1 == ~T8_E~0); 744903#L1099-1 assume !(1 == ~T9_E~0); 744904#L1104-1 assume !(1 == ~E_M~0); 745110#L1109-1 assume !(1 == ~E_1~0); 744702#L1114-1 assume !(1 == ~E_2~0); 744703#L1119-1 assume !(1 == ~E_3~0); 744760#L1124-1 assume !(1 == ~E_4~0); 744196#L1129-1 assume !(1 == ~E_5~0); 744197#L1134-1 assume !(1 == ~E_6~0); 744526#L1139-1 assume !(1 == ~E_7~0); 744527#L1144-1 assume !(1 == ~E_8~0); 744718#L1149-1 assume !(1 == ~E_9~0); 744361#L1154-1 assume { :end_inline_reset_delta_events } true; 744362#L1440-2
[2021-11-13 17:47:58,085 INFO L793 eck$LassoCheckResult]: Loop: 744362#L1440-2 assume !false; 782405#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 782395#L926 assume !false; 782389#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 782380#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 782369#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 782366#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 782362#L795 assume !(0 != eval_~tmp~0#1); 782363#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 795110#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 795108#L951-3 assume !(0 == ~M_E~0); 795106#L951-5 assume !(0 == ~T1_E~0); 795105#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 795104#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 795103#L966-3 assume !(0 == ~T4_E~0); 795101#L971-3 assume !(0 == ~T5_E~0); 795100#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 795097#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 795095#L986-3 assume !(0 == ~T8_E~0); 795093#L991-3 assume !(0 == ~T9_E~0); 795091#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 795089#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 795087#L1006-3 assume !(0 == ~E_2~0); 795086#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 795084#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 795082#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 795080#L1026-3 assume !(0 == ~E_6~0); 795078#L1031-3 assume !(0 == ~E_7~0); 795076#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 745488#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 745489#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 795003#L472-33 assume !(1 == ~m_pc~0); 795002#L472-35 is_master_triggered_~__retres1~0#1 := 0; 795001#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 794999#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 745171#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 744751#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 744752#L491-33 assume !(1 == ~t1_pc~0); 794232#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 794230#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 794228#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 794226#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 794224#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 794221#L510-33 assume !(1 == ~t2_pc~0); 794218#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 794216#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 794214#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 794212#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 794126#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 789979#L529-33 assume !(1 == ~t3_pc~0); 789976#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 789974#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 789972#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 789970#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 789967#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 789927#L548-33 assume 1 == ~t4_pc~0; 789920#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 789916#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 789914#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 789912#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 789910#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 789711#L567-33 assume !(1 == ~t5_pc~0); 777216#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 789687#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 789682#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 789677#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 789672#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 789666#L586-33 assume !(1 == ~t6_pc~0); 789660#L586-35 is_transmit6_triggered_~__retres1~6#1 := 0; 789653#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 789646#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 789641#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 789592#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 782760#L605-33 assume !(1 == ~t7_pc~0); 782756#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 782753#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 782750#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 782747#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 782744#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 782741#L624-33 assume 1 == ~t8_pc~0; 782739#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 782736#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 782733#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 782730#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 782727#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 782723#L643-33 assume !(1 == ~t9_pc~0); 773467#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 782717#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 782713#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 782709#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 782704#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 782699#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 782695#L1059-5 assume !(1 == ~T1_E~0); 782690#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 782684#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 782679#L1074-3 assume !(1 == ~T4_E~0); 782673#L1079-3 assume !(1 == ~T5_E~0); 782668#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 782662#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 782657#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 782653#L1099-3 assume !(1 == ~T9_E~0); 782648#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 782643#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 782638#L1114-3 assume !(1 == ~E_2~0); 782635#L1119-3 assume !(1 == ~E_3~0); 782634#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 782633#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 782632#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 782631#L1139-3 assume !(1 == ~E_7~0); 782630#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 782629#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 782628#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 782504#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 782493#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 782491#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 782488#L1459 assume !(0 == start_simulation_~tmp~3#1); 782485#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 782480#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 782465#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 782459#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 782453#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 782448#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 782439#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 782433#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 744362#L1440-2
[2021-11-13 17:47:58,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:58,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 2 times
[2021-11-13 17:47:58,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:58,086 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102944757]
[2021-11-13 17:47:58,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:58,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:58,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:47:58,098 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:47:58,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:47:58,174 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:47:58,174 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:47:58,174 INFO L85 PathProgramCache]: Analyzing trace with hash 1221635022, now seen corresponding path program 1 times
[2021-11-13 17:47:58,175 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:47:58,175 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847453597]
[2021-11-13 17:47:58,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:47:58,175 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:47:58,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:47:58,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:47:58,210 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:47:58,210 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847453597]
[2021-11-13 17:47:58,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847453597] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:47:58,210 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:47:58,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:47:58,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215879945]
[2021-11-13 17:47:58,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:47:58,211 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:47:58,212 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:47:58,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:47:58,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:47:58,212 INFO L87 Difference]: Start difference. First operand 51161 states and 71127 transitions. cyclomatic complexity: 19968 Second operand has 3 states, 3 states have (on average 41.333333333333336) internal successors, (124), 3 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:47:58,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:47:58,916 INFO L93 Difference]: Finished difference Result 91374 states and 126265 transitions.
[2021-11-13 17:47:58,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:47:58,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91374 states and 126265 transitions.
[2021-11-13 17:47:59,221 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 91104
[2021-11-13 17:47:59,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91374 states to 91374 states and 126265 transitions.
[2021-11-13 17:47:59,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91374
[2021-11-13 17:47:59,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91374
[2021-11-13 17:47:59,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91374 states and 126265 transitions.
[2021-11-13 17:47:59,477 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:47:59,477 INFO L681 BuchiCegarLoop]: Abstraction has 91374 states and 126265 transitions.
[2021-11-13 17:47:59,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91374 states and 126265 transitions.
[2021-11-13 17:48:00,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91374 to 91310.
[2021-11-13 17:48:00,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91310 states, 91310 states have (on average 1.3821158690176323) internal successors, (126201), 91309 states have internal predecessors, (126201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:00,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91310 states to 91310 states and 126201 transitions.
[2021-11-13 17:48:00,666 INFO L704 BuchiCegarLoop]: Abstraction has 91310 states and 126201 transitions.
[2021-11-13 17:48:00,666 INFO L587 BuchiCegarLoop]: Abstraction has 91310 states and 126201 transitions.
[2021-11-13 17:48:00,666 INFO L425 BuchiCegarLoop]: ======== Iteration 24============
[2021-11-13 17:48:00,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91310 states and 126201 transitions.
[2021-11-13 17:48:00,891 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 91040
[2021-11-13 17:48:00,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:00,891 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:00,897 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:00,897 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:00,898 INFO L791 eck$LassoCheckResult]: Stem: 887623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 887624#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 888046#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 887652#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 887532#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 887254#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 887255#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 887876#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 887946#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 887928#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 887929#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 887372#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 887361#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 887362#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 887173#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 887174#L951 assume !(0 == ~M_E~0); 886907#L951-2 assume !(0 == ~T1_E~0); 886908#L956-1 assume !(0 == ~T2_E~0); 887073#L961-1 assume !(0 == ~T3_E~0); 887548#L966-1 assume !(0 == ~T4_E~0); 887549#L971-1 assume !(0 == ~T5_E~0); 887714#L976-1 assume !(0 == ~T6_E~0); 887682#L981-1 assume !(0 == ~T7_E~0); 887408#L986-1 assume !(0 == ~T8_E~0); 887125#L991-1 assume !(0 == ~T9_E~0); 887126#L996-1 assume !(0 == ~E_M~0); 888016#L1001-1 assume !(0 == ~E_1~0); 887621#L1006-1 assume !(0 == ~E_2~0); 887622#L1011-1 assume 0 == ~E_3~0;~E_3~0 := 1; 887947#L1016-1 assume !(0 == ~E_4~0); 888076#L1021-1 assume !(0 == ~E_5~0); 888077#L1026-1 assume !(0 == ~E_6~0); 888115#L1031-1 assume !(0 == ~E_7~0); 888116#L1036-1 assume !(0 == ~E_8~0); 888186#L1041-1 assume !(0 == ~E_9~0); 888185#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 888070#L472 assume !(1 == ~m_pc~0); 887832#L472-2 is_master_triggered_~__retres1~0#1 := 0; 887833#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 888183#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 887610#L1179 assume !(0 != activate_threads_~tmp~1#1); 886727#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 886728#L491 assume !(1 == ~t1_pc~0); 887923#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 887693#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 887557#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 887558#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 886720#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 886721#L510 assume !(1 == ~t2_pc~0); 886686#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 886687#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 887890#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 887891#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 886961#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 886962#L529 assume !(1 == ~t3_pc~0); 887413#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 887741#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 887826#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 888002#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 886884#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 886885#L548 assume !(1 == ~t4_pc~0); 886783#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 886782#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 887082#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 886823#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 886824#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 886771#L567 assume !(1 == ~t5_pc~0); 886772#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 888081#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 887010#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 887011#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 887870#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 886895#L586 assume !(1 == ~t6_pc~0); 886896#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 888161#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 888160#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 888159#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 888158#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 888093#L605 assume !(1 == ~t7_pc~0); 887386#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 887387#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 888156#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 888082#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 888083#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 888155#L624 assume !(1 == ~t8_pc~0); 886955#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 886954#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 887590#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 887591#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 887836#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 888151#L643 assume !(1 == ~t9_pc~0); 888150#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 888149#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 888148#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 887130#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 887131#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 886938#L1059 assume !(1 == ~M_E~0); 886939#L1059-2 assume !(1 == ~T1_E~0); 887102#L1064-1 assume !(1 == ~T2_E~0); 887103#L1069-1 assume !(1 == ~T3_E~0); 887784#L1074-1 assume !(1 == ~T4_E~0); 887834#L1079-1 assume !(1 == ~T5_E~0); 887820#L1084-1 assume !(1 == ~T6_E~0); 887821#L1089-1 assume !(1 == ~T7_E~0); 887855#L1094-1 assume !(1 == ~T8_E~0); 887441#L1099-1 assume !(1 == ~T9_E~0); 887442#L1104-1 assume !(1 == ~E_M~0); 887668#L1109-1 assume !(1 == ~E_1~0); 887244#L1114-1 assume !(1 == ~E_2~0); 887245#L1119-1 assume 1 == ~E_3~0;~E_3~0 := 2; 887303#L1124-1 assume !(1 == ~E_4~0); 886737#L1129-1 assume !(1 == ~E_5~0); 886738#L1134-1 assume !(1 == ~E_6~0); 887069#L1139-1 assume !(1 == ~E_7~0); 887070#L1144-1 assume !(1 == ~E_8~0); 887261#L1149-1 assume !(1 == ~E_9~0); 886901#L1154-1 assume { :end_inline_reset_delta_events } true; 886902#L1440-2
[2021-11-13 17:48:00,898 INFO L793 eck$LassoCheckResult]: Loop: 886902#L1440-2 assume !false; 950056#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 950052#L926 assume !false; 950050#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 950047#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 950037#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 950035#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 950032#L795 assume !(0 != eval_~tmp~0#1); 950033#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 967601#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 967599#L951-3 assume !(0 == ~M_E~0); 967597#L951-5 assume !(0 == ~T1_E~0); 967595#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 967593#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 967591#L966-3 assume !(0 == ~T4_E~0); 967589#L971-3 assume !(0 == ~T5_E~0); 967587#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 967585#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 967583#L986-3 assume !(0 == ~T8_E~0); 967581#L991-3 assume !(0 == ~T9_E~0); 967579#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 967577#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 967575#L1006-3 assume !(0 == ~E_2~0); 967572#L1011-3 assume 0 == ~E_3~0;~E_3~0 := 1; 967573#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 975257#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 976393#L1026-3 assume !(0 == ~E_6~0); 975249#L1031-3 assume !(0 == ~E_7~0); 975250#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 975244#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 975242#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 975240#L472-33 assume !(1 == ~m_pc~0); 975236#L472-35 is_master_triggered_~__retres1~0#1 := 0; 975158#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975019#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 975016#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 975014#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 972904#L491-33 assume !(1 == ~t1_pc~0); 972905#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 972900#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 972901#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 972894#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 972895#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 972890#L510-33 assume !(1 == ~t2_pc~0); 972889#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 972884#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 972885#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 972874#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 972875#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 966513#L529-33 assume !(1 == ~t3_pc~0); 966512#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 966511#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 966510#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 966509#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 966508#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 966506#L548-33 assume !(1 == ~t4_pc~0); 966504#L548-35 is_transmit4_triggered_~__retres1~4#1 := 0; 966501#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 966498#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 966496#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 962386#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 950672#L567-33 assume !(1 == ~t5_pc~0); 950673#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 952485#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 952483#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 952481#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 950660#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 950658#L586-33 assume 1 == ~t6_pc~0; 950654#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 950652#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 950650#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 950648#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 950646#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 950223#L605-33 assume !(1 == ~t7_pc~0); 950221#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 950219#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 950217#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 950215#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 950212#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 950210#L624-33 assume 1 == ~t8_pc~0; 950207#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 950205#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 950203#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 950201#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 950200#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 950198#L643-33 assume !(1 == ~t9_pc~0); 934641#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 950195#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 950193#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 950191#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 950189#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 950187#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 950185#L1059-5 assume !(1 == ~T1_E~0); 950183#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 950181#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 950179#L1074-3 assume !(1 == ~T4_E~0); 950177#L1079-3 assume !(1 == ~T5_E~0); 950175#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 950173#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 950171#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 950169#L1099-3 assume !(1 == ~T9_E~0); 950167#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 950166#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 950164#L1114-3 assume !(1 == ~E_2~0); 950162#L1119-3 assume 1 == ~E_3~0;~E_3~0 := 2; 950159#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 950157#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 950155#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 950153#L1139-3 assume !(1 == ~E_7~0); 950151#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 950148#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 950146#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 950140#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 950131#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 950129#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 950126#L1459 assume !(0 == start_simulation_~tmp~3#1); 950123#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 950117#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 950102#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 950097#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 950090#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 950083#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 950074#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 950067#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 886902#L1440-2
[2021-11-13 17:48:00,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:00,899 INFO L85 PathProgramCache]: Analyzing trace with hash -818498043, now seen corresponding path program 1 times
[2021-11-13 17:48:00,899 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:00,899 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563536961]
[2021-11-13 17:48:00,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:00,900 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:00,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:00,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:00,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:00,927 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563536961]
[2021-11-13 17:48:00,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563536961] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:00,927 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:00,927 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2021-11-13 17:48:00,927 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128355659]
[2021-11-13 17:48:00,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:00,928 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:48:00,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:00,928 INFO L85 PathProgramCache]: Analyzing trace with hash -1358322288, now seen corresponding path program 1 times
[2021-11-13 17:48:00,928 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:00,929 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484539558]
[2021-11-13 17:48:00,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:00,929 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:00,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:00,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:00,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:00,962 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484539558]
[2021-11-13 17:48:00,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1484539558] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:00,962 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:00,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2021-11-13 17:48:00,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337818912]
[2021-11-13 17:48:00,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:00,963 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:48:00,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:00,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:48:00,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:48:00,964 INFO L87 Difference]: Start difference. First operand 91310 states and 126201 transitions. cyclomatic complexity: 34893 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:01,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:01,752 INFO L93 Difference]: Finished difference Result 51129 states and 70597 transitions.
[2021-11-13 17:48:01,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:48:01,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51129 states and 70597 transitions.
[2021-11-13 17:48:01,960 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 50976
[2021-11-13 17:48:02,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51129 states to 51129 states and 70597 transitions.
[2021-11-13 17:48:02,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51129
[2021-11-13 17:48:02,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51129
[2021-11-13 17:48:02,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51129 states and 70597 transitions.
[2021-11-13 17:48:02,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:48:02,130 INFO L681 BuchiCegarLoop]: Abstraction has 51129 states and 70597 transitions.
[2021-11-13 17:48:02,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51129 states and 70597 transitions.
[2021-11-13 17:48:02,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51129 to 51129.
[2021-11-13 17:48:02,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51129 states, 51129 states have (on average 1.3807623853390443) internal successors, (70597), 51128 states have internal predecessors, (70597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:02,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51129 states to 51129 states and 70597 transitions.
[2021-11-13 17:48:02,665 INFO L704 BuchiCegarLoop]: Abstraction has 51129 states and 70597 transitions.
[2021-11-13 17:48:02,665 INFO L587 BuchiCegarLoop]: Abstraction has 51129 states and 70597 transitions.
[2021-11-13 17:48:02,665 INFO L425 BuchiCegarLoop]: ======== Iteration 25============
[2021-11-13 17:48:02,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51129 states and 70597 transitions.
[2021-11-13 17:48:02,818 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 50976
[2021-11-13 17:48:02,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:02,818 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:02,823 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:02,823 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:02,824 INFO L791 eck$LassoCheckResult]: Stem: 1030059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1030060#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1030427#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1030088#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1029968#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1029688#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1029689#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1030290#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1030354#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1030339#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1030340#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1029809#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1029798#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1029799#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1029613#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1029614#L951 assume !(0 == ~M_E~0); 1029354#L951-2 assume !(0 == ~T1_E~0); 1029355#L956-1 assume !(0 == ~T2_E~0); 1029514#L961-1 assume !(0 == ~T3_E~0); 1029985#L966-1 assume !(0 == ~T4_E~0); 1029986#L971-1 assume !(0 == ~T5_E~0); 1030145#L976-1 assume !(0 == ~T6_E~0); 1030116#L981-1 assume !(0 == ~T7_E~0); 1029846#L986-1 assume !(0 == ~T8_E~0); 1029566#L991-1 assume !(0 == ~T9_E~0); 1029567#L996-1 assume !(0 == ~E_M~0); 1030402#L1001-1 assume !(0 == ~E_1~0); 1030057#L1006-1 assume !(0 == ~E_2~0); 1030058#L1011-1 assume !(0 == ~E_3~0); 1030355#L1016-1 assume !(0 == ~E_4~0); 1030377#L1021-1 assume !(0 == ~E_5~0); 1029166#L1026-1 assume !(0 == ~E_6~0); 1029167#L1031-1 assume !(0 == ~E_7~0); 1030000#L1036-1 assume !(0 == ~E_8~0); 1029996#L1041-1 assume !(0 == ~E_9~0); 1029997#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1030303#L472 assume !(1 == ~m_pc~0); 1030257#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1030033#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1030034#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1030044#L1179 assume !(0 != activate_threads_~tmp~1#1); 1029174#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1029175#L491 assume !(1 == ~t1_pc~0); 1029662#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1029663#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1029994#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1029145#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1029146#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1029168#L510 assume !(1 == ~t2_pc~0); 1029134#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1029135#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1030306#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030307#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1029408#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1029409#L529 assume !(1 == ~t3_pc~0); 1029851#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1030167#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1030250#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1030390#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1029331#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1029332#L548 assume !(1 == ~t4_pc~0); 1029231#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1029230#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1029523#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1029271#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1029272#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1029219#L567 assume !(1 == ~t5_pc~0); 1029220#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1029273#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1029455#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1029456#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1030284#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1029342#L586 assume !(1 == ~t6_pc~0); 1029343#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1029414#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1030420#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1030477#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1030279#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1030280#L605 assume !(1 == ~t7_pc~0); 1029823#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1029824#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1029989#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1029990#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1030446#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1029962#L624 assume !(1 == ~t8_pc~0); 1029402#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1029401#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1030025#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1030026#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1030262#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1029188#L643 assume !(1 == ~t9_pc~0); 1029189#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1030197#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1030118#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1029571#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1029572#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1029385#L1059 assume !(1 == ~M_E~0); 1029386#L1059-2 assume !(1 == ~T1_E~0); 1029543#L1064-1 assume !(1 == ~T2_E~0); 1029544#L1069-1 assume !(1 == ~T3_E~0); 1030210#L1074-1 assume !(1 == ~T4_E~0); 1030259#L1079-1 assume !(1 == ~T5_E~0); 1030243#L1084-1 assume !(1 == ~T6_E~0); 1030244#L1089-1 assume !(1 == ~T7_E~0); 1030272#L1094-1 assume !(1 == ~T8_E~0); 1029880#L1099-1 assume !(1 == ~T9_E~0); 1029881#L1104-1 assume !(1 == ~E_M~0); 1030104#L1109-1 assume !(1 == ~E_1~0); 1029681#L1114-1 assume !(1 == ~E_2~0); 1029682#L1119-1 assume !(1 == ~E_3~0); 1029739#L1124-1 assume !(1 == ~E_4~0); 1029184#L1129-1 assume !(1 == ~E_5~0); 1029185#L1134-1 assume !(1 == ~E_6~0); 1029510#L1139-1 assume !(1 == ~E_7~0); 1029511#L1144-1 assume !(1 == ~E_8~0); 1029696#L1149-1 assume !(1 == ~E_9~0); 1029348#L1154-1 assume { :end_inline_reset_delta_events } true; 1029349#L1440-2
[2021-11-13 17:48:02,825 INFO L793 eck$LassoCheckResult]: Loop: 1029349#L1440-2 assume !false; 1073987#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1065280#L926 assume !false; 1073836#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1073452#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1073412#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1073409#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1073405#L795 assume !(0 != eval_~tmp~0#1); 1073406#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1080108#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1080107#L951-3 assume !(0 == ~M_E~0); 1080106#L951-5 assume !(0 == ~T1_E~0); 1080104#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1079835#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1079834#L966-3 assume !(0 == ~T4_E~0); 1079833#L971-3 assume !(0 == ~T5_E~0); 1079831#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1079829#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1079827#L986-3 assume !(0 == ~T8_E~0); 1079825#L991-3 assume !(0 == ~T9_E~0); 1079823#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1079821#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1079819#L1006-3 assume !(0 == ~E_2~0); 1079817#L1011-3 assume !(0 == ~E_3~0); 1079815#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1079813#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1079811#L1026-3 assume !(0 == ~E_6~0); 1079809#L1031-3 assume !(0 == ~E_7~0); 1079807#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1079805#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1079803#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1079801#L472-33 assume !(1 == ~m_pc~0); 1079785#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1079783#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1079409#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1079408#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1079407#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1030436#L491-33 assume !(1 == ~t1_pc~0); 1029234#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1029235#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1030388#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1030413#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1030414#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1030107#L510-33 assume !(1 == ~t2_pc~0); 1030105#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1030106#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1029987#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1029988#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1029127#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1029128#L529-33 assume !(1 == ~t3_pc~0); 1029439#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1080084#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1080083#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1080082#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1080081#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1080080#L548-33 assume 1 == ~t4_pc~0; 1080078#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1030067#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1030068#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1077322#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1077321#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1077320#L567-33 assume !(1 == ~t5_pc~0); 1066156#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1074425#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1074423#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1074422#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1074421#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1074419#L586-33 assume 1 == ~t6_pc~0; 1074416#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1074414#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1074412#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1074410#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1074408#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1074406#L605-33 assume !(1 == ~t7_pc~0); 1068448#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1074402#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1074400#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1074398#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1074396#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1074393#L624-33 assume 1 == ~t8_pc~0; 1074391#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1074388#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1074384#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1074381#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1074378#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1074374#L643-33 assume !(1 == ~t9_pc~0); 1062430#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1074362#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1074356#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1074351#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1074346#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1074341#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1074338#L1059-5 assume !(1 == ~T1_E~0); 1074331#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1074326#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1074321#L1074-3 assume !(1 == ~T4_E~0); 1074316#L1079-3 assume !(1 == ~T5_E~0); 1074310#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1074304#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1074300#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1074296#L1099-3 assume !(1 == ~T9_E~0); 1074291#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1074286#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1074281#L1114-3 assume !(1 == ~E_2~0); 1074278#L1119-3 assume !(1 == ~E_3~0); 1074272#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1074266#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1074261#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1074256#L1139-3 assume !(1 == ~E_7~0); 1074251#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1074245#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1074239#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1074208#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1074195#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1074191#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1074184#L1459 assume !(0 == start_simulation_~tmp~3#1); 1074179#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1074137#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1074123#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1074120#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1074117#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1074112#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1074106#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1074101#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1029349#L1440-2
[2021-11-13 17:48:02,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:02,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 3 times
[2021-11-13 17:48:02,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:02,826 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288614515]
[2021-11-13 17:48:02,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:02,826 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:02,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:02,839 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:02,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:02,904 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:02,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:02,905 INFO L85 PathProgramCache]: Analyzing trace with hash -325774705, now seen corresponding path program 1 times
[2021-11-13 17:48:02,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:02,905 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353530338]
[2021-11-13 17:48:02,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:02,905 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:02,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:02,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:02,940 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:02,941 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353530338]
[2021-11-13 17:48:02,941 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353530338] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:02,941 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:02,941 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2021-11-13 17:48:02,941 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385263751]
[2021-11-13 17:48:02,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:02,942 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:48:02,942 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:02,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2021-11-13 17:48:02,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2021-11-13 17:48:02,943 INFO L87 Difference]: Start difference. First operand 51129 states and 70597 transitions. cyclomatic complexity: 19470 Second operand has 5 states, 5 states have (on average 24.8) internal successors, (124), 5 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:03,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:03,887 INFO L93 Difference]: Finished difference Result 94137 states and 128677 transitions.
[2021-11-13 17:48:03,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states.
[2021-11-13 17:48:03,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94137 states and 128677 transitions.
[2021-11-13 17:48:04,205 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 93952
[2021-11-13 17:48:04,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94137 states to 94137 states and 128677 transitions.
[2021-11-13 17:48:04,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94137
[2021-11-13 17:48:04,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94137
[2021-11-13 17:48:04,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94137 states and 128677 transitions.
[2021-11-13 17:48:04,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:48:04,445 INFO L681 BuchiCegarLoop]: Abstraction has 94137 states and 128677 transitions.
[2021-11-13 17:48:04,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94137 states and 128677 transitions.
[2021-11-13 17:48:04,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94137 to 51321.
[2021-11-13 17:48:04,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51321 states, 51321 states have (on average 1.379337892870365) internal successors, (70789), 51320 states have internal predecessors, (70789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:05,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51321 states to 51321 states and 70789 transitions.
[2021-11-13 17:48:05,702 INFO L704 BuchiCegarLoop]: Abstraction has 51321 states and 70789 transitions.
[2021-11-13 17:48:05,702 INFO L587 BuchiCegarLoop]: Abstraction has 51321 states and 70789 transitions.
[2021-11-13 17:48:05,702 INFO L425 BuchiCegarLoop]: ======== Iteration 26============
[2021-11-13 17:48:05,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51321 states and 70789 transitions.
[2021-11-13 17:48:05,822 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 51168
[2021-11-13 17:48:05,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:05,823 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:05,826 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:05,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:05,827 INFO L791 eck$LassoCheckResult]: Stem: 1175361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1175362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1175759#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1175390#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1175272#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1174983#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1174984#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1175620#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1175677#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1175664#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1175665#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1175105#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1175093#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1175094#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1174904#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1174905#L951 assume !(0 == ~M_E~0); 1174637#L951-2 assume !(0 == ~T1_E~0); 1174638#L956-1 assume !(0 == ~T2_E~0); 1174804#L961-1 assume !(0 == ~T3_E~0); 1175288#L966-1 assume !(0 == ~T4_E~0); 1175289#L971-1 assume !(0 == ~T5_E~0); 1175453#L976-1 assume !(0 == ~T6_E~0); 1175420#L981-1 assume !(0 == ~T7_E~0); 1175143#L986-1 assume !(0 == ~T8_E~0); 1174857#L991-1 assume !(0 == ~T9_E~0); 1174858#L996-1 assume !(0 == ~E_M~0); 1175730#L1001-1 assume !(0 == ~E_1~0); 1175359#L1006-1 assume !(0 == ~E_2~0); 1175360#L1011-1 assume !(0 == ~E_3~0); 1175678#L1016-1 assume !(0 == ~E_4~0); 1175705#L1021-1 assume !(0 == ~E_5~0); 1174448#L1026-1 assume !(0 == ~E_6~0); 1174449#L1031-1 assume !(0 == ~E_7~0); 1175301#L1036-1 assume !(0 == ~E_8~0); 1175297#L1041-1 assume !(0 == ~E_9~0); 1175298#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1175631#L472 assume !(1 == ~m_pc~0); 1175579#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1175335#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1175336#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1175345#L1179 assume !(0 != activate_threads_~tmp~1#1); 1174456#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1174457#L491 assume !(1 == ~t1_pc~0); 1174954#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1174955#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1175295#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1174427#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1174428#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1174450#L510 assume !(1 == ~t2_pc~0); 1174416#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1174417#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1175633#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1175634#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1174691#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1174692#L529 assume !(1 == ~t3_pc~0); 1175148#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1175484#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1175575#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1175720#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1174614#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1174615#L548 assume !(1 == ~t4_pc~0); 1174512#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1174511#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1174812#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1174552#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1174553#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1174500#L567 assume !(1 == ~t5_pc~0); 1174501#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1174554#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1174738#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1174739#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1175614#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1174625#L586 assume !(1 == ~t6_pc~0); 1174626#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1174697#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1175750#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1175824#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1175607#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1175608#L605 assume !(1 == ~t7_pc~0); 1175119#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1175120#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1175292#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1175293#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1175786#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1175265#L624 assume !(1 == ~t8_pc~0); 1174685#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1174684#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1175328#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1175329#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1175585#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1174470#L643 assume !(1 == ~t9_pc~0); 1174471#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1175522#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1175423#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1174862#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1174863#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1174668#L1059 assume !(1 == ~M_E~0); 1174669#L1059-2 assume !(1 == ~T1_E~0); 1174834#L1064-1 assume !(1 == ~T2_E~0); 1174835#L1069-1 assume !(1 == ~T3_E~0); 1175534#L1074-1 assume !(1 == ~T4_E~0); 1175581#L1079-1 assume !(1 == ~T5_E~0); 1175569#L1084-1 assume !(1 == ~T6_E~0); 1175570#L1089-1 assume !(1 == ~T7_E~0); 1175599#L1094-1 assume !(1 == ~T8_E~0); 1175180#L1099-1 assume !(1 == ~T9_E~0); 1175181#L1104-1 assume !(1 == ~E_M~0); 1175406#L1109-1 assume !(1 == ~E_1~0); 1174973#L1114-1 assume !(1 == ~E_2~0); 1174974#L1119-1 assume !(1 == ~E_3~0); 1175034#L1124-1 assume !(1 == ~E_4~0); 1174466#L1129-1 assume !(1 == ~E_5~0); 1174467#L1134-1 assume !(1 == ~E_6~0); 1174800#L1139-1 assume !(1 == ~E_7~0); 1174801#L1144-1 assume !(1 == ~E_8~0); 1174991#L1149-1 assume !(1 == ~E_9~0); 1174631#L1154-1 assume { :end_inline_reset_delta_events } true; 1174632#L1440-2
[2021-11-13 17:48:05,828 INFO L793 eck$LassoCheckResult]: Loop: 1174632#L1440-2 assume !false; 1215475#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1215470#L926 assume !false; 1215467#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1215461#L728 assume !(0 == ~m_st~0); 1215462#L732 assume !(0 == ~t1_st~0); 1215456#L736 assume !(0 == ~t2_st~0); 1215457#L740 assume !(0 == ~t3_st~0); 1215460#L744 assume !(0 == ~t4_st~0); 1215454#L748 assume !(0 == ~t5_st~0); 1215455#L752 assume !(0 == ~t6_st~0); 1215459#L756 assume !(0 == ~t7_st~0); 1215452#L760 assume !(0 == ~t8_st~0); 1215453#L764 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1215458#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1212862#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1212863#L795 assume !(0 != eval_~tmp~0#1); 1219621#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1219611#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1219612#L951-3 assume !(0 == ~M_E~0); 1219603#L951-5 assume !(0 == ~T1_E~0); 1219604#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1219595#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1219596#L966-3 assume !(0 == ~T4_E~0); 1219587#L971-3 assume !(0 == ~T5_E~0); 1219588#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1219580#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1219581#L986-3 assume !(0 == ~T8_E~0); 1220469#L991-3 assume !(0 == ~T9_E~0); 1219569#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1219570#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1219561#L1006-3 assume !(0 == ~E_2~0); 1219562#L1011-3 assume !(0 == ~E_3~0); 1219553#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1219554#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1219545#L1026-3 assume !(0 == ~E_6~0); 1219546#L1031-3 assume !(0 == ~E_7~0); 1219537#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1219538#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1219529#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1219530#L472-33 assume !(1 == ~m_pc~0); 1219521#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1219522#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1219513#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1219514#L1179-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1219505#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1219506#L491-33 assume !(1 == ~t1_pc~0); 1199080#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1219499#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1219500#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1220464#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1219489#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1219490#L510-33 assume !(1 == ~t2_pc~0); 1220460#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1219476#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1219477#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1219468#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1219469#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1219463#L529-33 assume !(1 == ~t3_pc~0); 1219464#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1219457#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1219458#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1219451#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1219452#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1219443#L548-33 assume 1 == ~t4_pc~0; 1219444#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1219436#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1219437#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1219430#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1219431#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1218424#L567-33 assume !(1 == ~t5_pc~0); 1218425#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1218420#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1218421#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1216391#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1216392#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1216353#L586-33 assume 1 == ~t6_pc~0; 1216354#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1216340#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1216341#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1216325#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1216326#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1216147#L605-33 assume !(1 == ~t7_pc~0); 1216148#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1216137#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1216138#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1216124#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1216125#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1216097#L624-33 assume 1 == ~t8_pc~0; 1216098#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1216048#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1216049#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1216035#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1216036#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1216021#L643-33 assume !(1 == ~t9_pc~0); 1216020#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1216019#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1216018#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1216017#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1216016#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1216015#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1216014#L1059-5 assume !(1 == ~T1_E~0); 1216013#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1216012#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1216011#L1074-3 assume !(1 == ~T4_E~0); 1216010#L1079-3 assume !(1 == ~T5_E~0); 1216009#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1216008#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1216007#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1216006#L1099-3 assume !(1 == ~T9_E~0); 1216005#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1216004#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1216003#L1114-3 assume !(1 == ~E_2~0); 1216002#L1119-3 assume !(1 == ~E_3~0); 1216001#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1216000#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1215999#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1215998#L1139-3 assume !(1 == ~E_7~0); 1215997#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1215996#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1215995#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1215993#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1215977#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1215969#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1215961#L1459 assume !(0 == start_simulation_~tmp~3#1); 1215501#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1215499#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1215489#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1215486#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1215484#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1215482#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1215480#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1215478#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1174632#L1440-2
[2021-11-13 17:48:05,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:05,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 4 times
[2021-11-13 17:48:05,829 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:05,829 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261256000]
[2021-11-13 17:48:05,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:05,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:05,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:05,840 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:05,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:05,897 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:05,898 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:05,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1193483740, now seen corresponding path program 1 times
[2021-11-13 17:48:05,898 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:05,898 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529037854]
[2021-11-13 17:48:05,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:05,899 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:05,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:05,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:05,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:05,969 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529037854]
[2021-11-13 17:48:05,970 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529037854] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:05,970 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:05,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2021-11-13 17:48:05,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433983524]
[2021-11-13 17:48:05,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:05,971 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:48:05,971 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:05,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2021-11-13 17:48:05,971 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2021-11-13 17:48:05,972 INFO L87 Difference]: Start difference. First operand 51321 states and 70789 transitions. cyclomatic complexity: 19470 Second operand has 5 states, 5 states have (on average 26.6) internal successors, (133), 5 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:06,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:06,497 INFO L93 Difference]: Finished difference Result 102601 states and 140836 transitions.
[2021-11-13 17:48:06,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states.
[2021-11-13 17:48:06,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102601 states and 140836 transitions.
[2021-11-13 17:48:06,867 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 102448
[2021-11-13 17:48:07,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102601 states to 102601 states and 140836 transitions.
[2021-11-13 17:48:07,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102601
[2021-11-13 17:48:07,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102601
[2021-11-13 17:48:07,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102601 states and 140836 transitions.
[2021-11-13 17:48:07,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:48:07,175 INFO L681 BuchiCegarLoop]: Abstraction has 102601 states and 140836 transitions.
[2021-11-13 17:48:07,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102601 states and 140836 transitions.
[2021-11-13 17:48:08,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102601 to 52233.
[2021-11-13 17:48:08,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52233 states, 52233 states have (on average 1.3674879865219305) internal successors, (71428), 52232 states have internal predecessors, (71428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:08,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52233 states to 52233 states and 71428 transitions.
[2021-11-13 17:48:08,372 INFO L704 BuchiCegarLoop]: Abstraction has 52233 states and 71428 transitions.
[2021-11-13 17:48:08,372 INFO L587 BuchiCegarLoop]: Abstraction has 52233 states and 71428 transitions.
[2021-11-13 17:48:08,372 INFO L425 BuchiCegarLoop]: ======== Iteration 27============
[2021-11-13 17:48:08,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52233 states and 71428 transitions.
[2021-11-13 17:48:08,505 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52080
[2021-11-13 17:48:08,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:08,505 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:08,509 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:08,509 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:08,510 INFO L791 eck$LassoCheckResult]: Stem: 1329283#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1329284#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1329667#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1329308#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1329196#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1328913#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1328914#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1329536#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1329595#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1329578#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1329579#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1329035#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1329022#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1329023#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1328835#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1328836#L951 assume !(0 == ~M_E~0); 1328572#L951-2 assume !(0 == ~T1_E~0); 1328573#L956-1 assume !(0 == ~T2_E~0); 1328735#L961-1 assume !(0 == ~T3_E~0); 1329214#L966-1 assume !(0 == ~T4_E~0); 1329215#L971-1 assume !(0 == ~T5_E~0); 1329367#L976-1 assume !(0 == ~T6_E~0); 1329337#L981-1 assume !(0 == ~T7_E~0); 1329074#L986-1 assume !(0 == ~T8_E~0); 1328786#L991-1 assume !(0 == ~T9_E~0); 1328787#L996-1 assume !(0 == ~E_M~0); 1329640#L1001-1 assume !(0 == ~E_1~0); 1329281#L1006-1 assume !(0 == ~E_2~0); 1329282#L1011-1 assume !(0 == ~E_3~0); 1329596#L1016-1 assume !(0 == ~E_4~0); 1329617#L1021-1 assume !(0 == ~E_5~0); 1328383#L1026-1 assume !(0 == ~E_6~0); 1328384#L1031-1 assume !(0 == ~E_7~0); 1329229#L1036-1 assume !(0 == ~E_8~0); 1329225#L1041-1 assume !(0 == ~E_9~0); 1329226#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1329547#L472 assume !(1 == ~m_pc~0); 1329492#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1329260#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1329261#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1329269#L1179 assume !(0 != activate_threads_~tmp~1#1); 1328391#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1328392#L491 assume !(1 == ~t1_pc~0); 1328883#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1328884#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1329223#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1328364#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1328365#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1328387#L510 assume !(1 == ~t2_pc~0); 1328351#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1328352#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1329551#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1329552#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1328626#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1328627#L529 assume !(1 == ~t3_pc~0); 1329080#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1329396#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1329486#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1329629#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1328549#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1328550#L548 assume !(1 == ~t4_pc~0); 1328449#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1328448#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1328743#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1328490#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1328491#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1328437#L567 assume !(1 == ~t5_pc~0); 1328438#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1328489#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1328673#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1328674#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1329529#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1328560#L586 assume !(1 == ~t6_pc~0); 1328561#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1328632#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1329658#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1329725#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1329521#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1329522#L605 assume !(1 == ~t7_pc~0); 1329050#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1329051#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1329218#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1329219#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1329692#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1329190#L624 assume !(1 == ~t8_pc~0); 1328620#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1328619#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1329254#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1329255#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1329495#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1328405#L643 assume !(1 == ~t9_pc~0); 1328406#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1329429#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1329339#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1328793#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1328794#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1328603#L1059 assume !(1 == ~M_E~0); 1328604#L1059-2 assume !(1 == ~T1_E~0); 1328763#L1064-1 assume !(1 == ~T2_E~0); 1328764#L1069-1 assume !(1 == ~T3_E~0); 1329440#L1074-1 assume !(1 == ~T4_E~0); 1329493#L1079-1 assume !(1 == ~T5_E~0); 1329480#L1084-1 assume !(1 == ~T6_E~0); 1329481#L1089-1 assume !(1 == ~T7_E~0); 1329515#L1094-1 assume !(1 == ~T8_E~0); 1329107#L1099-1 assume !(1 == ~T9_E~0); 1329108#L1104-1 assume !(1 == ~E_M~0); 1329323#L1109-1 assume !(1 == ~E_1~0); 1328904#L1114-1 assume !(1 == ~E_2~0); 1328905#L1119-1 assume !(1 == ~E_3~0); 1328963#L1124-1 assume !(1 == ~E_4~0); 1328403#L1129-1 assume !(1 == ~E_5~0); 1328404#L1134-1 assume !(1 == ~E_6~0); 1328731#L1139-1 assume !(1 == ~E_7~0); 1328732#L1144-1 assume !(1 == ~E_8~0); 1328923#L1149-1 assume !(1 == ~E_9~0); 1328566#L1154-1 assume { :end_inline_reset_delta_events } true; 1328567#L1440-2
[2021-11-13 17:48:08,510 INFO L793 eck$LassoCheckResult]: Loop: 1328567#L1440-2 assume !false; 1345750#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1332970#L926 assume !false; 1345749#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1345747#L728 assume !(0 == ~m_st~0); 1345748#L732 assume !(0 == ~t1_st~0); 1345742#L736 assume !(0 == ~t2_st~0); 1345743#L740 assume !(0 == ~t3_st~0); 1345746#L744 assume !(0 == ~t4_st~0); 1345740#L748 assume !(0 == ~t5_st~0); 1345741#L752 assume !(0 == ~t6_st~0); 1345745#L756 assume !(0 == ~t7_st~0); 1345738#L760 assume !(0 == ~t8_st~0); 1345739#L764 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1345744#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1345730#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1345731#L795 assume !(0 != eval_~tmp~0#1); 1353927#L941 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1353925#L663-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1353923#L951-3 assume !(0 == ~M_E~0); 1353921#L951-5 assume !(0 == ~T1_E~0); 1353919#L956-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1353917#L961-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1353915#L966-3 assume !(0 == ~T4_E~0); 1353913#L971-3 assume !(0 == ~T5_E~0); 1353911#L976-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1353909#L981-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1353907#L986-3 assume !(0 == ~T8_E~0); 1353905#L991-3 assume !(0 == ~T9_E~0); 1353903#L996-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1353901#L1001-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1353899#L1006-3 assume !(0 == ~E_2~0); 1353897#L1011-3 assume !(0 == ~E_3~0); 1353895#L1016-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1353893#L1021-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1353891#L1026-3 assume !(0 == ~E_6~0); 1353889#L1031-3 assume !(0 == ~E_7~0); 1353887#L1036-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1353885#L1041-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1353883#L1046-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1353881#L472-33 assume !(1 == ~m_pc~0); 1353879#L472-35 is_master_triggered_~__retres1~0#1 := 0; 1353868#L483-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1353869#L484-11 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1353664#L1179-33 assume !(0 != activate_threads_~tmp~1#1); 1353665#L1179-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1353607#L491-33 assume !(1 == ~t1_pc~0); 1353604#L491-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1353601#L502-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1353597#L503-11 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1353593#L1187-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1353589#L1187-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1353583#L510-33 assume !(1 == ~t2_pc~0); 1353577#L510-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1353573#L521-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1353569#L522-11 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1353565#L1195-33 assume !(0 != activate_threads_~tmp___1~0#1); 1353561#L1195-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1353557#L529-33 assume !(1 == ~t3_pc~0); 1353354#L529-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1353555#L540-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1353553#L541-11 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1353551#L1203-33 assume !(0 != activate_threads_~tmp___2~0#1); 1353549#L1203-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1353547#L548-33 assume 1 == ~t4_pc~0; 1353544#L549-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1353438#L559-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1353439#L560-11 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1353057#L1211-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1353058#L1211-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1345890#L567-33 assume !(1 == ~t5_pc~0); 1345887#L567-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1345884#L578-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1345881#L579-11 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1345877#L1219-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1345873#L1219-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1345870#L586-33 assume 1 == ~t6_pc~0; 1345866#L587-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1345864#L597-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1345865#L598-11 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1352850#L1227-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1352848#L1227-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1345859#L605-33 assume !(1 == ~t7_pc~0); 1345858#L605-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1345857#L616-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1345856#L617-11 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1345855#L1235-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1345854#L1235-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1345853#L624-33 assume 1 == ~t8_pc~0; 1345850#L625-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1345848#L635-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1345846#L636-11 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1345844#L1243-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1345842#L1243-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1345840#L643-33 assume !(1 == ~t9_pc~0); 1333314#L643-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1345836#L654-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1345834#L655-11 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1345832#L1251-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1345830#L1251-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1345828#L1059-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1345826#L1059-5 assume !(1 == ~T1_E~0); 1345825#L1064-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1345823#L1069-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1345821#L1074-3 assume !(1 == ~T4_E~0); 1345819#L1079-3 assume !(1 == ~T5_E~0); 1345817#L1084-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1345815#L1089-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1345813#L1094-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1345811#L1099-3 assume !(1 == ~T9_E~0); 1345809#L1104-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1345807#L1109-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1345805#L1114-3 assume !(1 == ~E_2~0); 1345803#L1119-3 assume !(1 == ~E_3~0); 1345801#L1124-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1345799#L1129-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1345797#L1134-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1345795#L1139-3 assume !(1 == ~E_7~0); 1345793#L1144-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1345791#L1149-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1345789#L1154-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1345783#L728-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1345773#L780-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1345771#L781-1 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1345769#L1459 assume !(0 == start_simulation_~tmp~3#1); 1345767#L1459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1345765#L728-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1345756#L780-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1345755#L781-2 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1345754#L1414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1345753#L1421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1345752#L1422 start_simulation_#t~ret32#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1345751#L1472 assume !(0 != start_simulation_~tmp___0~1#1); 1328567#L1440-2
[2021-11-13 17:48:08,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:08,511 INFO L85 PathProgramCache]: Analyzing trace with hash 1896389061, now seen corresponding path program 5 times
[2021-11-13 17:48:08,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:08,511 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066459450]
[2021-11-13 17:48:08,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:08,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:08,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:08,523 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:08,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:08,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:08,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:08,580 INFO L85 PathProgramCache]: Analyzing trace with hash -1964217306, now seen corresponding path program 1 times
[2021-11-13 17:48:08,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:08,580 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804873601]
[2021-11-13 17:48:08,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:08,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:08,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:08,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:08,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:08,614 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [804873601]
[2021-11-13 17:48:08,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [804873601] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:08,614 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:08,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:48:08,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347014291]
[2021-11-13 17:48:08,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:08,615 INFO L808 eck$LassoCheckResult]: loop already infeasible
[2021-11-13 17:48:08,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:08,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:48:08,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:48:08,616 INFO L87 Difference]: Start difference. First operand 52233 states and 71428 transitions. cyclomatic complexity: 19197 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:08,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:08,945 INFO L93 Difference]: Finished difference Result 93755 states and 126598 transitions.
[2021-11-13 17:48:08,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:48:08,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93755 states and 126598 transitions.
[2021-11-13 17:48:09,905 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 93600
[2021-11-13 17:48:10,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93755 states to 93755 states and 126598 transitions.
[2021-11-13 17:48:10,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93755
[2021-11-13 17:48:10,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93755
[2021-11-13 17:48:10,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93755 states and 126598 transitions.
[2021-11-13 17:48:10,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:48:10,230 INFO L681 BuchiCegarLoop]: Abstraction has 93755 states and 126598 transitions.
[2021-11-13 17:48:10,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93755 states and 126598 transitions.
[2021-11-13 17:48:10,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93755 to 91755.
[2021-11-13 17:48:10,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91755 states, 91755 states have (on average 1.3513160045774073) internal successors, (123990), 91754 states have internal predecessors, (123990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:11,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91755 states to 91755 states and 123990 transitions.
[2021-11-13 17:48:11,150 INFO L704 BuchiCegarLoop]: Abstraction has 91755 states and 123990 transitions.
[2021-11-13 17:48:11,150 INFO L587 BuchiCegarLoop]: Abstraction has 91755 states and 123990 transitions.
[2021-11-13 17:48:11,150 INFO L425 BuchiCegarLoop]: ======== Iteration 28============
[2021-11-13 17:48:11,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91755 states and 123990 transitions.
[2021-11-13 17:48:11,926 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 91600
[2021-11-13 17:48:11,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:11,926 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:11,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:11,927 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:11,928 INFO L791 eck$LassoCheckResult]: Stem: 1475278#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1475279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1475650#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1475305#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1475192#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1474915#L670-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1474916#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1475518#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1475575#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1475560#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1475561#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1475036#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1475024#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1475025#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1474834#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1474835#L951 assume !(0 == ~M_E~0); 1474565#L951-2 assume !(0 == ~T1_E~0); 1474566#L956-1 assume !(0 == ~T2_E~0); 1474731#L961-1 assume !(0 == ~T3_E~0); 1475210#L966-1 assume !(0 == ~T4_E~0); 1475211#L971-1 assume !(0 == ~T5_E~0); 1475359#L976-1 assume !(0 == ~T6_E~0); 1475331#L981-1 assume !(0 == ~T7_E~0); 1475076#L986-1 assume !(0 == ~T8_E~0); 1474783#L991-1 assume !(0 == ~T9_E~0); 1474784#L996-1 assume !(0 == ~E_M~0); 1475623#L1001-1 assume !(0 == ~E_1~0); 1475275#L1006-1 assume !(0 == ~E_2~0); 1475276#L1011-1 assume !(0 == ~E_3~0); 1475577#L1016-1 assume !(0 == ~E_4~0); 1475597#L1021-1 assume !(0 == ~E_5~0); 1474377#L1026-1 assume !(0 == ~E_6~0); 1474378#L1031-1 assume !(0 == ~E_7~0); 1475225#L1036-1 assume !(0 == ~E_8~0); 1475221#L1041-1 assume !(0 == ~E_9~0); 1475222#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1475530#L472 assume !(1 == ~m_pc~0); 1475472#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1475253#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1475254#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1475262#L1179 assume !(0 != activate_threads_~tmp~1#1); 1474385#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1474386#L491 assume !(1 == ~t1_pc~0); 1474882#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1474883#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1475217#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1474358#L1187 assume !(0 != activate_threads_~tmp___0~0#1); 1474359#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1474381#L510 assume !(1 == ~t2_pc~0); 1474345#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1474346#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1475533#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1475534#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1474618#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474619#L529 assume !(1 == ~t3_pc~0); 1475079#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1475387#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1475468#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1475609#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1474540#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1474541#L548 assume !(1 == ~t4_pc~0); 1474441#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1474440#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1474741#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1474483#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1474484#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1474434#L567 assume !(1 == ~t5_pc~0); 1474435#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1474485#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1474665#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1474666#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1475511#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1474551#L586 assume !(1 == ~t6_pc~0); 1474552#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1474626#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1475641#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1475703#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1475503#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1475504#L605 assume !(1 == ~t7_pc~0); 1475055#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1475056#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1475214#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1475215#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1475669#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1475186#L624 assume !(1 == ~t8_pc~0); 1474611#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1474610#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1475247#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1475248#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1475475#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1474399#L643 assume !(1 == ~t9_pc~0); 1474400#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1475418#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1475333#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1474790#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1474791#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1474594#L1059 assume !(1 == ~M_E~0); 1474595#L1059-2 assume !(1 == ~T1_E~0); 1474759#L1064-1 assume !(1 == ~T2_E~0); 1474760#L1069-1 assume !(1 == ~T3_E~0); 1475429#L1074-1 assume !(1 == ~T4_E~0); 1475474#L1079-1 assume !(1 == ~T5_E~0); 1475463#L1084-1 assume !(1 == ~T6_E~0); 1475464#L1089-1 assume !(1 == ~T7_E~0); 1475496#L1094-1 assume !(1 == ~T8_E~0); 1475107#L1099-1 assume !(1 == ~T9_E~0); 1475108#L1104-1 assume !(1 == ~E_M~0); 1475321#L1109-1 assume !(1 == ~E_1~0); 1474904#L1114-1 assume !(1 == ~E_2~0); 1474905#L1119-1 assume !(1 == ~E_3~0); 1474962#L1124-1 assume !(1 == ~E_4~0); 1474395#L1129-1 assume !(1 == ~E_5~0); 1474396#L1134-1 assume !(1 == ~E_6~0); 1474727#L1139-1 assume !(1 == ~E_7~0); 1474728#L1144-1 assume !(1 == ~E_8~0); 1474922#L1149-1 assume !(1 == ~E_9~0); 1474557#L1154-1 assume { :end_inline_reset_delta_events } true; 1474558#L1440-2 assume !false; 1518283#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1518278#L926
[2021-11-13 17:48:11,928 INFO L793 eck$LassoCheckResult]: Loop: 1518278#L926 assume !false; 1518276#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1518274#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1518273#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1518269#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1518267#L795 assume 0 != eval_~tmp~0#1; 1518264#L795-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1518263#L803 assume !(0 != eval_~tmp_ndt_1~0#1); 1518262#L800 assume !(0 == ~t1_st~0); 1518259#L814 assume !(0 == ~t2_st~0); 1518255#L828 assume !(0 == ~t3_st~0); 1518252#L842 assume !(0 == ~t4_st~0); 1518242#L856 assume !(0 == ~t5_st~0); 1518237#L870 assume !(0 == ~t6_st~0); 1518233#L884 assume !(0 == ~t7_st~0); 1518231#L898 assume !(0 == ~t8_st~0); 1518282#L912 assume !(0 == ~t9_st~0); 1518278#L926
[2021-11-13 17:48:11,928 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:11,929 INFO L85 PathProgramCache]: Analyzing trace with hash 1363771783, now seen corresponding path program 1 times
[2021-11-13 17:48:11,929 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:11,929 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929173027]
[2021-11-13 17:48:11,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:11,929 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:11,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:11,941 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:11,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:11,999 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:12,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:12,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1895676149, now seen corresponding path program 1 times
[2021-11-13 17:48:12,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:12,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422642545]
[2021-11-13 17:48:12,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:12,001 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:12,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:12,004 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:12,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:12,009 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:12,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:12,010 INFO L85 PathProgramCache]: Analyzing trace with hash 572699695, now seen corresponding path program 1 times
[2021-11-13 17:48:12,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:12,010 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [528921673]
[2021-11-13 17:48:12,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:12,010 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:12,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:12,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:12,045 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:12,045 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [528921673]
[2021-11-13 17:48:12,045 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [528921673] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:12,045 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:12,046 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:48:12,046 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933666154]
[2021-11-13 17:48:12,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:12,224 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:12,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:48:12,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:48:12,225 INFO L87 Difference]: Start difference. First operand 91755 states and 123990 transitions. cyclomatic complexity: 32238 Second operand has 3 states, 3 states have (on average 45.333333333333336) internal successors, (136), 3 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:12,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:12,835 INFO L93 Difference]: Finished difference Result 177824 states and 238645 transitions.
[2021-11-13 17:48:12,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:48:12,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177824 states and 238645 transitions.
[2021-11-13 17:48:14,222 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 177520
[2021-11-13 17:48:14,591 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177824 states to 177824 states and 238645 transitions.
[2021-11-13 17:48:14,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177824
[2021-11-13 17:48:14,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177824
[2021-11-13 17:48:14,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177824 states and 238645 transitions.
[2021-11-13 17:48:14,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2021-11-13 17:48:14,710 INFO L681 BuchiCegarLoop]: Abstraction has 177824 states and 238645 transitions.
[2021-11-13 17:48:14,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177824 states and 238645 transitions.
[2021-11-13 17:48:16,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177824 to 173920.
[2021-11-13 17:48:16,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173920 states, 173920 states have (on average 1.342715041398344) internal successors, (233525), 173919 states have internal predecessors, (233525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:16,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173920 states to 173920 states and 233525 transitions.
[2021-11-13 17:48:16,673 INFO L704 BuchiCegarLoop]: Abstraction has 173920 states and 233525 transitions.
[2021-11-13 17:48:16,673 INFO L587 BuchiCegarLoop]: Abstraction has 173920 states and 233525 transitions.
[2021-11-13 17:48:16,673 INFO L425 BuchiCegarLoop]: ======== Iteration 29============
[2021-11-13 17:48:16,673 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173920 states and 233525 transitions.
[2021-11-13 17:48:17,130 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 173616
[2021-11-13 17:48:17,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2021-11-13 17:48:17,131 INFO L119 BuchiIsEmpty]: Starting construction of run
[2021-11-13 17:48:17,847 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:17,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2021-11-13 17:48:17,848 INFO L791 eck$LassoCheckResult]: Stem: 1744885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1744886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1745297#L1403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1744916#L663 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1744789#L670 assume 1 == ~m_i~0;~m_st~0 := 0; 1744503#L670-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1744504#L675-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1774413#L680-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1774412#L685-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1774411#L690-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1774410#L695-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1774409#L700-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1774408#L705-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1774407#L710-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1774406#L715-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1774405#L951 assume !(0 == ~M_E~0); 1774404#L951-2 assume !(0 == ~T1_E~0); 1774403#L956-1 assume !(0 == ~T2_E~0); 1774402#L961-1 assume !(0 == ~T3_E~0); 1774401#L966-1 assume !(0 == ~T4_E~0); 1774400#L971-1 assume !(0 == ~T5_E~0); 1774399#L976-1 assume !(0 == ~T6_E~0); 1774398#L981-1 assume !(0 == ~T7_E~0); 1774397#L986-1 assume !(0 == ~T8_E~0); 1774396#L991-1 assume !(0 == ~T9_E~0); 1774395#L996-1 assume !(0 == ~E_M~0); 1774394#L1001-1 assume !(0 == ~E_1~0); 1774393#L1006-1 assume !(0 == ~E_2~0); 1774392#L1011-1 assume !(0 == ~E_3~0); 1774391#L1016-1 assume !(0 == ~E_4~0); 1774390#L1021-1 assume !(0 == ~E_5~0); 1774389#L1026-1 assume !(0 == ~E_6~0); 1774388#L1031-1 assume !(0 == ~E_7~0); 1774387#L1036-1 assume !(0 == ~E_8~0); 1774386#L1041-1 assume !(0 == ~E_9~0); 1774385#L1046-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1774384#L472 assume !(1 == ~m_pc~0); 1774383#L472-2 is_master_triggered_~__retres1~0#1 := 0; 1774382#L483 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1774381#L484 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1774380#L1179 assume !(0 != activate_threads_~tmp~1#1); 1774379#L1179-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774378#L491 assume !(1 == ~t1_pc~0); 1774377#L491-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1774376#L502 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1774375#L503 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1774374#L1187 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1743946#L1187-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1743968#L510 assume !(1 == ~t2_pc~0); 1743932#L510-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1743933#L521 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1745168#L522 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1745169#L1195 assume !(0 != activate_threads_~tmp___1~0#1); 1744207#L1195-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1744208#L529 assume !(1 == ~t3_pc~0); 1744669#L529-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1745002#L540 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1745090#L541 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1745247#L1203 assume !(0 != activate_threads_~tmp___2~0#1); 1744129#L1203-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1744130#L548 assume !(1 == ~t4_pc~0); 1744029#L548-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1744028#L559 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1744328#L560 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1744072#L1211 assume !(0 != activate_threads_~tmp___3~0#1); 1744073#L1211-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1774243#L567 assume !(1 == ~t5_pc~0); 1774241#L567-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1774239#L578 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1774236#L579 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1774234#L1219 assume !(0 != activate_threads_~tmp___4~0#1); 1774231#L1219-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1774229#L586 assume !(1 == ~t6_pc~0); 1774226#L586-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1774224#L597 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1774222#L598 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1774220#L1227 assume !(0 != activate_threads_~tmp___5~0#1); 1774217#L1227-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1774215#L605 assume !(1 == ~t7_pc~0); 1774213#L605-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1774211#L616 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1774209#L617 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1774207#L1235 assume !(0 != activate_threads_~tmp___6~0#1); 1774205#L1235-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1774203#L624 assume !(1 == ~t8_pc~0); 1774199#L624-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1774197#L635 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1774195#L636 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1774193#L1243 assume !(0 != activate_threads_~tmp___7~0#1); 1774191#L1243-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1774189#L643 assume !(1 == ~t9_pc~0); 1774188#L643-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1745034#L654 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1744946#L655 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1744377#L1251 assume !(0 != activate_threads_~tmp___8~0#1); 1744378#L1251-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1771416#L1059 assume !(1 == ~M_E~0); 1771414#L1059-2 assume !(1 == ~T1_E~0); 1771412#L1064-1 assume !(1 == ~T2_E~0); 1771410#L1069-1 assume !(1 == ~T3_E~0); 1771408#L1074-1 assume !(1 == ~T4_E~0); 1771406#L1079-1 assume !(1 == ~T5_E~0); 1771403#L1084-1 assume !(1 == ~T6_E~0); 1771401#L1089-1 assume !(1 == ~T7_E~0); 1771399#L1094-1 assume !(1 == ~T8_E~0); 1771397#L1099-1 assume !(1 == ~T9_E~0); 1771395#L1104-1 assume !(1 == ~E_M~0); 1771392#L1109-1 assume !(1 == ~E_1~0); 1771390#L1114-1 assume !(1 == ~E_2~0); 1771388#L1119-1 assume !(1 == ~E_3~0); 1771386#L1124-1 assume !(1 == ~E_4~0); 1771384#L1129-1 assume !(1 == ~E_5~0); 1771382#L1134-1 assume !(1 == ~E_6~0); 1771380#L1139-1 assume !(1 == ~E_7~0); 1771378#L1144-1 assume !(1 == ~E_8~0); 1771375#L1149-1 assume !(1 == ~E_9~0); 1771373#L1154-1 assume { :end_inline_reset_delta_events } true; 1771371#L1440-2 assume !false; 1768278#L1441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1768272#L926
[2021-11-13 17:48:17,848 INFO L793 eck$LassoCheckResult]: Loop: 1768272#L926 assume !false; 1768269#L791 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1753791#L728 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1753789#L780 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1753787#L781 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1750428#L795 assume 0 != eval_~tmp~0#1; 1750427#L795-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1750425#L803 assume !(0 != eval_~tmp_ndt_1~0#1); 1750424#L800 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1750421#L817 assume !(0 != eval_~tmp_ndt_2~0#1); 1750423#L814 assume !(0 == ~t2_st~0); 1842110#L828 assume !(0 == ~t3_st~0); 1842105#L842 assume !(0 == ~t4_st~0); 1842097#L856 assume !(0 == ~t5_st~0); 1769958#L870 assume !(0 == ~t6_st~0); 1769952#L884 assume !(0 == ~t7_st~0); 1753809#L898 assume !(0 == ~t8_st~0); 1753807#L912 assume !(0 == ~t9_st~0); 1768272#L926
[2021-11-13 17:48:17,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:17,849 INFO L85 PathProgramCache]: Analyzing trace with hash 981733315, now seen corresponding path program 1 times
[2021-11-13 17:48:17,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:17,849 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617723128]
[2021-11-13 17:48:17,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:17,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:17,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2021-11-13 17:48:17,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2021-11-13 17:48:17,953 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2021-11-13 17:48:17,953 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617723128]
[2021-11-13 17:48:17,954 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617723128] provided 1 perfect and 0 imperfect interpolant sequences
[2021-11-13 17:48:17,954 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2021-11-13 17:48:17,954 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2021-11-13 17:48:17,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315316360]
[2021-11-13 17:48:17,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2021-11-13 17:48:17,955 INFO L796 eck$LassoCheckResult]: stem already infeasible
[2021-11-13 17:48:17,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier
[2021-11-13 17:48:17,955 INFO L85 PathProgramCache]: Analyzing trace with hash 297636057, now seen corresponding path program 1 times
[2021-11-13 17:48:17,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2021-11-13 17:48:17,956 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113675995]
[2021-11-13 17:48:17,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2021-11-13 17:48:17,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2021-11-13 17:48:17,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:17,979 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2021-11-13 17:48:17,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2021-11-13 17:48:17,984 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2021-11-13 17:48:18,196 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2021-11-13 17:48:18,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2021-11-13 17:48:18,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2021-11-13 17:48:18,198 INFO L87 Difference]: Start difference. First operand 173920 states and 233525 transitions. cyclomatic complexity: 59608 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2021-11-13 17:48:18,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2021-11-13 17:48:18,790 INFO L93 Difference]: Finished difference Result 173803 states and 233365 transitions.
[2021-11-13 17:48:18,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2021-11-13 17:48:18,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173803 states and 233365 transitions.
[2021-11-13 17:48:19,490 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 173616