./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cad2c6f6e8ebe2adcd550e4a56b83be37e52f812ae33bfb645236c6925734dbf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:41:49,962 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:41:49,964 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:41:50,000 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:41:50,000 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:41:50,002 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:41:50,004 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:41:50,006 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:41:50,008 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:41:50,009 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:41:50,010 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:41:50,012 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:41:50,012 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:41:50,013 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:41:50,015 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:41:50,016 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:41:50,017 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:41:50,018 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:41:50,020 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:41:50,023 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:41:50,025 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:41:50,030 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:41:50,031 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:41:50,032 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:41:50,037 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:41:50,038 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:41:50,038 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:41:50,039 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:41:50,040 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:41:50,049 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:41:50,050 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:41:50,051 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:41:50,052 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:41:50,053 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:41:50,054 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:41:50,055 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:41:50,055 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:41:50,056 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:41:50,056 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:41:50,057 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:41:50,058 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:41:50,062 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-10-17 10:41:50,095 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:41:50,095 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:41:50,095 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:41:50,096 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:41:50,097 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:41:50,097 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:41:50,097 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:41:50,098 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:41:50,098 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:41:50,098 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:41:50,098 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:41:50,099 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:41:50,099 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:41:50,099 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:41:50,099 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:41:50,100 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:41:50,100 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:41:50,100 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:41:50,100 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:41:50,101 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:41:50,101 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:41:50,101 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:41:50,101 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:41:50,101 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:41:50,102 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:41:50,102 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:41:50,102 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:41:50,103 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:41:50,104 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:41:50,104 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cad2c6f6e8ebe2adcd550e4a56b83be37e52f812ae33bfb645236c6925734dbf [2022-10-17 10:41:50,396 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:41:50,417 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:41:50,420 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:41:50,421 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:41:50,422 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:41:50,424 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c [2022-10-17 10:41:50,499 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/data/8445a4744/61ea6e3d54a64a5bbc7914cc325eb056/FLAG17251915e [2022-10-17 10:41:50,985 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:41:50,985 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/sv-benchmarks/c/termination-crafted/Arrays01-EquivalentConstantIndices-1.c [2022-10-17 10:41:51,013 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/data/8445a4744/61ea6e3d54a64a5bbc7914cc325eb056/FLAG17251915e [2022-10-17 10:41:51,398 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/data/8445a4744/61ea6e3d54a64a5bbc7914cc325eb056 [2022-10-17 10:41:51,400 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:41:51,401 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:41:51,403 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:41:51,403 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:41:51,414 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:41:51,415 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,416 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7415240f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51, skipping insertion in model container [2022-10-17 10:41:51,417 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,426 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:41:51,444 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:41:51,634 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:41:51,637 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:41:51,654 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:41:51,672 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:41:51,673 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51 WrapperNode [2022-10-17 10:41:51,673 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:41:51,674 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:41:51,674 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:41:51,675 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:41:51,682 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,689 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,706 INFO L138 Inliner]: procedures = 8, calls = 9, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 32 [2022-10-17 10:41:51,707 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:41:51,708 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:41:51,708 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:41:51,708 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:41:51,716 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,717 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,718 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,719 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,723 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,727 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,728 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,729 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,731 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:41:51,732 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:41:51,732 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:41:51,733 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:41:51,734 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (1/1) ... [2022-10-17 10:41:51,741 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:51,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:51,768 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:51,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:41:51,821 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:41:51,821 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:41:51,821 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:41:51,822 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:41:51,822 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:41:51,822 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:41:51,887 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:41:51,890 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:41:52,022 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:41:52,028 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:41:52,028 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-10-17 10:41:52,030 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:41:52 BoogieIcfgContainer [2022-10-17 10:41:52,031 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:41:52,032 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:41:52,032 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:41:52,036 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:41:52,037 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:41:52,037 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:41:51" (1/3) ... [2022-10-17 10:41:52,038 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a3a40f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:41:52, skipping insertion in model container [2022-10-17 10:41:52,038 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:41:52,038 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:41:51" (2/3) ... [2022-10-17 10:41:52,039 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3a3a40f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:41:52, skipping insertion in model container [2022-10-17 10:41:52,039 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:41:52,039 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:41:52" (3/3) ... [2022-10-17 10:41:52,040 INFO L332 chiAutomizerObserver]: Analyzing ICFG Arrays01-EquivalentConstantIndices-1.c [2022-10-17 10:41:52,091 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:41:52,092 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:41:52,092 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:41:52,092 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:41:52,092 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:41:52,092 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:41:52,092 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:41:52,092 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:41:52,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:52,114 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-10-17 10:41:52,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:52,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:52,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:41:52,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:52,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:41:52,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:52,121 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2022-10-17 10:41:52,121 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:52,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:52,122 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:41:52,122 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:52,145 INFO L748 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 7#L13-3true [2022-10-17 10:41:52,145 INFO L750 eck$LassoCheckResult]: Loop: 7#L13-3true assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 6#L13-2true main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 7#L13-3true [2022-10-17 10:41:52,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:52,152 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:41:52,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:52,162 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841814212] [2022-10-17 10:41:52,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:52,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:52,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,259 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:52,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,291 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:52,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:52,295 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-10-17 10:41:52,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:52,295 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247429966] [2022-10-17 10:41:52,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:52,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:52,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,310 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:52,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,322 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:52,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:52,324 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-10-17 10:41:52,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:52,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948795753] [2022-10-17 10:41:52,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:52,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:52,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,352 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:52,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:52,370 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:52,676 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:41:52,677 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:41:52,677 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:41:52,677 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:41:52,678 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:41:52,678 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:52,678 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:41:52,678 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:41:52,679 INFO L133 ssoRankerPreferences]: Filename of dumped script: Arrays01-EquivalentConstantIndices-1.c_Iteration1_Lasso [2022-10-17 10:41:52,679 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:41:52,679 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:41:52,704 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,722 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,827 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,830 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,833 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,836 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:52,839 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:41:53,036 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:41:53,041 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:41:53,043 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,046 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 10:41:53,053 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,060 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,060 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,061 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,061 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,069 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:41:53,069 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:41:53,087 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,117 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,117 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,119 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 10:41:53,128 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,137 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,138 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,138 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,138 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,146 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:41:53,147 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:41:53,173 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,199 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,200 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,200 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,201 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,202 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:41:53,203 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,210 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,210 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,210 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,210 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,216 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:41:53,216 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:41:53,237 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,277 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,278 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,282 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,289 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,299 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,299 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,299 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,300 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,307 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:41:53,307 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:41:53,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:41:53,321 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,349 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,349 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,351 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:41:53,353 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,362 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,362 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:41:53,362 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,362 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,362 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,363 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:41:53,363 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:41:53,367 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,390 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,391 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:41:53,396 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,405 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,405 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:41:53,405 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,405 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,405 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,406 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:41:53,406 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:41:53,413 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:41:53,435 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,438 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,439 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:41:53,439 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:41:53,446 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:41:53,447 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:41:53,447 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:41:53,447 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:41:53,453 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:41:53,453 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:41:53,501 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:41:53,529 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2022-10-17 10:41:53,529 INFO L444 ModelExtractionUtils]: 3 out of 13 variables were initially zero. Simplification set additionally 7 variables to zero. [2022-10-17 10:41:53,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:41:53,531 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:53,537 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:41:53,539 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:41:53,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 10:41:53,550 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:41:53,550 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:41:53,551 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = 2095*v_rep(select #length ULTIMATE.start_main_~#a~0#1.base)_1 - 8*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2022-10-17 10:41:53,570 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:53,579 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2022-10-17 10:41:53,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:53,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:53,650 INFO L263 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:41:53,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:53,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:53,678 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:41:53,679 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:53,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:53,799 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:41:53,815 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:53,867 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 22 states and 31 transitions. Complement of second has 8 states. [2022-10-17 10:41:53,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:41:53,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:53,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 17 transitions. [2022-10-17 10:41:53,876 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 2 letters. Loop has 2 letters. [2022-10-17 10:41:53,877 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:41:53,877 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 4 letters. Loop has 2 letters. [2022-10-17 10:41:53,877 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:41:53,877 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 17 transitions. Stem has 2 letters. Loop has 4 letters. [2022-10-17 10:41:53,878 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:41:53,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 31 transitions. [2022-10-17 10:41:53,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:53,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 8 states and 10 transitions. [2022-10-17 10:41:53,886 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:53,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-10-17 10:41:53,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 10 transitions. [2022-10-17 10:41:53,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:53,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 10 transitions. [2022-10-17 10:41:53,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 10 transitions. [2022-10-17 10:41:53,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 7. [2022-10-17 10:41:53,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.2857142857142858) internal successors, (9), 6 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:53,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 9 transitions. [2022-10-17 10:41:53,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 9 transitions. [2022-10-17 10:41:53,931 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 9 transitions. [2022-10-17 10:41:53,932 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:41:53,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 9 transitions. [2022-10-17 10:41:53,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:53,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:53,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:53,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-10-17 10:41:53,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:53,935 INFO L748 eck$LassoCheckResult]: Stem: 77#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 78#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 81#L13-3 assume !(main_~i~0#1 < 1048); 75#L17-2 [2022-10-17 10:41:53,936 INFO L750 eck$LassoCheckResult]: Loop: 75#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 76#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 75#L17-2 [2022-10-17 10:41:53,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:53,938 INFO L85 PathProgramCache]: Analyzing trace with hash 29861, now seen corresponding path program 1 times [2022-10-17 10:41:53,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:53,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14731832] [2022-10-17 10:41:53,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:53,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:53,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:54,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:41:54,056 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14731832] [2022-10-17 10:41:54,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14731832] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:41:54,057 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:41:54,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:41:54,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807151339] [2022-10-17 10:41:54,061 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:41:54,063 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:41:54,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:54,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 1 times [2022-10-17 10:41:54,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:54,065 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128694138] [2022-10-17 10:41:54,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:54,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:54,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,099 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:54,161 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:41:54,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:41:54,165 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:41:54,166 INFO L87 Difference]: Start difference. First operand 7 states and 9 transitions. cyclomatic complexity: 4 Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 3 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:54,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:41:54,179 INFO L93 Difference]: Finished difference Result 8 states and 9 transitions. [2022-10-17 10:41:54,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8 states and 9 transitions. [2022-10-17 10:41:54,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:54,180 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8 states to 8 states and 9 transitions. [2022-10-17 10:41:54,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:54,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:41:54,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 9 transitions. [2022-10-17 10:41:54,181 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:54,181 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 9 transitions. [2022-10-17 10:41:54,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 9 transitions. [2022-10-17 10:41:54,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 7. [2022-10-17 10:41:54,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:54,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2022-10-17 10:41:54,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-10-17 10:41:54,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:41:54,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2022-10-17 10:41:54,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:41:54,186 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2022-10-17 10:41:54,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:54,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:54,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:54,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-10-17 10:41:54,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:54,188 INFO L748 eck$LassoCheckResult]: Stem: 98#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 99#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 102#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 100#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 101#L13-3 assume !(main_~i~0#1 < 1048); 96#L17-2 [2022-10-17 10:41:54,188 INFO L750 eck$LassoCheckResult]: Loop: 96#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 97#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 96#L17-2 [2022-10-17 10:41:54,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:54,189 INFO L85 PathProgramCache]: Analyzing trace with hash 28698723, now seen corresponding path program 1 times [2022-10-17 10:41:54,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:54,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843249324] [2022-10-17 10:41:54,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:54,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:54,249 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:41:54,250 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843249324] [2022-10-17 10:41:54,250 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1843249324] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:41:54,251 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87144955] [2022-10-17 10:41:54,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,251 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:41:54,251 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:54,257 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:41:54,276 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-10-17 10:41:54,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:54,308 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:41:54,308 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:54,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,320 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:41:54,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87144955] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:41:54,375 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:41:54,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-10-17 10:41:54,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789840046] [2022-10-17 10:41:54,376 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:41:54,376 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:41:54,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:54,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 2 times [2022-10-17 10:41:54,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:54,377 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408917343] [2022-10-17 10:41:54,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:54,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,384 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:54,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,390 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:54,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 10:41:54,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:41:54,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:41:54,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:41:54,450 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 3 Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:54,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:41:54,482 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2022-10-17 10:41:54,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2022-10-17 10:41:54,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:54,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 14 transitions. [2022-10-17 10:41:54,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:54,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:41:54,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 14 transitions. [2022-10-17 10:41:54,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:54,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-10-17 10:41:54,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 14 transitions. [2022-10-17 10:41:54,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2022-10-17 10:41:54,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.0769230769230769) internal successors, (14), 12 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:54,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2022-10-17 10:41:54,487 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-10-17 10:41:54,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:41:54,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-10-17 10:41:54,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:41:54,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 14 transitions. [2022-10-17 10:41:54,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:54,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:54,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:54,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1] [2022-10-17 10:41:54,490 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:54,490 INFO L748 eck$LassoCheckResult]: Stem: 152#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 156#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 154#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 155#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 157#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 162#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 161#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 160#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 159#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 158#L13-3 assume !(main_~i~0#1 < 1048); 150#L17-2 [2022-10-17 10:41:54,491 INFO L750 eck$LassoCheckResult]: Loop: 150#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 151#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 150#L17-2 [2022-10-17 10:41:54,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:54,491 INFO L85 PathProgramCache]: Analyzing trace with hash -1081477475, now seen corresponding path program 2 times [2022-10-17 10:41:54,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:54,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372204031] [2022-10-17 10:41:54,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:54,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:54,664 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:41:54,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372204031] [2022-10-17 10:41:54,665 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372204031] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:41:54,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [562088241] [2022-10-17 10:41:54,665 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:41:54,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:41:54,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:54,670 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:41:54,694 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-10-17 10:41:54,740 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:41:54,740 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:41:54,741 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:41:54,742 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:54,794 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,795 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:41:54,868 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:54,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [562088241] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:41:54,869 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:41:54,869 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-10-17 10:41:54,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896882767] [2022-10-17 10:41:54,869 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:41:54,871 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:41:54,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:54,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 3 times [2022-10-17 10:41:54,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:54,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293762377] [2022-10-17 10:41:54,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:54,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:54,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,884 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:54,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:54,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:54,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:41:54,950 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:41:54,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:41:54,951 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. cyclomatic complexity: 3 Second operand has 13 states, 12 states have (on average 2.0) internal successors, (24), 13 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:55,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:41:55,024 INFO L93 Difference]: Finished difference Result 25 states and 26 transitions. [2022-10-17 10:41:55,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 26 transitions. [2022-10-17 10:41:55,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:55,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 26 transitions. [2022-10-17 10:41:55,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:55,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:41:55,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 26 transitions. [2022-10-17 10:41:55,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:55,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-10-17 10:41:55,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 26 transitions. [2022-10-17 10:41:55,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2022-10-17 10:41:55,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.04) internal successors, (26), 24 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:55,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 26 transitions. [2022-10-17 10:41:55,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-10-17 10:41:55,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:41:55,044 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2022-10-17 10:41:55,044 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:41:55,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 26 transitions. [2022-10-17 10:41:55,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:55,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:55,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:55,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1] [2022-10-17 10:41:55,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:55,050 INFO L748 eck$LassoCheckResult]: Stem: 266#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 267#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 270#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 271#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 272#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 268#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 269#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 288#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 287#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 286#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 285#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 284#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 283#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 282#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 281#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 280#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 279#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 278#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 277#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 276#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 275#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 274#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 273#L13-3 assume !(main_~i~0#1 < 1048); 264#L17-2 [2022-10-17 10:41:55,050 INFO L750 eck$LassoCheckResult]: Loop: 264#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 265#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 264#L17-2 [2022-10-17 10:41:55,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:55,051 INFO L85 PathProgramCache]: Analyzing trace with hash 899905681, now seen corresponding path program 3 times [2022-10-17 10:41:55,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:55,051 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729352458] [2022-10-17 10:41:55,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:55,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:55,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:55,365 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:55,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:41:55,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729352458] [2022-10-17 10:41:55,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1729352458] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:41:55,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [978862973] [2022-10-17 10:41:55,366 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:41:55,367 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:41:55,367 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:55,390 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:41:55,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-10-17 10:41:55,495 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-10-17 10:41:55,496 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:41:55,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 134 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-17 10:41:55,499 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:55,549 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:55,549 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:41:55,784 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:55,786 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [978862973] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:41:55,786 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:41:55,786 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-10-17 10:41:55,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337871422] [2022-10-17 10:41:55,787 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:41:55,787 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:41:55,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:55,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 4 times [2022-10-17 10:41:55,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:55,789 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176881837] [2022-10-17 10:41:55,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:55,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:55,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:55,798 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:55,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:55,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:55,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:41:55,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-10-17 10:41:55,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-10-17 10:41:55,853 INFO L87 Difference]: Start difference. First operand 25 states and 26 transitions. cyclomatic complexity: 3 Second operand has 25 states, 24 states have (on average 2.0) internal successors, (48), 25 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:55,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:41:55,957 INFO L93 Difference]: Finished difference Result 49 states and 50 transitions. [2022-10-17 10:41:55,957 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 50 transitions. [2022-10-17 10:41:55,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:55,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 49 states and 50 transitions. [2022-10-17 10:41:55,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:55,964 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:41:55,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 50 transitions. [2022-10-17 10:41:55,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:55,965 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-10-17 10:41:55,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 50 transitions. [2022-10-17 10:41:55,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2022-10-17 10:41:55,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0204081632653061) internal successors, (50), 48 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:55,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2022-10-17 10:41:55,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-10-17 10:41:55,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:41:55,977 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2022-10-17 10:41:55,978 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:41:55,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 50 transitions. [2022-10-17 10:41:55,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:55,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:55,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:55,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1] [2022-10-17 10:41:55,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:55,986 INFO L748 eck$LassoCheckResult]: Stem: 500#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 504#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 505#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 506#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 502#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 503#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 546#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 545#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 544#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 543#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 542#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 541#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 540#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 539#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 538#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 537#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 536#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 535#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 534#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 533#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 532#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 531#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 530#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 529#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 528#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 527#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 526#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 525#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 524#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 523#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 522#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 521#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 520#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 519#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 518#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 517#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 516#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 515#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 514#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 513#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 512#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 511#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 510#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 509#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 508#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 507#L13-3 assume !(main_~i~0#1 < 1048); 498#L17-2 [2022-10-17 10:41:55,986 INFO L750 eck$LassoCheckResult]: Loop: 498#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 499#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 498#L17-2 [2022-10-17 10:41:55,987 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:55,987 INFO L85 PathProgramCache]: Analyzing trace with hash -111832455, now seen corresponding path program 4 times [2022-10-17 10:41:55,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:55,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24048076] [2022-10-17 10:41:55,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:55,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:56,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:41:56,713 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:56,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:41:56,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24048076] [2022-10-17 10:41:56,714 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24048076] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:41:56,714 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [196176705] [2022-10-17 10:41:56,714 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:41:56,714 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:41:56,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:41:56,716 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:41:56,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-10-17 10:41:56,809 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:41:56,809 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:41:56,811 INFO L263 TraceCheckSpWp]: Trace formula consists of 266 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-17 10:41:56,815 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:41:56,912 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:56,912 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:41:57,755 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:41:57,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [196176705] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:41:57,755 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:41:57,756 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-10-17 10:41:57,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249803753] [2022-10-17 10:41:57,756 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:41:57,757 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:41:57,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:57,757 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 5 times [2022-10-17 10:41:57,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:57,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666936833] [2022-10-17 10:41:57,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:57,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:57,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:57,764 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:41:57,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:41:57,770 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:41:57,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:41:57,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-10-17 10:41:57,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-10-17 10:41:57,813 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. cyclomatic complexity: 3 Second operand has 49 states, 48 states have (on average 2.0) internal successors, (96), 49 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:58,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:41:58,040 INFO L93 Difference]: Finished difference Result 97 states and 98 transitions. [2022-10-17 10:41:58,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 98 transitions. [2022-10-17 10:41:58,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:58,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 98 transitions. [2022-10-17 10:41:58,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:41:58,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:41:58,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 98 transitions. [2022-10-17 10:41:58,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:41:58,055 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-10-17 10:41:58,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 98 transitions. [2022-10-17 10:41:58,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2022-10-17 10:41:58,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0103092783505154) internal successors, (98), 96 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:41:58,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2022-10-17 10:41:58,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-10-17 10:41:58,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-10-17 10:41:58,068 INFO L428 stractBuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2022-10-17 10:41:58,068 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:41:58,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 98 transitions. [2022-10-17 10:41:58,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:41:58,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:41:58,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:41:58,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1] [2022-10-17 10:41:58,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:41:58,082 INFO L748 eck$LassoCheckResult]: Stem: 974#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 978#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 979#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 980#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 976#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 977#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1068#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1067#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1066#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1065#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1064#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1063#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1062#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1061#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1060#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1059#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1058#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1057#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1056#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1055#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1054#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1053#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1052#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1051#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1050#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1049#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1048#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1047#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1046#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1045#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1044#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1043#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1042#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1041#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1040#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1039#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1038#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1037#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1036#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1035#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1034#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1033#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1032#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1031#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1030#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1029#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1028#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1027#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1026#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1025#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1024#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1023#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1022#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1021#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1020#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1019#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1018#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1017#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1016#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1015#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1014#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1013#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1012#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1011#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1010#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1009#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1008#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1007#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1006#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1005#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1004#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1003#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1002#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1001#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1000#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 999#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 998#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 997#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 996#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 995#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 994#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 993#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 992#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 991#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 990#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 989#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 988#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 987#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 986#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 985#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 984#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 983#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 982#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 981#L13-3 assume !(main_~i~0#1 < 1048); 972#L17-2 [2022-10-17 10:41:58,086 INFO L750 eck$LassoCheckResult]: Loop: 972#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 973#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 972#L17-2 [2022-10-17 10:41:58,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:41:58,086 INFO L85 PathProgramCache]: Analyzing trace with hash -1497227703, now seen corresponding path program 5 times [2022-10-17 10:41:58,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:41:58,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732805271] [2022-10-17 10:41:58,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:41:58,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:41:58,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:00,419 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:00,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:00,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732805271] [2022-10-17 10:42:00,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [732805271] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:42:00,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1490017822] [2022-10-17 10:42:00,420 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:42:00,420 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:42:00,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:00,422 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:42:00,445 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_47fc26a3-1dfc-412a-bbe5-3ed6a99ed78c/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-10-17 10:42:13,896 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-10-17 10:42:13,896 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:42:13,925 INFO L263 TraceCheckSpWp]: Trace formula consists of 530 conjuncts, 48 conjunts are in the unsatisfiable core [2022-10-17 10:42:13,931 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:42:14,160 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:14,161 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:42:17,100 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:17,100 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1490017822] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:42:17,102 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:42:17,102 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-10-17 10:42:17,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698092983] [2022-10-17 10:42:17,103 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:42:17,104 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:42:17,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:17,105 INFO L85 PathProgramCache]: Analyzing trace with hash 1574, now seen corresponding path program 6 times [2022-10-17 10:42:17,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:17,105 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964654260] [2022-10-17 10:42:17,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:17,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:17,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:17,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:17,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:17,120 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:17,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:17,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-10-17 10:42:17,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-10-17 10:42:17,175 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. cyclomatic complexity: 3 Second operand has 97 states, 96 states have (on average 2.0) internal successors, (192), 97 states have internal predecessors, (192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:17,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:17,732 INFO L93 Difference]: Finished difference Result 193 states and 194 transitions. [2022-10-17 10:42:17,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 194 transitions. [2022-10-17 10:42:17,734 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:42:17,737 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 193 states and 194 transitions. [2022-10-17 10:42:17,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2022-10-17 10:42:17,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2022-10-17 10:42:17,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 194 transitions. [2022-10-17 10:42:17,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:17,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-10-17 10:42:17,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 194 transitions. [2022-10-17 10:42:17,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 193. [2022-10-17 10:42:17,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 193 states have (on average 1.005181347150259) internal successors, (194), 192 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:17,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 194 transitions. [2022-10-17 10:42:17,752 INFO L240 hiAutomatonCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-10-17 10:42:17,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-10-17 10:42:17,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 193 states and 194 transitions. [2022-10-17 10:42:17,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:42:17,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 193 states and 194 transitions. [2022-10-17 10:42:17,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:42:17,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:17,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:17,758 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1] [2022-10-17 10:42:17,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:42:17,764 INFO L748 eck$LassoCheckResult]: Stem: 1928#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1929#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post0#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem2#1, main_~#a~0#1.base, main_~#a~0#1.offset;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 1932#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1933#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1934#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1930#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1931#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2118#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2117#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2116#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2115#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2114#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2113#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2112#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2111#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2110#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2109#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2108#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2107#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2106#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2105#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2104#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2103#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2102#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2101#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2100#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2099#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2098#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2097#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2096#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2095#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2094#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2093#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2092#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2091#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2090#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2089#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2088#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2087#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2086#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2085#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2084#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2083#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2082#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2081#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2080#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2079#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2078#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2077#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2076#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2075#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2074#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2073#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2072#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2071#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2070#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2069#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2068#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2067#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2066#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2065#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2064#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2063#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2062#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2061#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2060#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2059#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2058#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2057#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2056#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2055#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2054#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2053#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2052#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2051#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2050#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2049#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2048#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2047#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2046#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2045#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2044#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2043#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2042#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2041#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2040#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2039#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2038#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2037#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2036#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2035#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2034#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2033#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2032#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2031#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2030#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2029#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2028#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2027#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2026#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2025#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2024#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2023#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2022#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2021#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2020#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2019#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2018#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2017#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2016#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2015#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2014#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2013#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2012#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2011#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2010#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2009#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2008#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2007#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2006#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2005#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2004#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2003#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2002#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 2001#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 2000#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1999#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1998#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1997#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1996#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1995#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1994#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1993#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1992#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1991#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1990#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1989#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1988#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1987#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1986#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1985#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1984#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1983#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1982#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1981#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1980#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1979#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1978#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1977#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1976#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1975#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1974#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1973#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1972#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1971#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1970#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1969#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1968#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1967#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1966#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1965#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1964#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1963#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1962#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1961#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1960#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1959#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1958#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1957#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1956#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1955#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1954#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1953#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1952#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1951#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1950#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1949#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1948#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1947#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1946#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1945#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1944#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1943#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1942#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1941#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1940#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1939#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1938#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1937#L13-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet1#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet1#1; 1936#L13-2 main_#t~post0#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post0#1;havoc main_#t~post0#1; 1935#L13-3 assume !(main_~i~0#1 < 1048); 1926#L17-2 [2022-10-17 10:42:17,765 INFO L750 eck$LassoCheckResult]: Loop: 1926#L17-2 call main_#t~mem2#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4); 1927#L17 assume !!(main_#t~mem2#1 >= 0);havoc main_#t~mem2#1;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);call write~int(main_#t~mem3#1 - 1, main_~#a~0#1.base, 12 + main_~#a~0#1.offset, 4);havoc main_#t~mem3#1; 1926#L17-2 [2022-10-17 10:42:17,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:17,765 INFO L85 PathProgramCache]: Analyzing trace with hash 2115802601, now seen corresponding path program 6 times [2022-10-17 10:42:17,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:17,766 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318918841] [2022-10-17 10:42:17,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:17,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:17,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat