./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 302c18c494f9017ecbb07643194b1d54ba0a6bba467355d4f775638dea57e539 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:12:20,116 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:12:20,118 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:12:20,182 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:12:20,182 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:12:20,189 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:12:20,193 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:12:20,197 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:12:20,200 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:12:20,210 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:12:20,211 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:12:20,213 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:12:20,214 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:12:20,218 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:12:20,221 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:12:20,223 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:12:20,226 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:12:20,227 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:12:20,229 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:12:20,242 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:12:20,245 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:12:20,247 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:12:20,251 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:12:20,253 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:12:20,259 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:12:20,259 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:12:20,260 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:12:20,263 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:12:20,264 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:12:20,265 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:12:20,266 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:12:20,267 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:12:20,269 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:12:20,272 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:12:20,273 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:12:20,273 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:12:20,274 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:12:20,282 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:12:20,282 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:12:20,284 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:12:20,285 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:12:20,286 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-10-17 10:12:20,357 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:12:20,359 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:12:20,360 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:12:20,360 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:12:20,362 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:12:20,362 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:12:20,363 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:12:20,363 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:12:20,363 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:12:20,364 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:12:20,365 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:12:20,366 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:12:20,366 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:12:20,366 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:12:20,366 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:12:20,367 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:12:20,367 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:12:20,367 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:12:20,368 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:12:20,368 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:12:20,368 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:12:20,368 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:12:20,369 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:12:20,369 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:12:20,370 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:12:20,370 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:12:20,370 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:12:20,371 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:12:20,372 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:12:20,372 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 302c18c494f9017ecbb07643194b1d54ba0a6bba467355d4f775638dea57e539 [2022-10-17 10:12:20,732 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:12:20,761 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:12:20,765 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:12:20,767 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:12:20,768 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:12:20,770 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c [2022-10-17 10:12:20,859 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/data/76df76124/9e8dedab3dc245aeb72a1d82d91e0e3f/FLAGb7a6cd75d [2022-10-17 10:12:21,426 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:12:21,426 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/sv-benchmarks/c/termination-crafted/Arrays03-ValueRestictsIndex-2.c [2022-10-17 10:12:21,434 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/data/76df76124/9e8dedab3dc245aeb72a1d82d91e0e3f/FLAGb7a6cd75d [2022-10-17 10:12:21,752 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/data/76df76124/9e8dedab3dc245aeb72a1d82d91e0e3f [2022-10-17 10:12:21,755 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:12:21,757 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:12:21,759 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:12:21,760 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:12:21,764 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:12:21,765 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:12:21" (1/1) ... [2022-10-17 10:12:21,767 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@69f6877a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:21, skipping insertion in model container [2022-10-17 10:12:21,767 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:12:21" (1/1) ... [2022-10-17 10:12:21,776 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:12:21,791 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:12:22,036 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:12:22,043 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:12:22,071 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:12:22,092 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:12:22,094 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22 WrapperNode [2022-10-17 10:12:22,094 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:12:22,096 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:12:22,096 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:12:22,096 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:12:22,105 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,119 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,145 INFO L138 Inliner]: procedures = 8, calls = 8, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 44 [2022-10-17 10:12:22,145 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:12:22,147 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:12:22,147 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:12:22,148 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:12:22,158 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,158 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,176 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,176 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,182 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,190 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,192 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,193 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,195 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:12:22,196 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:12:22,197 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:12:22,197 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:12:22,198 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (1/1) ... [2022-10-17 10:12:22,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:22,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:22,240 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:22,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:12:22,312 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:12:22,313 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:12:22,313 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:12:22,313 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:12:22,313 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:12:22,313 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:12:22,394 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:12:22,397 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:12:22,545 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:12:22,552 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:12:22,553 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-10-17 10:12:22,555 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:12:22 BoogieIcfgContainer [2022-10-17 10:12:22,555 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:12:22,557 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:12:22,557 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:12:22,562 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:12:22,563 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:12:22,563 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:12:21" (1/3) ... [2022-10-17 10:12:22,565 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@331c3570 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:12:22, skipping insertion in model container [2022-10-17 10:12:22,565 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:12:22,565 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:12:22" (2/3) ... [2022-10-17 10:12:22,566 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@331c3570 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:12:22, skipping insertion in model container [2022-10-17 10:12:22,566 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:12:22,566 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:12:22" (3/3) ... [2022-10-17 10:12:22,568 INFO L332 chiAutomizerObserver]: Analyzing ICFG Arrays03-ValueRestictsIndex-2.c [2022-10-17 10:12:22,635 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:12:22,635 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:12:22,635 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:12:22,636 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:12:22,636 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:12:22,636 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:12:22,636 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:12:22,637 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:12:22,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 12 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:22,664 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3 [2022-10-17 10:12:22,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:22,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:22,671 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:12:22,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:12:22,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:12:22,672 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 12 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:22,674 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3 [2022-10-17 10:12:22,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:22,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:22,675 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:12:22,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:12:22,684 INFO L748 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 6#L15-3true [2022-10-17 10:12:22,685 INFO L750 eck$LassoCheckResult]: Loop: 6#L15-3true assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 12#L15-2true main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 6#L15-3true [2022-10-17 10:12:22,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:22,693 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:12:22,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:22,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343977534] [2022-10-17 10:12:22,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:22,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:22,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:22,822 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:22,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:22,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:22,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:22,914 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-10-17 10:12:22,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:22,915 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771930757] [2022-10-17 10:12:22,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:22,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:22,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:22,954 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:22,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:22,973 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:22,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:22,976 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-10-17 10:12:22,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:22,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509093288] [2022-10-17 10:12:22,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:22,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:23,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:23,026 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:23,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:23,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:23,514 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:12:23,515 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:12:23,515 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:12:23,515 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:12:23,515 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:12:23,516 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:23,516 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:12:23,516 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:12:23,517 INFO L133 ssoRankerPreferences]: Filename of dumped script: Arrays03-ValueRestictsIndex-2.c_Iteration1_Lasso [2022-10-17 10:12:23,517 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:12:23,517 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:12:23,549 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,568 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,572 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,582 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,590 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,594 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,598 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,747 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,753 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,758 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,763 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,767 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:12:23,979 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:12:23,984 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:12:23,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:23,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:23,989 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:23,996 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,008 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,008 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,009 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,009 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,009 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,012 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,012 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,012 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 10:12:24,024 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,068 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,069 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,070 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,078 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,090 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,090 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,090 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,090 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,090 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,093 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,093 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,095 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 10:12:24,102 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,147 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,148 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,150 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,157 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,169 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,169 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,169 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,169 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,177 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:12:24,178 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:12:24,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:12:24,202 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,247 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,247 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,247 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,249 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,255 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,267 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,268 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,268 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,268 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,268 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:12:24,270 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,270 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,286 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,332 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,333 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,333 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,334 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,342 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,353 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,354 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,354 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,354 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,354 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,355 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,355 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:12:24,370 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,414 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,415 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,416 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,423 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,434 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,434 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,434 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,435 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,435 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,435 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,436 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:12:24,450 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,495 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,495 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,495 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,497 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,503 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,514 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,514 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,515 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,515 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,515 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,516 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,516 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,518 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:12:24,534 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,578 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,578 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,578 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,579 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,586 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,597 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,597 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,597 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,597 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,602 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:12:24,602 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:12:24,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 10:12:24,626 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,671 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,671 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,672 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,675 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-10-17 10:12:24,681 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,694 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,694 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,694 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,694 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,698 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:12:24,699 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:12:24,722 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,765 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,766 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,766 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,771 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-10-17 10:12:24,779 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,790 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,790 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,790 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,791 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,805 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:12:24,806 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:12:24,822 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,859 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,860 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,860 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,861 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,868 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,878 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,879 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:12:24,879 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,879 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,879 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,880 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:12:24,880 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:12:24,886 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-10-17 10:12:24,902 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:12:24,939 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:24,939 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:24,940 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:24,941 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:24,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-10-17 10:12:24,955 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:12:24,966 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:12:24,966 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:12:24,967 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:12:24,967 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:12:24,973 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:12:24,974 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:12:24,994 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:12:25,017 INFO L443 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2022-10-17 10:12:25,018 INFO L444 ModelExtractionUtils]: 5 out of 13 variables were initially zero. Simplification set additionally 5 variables to zero. [2022-10-17 10:12:25,020 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:12:25,020 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:25,026 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:12:25,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-10-17 10:12:25,063 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:12:25,088 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:12:25,088 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:12:25,089 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 2095 Supporting invariants [] [2022-10-17 10:12:25,130 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2022-10-17 10:12:25,137 INFO L156 tatePredicateManager]: 1 out of 1 supporting invariants were superfluous and have been removed [2022-10-17 10:12:25,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,197 INFO L263 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:12:25,199 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:25,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,221 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:12:25,222 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:25,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:25,303 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:12:25,305 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 12 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,374 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 12 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 30 states and 48 transitions. Complement of second has 7 states. [2022-10-17 10:12:25,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:12:25,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 30 transitions. [2022-10-17 10:12:25,391 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 2 letters. [2022-10-17 10:12:25,392 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:12:25,392 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 4 letters. Loop has 2 letters. [2022-10-17 10:12:25,393 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:12:25,393 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 4 letters. [2022-10-17 10:12:25,393 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:12:25,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 48 transitions. [2022-10-17 10:12:25,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 9 states and 12 transitions. [2022-10-17 10:12:25,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-10-17 10:12:25,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:25,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 12 transitions. [2022-10-17 10:12:25,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:25,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 12 transitions. [2022-10-17 10:12:25,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 12 transitions. [2022-10-17 10:12:25,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2022-10-17 10:12:25,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.3333333333333333) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 12 transitions. [2022-10-17 10:12:25,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 12 transitions. [2022-10-17 10:12:25,442 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 12 transitions. [2022-10-17 10:12:25,442 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:12:25,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 12 transitions. [2022-10-17 10:12:25,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:25,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:25,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-10-17 10:12:25,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:25,444 INFO L748 eck$LassoCheckResult]: Stem: 86#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 87#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 88#L15-3 assume !(main_~i~0#1 < 1048); 84#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 85#L20 assume !main_#t~short5#1; 91#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 92#L22-2 [2022-10-17 10:12:25,444 INFO L750 eck$LassoCheckResult]: Loop: 92#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 92#L22-2 [2022-10-17 10:12:25,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,445 INFO L85 PathProgramCache]: Analyzing trace with hash 889607089, now seen corresponding path program 1 times [2022-10-17 10:12:25,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:25,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495525298] [2022-10-17 10:12:25,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:25,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:25,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:25,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495525298] [2022-10-17 10:12:25,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495525298] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:12:25,545 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:12:25,545 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:12:25,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821754641] [2022-10-17 10:12:25,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:12:25,549 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:25,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,549 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 1 times [2022-10-17 10:12:25,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:25,550 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107155066] [2022-10-17 10:12:25,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:25,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:25,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:25,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:25,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:25,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:25,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:12:25,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:12:25,589 INFO L87 Difference]: Start difference. First operand 9 states and 12 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:25,628 INFO L93 Difference]: Finished difference Result 10 states and 12 transitions. [2022-10-17 10:12:25,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 12 transitions. [2022-10-17 10:12:25,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 10 states and 12 transitions. [2022-10-17 10:12:25,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:25,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:25,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 12 transitions. [2022-10-17 10:12:25,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:25,630 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 12 transitions. [2022-10-17 10:12:25,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 12 transitions. [2022-10-17 10:12:25,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 9. [2022-10-17 10:12:25,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2022-10-17 10:12:25,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 11 transitions. [2022-10-17 10:12:25,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:12:25,634 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2022-10-17 10:12:25,634 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:12:25,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 11 transitions. [2022-10-17 10:12:25,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:25,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:25,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:25,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:25,636 INFO L748 eck$LassoCheckResult]: Stem: 111#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 113#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 114#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 115#L15-3 assume !(main_~i~0#1 < 1048); 109#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 110#L20 assume !main_#t~short5#1; 116#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 117#L22-2 [2022-10-17 10:12:25,636 INFO L750 eck$LassoCheckResult]: Loop: 117#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 117#L22-2 [2022-10-17 10:12:25,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,636 INFO L85 PathProgramCache]: Analyzing trace with hash 265183027, now seen corresponding path program 1 times [2022-10-17 10:12:25,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:25,637 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478534777] [2022-10-17 10:12:25,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:25,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,769 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:25,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:25,769 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478534777] [2022-10-17 10:12:25,769 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478534777] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:25,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1167175321] [2022-10-17 10:12:25,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:25,771 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:25,774 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:25,777 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-10-17 10:12:25,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,824 INFO L263 TraceCheckSpWp]: Trace formula consists of 48 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:12:25,825 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:25,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:12:25,833 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:12:25,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1167175321] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:12:25,834 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-17 10:12:25,834 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [4] total 5 [2022-10-17 10:12:25,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427419212] [2022-10-17 10:12:25,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:12:25,835 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:25,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,836 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 2 times [2022-10-17 10:12:25,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:25,836 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007449976] [2022-10-17 10:12:25,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:25,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:25,841 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:25,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:25,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:25,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:25,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:12:25,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:12:25,862 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. cyclomatic complexity: 4 Second operand has 3 states, 2 states have (on average 4.0) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:25,871 INFO L93 Difference]: Finished difference Result 10 states and 11 transitions. [2022-10-17 10:12:25,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 11 transitions. [2022-10-17 10:12:25,872 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 9 states and 10 transitions. [2022-10-17 10:12:25,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:25,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:25,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2022-10-17 10:12:25,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:25,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-10-17 10:12:25,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2022-10-17 10:12:25,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2022-10-17 10:12:25,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:25,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2022-10-17 10:12:25,876 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-10-17 10:12:25,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:12:25,877 INFO L428 stractBuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2022-10-17 10:12:25,877 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:12:25,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2022-10-17 10:12:25,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:25,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:25,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:25,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:25,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:25,879 INFO L748 eck$LassoCheckResult]: Stem: 159#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 160#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 161#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 162#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 163#L15-3 assume !(main_~i~0#1 < 1048); 157#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 158#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 164#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 165#L22-2 [2022-10-17 10:12:25,880 INFO L750 eck$LassoCheckResult]: Loop: 165#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 165#L22-2 [2022-10-17 10:12:25,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:25,880 INFO L85 PathProgramCache]: Analyzing trace with hash 265182965, now seen corresponding path program 1 times [2022-10-17 10:12:25,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:25,881 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168723255] [2022-10-17 10:12:25,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:25,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:25,948 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:25,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:25,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168723255] [2022-10-17 10:12:25,949 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168723255] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:25,950 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [11606353] [2022-10-17 10:12:25,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:25,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:25,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:25,952 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:25,975 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-10-17 10:12:26,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:26,024 INFO L263 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:12:26,025 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:26,062 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:26,062 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:12:26,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:26,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [11606353] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:12:26,107 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:12:26,107 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2022-10-17 10:12:26,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692224198] [2022-10-17 10:12:26,107 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:12:26,108 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:26,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:26,108 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 3 times [2022-10-17 10:12:26,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:26,109 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483478666] [2022-10-17 10:12:26,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:26,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:26,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:26,113 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:26,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:26,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:26,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:26,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:12:26,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:12:26,133 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:26,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:26,160 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2022-10-17 10:12:26,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2022-10-17 10:12:26,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:26,162 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2022-10-17 10:12:26,162 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:26,163 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:26,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2022-10-17 10:12:26,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:26,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-10-17 10:12:26,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2022-10-17 10:12:26,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2022-10-17 10:12:26,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:26,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2022-10-17 10:12:26,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-10-17 10:12:26,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:12:26,168 INFO L428 stractBuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2022-10-17 10:12:26,168 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:12:26,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2022-10-17 10:12:26,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:26,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:26,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:26,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:26,170 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:26,171 INFO L748 eck$LassoCheckResult]: Stem: 235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 237#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 238#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 239#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 240#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 247#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 246#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 245#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 244#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 243#L15-3 assume !(main_~i~0#1 < 1048); 233#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 234#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 241#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 242#L22-2 [2022-10-17 10:12:26,171 INFO L750 eck$LassoCheckResult]: Loop: 242#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 242#L22-2 [2022-10-17 10:12:26,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:26,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1745752453, now seen corresponding path program 2 times [2022-10-17 10:12:26,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:26,172 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141691189] [2022-10-17 10:12:26,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:26,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:26,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:26,294 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-10-17 10:12:26,391 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:26,391 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:26,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141691189] [2022-10-17 10:12:26,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141691189] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:26,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [515317548] [2022-10-17 10:12:26,393 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:12:26,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:26,393 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:26,394 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:26,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-10-17 10:12:26,496 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:12:26,496 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:12:26,498 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:12:26,499 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:26,556 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:26,556 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:12:26,684 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:26,684 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [515317548] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:12:26,684 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:12:26,685 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2022-10-17 10:12:26,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369914538] [2022-10-17 10:12:26,685 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:12:26,686 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:26,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:26,687 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 4 times [2022-10-17 10:12:26,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:26,687 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778527717] [2022-10-17 10:12:26,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:26,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:26,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:26,695 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:26,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:26,698 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:26,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:26,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:12:26,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:12:26,730 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 2.076923076923077) internal successors, (27), 13 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:26,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:26,817 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2022-10-17 10:12:26,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2022-10-17 10:12:26,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:26,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2022-10-17 10:12:26,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:26,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:26,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2022-10-17 10:12:26,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:26,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-10-17 10:12:26,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2022-10-17 10:12:26,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2022-10-17 10:12:26,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:26,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2022-10-17 10:12:26,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-10-17 10:12:26,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:12:26,836 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2022-10-17 10:12:26,836 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:12:26,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2022-10-17 10:12:26,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:26,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:26,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:26,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:26,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:26,839 INFO L748 eck$LassoCheckResult]: Stem: 371#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 373#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 374#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 375#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 376#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 379#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 395#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 394#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 393#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 392#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 391#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 390#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 389#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 388#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 387#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 386#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 385#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 384#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 383#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 382#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 381#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 380#L15-3 assume !(main_~i~0#1 < 1048); 369#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 370#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 377#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 378#L22-2 [2022-10-17 10:12:26,839 INFO L750 eck$LassoCheckResult]: Loop: 378#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 378#L22-2 [2022-10-17 10:12:26,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:26,840 INFO L85 PathProgramCache]: Analyzing trace with hash -95700985, now seen corresponding path program 3 times [2022-10-17 10:12:26,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:26,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453742083] [2022-10-17 10:12:26,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:26,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:26,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:27,290 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:27,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:27,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453742083] [2022-10-17 10:12:27,291 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453742083] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:27,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1291675153] [2022-10-17 10:12:27,291 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:12:27,291 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:27,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:27,299 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:27,325 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-10-17 10:12:27,498 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-10-17 10:12:27,498 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:12:27,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-17 10:12:27,503 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:27,624 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:27,624 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:12:27,895 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:27,895 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1291675153] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:12:27,896 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:12:27,896 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 25 [2022-10-17 10:12:27,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830524370] [2022-10-17 10:12:27,897 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:12:27,898 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:27,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:27,899 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 5 times [2022-10-17 10:12:27,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:27,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958601211] [2022-10-17 10:12:27,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:27,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:27,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:27,905 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:27,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:27,910 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:27,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:27,933 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-10-17 10:12:27,934 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-10-17 10:12:27,935 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 2.04) internal successors, (51), 25 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:28,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:28,058 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2022-10-17 10:12:28,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2022-10-17 10:12:28,068 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:28,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2022-10-17 10:12:28,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:28,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:28,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2022-10-17 10:12:28,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:28,071 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-10-17 10:12:28,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2022-10-17 10:12:28,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2022-10-17 10:12:28,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:28,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2022-10-17 10:12:28,084 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-10-17 10:12:28,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:12:28,086 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2022-10-17 10:12:28,089 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:12:28,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2022-10-17 10:12:28,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:28,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:28,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:28,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:28,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:28,102 INFO L748 eck$LassoCheckResult]: Stem: 627#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 629#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 630#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 631#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 632#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 635#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 675#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 674#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 673#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 672#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 671#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 670#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 669#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 668#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 667#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 666#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 665#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 664#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 663#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 662#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 661#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 660#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 659#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 658#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 657#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 656#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 655#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 654#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 653#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 652#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 651#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 650#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 649#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 648#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 647#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 646#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 645#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 644#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 643#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 642#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 641#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 640#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 639#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 638#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 637#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 636#L15-3 assume !(main_~i~0#1 < 1048); 625#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 626#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 633#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 634#L22-2 [2022-10-17 10:12:28,102 INFO L750 eck$LassoCheckResult]: Loop: 634#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 634#L22-2 [2022-10-17 10:12:28,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:28,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1293972767, now seen corresponding path program 4 times [2022-10-17 10:12:28,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:28,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322541099] [2022-10-17 10:12:28,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:28,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:28,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:29,179 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:29,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:29,179 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322541099] [2022-10-17 10:12:29,180 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322541099] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:29,180 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1355613775] [2022-10-17 10:12:29,180 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:12:29,180 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:29,180 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:29,182 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:29,183 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-10-17 10:12:29,324 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:12:29,324 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:12:29,327 INFO L263 TraceCheckSpWp]: Trace formula consists of 286 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-17 10:12:29,332 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:29,480 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:29,481 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:12:30,488 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:30,489 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1355613775] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:12:30,489 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:12:30,489 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 49 [2022-10-17 10:12:30,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001926575] [2022-10-17 10:12:30,490 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:12:30,490 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:30,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:30,491 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 6 times [2022-10-17 10:12:30,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:30,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320394672] [2022-10-17 10:12:30,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:30,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:30,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:30,496 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:30,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:30,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:30,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:30,514 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-10-17 10:12:30,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-10-17 10:12:30,516 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 2.020408163265306) internal successors, (99), 49 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:30,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:30,781 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2022-10-17 10:12:30,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2022-10-17 10:12:30,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:30,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2022-10-17 10:12:30,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:30,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:30,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2022-10-17 10:12:30,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:30,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-10-17 10:12:30,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2022-10-17 10:12:30,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2022-10-17 10:12:30,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:30,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2022-10-17 10:12:30,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-10-17 10:12:30,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-10-17 10:12:30,817 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2022-10-17 10:12:30,818 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:12:30,818 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2022-10-17 10:12:30,822 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:30,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:30,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:30,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:30,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:30,830 INFO L748 eck$LassoCheckResult]: Stem: 1123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 1125#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1126#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1127#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1128#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1131#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1219#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1218#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1217#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1216#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1215#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1214#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1213#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1212#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1211#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1210#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1209#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1208#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1207#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1206#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1205#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1204#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1203#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1202#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1201#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1200#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1199#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1198#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1197#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1196#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1195#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1194#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1193#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1192#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1191#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1190#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1189#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1188#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1187#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1186#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1185#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1184#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1183#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1182#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1181#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1180#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1179#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1178#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1177#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1176#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1175#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1174#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1173#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1172#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1171#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1170#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1169#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1168#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1167#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1166#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1165#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1164#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1163#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1162#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1161#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1160#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1159#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1158#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1157#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1156#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1155#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1154#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1153#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1152#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1151#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1150#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1149#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1148#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1147#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1146#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1145#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1144#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1143#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1142#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1141#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1140#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1139#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1138#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1137#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1136#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1135#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1134#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 1133#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 1132#L15-3 assume !(main_~i~0#1 < 1048); 1121#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 1122#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 1129#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 1130#L22-2 [2022-10-17 10:12:30,835 INFO L750 eck$LassoCheckResult]: Loop: 1130#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 1130#L22-2 [2022-10-17 10:12:30,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:30,836 INFO L85 PathProgramCache]: Analyzing trace with hash -675113137, now seen corresponding path program 5 times [2022-10-17 10:12:30,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:30,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854189226] [2022-10-17 10:12:30,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:30,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:31,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:12:33,971 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:33,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:12:33,972 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854189226] [2022-10-17 10:12:33,972 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854189226] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:12:33,973 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [616528193] [2022-10-17 10:12:33,973 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:12:33,973 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:12:33,973 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:12:33,978 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:12:34,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_1b1e7b27-b26d-4ccc-bab7-2bffcbd44362/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-10-17 10:12:41,030 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-10-17 10:12:41,030 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:12:41,047 INFO L263 TraceCheckSpWp]: Trace formula consists of 550 conjuncts, 48 conjunts are in the unsatisfiable core [2022-10-17 10:12:41,054 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:12:41,306 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:41,306 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:12:44,729 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:12:44,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [616528193] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:12:44,729 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:12:44,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 97 [2022-10-17 10:12:44,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317638232] [2022-10-17 10:12:44,730 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:12:44,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:12:44,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:44,732 INFO L85 PathProgramCache]: Analyzing trace with hash 67, now seen corresponding path program 7 times [2022-10-17 10:12:44,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:44,732 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815864995] [2022-10-17 10:12:44,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:44,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:44,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:44,737 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:12:44,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:12:44,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:12:44,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:12:44,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-10-17 10:12:44,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-10-17 10:12:44,778 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 2.0103092783505154) internal successors, (195), 97 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:45,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:12:45,275 INFO L93 Difference]: Finished difference Result 195 states and 196 transitions. [2022-10-17 10:12:45,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 196 transitions. [2022-10-17 10:12:45,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:45,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 196 transitions. [2022-10-17 10:12:45,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:12:45,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:12:45,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 196 transitions. [2022-10-17 10:12:45,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:12:45,299 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-10-17 10:12:45,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 196 transitions. [2022-10-17 10:12:45,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2022-10-17 10:12:45,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.005128205128205) internal successors, (196), 194 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:12:45,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 196 transitions. [2022-10-17 10:12:45,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-10-17 10:12:45,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-10-17 10:12:45,318 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 196 transitions. [2022-10-17 10:12:45,318 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:12:45,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 196 transitions. [2022-10-17 10:12:45,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:12:45,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:12:45,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:12:45,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 94, 1, 1, 1, 1, 1, 1] [2022-10-17 10:12:45,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:12:45,325 INFO L748 eck$LassoCheckResult]: Stem: 2099#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2100#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_#t~nondet2#1, main_#t~post1#1, main_~i~0#1, main_#t~mem3#1, main_#t~mem4#1, main_#t~short5#1, main_#t~nondet6#1, main_~x~0#1, main_~k~0#1, main_~#a~0#1.base, main_~#a~0#1.offset;main_~k~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;call main_~#a~0#1.base, main_~#a~0#1.offset := #Ultimate.allocOnStack(4192);main_~i~0#1 := 0; 2101#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2102#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2103#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2104#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2107#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2291#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2290#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2289#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2288#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2287#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2286#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2285#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2284#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2283#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2282#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2281#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2280#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2279#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2278#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2277#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2276#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2275#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2274#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2273#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2272#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2271#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2270#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2269#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2268#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2267#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2266#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2265#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2264#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2263#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2262#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2261#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2260#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2259#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2258#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2257#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2256#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2255#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2254#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2253#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2252#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2251#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2250#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2249#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2248#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2247#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2246#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2245#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2244#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2243#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2242#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2241#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2240#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2239#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2238#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2237#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2236#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2235#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2234#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2233#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2232#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2231#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2230#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2229#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2228#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2227#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2226#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2225#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2224#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2223#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2222#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2221#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2220#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2219#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2218#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2217#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2216#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2215#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2214#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2213#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2212#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2211#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2210#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2209#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2208#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2207#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2206#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2205#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2204#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2203#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2202#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2201#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2200#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2199#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2198#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2197#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2196#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2195#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2194#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2193#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2192#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2191#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2190#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2189#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2188#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2187#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2186#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2185#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2184#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2183#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2182#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2181#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2180#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2179#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2178#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2177#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2176#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2175#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2174#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2173#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2172#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2171#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2170#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2169#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2168#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2167#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2166#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2165#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2164#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2163#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2162#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2161#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2160#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2159#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2158#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2157#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2156#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2155#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2154#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2153#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2152#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2151#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2150#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2149#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2148#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2147#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2146#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2145#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2144#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2143#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2142#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2141#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2140#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2139#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2138#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2137#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2136#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2135#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2134#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2133#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2132#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2131#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2130#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2129#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2128#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2127#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2126#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2125#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2124#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2123#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2122#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2121#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2120#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2119#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2118#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2117#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2116#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2115#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2114#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2113#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2112#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2111#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2110#L15-3 assume !!(main_~i~0#1 < 1048);call write~int(main_#t~nondet2#1, main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1; 2109#L15-2 main_#t~post1#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post1#1;havoc main_#t~post1#1; 2108#L15-3 assume !(main_~i~0#1 < 1048); 2097#L15-4 assume main_~k~0#1 >= 0 && main_~k~0#1 < 1048;call main_#t~mem3#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset, 4);main_#t~short5#1 := 23 == main_#t~mem3#1; 2098#L20 assume main_#t~short5#1;call main_#t~mem4#1 := read~int(main_~#a~0#1.base, main_~#a~0#1.offset + 4 * main_~k~0#1, 4);main_#t~short5#1 := 42 == main_#t~mem4#1; 2105#L20-2 assume main_#t~short5#1;havoc main_#t~mem3#1;havoc main_#t~mem4#1;havoc main_#t~short5#1;main_~x~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1; 2106#L22-2 [2022-10-17 10:12:45,326 INFO L750 eck$LassoCheckResult]: Loop: 2106#L22-2 assume !!(main_~x~0#1 >= 0);main_~x~0#1 := main_~x~0#1 - main_~k~0#1; 2106#L22-2 [2022-10-17 10:12:45,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:12:45,327 INFO L85 PathProgramCache]: Analyzing trace with hash -1064731729, now seen corresponding path program 6 times [2022-10-17 10:12:45,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:12:45,327 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007935149] [2022-10-17 10:12:45,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:12:45,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:12:45,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat