./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6ef2b56a2f4ebf2e6f7f4ededf8760f087ff726b08e36644d8dcb52a8d087cd1 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:42:38,000 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:42:38,003 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:42:38,052 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:42:38,052 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:42:38,056 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:42:38,059 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:42:38,064 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:42:38,066 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:42:38,072 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:42:38,073 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:42:38,075 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:42:38,076 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:42:38,079 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:42:38,081 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:42:38,083 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:42:38,084 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:42:38,085 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:42:38,087 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:42:38,094 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:42:38,096 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:42:38,097 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:42:38,101 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:42:38,102 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:42:38,112 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:42:38,112 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:42:38,113 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:42:38,114 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:42:38,115 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:42:38,117 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:42:38,118 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:42:38,119 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:42:38,121 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:42:38,122 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:42:38,123 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:42:38,124 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:42:38,124 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:42:38,125 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:42:38,125 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:42:38,126 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:42:38,127 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:42:38,127 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:42:38,166 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:42:38,166 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:42:38,167 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:42:38,167 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:42:38,169 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:42:38,169 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:42:38,169 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:42:38,170 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:42:38,170 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:42:38,170 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:42:38,171 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:42:38,171 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:42:38,172 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:42:38,172 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:42:38,172 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:42:38,173 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:42:38,173 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:42:38,173 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:42:38,174 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:42:38,174 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:42:38,174 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:42:38,174 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:42:38,175 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:42:38,175 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:42:38,175 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:42:38,176 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:42:38,176 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:42:38,176 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:42:38,176 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:42:38,177 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:42:38,177 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:42:38,178 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:42:38,179 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6ef2b56a2f4ebf2e6f7f4ededf8760f087ff726b08e36644d8dcb52a8d087cd1 [2022-10-17 10:42:38,465 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:42:38,489 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:42:38,492 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:42:38,493 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:42:38,494 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:42:38,495 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c [2022-10-17 10:42:38,578 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/data/a8024dc29/3f615fe28a8f41498b1b6c946866e719/FLAG970a3473c [2022-10-17 10:42:38,990 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:42:38,991 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/sv-benchmarks/c/ldv-memsafety/ArraysOfVariableLength6.c [2022-10-17 10:42:38,996 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/data/a8024dc29/3f615fe28a8f41498b1b6c946866e719/FLAG970a3473c [2022-10-17 10:42:39,398 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/data/a8024dc29/3f615fe28a8f41498b1b6c946866e719 [2022-10-17 10:42:39,400 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:42:39,402 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:42:39,404 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:42:39,404 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:42:39,407 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:42:39,408 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,409 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@551d9642 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39, skipping insertion in model container [2022-10-17 10:42:39,409 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,416 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:42:39,428 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:42:39,648 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:42:39,656 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:42:39,683 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:42:39,697 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:42:39,698 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39 WrapperNode [2022-10-17 10:42:39,698 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:42:39,701 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:42:39,701 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:42:39,701 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:42:39,708 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,716 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,742 INFO L138 Inliner]: procedures = 8, calls = 14, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 69 [2022-10-17 10:42:39,742 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:42:39,743 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:42:39,744 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:42:39,744 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:42:39,752 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,752 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,763 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,764 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,773 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,782 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,784 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,785 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,791 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:42:39,794 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:42:39,795 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:42:39,795 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:42:39,796 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (1/1) ... [2022-10-17 10:42:39,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:42:39,816 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:39,836 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:42:39,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:42:39,875 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:42:39,876 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:42:39,876 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:42:39,876 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:42:39,876 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:42:39,876 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:42:39,952 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:42:39,954 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:42:40,088 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:42:40,094 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:42:40,094 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-10-17 10:42:40,096 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:42:40 BoogieIcfgContainer [2022-10-17 10:42:40,096 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:42:40,097 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:42:40,097 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:42:40,102 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:42:40,102 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:42:40,103 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:42:39" (1/3) ... [2022-10-17 10:42:40,104 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ee70150 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:42:40, skipping insertion in model container [2022-10-17 10:42:40,104 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:42:40,104 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:42:39" (2/3) ... [2022-10-17 10:42:40,105 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2ee70150 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:42:40, skipping insertion in model container [2022-10-17 10:42:40,105 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:42:40,105 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:42:40" (3/3) ... [2022-10-17 10:42:40,106 INFO L332 chiAutomizerObserver]: Analyzing ICFG ArraysOfVariableLength6.c [2022-10-17 10:42:40,159 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:42:40,160 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:42:40,160 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:42:40,160 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:42:40,160 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:42:40,160 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:42:40,161 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:42:40,161 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:42:40,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:40,183 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:42:40,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:40,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:40,188 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:40,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-10-17 10:42:40,202 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:42:40,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:40,205 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:42:40,206 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:40,206 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:40,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:40,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-10-17 10:42:40,214 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 7#L25-3true [2022-10-17 10:42:40,230 INFO L750 eck$LassoCheckResult]: Loop: 7#L25-3true assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6#L15-3true assume !(foo_~i~0#1 < foo_~size#1); 11#L15-4true foo_#res#1 := foo_~i~0#1; 12#L18true main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 13#L25-2true main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7#L25-3true [2022-10-17 10:42:40,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:40,236 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:42:40,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:40,258 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374518618] [2022-10-17 10:42:40,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:40,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:40,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:40,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:40,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:40,398 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:40,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:40,402 INFO L85 PathProgramCache]: Analyzing trace with hash 38364915, now seen corresponding path program 1 times [2022-10-17 10:42:40,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:40,402 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643313370] [2022-10-17 10:42:40,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:40,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:40,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:40,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:40,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:40,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [643313370] [2022-10-17 10:42:40,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [643313370] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:42:40,588 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:42:40,588 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:42:40,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857939294] [2022-10-17 10:42:40,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:42:40,593 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:42:40,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:40,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:42:40,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:42:40,635 INFO L87 Difference]: Start difference. First operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:40,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:40,656 INFO L93 Difference]: Finished difference Result 19 states and 22 transitions. [2022-10-17 10:42:40,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 22 transitions. [2022-10-17 10:42:40,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11 [2022-10-17 10:42:40,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 14 states and 16 transitions. [2022-10-17 10:42:40,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2022-10-17 10:42:40,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2022-10-17 10:42:40,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 16 transitions. [2022-10-17 10:42:40,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:40,673 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 16 transitions. [2022-10-17 10:42:40,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 16 transitions. [2022-10-17 10:42:40,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 13. [2022-10-17 10:42:40,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.1538461538461537) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:40,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2022-10-17 10:42:40,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 15 transitions. [2022-10-17 10:42:40,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:42:40,713 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 15 transitions. [2022-10-17 10:42:40,713 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:42:40,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 15 transitions. [2022-10-17 10:42:40,714 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2022-10-17 10:42:40,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:40,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:40,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:40,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:42:40,716 INFO L748 eck$LassoCheckResult]: Stem: 51#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 52#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 48#L25-3 [2022-10-17 10:42:40,716 INFO L750 eck$LassoCheckResult]: Loop: 48#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 54#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 55#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 57#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 45#L15-4 foo_#res#1 := foo_~i~0#1; 46#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 47#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 48#L25-3 [2022-10-17 10:42:40,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:40,717 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2022-10-17 10:42:40,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:40,718 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37389286] [2022-10-17 10:42:40,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:40,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:40,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:40,733 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:40,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:40,747 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:40,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:40,748 INFO L85 PathProgramCache]: Analyzing trace with hash -1732759051, now seen corresponding path program 1 times [2022-10-17 10:42:40,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:40,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373235095] [2022-10-17 10:42:40,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:40,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:40,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:40,870 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:40,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:40,870 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373235095] [2022-10-17 10:42:40,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373235095] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:42:40,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1308501370] [2022-10-17 10:42:40,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:40,872 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:42:40,872 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:40,873 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:42:40,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-17 10:42:40,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:40,939 INFO L263 TraceCheckSpWp]: Trace formula consists of 46 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:42:40,941 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:42:41,076 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:41,077 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:42:41,113 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:41,113 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1308501370] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:42:41,114 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:42:41,114 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 7 [2022-10-17 10:42:41,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017635622] [2022-10-17 10:42:41,115 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:42:41,115 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:42:41,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:41,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-10-17 10:42:41,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=29, Unknown=0, NotChecked=0, Total=56 [2022-10-17 10:42:41,116 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. cyclomatic complexity: 4 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:41,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:41,181 INFO L93 Difference]: Finished difference Result 19 states and 21 transitions. [2022-10-17 10:42:41,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 21 transitions. [2022-10-17 10:42:41,184 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-10-17 10:42:41,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 21 transitions. [2022-10-17 10:42:41,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-10-17 10:42:41,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-10-17 10:42:41,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 21 transitions. [2022-10-17 10:42:41,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:41,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-10-17 10:42:41,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 21 transitions. [2022-10-17 10:42:41,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-10-17 10:42:41,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:41,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2022-10-17 10:42:41,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-10-17 10:42:41,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:42:41,190 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-10-17 10:42:41,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:42:41,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2022-10-17 10:42:41,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-10-17 10:42:41,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:41,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:41,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:41,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2022-10-17 10:42:41,192 INFO L748 eck$LassoCheckResult]: Stem: 128#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 127#L25-3 [2022-10-17 10:42:41,192 INFO L750 eck$LassoCheckResult]: Loop: 127#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 133#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 134#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 136#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 142#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 141#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 140#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 139#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 138#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 137#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 124#L15-4 foo_#res#1 := foo_~i~0#1; 125#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 126#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 127#L25-3 [2022-10-17 10:42:41,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:41,193 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 3 times [2022-10-17 10:42:41,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:41,194 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286912017] [2022-10-17 10:42:41,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:41,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:41,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:41,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:41,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:41,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:41,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:41,215 INFO L85 PathProgramCache]: Analyzing trace with hash -1316700165, now seen corresponding path program 2 times [2022-10-17 10:42:41,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:41,216 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229851821] [2022-10-17 10:42:41,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:41,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:41,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:41,412 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:41,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:41,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229851821] [2022-10-17 10:42:41,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229851821] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:42:41,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1349309573] [2022-10-17 10:42:41,413 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:42:41,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:42:41,414 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:41,418 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:42:41,428 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-17 10:42:41,483 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:42:41,483 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:42:41,484 INFO L263 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:42:41,486 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:42:41,640 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:41,640 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:42:41,781 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:41,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1349309573] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:42:41,783 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:42:41,783 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 16 [2022-10-17 10:42:41,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1918278484] [2022-10-17 10:42:41,784 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:42:41,786 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:42:41,786 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:41,787 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-10-17 10:42:41,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=146, Unknown=0, NotChecked=0, Total=272 [2022-10-17 10:42:41,790 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. cyclomatic complexity: 4 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 16 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:41,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:41,869 INFO L93 Difference]: Finished difference Result 31 states and 33 transitions. [2022-10-17 10:42:41,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 33 transitions. [2022-10-17 10:42:41,875 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2022-10-17 10:42:41,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 33 transitions. [2022-10-17 10:42:41,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2022-10-17 10:42:41,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2022-10-17 10:42:41,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 33 transitions. [2022-10-17 10:42:41,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:41,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-10-17 10:42:41,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 33 transitions. [2022-10-17 10:42:41,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2022-10-17 10:42:41,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.064516129032258) internal successors, (33), 30 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:41,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2022-10-17 10:42:41,890 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-10-17 10:42:41,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:42:41,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 33 transitions. [2022-10-17 10:42:41,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:42:41,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 33 transitions. [2022-10-17 10:42:41,894 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2022-10-17 10:42:41,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:41,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:41,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:41,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [10, 10, 1, 1, 1, 1, 1] [2022-10-17 10:42:41,896 INFO L748 eck$LassoCheckResult]: Stem: 270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 269#L25-3 [2022-10-17 10:42:41,896 INFO L750 eck$LassoCheckResult]: Loop: 269#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 278#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 279#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 275#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 276#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 296#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 295#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 294#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 293#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 292#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 291#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 290#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 289#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 288#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 287#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 286#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 285#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 284#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 283#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 282#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 281#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 280#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 266#L15-4 foo_#res#1 := foo_~i~0#1; 267#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 268#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 269#L25-3 [2022-10-17 10:42:41,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:41,904 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 4 times [2022-10-17 10:42:41,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:41,904 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977480355] [2022-10-17 10:42:41,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:41,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:41,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:41,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:41,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:41,928 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:41,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:41,929 INFO L85 PathProgramCache]: Analyzing trace with hash 2131617415, now seen corresponding path program 3 times [2022-10-17 10:42:41,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:41,935 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269374809] [2022-10-17 10:42:41,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:41,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:42,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:42,363 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:42,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:42,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269374809] [2022-10-17 10:42:42,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [269374809] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:42:42,365 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1801202938] [2022-10-17 10:42:42,366 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:42:42,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:42:42,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:42,403 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:42:42,422 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-10-17 10:42:42,498 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-10-17 10:42:42,498 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:42:42,499 INFO L263 TraceCheckSpWp]: Trace formula consists of 154 conjuncts, 14 conjunts are in the unsatisfiable core [2022-10-17 10:42:42,502 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:42:42,851 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:42,851 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:42:43,253 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:43,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1801202938] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:42:43,254 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:42:43,254 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 34 [2022-10-17 10:42:43,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889383649] [2022-10-17 10:42:43,255 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:42:43,255 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:42:43,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:43,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-10-17 10:42:43,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=650, Unknown=0, NotChecked=0, Total=1190 [2022-10-17 10:42:43,257 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. cyclomatic complexity: 4 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 34 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:43,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:43,358 INFO L93 Difference]: Finished difference Result 55 states and 57 transitions. [2022-10-17 10:42:43,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 57 transitions. [2022-10-17 10:42:43,359 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2022-10-17 10:42:43,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 57 transitions. [2022-10-17 10:42:43,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2022-10-17 10:42:43,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2022-10-17 10:42:43,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 57 transitions. [2022-10-17 10:42:43,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:43,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-10-17 10:42:43,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 57 transitions. [2022-10-17 10:42:43,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2022-10-17 10:42:43,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.0363636363636364) internal successors, (57), 54 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:43,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 57 transitions. [2022-10-17 10:42:43,367 INFO L240 hiAutomatonCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-10-17 10:42:43,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:42:43,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 55 states and 57 transitions. [2022-10-17 10:42:43,369 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:42:43,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 57 transitions. [2022-10-17 10:42:43,370 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 52 [2022-10-17 10:42:43,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:43,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:43,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:43,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [22, 22, 1, 1, 1, 1, 1] [2022-10-17 10:42:43,372 INFO L748 eck$LassoCheckResult]: Stem: 538#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 539#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 537#L25-3 [2022-10-17 10:42:43,372 INFO L750 eck$LassoCheckResult]: Loop: 537#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 546#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 547#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 543#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 544#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 588#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 587#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 586#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 585#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 584#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 583#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 582#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 581#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 580#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 579#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 578#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 577#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 576#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 575#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 574#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 573#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 572#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 571#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 570#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 569#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 568#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 567#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 566#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 565#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 564#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 563#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 562#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 561#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 560#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 559#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 558#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 557#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 556#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 555#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 554#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 553#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 552#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 551#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 550#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 549#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 548#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 534#L15-4 foo_#res#1 := foo_~i~0#1; 535#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 536#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 537#L25-3 [2022-10-17 10:42:43,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:43,373 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 5 times [2022-10-17 10:42:43,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:43,374 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226142982] [2022-10-17 10:42:43,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:43,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:43,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:43,382 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:43,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:43,387 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:43,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:43,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1575559777, now seen corresponding path program 4 times [2022-10-17 10:42:43,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:43,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872045155] [2022-10-17 10:42:43,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:43,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:43,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:42:44,314 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:44,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:42:44,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872045155] [2022-10-17 10:42:44,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872045155] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:42:44,315 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1631776535] [2022-10-17 10:42:44,315 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:42:44,315 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:42:44,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:42:44,317 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:42:44,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8a47971-b65f-4691-958c-e9cc2bb52ed2/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-10-17 10:42:44,418 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:42:44,418 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:42:44,420 INFO L263 TraceCheckSpWp]: Trace formula consists of 298 conjuncts, 26 conjunts are in the unsatisfiable core [2022-10-17 10:42:44,437 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:42:45,358 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:45,358 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:42:46,552 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:42:46,552 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1631776535] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:42:46,552 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:42:46,552 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 70 [2022-10-17 10:42:46,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768053068] [2022-10-17 10:42:46,553 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:42:46,553 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:42:46,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:42:46,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2022-10-17 10:42:46,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2050, Invalid=2920, Unknown=0, NotChecked=0, Total=4970 [2022-10-17 10:42:46,558 INFO L87 Difference]: Start difference. First operand 55 states and 57 transitions. cyclomatic complexity: 4 Second operand has 71 states, 71 states have (on average 1.9859154929577465) internal successors, (141), 70 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:46,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:42:46,743 INFO L93 Difference]: Finished difference Result 75 states and 77 transitions. [2022-10-17 10:42:46,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 77 transitions. [2022-10-17 10:42:46,745 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2022-10-17 10:42:46,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 77 transitions. [2022-10-17 10:42:46,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2022-10-17 10:42:46,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2022-10-17 10:42:46,747 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 77 transitions. [2022-10-17 10:42:46,747 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:42:46,747 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-10-17 10:42:46,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 77 transitions. [2022-10-17 10:42:46,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2022-10-17 10:42:46,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0266666666666666) internal successors, (77), 74 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:42:46,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 77 transitions. [2022-10-17 10:42:46,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-10-17 10:42:46,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2022-10-17 10:42:46,754 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 77 transitions. [2022-10-17 10:42:46,754 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:42:46,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 77 transitions. [2022-10-17 10:42:46,756 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 72 [2022-10-17 10:42:46,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:42:46,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:42:46,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:42:46,757 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [32, 32, 1, 1, 1, 1, 1] [2022-10-17 10:42:46,757 INFO L748 eck$LassoCheckResult]: Stem: 1030#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~buffer~0#1, main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(400);havoc main_~buffer~0#1;call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);havoc main_~c~0#1.base, main_~c~0#1.offset;main_~i~1#1 := 0; 1028#L25-3 [2022-10-17 10:42:46,758 INFO L750 eck$LassoCheckResult]: Loop: 1028#L25-3 assume !!(main_~i~1#1 % 4294967296 < 32);main_~c~0#1.base, main_~c~0#1.offset := main_~#mask~0#1.base, main_~#mask~0#1.offset;assume { :begin_inline_foo } true;foo_#in~size#1, foo_#in~b#1.base, foo_#in~b#1.offset := 32, main_~c~0#1.base, main_~c~0#1.offset;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~size#1, foo_~b#1.base, foo_~b#1.offset, foo_~a~0#1, foo_~i~0#1;foo_~size#1 := foo_#in~size#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1038#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1039#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1035#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1036#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1100#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1099#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1098#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1097#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1096#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1095#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1094#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1093#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1092#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1091#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1090#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1089#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1088#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1087#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1086#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1085#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1084#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1083#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1082#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1081#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1080#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1079#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1078#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1077#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1076#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1075#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1074#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1073#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1072#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1071#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1070#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1069#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1068#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1067#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1066#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1065#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1064#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1063#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1062#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1061#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1060#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1059#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1058#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1057#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1056#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1055#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1054#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1053#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1052#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1051#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1050#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1049#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1048#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1047#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1046#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1045#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1044#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1043#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1042#L15-3 assume !!(foo_~i~0#1 < foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1041#L15-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1040#L15-3 assume !(foo_~i~0#1 < foo_~size#1); 1029#L15-4 foo_#res#1 := foo_~i~0#1; 1026#L18 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1027#L25-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1028#L25-3 [2022-10-17 10:42:46,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:46,758 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 6 times [2022-10-17 10:42:46,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:46,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15599791] [2022-10-17 10:42:46,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:46,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:46,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:46,765 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:46,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:46,770 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:46,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:46,770 INFO L85 PathProgramCache]: Analyzing trace with hash 776556339, now seen corresponding path program 5 times [2022-10-17 10:42:46,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:46,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292682806] [2022-10-17 10:42:46,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:46,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:46,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:46,834 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:46,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:46,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:42:46,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:42:46,941 INFO L85 PathProgramCache]: Analyzing trace with hash -378248015, now seen corresponding path program 1 times [2022-10-17 10:42:46,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:42:46,941 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475321438] [2022-10-17 10:42:46,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:42:46,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:42:47,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:47,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:42:47,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:42:47,096 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace