./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ef4a52e45666a829b602608a46cff9c8137910dd58bdfaebe016ce17984d1ac8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:50:23,262 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:50:23,265 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:50:23,324 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:50:23,325 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:50:23,330 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:50:23,333 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:50:23,337 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:50:23,342 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:50:23,348 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:50:23,349 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:50:23,352 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:50:23,353 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:50:23,356 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:50:23,359 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:50:23,361 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:50:23,363 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:50:23,364 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:50:23,366 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:50:23,375 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:50:23,377 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:50:23,378 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:50:23,382 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:50:23,384 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:50:23,394 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:50:23,395 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:50:23,395 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:50:23,398 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:50:23,398 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:50:23,400 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:50:23,401 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:50:23,403 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:50:23,405 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:50:23,407 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:50:23,408 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:50:23,408 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:50:23,409 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:50:23,409 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:50:23,410 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:50:23,411 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:50:23,412 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:50:23,413 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:50:23,458 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:50:23,458 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:50:23,459 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:50:23,459 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:50:23,461 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:50:23,461 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:50:23,461 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:50:23,462 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:50:23,462 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:50:23,462 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:50:23,463 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:50:23,464 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:50:23,464 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:50:23,464 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:50:23,465 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:50:23,465 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:50:23,465 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:50:23,465 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:50:23,465 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:50:23,466 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:50:23,466 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:50:23,466 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:50:23,466 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:50:23,468 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:50:23,468 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:50:23,469 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:50:23,469 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:50:23,469 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:50:23,469 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:50:23,470 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:50:23,470 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:50:23,471 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:50:23,472 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ef4a52e45666a829b602608a46cff9c8137910dd58bdfaebe016ce17984d1ac8 [2022-10-17 10:50:23,827 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:50:23,865 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:50:23,868 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:50:23,869 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:50:23,870 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:50:23,871 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c [2022-10-17 10:50:23,947 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/data/a5acbecc9/ea154e4679ec41fa9bc1bc5c89cdadff/FLAG14d1d7b73 [2022-10-17 10:50:24,369 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:50:24,370 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c [2022-10-17 10:50:24,376 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/data/a5acbecc9/ea154e4679ec41fa9bc1bc5c89cdadff/FLAG14d1d7b73 [2022-10-17 10:50:24,790 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/data/a5acbecc9/ea154e4679ec41fa9bc1bc5c89cdadff [2022-10-17 10:50:24,794 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:50:24,796 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:50:24,800 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:50:24,800 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:50:24,805 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:50:24,805 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:50:24" (1/1) ... [2022-10-17 10:50:24,808 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5a468d93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:24, skipping insertion in model container [2022-10-17 10:50:24,808 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:50:24" (1/1) ... [2022-10-17 10:50:24,816 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:50:24,830 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:50:25,063 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:50:25,073 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:50:25,097 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:50:25,113 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:50:25,113 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25 WrapperNode [2022-10-17 10:50:25,113 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:50:25,117 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:50:25,117 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:50:25,117 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:50:25,126 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,134 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,166 INFO L138 Inliner]: procedures = 8, calls = 14, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 66 [2022-10-17 10:50:25,166 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:50:25,167 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:50:25,167 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:50:25,167 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:50:25,177 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,177 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,188 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,188 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,193 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,197 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,198 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,200 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,202 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:50:25,203 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:50:25,203 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:50:25,204 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:50:25,205 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (1/1) ... [2022-10-17 10:50:25,212 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:25,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:25,242 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:25,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:50:25,282 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:50:25,282 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:50:25,283 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:50:25,283 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:50:25,283 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:50:25,283 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:50:25,355 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:50:25,358 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:50:25,615 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:50:25,621 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:50:25,621 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-10-17 10:50:25,623 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:50:25 BoogieIcfgContainer [2022-10-17 10:50:25,623 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:50:25,625 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:50:25,625 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:50:25,642 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:50:25,643 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:50:25,644 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:50:24" (1/3) ... [2022-10-17 10:50:25,645 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64231b56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:50:25, skipping insertion in model container [2022-10-17 10:50:25,645 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:50:25,645 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:50:25" (2/3) ... [2022-10-17 10:50:25,645 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@64231b56 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:50:25, skipping insertion in model container [2022-10-17 10:50:25,646 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:50:25,646 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:50:25" (3/3) ... [2022-10-17 10:50:25,647 INFO L332 chiAutomizerObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration.c [2022-10-17 10:50:25,776 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:50:25,789 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:50:25,790 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:50:25,790 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:50:25,790 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:50:25,790 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:50:25,790 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:50:25,791 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:50:25,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:25,817 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:50:25,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:25,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:25,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:50:25,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-10-17 10:50:25,824 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:50:25,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:25,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:50:25,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:25,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:25,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:50:25,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-10-17 10:50:25,838 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 15#L26-3true [2022-10-17 10:50:25,839 INFO L750 eck$LassoCheckResult]: Loop: 15#L26-3true assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8#L17-3true assume !(foo_~i~0#1 <= foo_~size#1); 9#L17-4true foo_#res#1 := foo_~i~0#1; 16#L20true main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 14#L26-2true main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15#L26-3true [2022-10-17 10:50:25,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:25,850 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:50:25,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:25,861 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318592554] [2022-10-17 10:50:25,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:25,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:25,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:25,973 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:25,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:26,007 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:26,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:26,011 INFO L85 PathProgramCache]: Analyzing trace with hash 38364915, now seen corresponding path program 1 times [2022-10-17 10:50:26,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:26,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256275825] [2022-10-17 10:50:26,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:26,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:26,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:26,047 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:26,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:26,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:26,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:26,097 INFO L85 PathProgramCache]: Analyzing trace with hash 1809804401, now seen corresponding path program 1 times [2022-10-17 10:50:26,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:26,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393298353] [2022-10-17 10:50:26,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:26,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:26,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:26,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:26,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:26,446 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393298353] [2022-10-17 10:50:26,447 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393298353] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:50:26,448 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:50:26,448 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 10:50:26,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602581586] [2022-10-17 10:50:26,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:50:26,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:26,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:50:26,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:50:26,750 INFO L87 Difference]: Start difference. First operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:26,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:26,850 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2022-10-17 10:50:26,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 36 transitions. [2022-10-17 10:50:26,859 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11 [2022-10-17 10:50:26,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 23 states and 26 transitions. [2022-10-17 10:50:26,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-10-17 10:50:26,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-10-17 10:50:26,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 26 transitions. [2022-10-17 10:50:26,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:26,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 26 transitions. [2022-10-17 10:50:26,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 26 transitions. [2022-10-17 10:50:26,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 14. [2022-10-17 10:50:26,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.1428571428571428) internal successors, (16), 13 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:26,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 16 transitions. [2022-10-17 10:50:26,903 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 16 transitions. [2022-10-17 10:50:26,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:50:26,911 INFO L428 stractBuchiCegarLoop]: Abstraction has 14 states and 16 transitions. [2022-10-17 10:50:26,911 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:50:26,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 16 transitions. [2022-10-17 10:50:26,915 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:50:26,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:26,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:26,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-10-17 10:50:26,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:50:26,917 INFO L748 eck$LassoCheckResult]: Stem: 68#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 69#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 74#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 73#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 63#L17-2 [2022-10-17 10:50:26,918 INFO L750 eck$LassoCheckResult]: Loop: 63#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 64#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 63#L17-2 [2022-10-17 10:50:26,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:26,919 INFO L85 PathProgramCache]: Analyzing trace with hash 925771, now seen corresponding path program 1 times [2022-10-17 10:50:26,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:26,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110439111] [2022-10-17 10:50:26,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:26,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:26,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:26,973 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:26,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,008 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:27,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:27,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 1 times [2022-10-17 10:50:27,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:27,010 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807253469] [2022-10-17 10:50:27,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:27,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,028 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:27,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:27,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:27,040 INFO L85 PathProgramCache]: Analyzing trace with hash 889666569, now seen corresponding path program 1 times [2022-10-17 10:50:27,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:27,040 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220001865] [2022-10-17 10:50:27,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:27,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:27,241 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:27,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:27,243 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220001865] [2022-10-17 10:50:27,243 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220001865] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:27,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [344206528] [2022-10-17 10:50:27,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:27,245 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:27,247 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:27,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-10-17 10:50:27,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:27,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 72 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:50:27,315 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:27,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:27,433 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-10-17 10:50:27,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [344206528] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:50:27,434 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-10-17 10:50:27,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 7 [2022-10-17 10:50:27,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260674029] [2022-10-17 10:50:27,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:50:27,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:27,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:50:27,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2022-10-17 10:50:27,493 INFO L87 Difference]: Start difference. First operand 14 states and 16 transitions. cyclomatic complexity: 4 Second operand has 5 states, 4 states have (on average 1.5) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:27,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:27,560 INFO L93 Difference]: Finished difference Result 30 states and 33 transitions. [2022-10-17 10:50:27,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 33 transitions. [2022-10-17 10:50:27,562 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 12 [2022-10-17 10:50:27,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 33 transitions. [2022-10-17 10:50:27,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2022-10-17 10:50:27,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-10-17 10:50:27,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 33 transitions. [2022-10-17 10:50:27,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:27,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 33 transitions. [2022-10-17 10:50:27,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 33 transitions. [2022-10-17 10:50:27,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 16. [2022-10-17 10:50:27,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.125) internal successors, (18), 15 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:27,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 18 transitions. [2022-10-17 10:50:27,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 18 transitions. [2022-10-17 10:50:27,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:50:27,569 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2022-10-17 10:50:27,569 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:50:27,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 18 transitions. [2022-10-17 10:50:27,570 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2022-10-17 10:50:27,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:27,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:27,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-10-17 10:50:27,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2022-10-17 10:50:27,571 INFO L748 eck$LassoCheckResult]: Stem: 144#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 149#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 152#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 154#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 150#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 151#L17-4 [2022-10-17 10:50:27,571 INFO L750 eck$LassoCheckResult]: Loop: 151#L17-4 foo_#res#1 := foo_~i~0#1; 153#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 147#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 148#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 140#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 151#L17-4 [2022-10-17 10:50:27,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:27,572 INFO L85 PathProgramCache]: Analyzing trace with hash 889666567, now seen corresponding path program 1 times [2022-10-17 10:50:27,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:27,572 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500624475] [2022-10-17 10:50:27,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:27,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,586 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:27,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,599 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:27,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:27,600 INFO L85 PathProgramCache]: Analyzing trace with hash 51595455, now seen corresponding path program 2 times [2022-10-17 10:50:27,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:27,600 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694048630] [2022-10-17 10:50:27,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:27,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:27,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:27,619 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:27,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:27,620 INFO L85 PathProgramCache]: Analyzing trace with hash 1198432377, now seen corresponding path program 1 times [2022-10-17 10:50:27,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:27,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325192784] [2022-10-17 10:50:27,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:27,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:27,723 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:27,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:27,723 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325192784] [2022-10-17 10:50:27,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325192784] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:27,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115848459] [2022-10-17 10:50:27,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:27,724 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:27,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:27,726 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:27,735 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-10-17 10:50:27,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:27,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:50:27,806 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:27,855 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:27,856 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:27,938 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:27,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1115848459] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:27,939 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:27,939 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 8 [2022-10-17 10:50:27,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128752184] [2022-10-17 10:50:27,940 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:28,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:28,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-10-17 10:50:28,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-10-17 10:50:28,124 INFO L87 Difference]: Start difference. First operand 16 states and 18 transitions. cyclomatic complexity: 4 Second operand has 9 states, 8 states have (on average 3.875) internal successors, (31), 9 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:28,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:28,260 INFO L93 Difference]: Finished difference Result 25 states and 27 transitions. [2022-10-17 10:50:28,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 27 transitions. [2022-10-17 10:50:28,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:50:28,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 27 transitions. [2022-10-17 10:50:28,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-10-17 10:50:28,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-10-17 10:50:28,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 27 transitions. [2022-10-17 10:50:28,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:28,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 27 transitions. [2022-10-17 10:50:28,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 27 transitions. [2022-10-17 10:50:28,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 19. [2022-10-17 10:50:28,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:28,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2022-10-17 10:50:28,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-10-17 10:50:28,266 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:50:28,267 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-10-17 10:50:28,267 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:50:28,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2022-10-17 10:50:28,268 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:50:28,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:28,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:28,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-10-17 10:50:28,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1, 1, 1, 1] [2022-10-17 10:50:28,269 INFO L748 eck$LassoCheckResult]: Stem: 262#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 263#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 270#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 273#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 278#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 276#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 274#L17-4 [2022-10-17 10:50:28,269 INFO L750 eck$LassoCheckResult]: Loop: 274#L17-4 foo_#res#1 := foo_~i~0#1; 272#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 267#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 268#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 275#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 260#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 261#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 271#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 277#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 274#L17-4 [2022-10-17 10:50:28,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:28,269 INFO L85 PathProgramCache]: Analyzing trace with hash 889666567, now seen corresponding path program 2 times [2022-10-17 10:50:28,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:28,270 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020790462] [2022-10-17 10:50:28,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:28,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:28,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:28,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:28,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:28,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1121476027, now seen corresponding path program 1 times [2022-10-17 10:50:28,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:28,303 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [766361685] [2022-10-17 10:50:28,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:28,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:28,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,326 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:28,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:28,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:28,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1242740619, now seen corresponding path program 2 times [2022-10-17 10:50:28,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:28,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933234433] [2022-10-17 10:50:28,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:28,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:28,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,358 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:28,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:28,376 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:28,628 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 29 [2022-10-17 10:50:29,089 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 14 [2022-10-17 10:50:29,203 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:50:29,203 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:50:29,204 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:50:29,204 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:50:29,204 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:50:29,204 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:29,204 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:50:29,205 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:50:29,205 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration4_Lasso [2022-10-17 10:50:29,205 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:50:29,205 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:50:29,229 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,239 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,241 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,245 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,648 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,652 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,655 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,658 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,660 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,663 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:29,666 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:30,077 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:50:30,082 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:50:30,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,112 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,117 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:50:30,117 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,127 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,128 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,128 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,128 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,141 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:30,142 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:30,154 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,185 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-10-17 10:50:30,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,187 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,188 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,197 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:50:30,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,198 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:30,198 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,198 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,198 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,200 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:30,200 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:30,203 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,228 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:30,229 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,230 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:50:30,235 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,242 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,242 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:30,243 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,243 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,243 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,244 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:30,244 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:30,249 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,274 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2022-10-17 10:50:30,275 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,276 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,277 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,279 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:50:30,285 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,286 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:30,286 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,286 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,286 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,287 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:30,287 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:30,292 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,321 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2022-10-17 10:50:30,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,321 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,322 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,323 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:50:30,327 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,335 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,335 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,336 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,336 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,344 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:30,344 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:30,376 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,396 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:30,396 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,396 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,397 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,402 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 10:50:30,403 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,410 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,410 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,411 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,411 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,415 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:30,415 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:30,428 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,454 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:30,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,454 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,455 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,457 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-10-17 10:50:30,458 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,465 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,465 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,465 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,465 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,467 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:30,468 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:30,471 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:30,494 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2022-10-17 10:50:30,495 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,495 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,496 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-10-17 10:50:30,500 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:30,507 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:30,507 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:30,507 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:30,507 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:30,525 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:30,525 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:30,550 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:50:30,600 INFO L443 ModelExtractionUtils]: Simplification made 7 calls to the SMT solver. [2022-10-17 10:50:30,600 INFO L444 ModelExtractionUtils]: 17 out of 37 variables were initially zero. Simplification set additionally 17 variables to zero. [2022-10-17 10:50:30,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:30,602 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:30,614 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:30,616 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-10-17 10:50:30,616 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:50:30,634 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:50:30,634 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:50:30,635 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~1#1) = -2*ULTIMATE.start_main_~i~1#1 + 1 Supporting invariants [] [2022-10-17 10:50:30,671 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:30,705 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-10-17 10:50:30,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:30,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:30,764 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:50:30,765 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:30,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:30,788 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 9 conjunts are in the unsatisfiable core [2022-10-17 10:50:30,789 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:30,922 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:30,927 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 5 loop predicates [2022-10-17 10:50:30,928 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 19 states and 21 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:31,056 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 19 states and 21 transitions. cyclomatic complexity: 4. Second operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 41 states and 47 transitions. Complement of second has 13 states. [2022-10-17 10:50:31,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 7 states 1 stem states 5 non-accepting loop states 1 accepting loop states [2022-10-17 10:50:31,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:31,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 24 transitions. [2022-10-17 10:50:31,060 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 6 letters. Loop has 9 letters. [2022-10-17 10:50:31,061 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:31,061 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 15 letters. Loop has 9 letters. [2022-10-17 10:50:31,062 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:31,062 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 6 letters. Loop has 18 letters. [2022-10-17 10:50:31,062 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:31,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 47 transitions. [2022-10-17 10:50:31,065 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2022-10-17 10:50:31,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 46 transitions. [2022-10-17 10:50:31,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2022-10-17 10:50:31,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-10-17 10:50:31,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 46 transitions. [2022-10-17 10:50:31,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:50:31,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40 states and 46 transitions. [2022-10-17 10:50:31,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 46 transitions. [2022-10-17 10:50:31,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 34. [2022-10-17 10:50:31,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:31,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2022-10-17 10:50:31,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2022-10-17 10:50:31,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2022-10-17 10:50:31,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:50:31,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2022-10-17 10:50:31,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:50:31,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:31,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:31,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:50:31,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2022-10-17 10:50:31,082 INFO L748 eck$LassoCheckResult]: Stem: 427#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 438#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 441#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 450#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 446#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 447#L17-4 foo_#res#1 := foo_~i~0#1; 439#L20 [2022-10-17 10:50:31,082 INFO L750 eck$LassoCheckResult]: Loop: 439#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 430#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 431#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 445#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 420#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 421#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 452#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 434#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 435#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 453#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 443#L17-4 foo_#res#1 := foo_~i~0#1; 439#L20 [2022-10-17 10:50:31,082 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:31,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1809859825, now seen corresponding path program 1 times [2022-10-17 10:50:31,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:31,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1836825266] [2022-10-17 10:50:31,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:31,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:31,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:31,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:31,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:31,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:31,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:31,132 INFO L85 PathProgramCache]: Analyzing trace with hash 961271861, now seen corresponding path program 2 times [2022-10-17 10:50:31,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:31,135 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466299994] [2022-10-17 10:50:31,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:31,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:31,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:31,161 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:31,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:31,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:31,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:31,187 INFO L85 PathProgramCache]: Analyzing trace with hash 132390213, now seen corresponding path program 3 times [2022-10-17 10:50:31,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:31,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939925658] [2022-10-17 10:50:31,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:31,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:31,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:31,342 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:31,374 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 10 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:31,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:31,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939925658] [2022-10-17 10:50:31,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939925658] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:31,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1636131625] [2022-10-17 10:50:31,375 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:50:31,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:31,375 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:31,376 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:31,402 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-10-17 10:50:31,450 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-10-17 10:50:31,450 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:31,451 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:50:31,453 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:31,539 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:31,539 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:31,620 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:31,620 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1636131625] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:31,620 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:31,620 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2022-10-17 10:50:31,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410680583] [2022-10-17 10:50:31,623 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:31,878 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 32 [2022-10-17 10:50:31,991 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:31,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-10-17 10:50:31,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2022-10-17 10:50:31,992 INFO L87 Difference]: Start difference. First operand 34 states and 40 transitions. cyclomatic complexity: 9 Second operand has 12 states, 12 states have (on average 2.9166666666666665) internal successors, (35), 12 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:32,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:32,266 INFO L93 Difference]: Finished difference Result 83 states and 91 transitions. [2022-10-17 10:50:32,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 91 transitions. [2022-10-17 10:50:32,269 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 20 [2022-10-17 10:50:32,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 78 states and 86 transitions. [2022-10-17 10:50:32,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54 [2022-10-17 10:50:32,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54 [2022-10-17 10:50:32,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 86 transitions. [2022-10-17 10:50:32,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:50:32,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78 states and 86 transitions. [2022-10-17 10:50:32,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 86 transitions. [2022-10-17 10:50:32,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 45. [2022-10-17 10:50:32,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1333333333333333) internal successors, (51), 44 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:32,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 51 transitions. [2022-10-17 10:50:32,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 51 transitions. [2022-10-17 10:50:32,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-10-17 10:50:32,285 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 51 transitions. [2022-10-17 10:50:32,285 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:50:32,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 51 transitions. [2022-10-17 10:50:32,287 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:50:32,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:32,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:32,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:50:32,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:50:32,289 INFO L748 eck$LassoCheckResult]: Stem: 685#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 686#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 695#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 692#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 693#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 701#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 702#L17-4 foo_#res#1 := foo_~i~0#1; 712#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 711#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 707#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 691#L26-4 main_~i~1#1 := 0; 682#L29-3 [2022-10-17 10:50:32,289 INFO L750 eck$LassoCheckResult]: Loop: 682#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 683#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 684#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 682#L29-3 [2022-10-17 10:50:32,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:32,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1198432331, now seen corresponding path program 1 times [2022-10-17 10:50:32,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:32,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096993096] [2022-10-17 10:50:32,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:32,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:32,392 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:32,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:32,393 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096993096] [2022-10-17 10:50:32,395 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096993096] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:32,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [416583068] [2022-10-17 10:50:32,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:32,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:32,401 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:32,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-10-17 10:50:32,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:32,463 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:50:32,464 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:32,489 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:32,490 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:32,526 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-10-17 10:50:32,526 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [416583068] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:32,527 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:32,527 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2022-10-17 10:50:32,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756199037] [2022-10-17 10:50:32,527 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:32,528 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:50:32,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:32,528 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 1 times [2022-10-17 10:50:32,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:32,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757367200] [2022-10-17 10:50:32,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:32,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,533 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:32,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,536 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:32,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:32,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:50:32,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:50:32,580 INFO L87 Difference]: Start difference. First operand 45 states and 51 transitions. cyclomatic complexity: 9 Second operand has 7 states, 7 states have (on average 3.142857142857143) internal successors, (22), 7 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:32,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:32,659 INFO L93 Difference]: Finished difference Result 85 states and 95 transitions. [2022-10-17 10:50:32,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 95 transitions. [2022-10-17 10:50:32,661 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-10-17 10:50:32,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 82 states and 92 transitions. [2022-10-17 10:50:32,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2022-10-17 10:50:32,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2022-10-17 10:50:32,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 92 transitions. [2022-10-17 10:50:32,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:50:32,663 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 92 transitions. [2022-10-17 10:50:32,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 92 transitions. [2022-10-17 10:50:32,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 66. [2022-10-17 10:50:32,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1363636363636365) internal successors, (75), 65 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:32,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 75 transitions. [2022-10-17 10:50:32,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 75 transitions. [2022-10-17 10:50:32,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:50:32,670 INFO L428 stractBuchiCegarLoop]: Abstraction has 66 states and 75 transitions. [2022-10-17 10:50:32,670 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:50:32,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 75 transitions. [2022-10-17 10:50:32,671 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-10-17 10:50:32,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:32,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:32,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 3, 2, 2, 2, 2, 1, 1] [2022-10-17 10:50:32,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:50:32,673 INFO L748 eck$LassoCheckResult]: Stem: 884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 894#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 938#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 936#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 935#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 932#L17-4 foo_#res#1 := foo_~i~0#1; 931#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 930#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 929#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 928#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 927#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 926#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 925#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 924#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 922#L17-4 foo_#res#1 := foo_~i~0#1; 921#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 889#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 890#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 895#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 880#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 881#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 939#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 937#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 934#L17-2 [2022-10-17 10:50:32,673 INFO L750 eck$LassoCheckResult]: Loop: 934#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 933#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 934#L17-2 [2022-10-17 10:50:32,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:32,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1084446665, now seen corresponding path program 4 times [2022-10-17 10:50:32,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:32,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720775539] [2022-10-17 10:50:32,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:32,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,698 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:32,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,719 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:32,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:32,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 2 times [2022-10-17 10:50:32,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:32,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408710678] [2022-10-17 10:50:32,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:32,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,724 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:32,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:32,728 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:32,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:32,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1523807225, now seen corresponding path program 5 times [2022-10-17 10:50:32,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:32,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144001915] [2022-10-17 10:50:32,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:32,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:32,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:32,902 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 48 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-10-17 10:50:32,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:32,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144001915] [2022-10-17 10:50:32,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144001915] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:32,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [182734349] [2022-10-17 10:50:32,903 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:50:32,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:32,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:32,908 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:32,913 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-10-17 10:50:32,998 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-10-17 10:50:32,998 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:32,999 INFO L263 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 14 conjunts are in the unsatisfiable core [2022-10-17 10:50:33,001 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:33,166 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 11 proven. 42 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-10-17 10:50:33,166 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:33,311 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 8 proven. 45 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-10-17 10:50:33,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [182734349] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:33,312 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:33,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 11, 11] total 19 [2022-10-17 10:50:33,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978394835] [2022-10-17 10:50:33,314 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:33,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:33,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-10-17 10:50:33,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=299, Unknown=0, NotChecked=0, Total=380 [2022-10-17 10:50:33,362 INFO L87 Difference]: Start difference. First operand 66 states and 75 transitions. cyclomatic complexity: 13 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:33,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:33,767 INFO L93 Difference]: Finished difference Result 87 states and 95 transitions. [2022-10-17 10:50:33,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 95 transitions. [2022-10-17 10:50:33,768 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:50:33,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 95 transitions. [2022-10-17 10:50:33,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48 [2022-10-17 10:50:33,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48 [2022-10-17 10:50:33,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 95 transitions. [2022-10-17 10:50:33,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:50:33,770 INFO L218 hiAutomatonCegarLoop]: Abstraction has 87 states and 95 transitions. [2022-10-17 10:50:33,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 95 transitions. [2022-10-17 10:50:33,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 68. [2022-10-17 10:50:33,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1176470588235294) internal successors, (76), 67 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:33,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 76 transitions. [2022-10-17 10:50:33,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 76 transitions. [2022-10-17 10:50:33,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:50:33,779 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 76 transitions. [2022-10-17 10:50:33,781 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:50:33,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 76 transitions. [2022-10-17 10:50:33,782 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:50:33,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:33,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:33,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 3, 3, 1, 1] [2022-10-17 10:50:33,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2022-10-17 10:50:33,788 INFO L748 eck$LassoCheckResult]: Stem: 1247#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1257#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1299#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1297#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1282#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1283#L17-4 foo_#res#1 := foo_~i~0#1; 1296#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1295#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1294#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1293#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1292#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1291#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1290#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1289#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1287#L17-4 foo_#res#1 := foo_~i~0#1; 1288#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1301#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1258#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1259#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1307#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1306#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1305#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1303#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1302#L17-4 foo_#res#1 := foo_~i~0#1; 1260#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1261#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1281#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1265#L17-3 [2022-10-17 10:50:33,788 INFO L750 eck$LassoCheckResult]: Loop: 1265#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1280#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1279#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1277#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1275#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1272#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1271#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1269#L17-4 foo_#res#1 := foo_~i~0#1; 1267#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1266#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1264#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1265#L17-3 [2022-10-17 10:50:33,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:33,789 INFO L85 PathProgramCache]: Analyzing trace with hash 203385399, now seen corresponding path program 6 times [2022-10-17 10:50:33,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:33,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40164151] [2022-10-17 10:50:33,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:33,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:33,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:33,966 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 15 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-10-17 10:50:33,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:33,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40164151] [2022-10-17 10:50:33,966 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40164151] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:33,966 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [182455228] [2022-10-17 10:50:33,966 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-10-17 10:50:33,967 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:33,967 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:33,968 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:33,993 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-10-17 10:50:34,060 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2022-10-17 10:50:34,060 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:34,061 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 9 conjunts are in the unsatisfiable core [2022-10-17 10:50:34,063 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:34,159 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 23 proven. 25 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-10-17 10:50:34,160 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:34,290 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 23 proven. 25 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-10-17 10:50:34,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [182455228] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:34,290 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:34,291 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2022-10-17 10:50:34,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554417393] [2022-10-17 10:50:34,292 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:34,293 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:50:34,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:34,294 INFO L85 PathProgramCache]: Analyzing trace with hash -81249831, now seen corresponding path program 3 times [2022-10-17 10:50:34,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:34,294 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945677044] [2022-10-17 10:50:34,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:34,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:34,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,307 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:34,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,327 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:34,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:34,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-10-17 10:50:34,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=152, Unknown=0, NotChecked=0, Total=210 [2022-10-17 10:50:34,675 INFO L87 Difference]: Start difference. First operand 68 states and 76 transitions. cyclomatic complexity: 11 Second operand has 15 states, 15 states have (on average 3.066666666666667) internal successors, (46), 15 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:34,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:34,908 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2022-10-17 10:50:34,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74 states and 78 transitions. [2022-10-17 10:50:34,909 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2022-10-17 10:50:34,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74 states to 52 states and 54 transitions. [2022-10-17 10:50:34,910 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2022-10-17 10:50:34,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2022-10-17 10:50:34,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 54 transitions. [2022-10-17 10:50:34,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:34,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 54 transitions. [2022-10-17 10:50:34,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 54 transitions. [2022-10-17 10:50:34,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 45. [2022-10-17 10:50:34,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0444444444444445) internal successors, (47), 44 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:34,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2022-10-17 10:50:34,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 47 transitions. [2022-10-17 10:50:34,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:50:34,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2022-10-17 10:50:34,922 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:50:34,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 47 transitions. [2022-10-17 10:50:34,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:50:34,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:34,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:34,925 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 3, 3, 3, 3, 1, 1] [2022-10-17 10:50:34,925 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2022-10-17 10:50:34,925 INFO L748 eck$LassoCheckResult]: Stem: 1579#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1580#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1585#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1618#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1574#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1575#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1584#L17-4 foo_#res#1 := foo_~i~0#1; 1589#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1581#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1582#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1588#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1617#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1616#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1615#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1614#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1613#L17-4 foo_#res#1 := foo_~i~0#1; 1586#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1587#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1612#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1611#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1610#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1609#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1608#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1607#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1606#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1605#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1604#L17-4 foo_#res#1 := foo_~i~0#1; 1603#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1602#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1601#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1591#L17-3 [2022-10-17 10:50:34,925 INFO L750 eck$LassoCheckResult]: Loop: 1591#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1600#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1599#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1598#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1597#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1596#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1595#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1594#L17-4 foo_#res#1 := foo_~i~0#1; 1593#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1592#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1590#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1591#L17-3 [2022-10-17 10:50:34,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:34,926 INFO L85 PathProgramCache]: Analyzing trace with hash -463974539, now seen corresponding path program 7 times [2022-10-17 10:50:34,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:34,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1712365150] [2022-10-17 10:50:34,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:34,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:34,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,950 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:34,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,973 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:34,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:34,973 INFO L85 PathProgramCache]: Analyzing trace with hash -81249831, now seen corresponding path program 4 times [2022-10-17 10:50:34,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:34,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034259988] [2022-10-17 10:50:34,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:34,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:34,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,981 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:34,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:34,989 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:34,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:34,989 INFO L85 PathProgramCache]: Analyzing trace with hash -1101563419, now seen corresponding path program 8 times [2022-10-17 10:50:34,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:34,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120471799] [2022-10-17 10:50:34,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:34,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:35,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:35,257 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 49 proven. 79 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-10-17 10:50:35,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:35,257 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120471799] [2022-10-17 10:50:35,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120471799] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:35,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1936394564] [2022-10-17 10:50:35,258 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:50:35,258 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:35,258 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:35,263 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:35,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-10-17 10:50:35,366 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:50:35,366 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:35,368 INFO L263 TraceCheckSpWp]: Trace formula consists of 270 conjuncts, 11 conjunts are in the unsatisfiable core [2022-10-17 10:50:35,375 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:35,518 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 65 proven. 63 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-10-17 10:50:35,518 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:35,669 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 65 proven. 63 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2022-10-17 10:50:35,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1936394564] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:35,669 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:35,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 19 [2022-10-17 10:50:35,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1405058851] [2022-10-17 10:50:35,670 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:35,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:35,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-10-17 10:50:35,991 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=254, Unknown=0, NotChecked=0, Total=342 [2022-10-17 10:50:35,991 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. cyclomatic complexity: 4 Second operand has 19 states, 19 states have (on average 3.1052631578947367) internal successors, (59), 19 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:36,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:36,436 INFO L93 Difference]: Finished difference Result 57 states and 59 transitions. [2022-10-17 10:50:36,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 59 transitions. [2022-10-17 10:50:36,437 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17 [2022-10-17 10:50:36,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 59 transitions. [2022-10-17 10:50:36,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57 [2022-10-17 10:50:36,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57 [2022-10-17 10:50:36,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 59 transitions. [2022-10-17 10:50:36,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:36,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 59 transitions. [2022-10-17 10:50:36,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 59 transitions. [2022-10-17 10:50:36,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 47. [2022-10-17 10:50:36,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0425531914893618) internal successors, (49), 46 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:36,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2022-10-17 10:50:36,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 49 transitions. [2022-10-17 10:50:36,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-10-17 10:50:36,446 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2022-10-17 10:50:36,446 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:50:36,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2022-10-17 10:50:36,447 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2022-10-17 10:50:36,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:36,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:36,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 3, 3, 3, 3, 1, 1] [2022-10-17 10:50:36,448 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2022-10-17 10:50:36,449 INFO L748 eck$LassoCheckResult]: Stem: 1965#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1972#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1970#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1971#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2005#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1976#L17-4 foo_#res#1 := foo_~i~0#1; 1977#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1967#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1968#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1975#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1960#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1961#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2006#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2004#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2003#L17-4 foo_#res#1 := foo_~i~0#1; 1973#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1974#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2002#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2001#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2000#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1999#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1998#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1997#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1996#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1995#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1994#L17-4 foo_#res#1 := foo_~i~0#1; 1993#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1992#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1991#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1979#L17-3 [2022-10-17 10:50:36,449 INFO L750 eck$LassoCheckResult]: Loop: 1979#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1990#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1989#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1988#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1987#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1986#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1985#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1984#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1983#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1982#L17-4 foo_#res#1 := foo_~i~0#1; 1981#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1980#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1978#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1979#L17-3 [2022-10-17 10:50:36,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:36,449 INFO L85 PathProgramCache]: Analyzing trace with hash -463974539, now seen corresponding path program 9 times [2022-10-17 10:50:36,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:36,450 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638587040] [2022-10-17 10:50:36,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:36,450 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:36,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:36,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,525 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:36,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:36,526 INFO L85 PathProgramCache]: Analyzing trace with hash 879476375, now seen corresponding path program 5 times [2022-10-17 10:50:36,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:36,527 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308020713] [2022-10-17 10:50:36,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:36,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:36,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:36,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,575 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:36,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:36,576 INFO L85 PathProgramCache]: Analyzing trace with hash -389338205, now seen corresponding path program 10 times [2022-10-17 10:50:36,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:36,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537093119] [2022-10-17 10:50:36,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:36,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:36,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,634 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:36,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:36,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:38,483 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:50:38,483 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:50:38,483 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:50:38,484 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:50:38,484 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:50:38,484 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:38,484 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:50:38,484 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:50:38,484 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration10_Lasso [2022-10-17 10:50:38,484 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:50:38,484 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:50:38,488 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,492 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,495 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,497 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,499 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,501 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,502 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,504 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,506 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,967 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,970 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:38,973 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:39,428 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:50:39,428 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:50:39,429 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,429 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,437 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,439 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2022-10-17 10:50:39,443 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,450 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,450 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,451 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,451 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,451 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,451 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,451 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,455 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,482 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,484 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,485 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2022-10-17 10:50:39,485 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,492 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,492 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,493 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,496 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:39,496 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:39,503 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,523 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,523 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,524 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2022-10-17 10:50:39,529 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,536 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,536 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,536 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,536 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,536 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,537 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,537 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,539 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,560 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,560 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,561 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2022-10-17 10:50:39,562 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,570 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,570 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,570 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,570 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,570 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,570 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,570 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,572 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,598 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,599 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2022-10-17 10:50:39,600 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,607 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,607 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,608 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,608 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,608 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,608 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,608 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,609 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,637 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,638 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2022-10-17 10:50:39,640 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,647 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,647 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,647 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,647 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,647 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,647 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,648 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,648 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,675 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,675 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,675 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,676 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2022-10-17 10:50:39,681 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,688 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,688 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:39,688 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,688 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,688 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,689 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:39,689 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:39,690 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,710 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,710 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,711 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,712 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2022-10-17 10:50:39,717 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,723 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,724 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,724 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,724 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,725 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:39,725 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:39,727 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:39,748 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,749 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,750 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2022-10-17 10:50:39,751 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:39,759 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:39,759 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:39,760 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:39,760 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:39,786 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:39,787 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:39,825 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:50:39,865 INFO L443 ModelExtractionUtils]: Simplification made 8 calls to the SMT solver. [2022-10-17 10:50:39,865 INFO L444 ModelExtractionUtils]: 23 out of 40 variables were initially zero. Simplification set additionally 13 variables to zero. [2022-10-17 10:50:39,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:39,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:39,872 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:39,873 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:50:39,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2022-10-17 10:50:39,899 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:50:39,899 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:50:39,899 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~#b~0#1.offset, v_rep(select #length ULTIMATE.start_main_~#b~0#1.base)_2, ULTIMATE.start_main_~i~1#1) = -1*ULTIMATE.start_main_~#b~0#1.offset + 2*v_rep(select #length ULTIMATE.start_main_~#b~0#1.base)_2 - 4*ULTIMATE.start_main_~i~1#1 Supporting invariants [] [2022-10-17 10:50:39,933 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:39,951 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-10-17 10:50:39,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:40,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:40,008 INFO L263 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:50:40,009 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:40,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:40,075 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:50:40,076 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:40,188 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2022-10-17 10:50:40,189 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 10:50:40,189 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 47 states and 49 transitions. cyclomatic complexity: 4 Second operand has 5 states, 5 states have (on average 3.6) internal successors, (18), 5 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:40,222 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 47 states and 49 transitions. cyclomatic complexity: 4. Second operand has 5 states, 5 states have (on average 3.6) internal successors, (18), 5 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 83 states and 87 transitions. Complement of second has 7 states. [2022-10-17 10:50:40,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:50:40,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 3.6) internal successors, (18), 5 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:40,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 12 transitions. [2022-10-17 10:50:40,226 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 30 letters. Loop has 13 letters. [2022-10-17 10:50:40,229 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:40,230 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 43 letters. Loop has 13 letters. [2022-10-17 10:50:40,233 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:40,233 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 12 transitions. Stem has 30 letters. Loop has 26 letters. [2022-10-17 10:50:40,236 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:40,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 87 transitions. [2022-10-17 10:50:40,239 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-10-17 10:50:40,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 56 states and 60 transitions. [2022-10-17 10:50:40,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-10-17 10:50:40,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2022-10-17 10:50:40,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 60 transitions. [2022-10-17 10:50:40,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:50:40,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56 states and 60 transitions. [2022-10-17 10:50:40,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 60 transitions. [2022-10-17 10:50:40,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 49. [2022-10-17 10:50:40,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0816326530612246) internal successors, (53), 48 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:40,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 53 transitions. [2022-10-17 10:50:40,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49 states and 53 transitions. [2022-10-17 10:50:40,259 INFO L428 stractBuchiCegarLoop]: Abstraction has 49 states and 53 transitions. [2022-10-17 10:50:40,259 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:50:40,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 53 transitions. [2022-10-17 10:50:40,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2022-10-17 10:50:40,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:40,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:40,261 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 3, 3, 3, 3, 1, 1] [2022-10-17 10:50:40,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:50:40,266 INFO L748 eck$LassoCheckResult]: Stem: 2270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2271#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 2276#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2278#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2311#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2309#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2307#L17-4 foo_#res#1 := foo_~i~0#1; 2306#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2305#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2279#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2275#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2265#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2266#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2310#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2308#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2280#L17-4 foo_#res#1 := foo_~i~0#1; 2277#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2272#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2273#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2304#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2303#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2302#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2301#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2300#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2299#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2298#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2297#L17-4 foo_#res#1 := foo_~i~0#1; 2296#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2295#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2294#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2264#L17-3 [2022-10-17 10:50:40,267 INFO L750 eck$LassoCheckResult]: Loop: 2264#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2263#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2264#L17-3 [2022-10-17 10:50:40,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:40,268 INFO L85 PathProgramCache]: Analyzing trace with hash -463974539, now seen corresponding path program 11 times [2022-10-17 10:50:40,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:40,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939609361] [2022-10-17 10:50:40,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:40,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:40,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,297 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:40,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,333 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:40,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:40,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1539, now seen corresponding path program 3 times [2022-10-17 10:50:40,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:40,334 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040981898] [2022-10-17 10:50:40,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:40,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:40,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,339 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:40,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,342 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:40,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:40,343 INFO L85 PathProgramCache]: Analyzing trace with hash 797067383, now seen corresponding path program 12 times [2022-10-17 10:50:40,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:40,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097312801] [2022-10-17 10:50:40,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:40,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:40,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,373 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:40,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:40,414 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:40,592 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:41,770 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:50:41,770 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:50:41,770 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:50:41,770 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:50:41,770 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:50:41,770 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:41,771 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:50:41,771 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:50:41,771 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration11_Lasso [2022-10-17 10:50:41,771 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:50:41,771 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:50:41,773 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:41,775 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:41,777 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:41,779 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:41,781 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:41,783 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,040 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,042 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,043 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,046 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,048 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:50:42,324 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:50:42,325 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:50:42,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,325 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,327 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-10-17 10:50:42,330 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,337 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,337 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,337 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,338 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,338 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,338 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,338 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,343 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,365 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,365 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,366 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,368 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-10-17 10:50:42,368 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,375 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,375 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,375 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,376 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,376 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,376 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,376 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,377 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,401 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,401 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,401 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,402 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-10-17 10:50:42,404 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,411 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,411 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,411 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,411 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,411 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,412 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,412 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,413 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,435 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,435 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,435 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,436 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,437 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-10-17 10:50:42,438 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,445 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,446 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,446 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,446 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,447 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:42,447 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:42,450 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,482 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,483 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,484 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2022-10-17 10:50:42,485 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,492 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,492 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,492 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,492 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,493 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,493 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,494 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,515 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,515 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,516 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,516 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,517 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-10-17 10:50:42,517 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,525 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,525 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,525 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,525 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,526 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:42,526 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:42,529 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,550 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2022-10-17 10:50:42,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,550 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,551 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-10-17 10:50:42,553 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,560 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,560 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,560 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,560 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,561 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,561 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,561 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,562 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,583 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2022-10-17 10:50:42,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,584 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-10-17 10:50:42,585 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,592 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,592 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,593 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,593 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,594 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:42,594 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:42,619 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,659 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,663 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,667 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,676 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,676 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,676 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,677 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:42,678 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:42,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-10-17 10:50:42,699 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,735 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,735 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,736 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,737 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,738 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2022-10-17 10:50:42,743 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,752 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,752 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:50:42,752 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,752 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,752 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,752 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:50:42,753 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:50:42,766 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:50:42,795 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,796 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2022-10-17 10:50:42,797 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:50:42,804 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:50:42,804 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:50:42,804 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:50:42,804 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:50:42,810 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:50:42,810 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:50:42,822 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:50:42,854 INFO L443 ModelExtractionUtils]: Simplification made 15 calls to the SMT solver. [2022-10-17 10:50:42,854 INFO L444 ModelExtractionUtils]: 7 out of 34 variables were initially zero. Simplification set additionally 24 variables to zero. [2022-10-17 10:50:42,854 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:50:42,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:42,855 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:50:42,857 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2022-10-17 10:50:42,857 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:50:42,867 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:50:42,867 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:50:42,867 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_foo_~i~0#1) = -2*ULTIMATE.start_foo_~i~0#1 + 63 Supporting invariants [] [2022-10-17 10:50:42,890 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:42,907 INFO L156 tatePredicateManager]: 9 out of 9 supporting invariants were superfluous and have been removed [2022-10-17 10:50:42,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:42,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:42,964 INFO L263 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:50:42,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,004 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,005 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:43,014 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:50:43,014 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,029 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 54 states and 58 transitions. Complement of second has 7 states. [2022-10-17 10:50:43,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:50:43,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 9 transitions. [2022-10-17 10:50:43,032 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 9 transitions. Stem has 30 letters. Loop has 2 letters. [2022-10-17 10:50:43,032 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:43,032 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:50:43,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:43,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,086 INFO L263 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,091 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,130 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,131 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:43,141 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:50:43,141 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,162 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 54 states and 58 transitions. Complement of second has 7 states. [2022-10-17 10:50:43,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:50:43,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 9 transitions. [2022-10-17 10:50:43,163 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 9 transitions. Stem has 30 letters. Loop has 2 letters. [2022-10-17 10:50:43,164 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:43,164 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:50:43,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:43,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,216 INFO L263 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,262 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,262 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:43,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:50:43,283 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:50:43,283 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,315 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 49 states and 53 transitions. cyclomatic complexity: 7. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 81 states and 88 transitions. Complement of second has 6 states. [2022-10-17 10:50:43,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:50:43,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 26 transitions. [2022-10-17 10:50:43,317 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 26 transitions. Stem has 30 letters. Loop has 2 letters. [2022-10-17 10:50:43,319 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:43,320 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 26 transitions. Stem has 32 letters. Loop has 2 letters. [2022-10-17 10:50:43,323 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:43,323 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 26 transitions. Stem has 30 letters. Loop has 4 letters. [2022-10-17 10:50:43,324 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:50:43,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 88 transitions. [2022-10-17 10:50:43,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:43,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 47 states and 49 transitions. [2022-10-17 10:50:43,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-10-17 10:50:43,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-10-17 10:50:43,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 49 transitions. [2022-10-17 10:50:43,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:43,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 49 transitions. [2022-10-17 10:50:43,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 49 transitions. [2022-10-17 10:50:43,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2022-10-17 10:50:43,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0425531914893618) internal successors, (49), 46 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:43,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2022-10-17 10:50:43,335 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 49 transitions. [2022-10-17 10:50:43,335 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2022-10-17 10:50:43,335 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:50:43,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2022-10-17 10:50:43,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:43,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:43,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:43,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 4, 4, 4, 4, 4, 1, 1, 1, 1] [2022-10-17 10:50:43,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:50:43,338 INFO L748 eck$LassoCheckResult]: Stem: 2865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2866#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 2876#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2873#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2874#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2908#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2879#L17-4 foo_#res#1 := foo_~i~0#1; 2880#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2905#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2878#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2875#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2863#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2864#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2909#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2907#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2906#L17-4 foo_#res#1 := foo_~i~0#1; 2877#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2870#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2871#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2904#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2903#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2902#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2901#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2900#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2899#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2898#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2897#L17-4 foo_#res#1 := foo_~i~0#1; 2896#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2895#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2894#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2882#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2893#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2892#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2891#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2890#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2889#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2888#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2887#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2886#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2885#L17-4 foo_#res#1 := foo_~i~0#1; 2884#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2883#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2881#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 2872#L26-4 main_~i~1#1 := 0; 2867#L29-3 [2022-10-17 10:50:43,338 INFO L750 eck$LassoCheckResult]: Loop: 2867#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 2868#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 2869#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2867#L29-3 [2022-10-17 10:50:43,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:43,339 INFO L85 PathProgramCache]: Analyzing trace with hash 815417503, now seen corresponding path program 2 times [2022-10-17 10:50:43,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:43,339 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773938297] [2022-10-17 10:50:43,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:43,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:43,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:43,599 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2022-10-17 10:50:43,711 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2022-10-17 10:50:43,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:43,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773938297] [2022-10-17 10:50:43,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773938297] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:43,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [277928760] [2022-10-17 10:50:43,711 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:50:43,712 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:43,712 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:43,713 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:43,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-10-17 10:50:43,865 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:50:43,865 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:43,866 INFO L263 TraceCheckSpWp]: Trace formula consists of 270 conjuncts, 11 conjunts are in the unsatisfiable core [2022-10-17 10:50:43,868 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:44,030 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2022-10-17 10:50:44,030 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:44,190 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2022-10-17 10:50:44,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [277928760] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:44,191 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:44,191 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2022-10-17 10:50:44,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580725541] [2022-10-17 10:50:44,191 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:44,191 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:50:44,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:44,192 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 2 times [2022-10-17 10:50:44,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:44,192 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526713447] [2022-10-17 10:50:44,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:44,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:44,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:44,197 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:44,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:44,201 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:44,247 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:44,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:50:44,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:50:44,248 INFO L87 Difference]: Start difference. First operand 47 states and 49 transitions. cyclomatic complexity: 4 Second operand has 13 states, 13 states have (on average 4.923076923076923) internal successors, (64), 13 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:44,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:44,712 INFO L93 Difference]: Finished difference Result 153 states and 161 transitions. [2022-10-17 10:50:44,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153 states and 161 transitions. [2022-10-17 10:50:44,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:44,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153 states to 153 states and 161 transitions. [2022-10-17 10:50:44,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2022-10-17 10:50:44,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36 [2022-10-17 10:50:44,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153 states and 161 transitions. [2022-10-17 10:50:44,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:44,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153 states and 161 transitions. [2022-10-17 10:50:44,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states and 161 transitions. [2022-10-17 10:50:44,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 125. [2022-10-17 10:50:44,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125 states, 125 states have (on average 1.064) internal successors, (133), 124 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:44,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 133 transitions. [2022-10-17 10:50:44,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125 states and 133 transitions. [2022-10-17 10:50:44,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:50:44,724 INFO L428 stractBuchiCegarLoop]: Abstraction has 125 states and 133 transitions. [2022-10-17 10:50:44,724 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:50:44,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125 states and 133 transitions. [2022-10-17 10:50:44,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:44,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:44,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:44,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [34, 34, 10, 10, 10, 10, 10, 1, 1, 1, 1] [2022-10-17 10:50:44,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:50:44,728 INFO L748 eck$LassoCheckResult]: Stem: 3350#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 3355#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3356#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3357#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3468#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3466#L17-4 foo_#res#1 := foo_~i~0#1; 3465#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3464#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3359#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3358#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3345#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3346#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3469#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3467#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3361#L17-4 foo_#res#1 := foo_~i~0#1; 3360#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3352#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3353#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3463#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3462#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3461#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3460#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3459#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3458#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3457#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3456#L17-4 foo_#res#1 := foo_~i~0#1; 3455#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3454#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3453#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3452#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3451#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3450#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3449#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3448#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3447#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3446#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3445#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3444#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3443#L17-4 foo_#res#1 := foo_~i~0#1; 3442#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3441#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3440#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3439#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3438#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3437#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3436#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3435#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3434#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3433#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3432#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3431#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3430#L17-4 foo_#res#1 := foo_~i~0#1; 3429#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3428#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3427#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3426#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3425#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3424#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3423#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3422#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3421#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3420#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3419#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3418#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3417#L17-4 foo_#res#1 := foo_~i~0#1; 3416#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3415#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3414#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3413#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3412#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3411#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3410#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3409#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3408#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3407#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3406#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3405#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3404#L17-4 foo_#res#1 := foo_~i~0#1; 3403#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3402#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3401#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3400#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3399#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3398#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3397#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3396#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3395#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3394#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3393#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3392#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3391#L17-4 foo_#res#1 := foo_~i~0#1; 3390#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3389#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3388#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3387#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3386#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3385#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3384#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3383#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3382#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3381#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3380#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3379#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3378#L17-4 foo_#res#1 := foo_~i~0#1; 3377#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3376#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3375#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3363#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3374#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3373#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3372#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3371#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3370#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3369#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3368#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3367#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3366#L17-4 foo_#res#1 := foo_~i~0#1; 3365#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3364#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3362#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 3354#L26-4 main_~i~1#1 := 0; 3347#L29-3 [2022-10-17 10:50:44,728 INFO L750 eck$LassoCheckResult]: Loop: 3347#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 3348#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 3349#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3347#L29-3 [2022-10-17 10:50:44,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:44,729 INFO L85 PathProgramCache]: Analyzing trace with hash -186631969, now seen corresponding path program 3 times [2022-10-17 10:50:44,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:44,729 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [541211346] [2022-10-17 10:50:44,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:44,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:44,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:45,564 INFO L134 CoverageAnalysis]: Checked inductivity of 1697 backedges. 626 proven. 65 refuted. 0 times theorem prover too weak. 1006 trivial. 0 not checked. [2022-10-17 10:50:45,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:45,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [541211346] [2022-10-17 10:50:45,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [541211346] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:45,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [60176026] [2022-10-17 10:50:45,565 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:50:45,566 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:45,566 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:45,575 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:45,595 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-10-17 10:50:45,743 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2022-10-17 10:50:45,743 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:45,745 INFO L263 TraceCheckSpWp]: Trace formula consists of 222 conjuncts, 13 conjunts are in the unsatisfiable core [2022-10-17 10:50:45,749 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:46,135 INFO L134 CoverageAnalysis]: Checked inductivity of 1697 backedges. 333 proven. 35 refuted. 0 times theorem prover too weak. 1329 trivial. 0 not checked. [2022-10-17 10:50:46,135 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:46,648 INFO L134 CoverageAnalysis]: Checked inductivity of 1697 backedges. 0 proven. 368 refuted. 0 times theorem prover too weak. 1329 trivial. 0 not checked. [2022-10-17 10:50:46,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [60176026] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:46,649 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:46,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 11, 11] total 32 [2022-10-17 10:50:46,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631969696] [2022-10-17 10:50:46,650 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:46,650 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:50:46,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:46,651 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 3 times [2022-10-17 10:50:46,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:46,651 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410037311] [2022-10-17 10:50:46,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:46,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:46,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:46,655 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:46,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:46,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:46,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:46,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-10-17 10:50:46,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=186, Invalid=806, Unknown=0, NotChecked=0, Total=992 [2022-10-17 10:50:46,701 INFO L87 Difference]: Start difference. First operand 125 states and 133 transitions. cyclomatic complexity: 16 Second operand has 32 states, 32 states have (on average 2.53125) internal successors, (81), 32 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:49,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:49,393 INFO L93 Difference]: Finished difference Result 253 states and 289 transitions. [2022-10-17 10:50:49,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253 states and 289 transitions. [2022-10-17 10:50:49,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:49,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253 states to 253 states and 289 transitions. [2022-10-17 10:50:49,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-10-17 10:50:49,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2022-10-17 10:50:49,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253 states and 289 transitions. [2022-10-17 10:50:49,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:49,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 253 states and 289 transitions. [2022-10-17 10:50:49,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states and 289 transitions. [2022-10-17 10:50:49,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 147. [2022-10-17 10:50:49,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.08843537414966) internal successors, (160), 146 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:49,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 160 transitions. [2022-10-17 10:50:49,410 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 160 transitions. [2022-10-17 10:50:49,413 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2022-10-17 10:50:49,414 INFO L428 stractBuchiCegarLoop]: Abstraction has 147 states and 160 transitions. [2022-10-17 10:50:49,414 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:50:49,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 160 transitions. [2022-10-17 10:50:49,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:49,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:49,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:49,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [45, 45, 10, 10, 10, 10, 10, 1, 1, 1, 1] [2022-10-17 10:50:49,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:50:49,424 INFO L748 eck$LassoCheckResult]: Stem: 4593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4594#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 4601#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4602#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4603#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4737#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4736#L17-4 foo_#res#1 := foo_~i~0#1; 4735#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4734#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4605#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4606#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4591#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4592#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4604#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4685#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4608#L17-4 foo_#res#1 := foo_~i~0#1; 4607#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4598#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4599#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4733#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4732#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4731#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4730#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4729#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4728#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4727#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4726#L17-4 foo_#res#1 := foo_~i~0#1; 4725#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4724#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4723#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4722#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4721#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4720#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4719#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4718#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4717#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4716#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4715#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4714#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4713#L17-4 foo_#res#1 := foo_~i~0#1; 4712#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4711#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4710#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4709#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4708#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4707#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4706#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4705#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4704#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4703#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4702#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4701#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4700#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4699#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4698#L17-4 foo_#res#1 := foo_~i~0#1; 4697#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4696#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4695#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4694#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4693#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4692#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4691#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4690#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4689#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4688#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4687#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4686#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4684#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4683#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4682#L17-4 foo_#res#1 := foo_~i~0#1; 4681#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4680#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4679#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4678#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4677#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4676#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4675#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4674#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4673#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4672#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4671#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4670#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4669#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4668#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4667#L17-4 foo_#res#1 := foo_~i~0#1; 4666#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4665#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4664#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4663#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4662#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4661#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4660#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4659#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4658#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4657#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4656#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4655#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4654#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4653#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4652#L17-4 foo_#res#1 := foo_~i~0#1; 4651#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4650#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4649#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4648#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4647#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4646#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4645#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4644#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4643#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4642#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4641#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4640#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4639#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4638#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4617#L17-4 foo_#res#1 := foo_~i~0#1; 4637#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4636#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4635#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4610#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4634#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4633#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4632#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4631#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4630#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4629#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4628#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4627#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4626#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4625#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4624#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4623#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4622#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4621#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4620#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4619#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4618#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4616#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4615#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4614#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4613#L17-4 foo_#res#1 := foo_~i~0#1; 4612#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4611#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4609#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 4600#L26-4 main_~i~1#1 := 0; 4595#L29-3 [2022-10-17 10:50:49,424 INFO L750 eck$LassoCheckResult]: Loop: 4595#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 4596#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 4597#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4595#L29-3 [2022-10-17 10:50:49,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:49,433 INFO L85 PathProgramCache]: Analyzing trace with hash -1269033687, now seen corresponding path program 4 times [2022-10-17 10:50:49,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:49,433 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538265295] [2022-10-17 10:50:49,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:49,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:49,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:50,407 INFO L134 CoverageAnalysis]: Checked inductivity of 2665 backedges. 1576 proven. 98 refuted. 0 times theorem prover too weak. 991 trivial. 0 not checked. [2022-10-17 10:50:50,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:50,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538265295] [2022-10-17 10:50:50,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538265295] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:50,408 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [5780897] [2022-10-17 10:50:50,408 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:50:50,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:50,409 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:50,411 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:50,434 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-10-17 10:50:50,697 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:50:50,697 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:50:50,703 INFO L263 TraceCheckSpWp]: Trace formula consists of 858 conjuncts, 15 conjunts are in the unsatisfiable core [2022-10-17 10:50:50,708 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:50:50,983 INFO L134 CoverageAnalysis]: Checked inductivity of 2665 backedges. 1644 proven. 220 refuted. 0 times theorem prover too weak. 801 trivial. 0 not checked. [2022-10-17 10:50:50,984 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:50:51,276 INFO L134 CoverageAnalysis]: Checked inductivity of 2665 backedges. 1644 proven. 220 refuted. 0 times theorem prover too weak. 801 trivial. 0 not checked. [2022-10-17 10:50:51,276 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [5780897] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:50:51,277 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:50:51,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14, 14] total 32 [2022-10-17 10:50:51,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849919490] [2022-10-17 10:50:51,277 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:50:51,278 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:50:51,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:51,279 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 4 times [2022-10-17 10:50:51,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:51,279 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273437210] [2022-10-17 10:50:51,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:51,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:51,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:51,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:50:51,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:50:51,286 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:50:51,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:50:51,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-10-17 10:50:51,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=188, Invalid=804, Unknown=0, NotChecked=0, Total=992 [2022-10-17 10:50:51,327 INFO L87 Difference]: Start difference. First operand 147 states and 160 transitions. cyclomatic complexity: 21 Second operand has 32 states, 32 states have (on average 3.1875) internal successors, (102), 32 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:52,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:50:52,543 INFO L93 Difference]: Finished difference Result 197 states and 211 transitions. [2022-10-17 10:50:52,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 197 states and 211 transitions. [2022-10-17 10:50:52,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:52,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 197 states to 197 states and 211 transitions. [2022-10-17 10:50:52,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-10-17 10:50:52,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-10-17 10:50:52,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 211 transitions. [2022-10-17 10:50:52,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:50:52,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 211 transitions. [2022-10-17 10:50:52,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 211 transitions. [2022-10-17 10:50:52,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 163. [2022-10-17 10:50:52,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.0797546012269938) internal successors, (176), 162 states have internal predecessors, (176), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:50:52,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 176 transitions. [2022-10-17 10:50:52,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163 states and 176 transitions. [2022-10-17 10:50:52,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2022-10-17 10:50:52,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 163 states and 176 transitions. [2022-10-17 10:50:52,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:50:52,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 176 transitions. [2022-10-17 10:50:52,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:50:52,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:50:52,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:50:52,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [49, 49, 10, 10, 10, 10, 10, 1, 1, 1, 1] [2022-10-17 10:50:52,562 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:50:52,563 INFO L748 eck$LassoCheckResult]: Stem: 5887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 5892#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5893#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5894#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6043#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 6041#L17-4 foo_#res#1 := foo_~i~0#1; 6040#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5889#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5890#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5895#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5882#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5883#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6044#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6042#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5898#L17-4 foo_#res#1 := foo_~i~0#1; 5896#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5897#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6039#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6038#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6037#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6036#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6035#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6034#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6033#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6032#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 6031#L17-4 foo_#res#1 := foo_~i~0#1; 6030#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6029#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6028#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6027#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6026#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6025#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6024#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6023#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6022#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6021#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6019#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6016#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 6014#L17-4 foo_#res#1 := foo_~i~0#1; 6012#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6010#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6008#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 6006#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6005#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6004#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6003#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6002#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6001#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6000#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5999#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5998#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5997#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5996#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5995#L17-4 foo_#res#1 := foo_~i~0#1; 5994#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5993#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5992#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5991#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5990#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5989#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5988#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5987#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5986#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5985#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5984#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5983#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5982#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5981#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5980#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5979#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5978#L17-4 foo_#res#1 := foo_~i~0#1; 5977#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5976#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5975#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5974#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5973#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5972#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5971#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5970#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5969#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5968#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5967#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5966#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5965#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5964#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5963#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5962#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5961#L17-4 foo_#res#1 := foo_~i~0#1; 5960#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5959#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5958#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5957#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5956#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5955#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5954#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5953#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5952#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5951#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5950#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5949#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5948#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5947#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5946#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5945#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5944#L17-4 foo_#res#1 := foo_~i~0#1; 5943#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5942#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5941#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5940#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5939#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5938#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5937#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5936#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5935#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5934#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5933#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5932#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5931#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5930#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5929#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5928#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5907#L17-4 foo_#res#1 := foo_~i~0#1; 5927#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5926#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5925#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5900#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5924#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5923#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5922#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5921#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5920#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5919#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5918#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5917#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5916#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5915#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5914#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5913#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5912#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5911#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5910#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5909#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5908#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5906#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 && foo_~i~0#1 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5905#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5904#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5903#L17-4 foo_#res#1 := foo_~i~0#1; 5902#L20 main_#t~ret3#1 := foo_#res#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5901#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5899#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 5891#L26-4 main_~i~1#1 := 0; 5884#L29-3 [2022-10-17 10:50:52,563 INFO L750 eck$LassoCheckResult]: Loop: 5884#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 5885#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 5886#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5884#L29-3 [2022-10-17 10:50:52,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:50:52,564 INFO L85 PathProgramCache]: Analyzing trace with hash 1333863593, now seen corresponding path program 5 times [2022-10-17 10:50:52,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:50:52,564 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154290672] [2022-10-17 10:50:52,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:50:52,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:50:52,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:50:53,724 INFO L134 CoverageAnalysis]: Checked inductivity of 3077 backedges. 1833 proven. 137 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2022-10-17 10:50:53,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:50:53,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154290672] [2022-10-17 10:50:53,724 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154290672] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:50:53,724 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1542045680] [2022-10-17 10:50:53,724 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:50:53,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:50:53,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:50:53,731 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:50:53,750 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7cbcce90-2e61-4b51-a0b9-e71209254134/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process