./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:13:12,415 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:13:12,417 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:13:12,456 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:13:12,457 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:13:12,458 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:13:12,460 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:13:12,463 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:13:12,465 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:13:12,467 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:13:12,468 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:13:12,470 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:13:12,471 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:13:12,472 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:13:12,474 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:13:12,475 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:13:12,476 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:13:12,477 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:13:12,480 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:13:12,483 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:13:12,485 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:13:12,486 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:13:12,488 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:13:12,489 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:13:12,494 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:13:12,495 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:13:12,495 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:13:12,497 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:13:12,497 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:13:12,498 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:13:12,499 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:13:12,500 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:13:12,501 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:13:12,502 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:13:12,503 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:13:12,505 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:13:12,506 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:13:12,507 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:13:12,508 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:13:12,509 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:13:12,510 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:13:12,511 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-64bit-Automizer_Default.epf [2022-10-17 10:13:12,553 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:13:12,555 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:13:12,555 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:13:12,555 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:13:12,557 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:13:12,557 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:13:12,557 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:13:12,557 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:13:12,558 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:13:12,558 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:13:12,559 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:13:12,559 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:13:12,559 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:13:12,560 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:13:12,560 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:13:12,560 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:13:12,560 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:13:12,561 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:13:12,561 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:13:12,561 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:13:12,561 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:13:12,561 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:13:12,562 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:13:12,562 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:13:12,562 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:13:12,562 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:13:12,563 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:13:12,563 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:13:12,564 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:13:12,564 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2022-10-17 10:13:12,922 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:13:12,954 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:13:12,958 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:13:12,960 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:13:12,961 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:13:12,963 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2022-10-17 10:13:13,058 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/data/6b7a88340/630358e09ae54ce0bbd78b9ef0153314/FLAG6bef910fa [2022-10-17 10:13:13,627 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:13:13,627 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2022-10-17 10:13:13,633 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/data/6b7a88340/630358e09ae54ce0bbd78b9ef0153314/FLAG6bef910fa [2022-10-17 10:13:14,008 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/data/6b7a88340/630358e09ae54ce0bbd78b9ef0153314 [2022-10-17 10:13:14,013 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:13:14,015 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:13:14,025 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:13:14,025 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:13:14,029 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:13:14,030 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,031 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b25a33a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14, skipping insertion in model container [2022-10-17 10:13:14,031 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,047 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:13:14,062 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:13:14,243 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:13:14,246 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:13:14,255 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:13:14,264 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:13:14,264 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14 WrapperNode [2022-10-17 10:13:14,265 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:13:14,265 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:13:14,266 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:13:14,266 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:13:14,280 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,284 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,298 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 18 [2022-10-17 10:13:14,298 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:13:14,299 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:13:14,299 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:13:14,299 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:13:14,308 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,308 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,308 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,309 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,310 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,313 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,314 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,314 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,315 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:13:14,316 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:13:14,316 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:13:14,316 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:13:14,317 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (1/1) ... [2022-10-17 10:13:14,323 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:14,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:14,362 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:14,378 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:13:14,422 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:13:14,422 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:13:14,492 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:13:14,494 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:13:14,562 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:13:14,569 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:13:14,569 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-10-17 10:13:14,571 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:13:14 BoogieIcfgContainer [2022-10-17 10:13:14,571 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:13:14,572 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:13:14,572 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:13:14,579 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:13:14,580 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:13:14,580 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:13:14" (1/3) ... [2022-10-17 10:13:14,581 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5396d2f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:13:14, skipping insertion in model container [2022-10-17 10:13:14,581 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:13:14,581 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:13:14" (2/3) ... [2022-10-17 10:13:14,581 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5396d2f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:13:14, skipping insertion in model container [2022-10-17 10:13:14,581 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:13:14,581 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:13:14" (3/3) ... [2022-10-17 10:13:14,583 INFO L332 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2022-10-17 10:13:14,633 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:13:14,633 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:13:14,633 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:13:14,633 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:13:14,633 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:13:14,634 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:13:14,634 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:13:14,634 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:13:14,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:14,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:13:14,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:14,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:14,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:13:14,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:14,663 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:13:14,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:14,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:13:14,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:14,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:14,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:13:14,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:14,673 INFO L748 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2022-10-17 10:13:14,674 INFO L750 eck$LassoCheckResult]: Loop: 3#L12-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 9#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2022-10-17 10:13:14,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:14,680 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:13:14,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:14,691 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740562635] [2022-10-17 10:13:14,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:14,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:14,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:14,768 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:14,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:14,788 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:14,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:14,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 1 times [2022-10-17 10:13:14,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:14,792 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874766169] [2022-10-17 10:13:14,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:14,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:14,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:14,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:14,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:14,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:14,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:14,811 INFO L85 PathProgramCache]: Analyzing trace with hash 925806, now seen corresponding path program 1 times [2022-10-17 10:13:14,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:14,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089189815] [2022-10-17 10:13:14,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:14,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:14,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:14,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:14,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:14,912 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089189815] [2022-10-17 10:13:14,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089189815] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:13:14,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:13:14,913 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:13:14,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843346303] [2022-10-17 10:13:14,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:13:14,987 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:15,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:13:15,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:13:15,023 INFO L87 Difference]: Start difference. First operand has 9 states, 8 states have (on average 1.5) internal successors, (12), 8 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:15,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:15,053 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2022-10-17 10:13:15,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 19 transitions. [2022-10-17 10:13:15,056 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:15,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 8 states and 11 transitions. [2022-10-17 10:13:15,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-10-17 10:13:15,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-10-17 10:13:15,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 11 transitions. [2022-10-17 10:13:15,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:13:15,062 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2022-10-17 10:13:15,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 11 transitions. [2022-10-17 10:13:15,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2022-10-17 10:13:15,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.375) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:15,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 11 transitions. [2022-10-17 10:13:15,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8 states and 11 transitions. [2022-10-17 10:13:15,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:13:15,094 INFO L428 stractBuchiCegarLoop]: Abstraction has 8 states and 11 transitions. [2022-10-17 10:13:15,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:13:15,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 11 transitions. [2022-10-17 10:13:15,095 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:15,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:15,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:15,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:13:15,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:13:15,097 INFO L748 eck$LassoCheckResult]: Stem: 39#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 40#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 41#L12-1 [2022-10-17 10:13:15,097 INFO L750 eck$LassoCheckResult]: Loop: 41#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 42#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 43#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 41#L12-1 [2022-10-17 10:13:15,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:15,098 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2022-10-17 10:13:15,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:15,099 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030015997] [2022-10-17 10:13:15,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:15,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:15,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:15,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,108 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:15,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:15,109 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 1 times [2022-10-17 10:13:15,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:15,110 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212580417] [2022-10-17 10:13:15,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:15,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:15,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:15,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:15,129 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:15,129 INFO L85 PathProgramCache]: Analyzing trace with hash 28699757, now seen corresponding path program 1 times [2022-10-17 10:13:15,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:15,130 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [142295899] [2022-10-17 10:13:15,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:15,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:15,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,139 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:15,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:15,147 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:15,233 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:15,234 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:15,234 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:15,234 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:15,234 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:13:15,234 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,234 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:15,234 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:15,235 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2022-10-17 10:13:15,235 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:15,235 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:15,257 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,275 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,284 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,414 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:15,415 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:13:15,417 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,419 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,428 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:15,429 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:15,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 10:13:15,459 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:15,459 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_1=1} Honda state: {v_rep~unnamed0~0~true_1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:15,505 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:15,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,507 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 10:13:15,517 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:15,517 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:15,543 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:15,543 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_1=0} Honda state: {v_rep~unnamed0~0~false_1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:15,580 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:15,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,582 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,583 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,592 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:15,593 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:15,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:13:15,647 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:15,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,648 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,649 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,655 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:13:15,655 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:15,688 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:13:15,732 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:13:15,735 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:15,735 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:15,735 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:15,736 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:15,736 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:15,736 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:13:15,736 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,736 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:15,736 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:15,737 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2022-10-17 10:13:15,737 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:15,737 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:15,739 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,747 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,756 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:15,858 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:15,864 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:13:15,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,868 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:13:15,877 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:15,887 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:15,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:15,887 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:15,888 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:15,893 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:15,893 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:15,908 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:15,945 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:15,946 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:15,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:15,948 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:15,956 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:15,965 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:15,965 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:15,965 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:15,966 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:15,969 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:15,969 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:15,974 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:13:16,001 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:16,037 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:16,037 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,037 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,038 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:13:16,043 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:16,051 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:16,051 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:13:16,051 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:16,051 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:16,052 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:16,054 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:13:16,054 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:13:16,064 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:13:16,070 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2022-10-17 10:13:16,070 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2022-10-17 10:13:16,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,072 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,077 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,081 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:13:16,081 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:13:16,081 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:13:16,082 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2022-10-17 10:13:16,104 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 10:13:16,120 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:16,125 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:13:16,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:16,153 INFO L263 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:16,154 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:16,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:16,166 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:13:16,166 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:16,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:16,196 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:13:16,198 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:16,236 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 8 states and 11 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 11 states and 15 transitions. Complement of second has 5 states. [2022-10-17 10:13:16,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:16,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:16,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 5 transitions. [2022-10-17 10:13:16,240 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 3 letters. [2022-10-17 10:13:16,241 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:16,241 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 5 letters. Loop has 3 letters. [2022-10-17 10:13:16,241 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:16,241 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 5 transitions. Stem has 2 letters. Loop has 6 letters. [2022-10-17 10:13:16,242 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:16,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 15 transitions. [2022-10-17 10:13:16,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:13:16,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 15 transitions. [2022-10-17 10:13:16,244 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:13:16,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-10-17 10:13:16,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 15 transitions. [2022-10-17 10:13:16,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:16,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2022-10-17 10:13:16,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 15 transitions. [2022-10-17 10:13:16,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2022-10-17 10:13:16,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:16,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2022-10-17 10:13:16,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2022-10-17 10:13:16,247 INFO L428 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2022-10-17 10:13:16,247 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:13:16,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2022-10-17 10:13:16,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2022-10-17 10:13:16,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:16,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:16,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-10-17 10:13:16,249 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:16,249 INFO L748 eck$LassoCheckResult]: Stem: 97#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 98#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 99#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 93#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 95#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 90#L12-1 [2022-10-17 10:13:16,249 INFO L750 eck$LassoCheckResult]: Loop: 90#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 91#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 90#L12-1 [2022-10-17 10:13:16,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,250 INFO L85 PathProgramCache]: Analyzing trace with hash 28699755, now seen corresponding path program 1 times [2022-10-17 10:13:16,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,250 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004529179] [2022-10-17 10:13:16,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,257 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:16,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,263 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:16,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 2 times [2022-10-17 10:13:16,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,264 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950656313] [2022-10-17 10:13:16,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,269 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:16,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:16,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1810661142, now seen corresponding path program 1 times [2022-10-17 10:13:16,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2121897388] [2022-10-17 10:13:16,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:16,367 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:16,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:16,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2121897388] [2022-10-17 10:13:16,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2121897388] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:16,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [420636136] [2022-10-17 10:13:16,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:16,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,370 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-10-17 10:13:16,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:16,417 INFO L263 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:13:16,418 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:16,494 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:16,494 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:16,557 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:16,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [420636136] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:16,558 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:16,558 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-10-17 10:13:16,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016104738] [2022-10-17 10:13:16,559 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:16,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:16,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:13:16,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:13:16,586 INFO L87 Difference]: Start difference. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 7 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:16,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:16,644 INFO L93 Difference]: Finished difference Result 23 states and 28 transitions. [2022-10-17 10:13:16,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 28 transitions. [2022-10-17 10:13:16,646 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:16,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 28 transitions. [2022-10-17 10:13:16,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-10-17 10:13:16,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2022-10-17 10:13:16,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 28 transitions. [2022-10-17 10:13:16,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:16,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2022-10-17 10:13:16,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 28 transitions. [2022-10-17 10:13:16,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2022-10-17 10:13:16,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 22 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:16,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 28 transitions. [2022-10-17 10:13:16,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 28 transitions. [2022-10-17 10:13:16,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:13:16,653 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 28 transitions. [2022-10-17 10:13:16,654 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:13:16,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 28 transitions. [2022-10-17 10:13:16,655 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:16,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:16,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:16,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 1, 1, 1] [2022-10-17 10:13:16,657 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:13:16,657 INFO L748 eck$LassoCheckResult]: Stem: 182#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 184#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 177#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 185#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 175#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 179#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 188#L12-1 [2022-10-17 10:13:16,657 INFO L750 eck$LassoCheckResult]: Loop: 188#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 188#L12-1 [2022-10-17 10:13:16,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,658 INFO L85 PathProgramCache]: Analyzing trace with hash -1805445589, now seen corresponding path program 1 times [2022-10-17 10:13:16,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279474885] [2022-10-17 10:13:16,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,669 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:16,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,679 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:16,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,680 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 2 times [2022-10-17 10:13:16,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,681 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919576155] [2022-10-17 10:13:16,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,686 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:16,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,691 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:16,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:16,692 INFO L85 PathProgramCache]: Analyzing trace with hash -154083067, now seen corresponding path program 2 times [2022-10-17 10:13:16,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:16,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [925758756] [2022-10-17 10:13:16,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:16,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:16,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,706 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:16,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:16,717 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:16,778 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:16,778 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:16,778 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:16,778 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:16,778 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:13:16,778 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,778 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:16,779 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:16,779 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2022-10-17 10:13:16,779 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:16,779 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:16,780 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:16,784 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:16,798 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:16,867 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:16,867 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:13:16,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,869 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,875 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:16,875 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:16,892 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-10-17 10:13:16,902 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:16,902 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:16,929 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:16,930 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,930 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,931 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,933 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-10-17 10:13:16,934 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:16,934 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:16,965 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:16,965 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:16,984 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2022-10-17 10:13:16,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:16,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:16,990 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:16,991 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-10-17 10:13:16,992 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:16,992 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:17,039 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,039 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,039 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,040 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,041 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-10-17 10:13:17,043 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:13:17,043 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:17,122 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:13:17,128 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,129 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:17,129 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:17,129 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:17,129 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:17,129 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:13:17,129 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,129 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:17,129 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:17,129 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2022-10-17 10:13:17,129 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:17,129 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:17,131 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,137 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,140 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,223 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:17,223 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:13:17,224 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,228 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,237 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:17,248 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:17,248 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:17,248 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:17,248 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:17,255 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:17,256 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:17,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2022-10-17 10:13:17,276 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:17,319 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,319 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,320 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,321 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,329 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:17,339 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:17,339 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:17,339 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:17,339 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:17,348 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:17,348 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:17,353 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2022-10-17 10:13:17,364 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:17,407 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,409 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,415 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:17,436 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:17,436 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:13:17,436 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:17,436 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:17,437 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:17,438 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:13:17,438 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:13:17,453 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:13:17,453 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2022-10-17 10:13:17,459 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2022-10-17 10:13:17,459 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2022-10-17 10:13:17,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,462 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2022-10-17 10:13:17,492 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:13:17,492 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:13:17,492 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:13:17,492 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2022-10-17 10:13:17,531 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,533 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:13:17,552 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:17,564 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:17,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:17,585 INFO L263 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:17,586 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:17,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:17,629 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:13:17,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:17,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:17,662 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:13:17,663 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:17,695 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 23 states and 28 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 50 transitions. Complement of second has 5 states. [2022-10-17 10:13:17,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:17,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:17,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2022-10-17 10:13:17,700 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 3 letters. [2022-10-17 10:13:17,701 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:17,702 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2022-10-17 10:13:17,702 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:17,702 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 11 letters. Loop has 6 letters. [2022-10-17 10:13:17,703 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:17,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 50 transitions. [2022-10-17 10:13:17,711 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:17,714 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 38 states and 44 transitions. [2022-10-17 10:13:17,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-10-17 10:13:17,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2022-10-17 10:13:17,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 44 transitions. [2022-10-17 10:13:17,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:17,717 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 44 transitions. [2022-10-17 10:13:17,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 44 transitions. [2022-10-17 10:13:17,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 34. [2022-10-17 10:13:17,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:17,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2022-10-17 10:13:17,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2022-10-17 10:13:17,726 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2022-10-17 10:13:17,726 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:13:17,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2022-10-17 10:13:17,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2022-10-17 10:13:17,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:17,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:17,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 1, 1, 1] [2022-10-17 10:13:17,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:13:17,733 INFO L748 eck$LassoCheckResult]: Stem: 311#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 313#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 307#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 305#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 322#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 304#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 309#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 335#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 333#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 325#L12-1 [2022-10-17 10:13:17,734 INFO L750 eck$LassoCheckResult]: Loop: 325#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 323#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 325#L12-1 [2022-10-17 10:13:17,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:17,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1972849857, now seen corresponding path program 3 times [2022-10-17 10:13:17,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:17,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785489670] [2022-10-17 10:13:17,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:17,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:17,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,754 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:17,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,781 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:17,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:17,782 INFO L85 PathProgramCache]: Analyzing trace with hash 40815, now seen corresponding path program 3 times [2022-10-17 10:13:17,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:17,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1374995891] [2022-10-17 10:13:17,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:17,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:17,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,787 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:17,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,796 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:17,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:17,799 INFO L85 PathProgramCache]: Analyzing trace with hash 837622447, now seen corresponding path program 4 times [2022-10-17 10:13:17,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:17,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381796639] [2022-10-17 10:13:17,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:17,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:17,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,823 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:17,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:17,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:17,873 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:17,873 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:17,874 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:17,874 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:17,874 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:13:17,874 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,874 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:17,874 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:17,874 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2022-10-17 10:13:17,874 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:17,875 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:17,876 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,879 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,882 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:17,943 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:17,944 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:13:17,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:17,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:17,945 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:17,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2022-10-17 10:13:17,956 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:17,957 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:17,980 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:17,980 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:18,013 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,014 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,016 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,027 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:18,027 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:18,045 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2022-10-17 10:13:18,056 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:13:18,056 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_5=0} Honda state: {v_rep~unnamed0~0~false_5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:13:18,089 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,090 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,090 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,091 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,095 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2022-10-17 10:13:18,096 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:18,096 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:18,131 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,132 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,132 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,133 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,136 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2022-10-17 10:13:18,136 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:13:18,136 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:18,202 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:13:18,204 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,204 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:18,204 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:18,205 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:18,205 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:18,205 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:13:18,205 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,205 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:18,205 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:18,205 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2022-10-17 10:13:18,205 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:18,205 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:18,206 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:18,212 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:18,215 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:18,288 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:18,288 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:13:18,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,288 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,289 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,297 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:18,307 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:18,307 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:18,307 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:18,307 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:18,310 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:18,310 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:18,315 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2022-10-17 10:13:18,327 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:18,349 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,352 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2022-10-17 10:13:18,358 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:18,366 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:18,366 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:18,366 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:18,366 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:18,369 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:13:18,369 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:13:18,395 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:13:18,416 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,416 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,416 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,418 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2022-10-17 10:13:18,419 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:18,438 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:18,438 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:13:18,438 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:18,438 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:18,438 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:18,441 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:13:18,441 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:13:18,443 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:13:18,466 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2022-10-17 10:13:18,466 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2022-10-17 10:13:18,467 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:18,467 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:18,468 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:18,469 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2022-10-17 10:13:18,469 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:13:18,470 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:13:18,470 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:13:18,470 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2022-10-17 10:13:18,489 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:18,490 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:13:18,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:18,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,529 INFO L263 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,530 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,559 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,560 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:18,597 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:13:18,598 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,611 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2022-10-17 10:13:18,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:18,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2022-10-17 10:13:18,613 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2022-10-17 10:13:18,613 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:18,613 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:13:18,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:18,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,648 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,679 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,679 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:18,716 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:13:18,716 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,739 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 51 transitions. Complement of second has 5 states. [2022-10-17 10:13:18,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:18,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 9 transitions. [2022-10-17 10:13:18,747 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 9 transitions. Stem has 14 letters. Loop has 3 letters. [2022-10-17 10:13:18,747 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:18,747 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:13:18,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:18,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,778 INFO L263 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,780 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:18,829 WARN L261 TraceCheckSpWp]: Trace formula consists of 8 conjuncts, 5 conjunts are in the unsatisfiable core [2022-10-17 10:13:18,829 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:18,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:18,849 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:13:18,849 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,872 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 34 states and 40 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 69 transitions. Complement of second has 4 states. [2022-10-17 10:13:18,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:18,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.3333333333333335) internal successors, (10), 3 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2022-10-17 10:13:18,877 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 3 letters. [2022-10-17 10:13:18,877 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:18,877 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 17 letters. Loop has 3 letters. [2022-10-17 10:13:18,878 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:18,878 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 14 letters. Loop has 6 letters. [2022-10-17 10:13:18,879 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:18,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 69 transitions. [2022-10-17 10:13:18,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2022-10-17 10:13:18,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 47 states and 58 transitions. [2022-10-17 10:13:18,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2022-10-17 10:13:18,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2022-10-17 10:13:18,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 58 transitions. [2022-10-17 10:13:18,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:18,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47 states and 58 transitions. [2022-10-17 10:13:18,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 58 transitions. [2022-10-17 10:13:18,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 31. [2022-10-17 10:13:18,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.2903225806451613) internal successors, (40), 30 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:18,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 40 transitions. [2022-10-17 10:13:18,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 40 transitions. [2022-10-17 10:13:18,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 31 states and 40 transitions. [2022-10-17 10:13:18,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:13:18,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 40 transitions. [2022-10-17 10:13:18,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2022-10-17 10:13:18,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:18,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:18,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 3, 2, 1, 1] [2022-10-17 10:13:18,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1] [2022-10-17 10:13:18,902 INFO L748 eck$LassoCheckResult]: Stem: 673#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 674#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 675#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 667#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 694#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 664#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 669#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 670#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 676#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 672#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 692#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 686#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 685#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 684#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 682#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 680#L12-1 [2022-10-17 10:13:18,902 INFO L750 eck$LassoCheckResult]: Loop: 680#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 681#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 690#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 688#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 689#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 687#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 680#L12-1 [2022-10-17 10:13:18,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:18,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1031341869, now seen corresponding path program 5 times [2022-10-17 10:13:18,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:18,903 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144207117] [2022-10-17 10:13:18,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:18,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:18,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:19,063 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:19,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:19,083 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144207117] [2022-10-17 10:13:19,084 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144207117] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:19,084 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2105777837] [2022-10-17 10:13:19,084 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:13:19,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:19,085 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:19,086 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:19,103 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-10-17 10:13:19,133 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2022-10-17 10:13:19,134 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:19,134 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:13:19,135 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:19,147 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:19,195 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:19,247 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:19,248 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:19,311 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:19,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2105777837] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:19,312 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:19,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2022-10-17 10:13:19,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97749096] [2022-10-17 10:13:19,315 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:19,316 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:19,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:19,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1215871107, now seen corresponding path program 1 times [2022-10-17 10:13:19,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:19,317 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177088733] [2022-10-17 10:13:19,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:19,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:19,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:19,334 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:19,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:19,343 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:19,413 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:19,413 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:19,413 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:19,413 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:19,413 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:13:19,414 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,414 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:19,414 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:19,414 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2022-10-17 10:13:19,414 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:19,414 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:19,415 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,438 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,442 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,507 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:19,508 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:13:19,508 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,508 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:19,509 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:19,513 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:19,513 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:19,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2022-10-17 10:13:19,586 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:19,586 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,586 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:19,587 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:19,589 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:13:19,589 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:19,593 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2022-10-17 10:13:19,744 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:13:19,748 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2022-10-17 10:13:19,748 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:19,748 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:19,749 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:19,749 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:19,749 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:13:19,749 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,749 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:19,749 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:19,749 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2022-10-17 10:13:19,749 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:19,749 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:19,750 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,768 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,773 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:19,840 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:19,840 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:13:19,840 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:19,844 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:19,846 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:19,855 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:19,855 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:13:19,856 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:19,856 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:19,856 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:19,857 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:13:19,857 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:13:19,861 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2022-10-17 10:13:19,868 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:13:19,881 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-10-17 10:13:19,882 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2022-10-17 10:13:19,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:19,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:19,883 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:19,885 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:13:19,885 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:13:19,885 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:13:19,885 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2022-10-17 10:13:19,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2022-10-17 10:13:19,923 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:19,924 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:13:19,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:19,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:19,951 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:19,952 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:19,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:19,989 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:13:19,990 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,041 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:20,041 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 10:13:20,041 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,081 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 57 states and 67 transitions. Complement of second has 7 states. [2022-10-17 10:13:20,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:20,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2022-10-17 10:13:20,087 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 17 letters. Loop has 6 letters. [2022-10-17 10:13:20,088 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,089 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:13:20,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:20,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,117 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,118 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,154 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,155 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,213 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:20,214 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 10:13:20,214 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,269 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 59 states and 70 transitions. Complement of second has 9 states. [2022-10-17 10:13:20,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 3 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:20,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 12 transitions. [2022-10-17 10:13:20,274 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 12 transitions. Stem has 17 letters. Loop has 6 letters. [2022-10-17 10:13:20,274 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,276 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:13:20,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:20,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,304 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,305 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,338 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,338 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,391 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:20,392 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 10:13:20,392 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,426 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 73 states and 94 transitions. Complement of second has 6 states. [2022-10-17 10:13:20,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:20,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 16 transitions. [2022-10-17 10:13:20,430 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 16 transitions. Stem has 17 letters. Loop has 6 letters. [2022-10-17 10:13:20,431 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,431 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2022-10-17 10:13:20,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:20,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,457 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,463 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,490 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:13:20,496 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:20,548 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:20,549 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and with honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 10:13:20,549 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,605 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 31 states and 40 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 75 states and 94 transitions. Complement of second has 10 states. [2022-10-17 10:13:20,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 6 states 1 stem states 4 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:20,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 20 transitions. [2022-10-17 10:13:20,607 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 17 letters. Loop has 6 letters. [2022-10-17 10:13:20,609 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,609 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 23 letters. Loop has 6 letters. [2022-10-17 10:13:20,613 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,613 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 20 transitions. Stem has 17 letters. Loop has 12 letters. [2022-10-17 10:13:20,614 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:20,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 94 transitions. [2022-10-17 10:13:20,620 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 21 [2022-10-17 10:13:20,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 53 states and 69 transitions. [2022-10-17 10:13:20,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2022-10-17 10:13:20,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2022-10-17 10:13:20,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 69 transitions. [2022-10-17 10:13:20,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:20,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 69 transitions. [2022-10-17 10:13:20,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 69 transitions. [2022-10-17 10:13:20,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 41. [2022-10-17 10:13:20,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.3170731707317074) internal successors, (54), 40 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 54 transitions. [2022-10-17 10:13:20,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 54 transitions. [2022-10-17 10:13:20,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:20,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:13:20,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:13:20,635 INFO L87 Difference]: Start difference. First operand 41 states and 54 transitions. Second operand has 13 states, 13 states have (on average 3.076923076923077) internal successors, (40), 13 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:20,737 INFO L93 Difference]: Finished difference Result 77 states and 90 transitions. [2022-10-17 10:13:20,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 90 transitions. [2022-10-17 10:13:20,743 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2022-10-17 10:13:20,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 61 states and 74 transitions. [2022-10-17 10:13:20,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2022-10-17 10:13:20,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2022-10-17 10:13:20,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 74 transitions. [2022-10-17 10:13:20,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:20,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61 states and 74 transitions. [2022-10-17 10:13:20,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 74 transitions. [2022-10-17 10:13:20,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 58. [2022-10-17 10:13:20,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.2241379310344827) internal successors, (71), 57 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:20,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 71 transitions. [2022-10-17 10:13:20,749 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 71 transitions. [2022-10-17 10:13:20,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-10-17 10:13:20,750 INFO L428 stractBuchiCegarLoop]: Abstraction has 58 states and 71 transitions. [2022-10-17 10:13:20,751 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:13:20,751 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 71 transitions. [2022-10-17 10:13:20,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2022-10-17 10:13:20,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:20,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:20,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 9, 2, 1, 1] [2022-10-17 10:13:20,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 2, 1] [2022-10-17 10:13:20,754 INFO L748 eck$LassoCheckResult]: Stem: 1527#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 1528#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1552#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1550#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1547#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1524#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1579#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1578#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1576#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1575#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1574#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1573#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1572#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1571#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1569#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1566#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1559#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1558#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1557#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1555#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1539#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1540#L12 [2022-10-17 10:13:20,754 INFO L750 eck$LassoCheckResult]: Loop: 1540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1551#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1536#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1555#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1539#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1540#L12 [2022-10-17 10:13:20,754 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:20,754 INFO L85 PathProgramCache]: Analyzing trace with hash -566648130, now seen corresponding path program 6 times [2022-10-17 10:13:20,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:20,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240062140] [2022-10-17 10:13:20,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:20,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:20,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:20,854 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:21,104 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2022-10-17 10:13:21,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:21,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240062140] [2022-10-17 10:13:21,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240062140] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:21,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [5888720] [2022-10-17 10:13:21,105 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-10-17 10:13:21,105 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:21,106 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:21,107 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:21,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-10-17 10:13:21,150 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2022-10-17 10:13:21,151 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:21,152 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 10 conjunts are in the unsatisfiable core [2022-10-17 10:13:21,154 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:21,313 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2022-10-17 10:13:21,314 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:21,476 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 80 proven. 84 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2022-10-17 10:13:21,476 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [5888720] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:21,477 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:21,477 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2022-10-17 10:13:21,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808081969] [2022-10-17 10:13:21,477 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:21,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:21,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:21,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1423235079, now seen corresponding path program 2 times [2022-10-17 10:13:21,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:21,479 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991427128] [2022-10-17 10:13:21,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:21,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:21,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:21,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:21,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:21,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:21,564 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:21,564 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:21,564 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:21,564 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:21,564 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:13:21,565 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:21,565 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:21,565 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:21,565 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2022-10-17 10:13:21,565 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:21,565 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:21,567 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:21,576 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:21,580 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:21,637 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:21,638 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:13:21,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:21,638 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:21,639 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:21,649 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:13:21,649 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:21,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2022-10-17 10:13:21,715 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:21,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:21,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:21,717 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:21,721 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:13:21,721 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:13:21,739 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2022-10-17 10:13:21,937 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:13:21,945 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:21,945 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:13:21,945 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:13:21,945 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:13:21,945 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:13:21,945 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:13:21,945 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:21,946 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:13:21,946 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:13:21,946 INFO L133 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration7_Loop [2022-10-17 10:13:21,946 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:13:21,946 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:13:21,947 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:21,956 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:21,960 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:13:22,005 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:13:22,006 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:13:22,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:22,006 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:22,007 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:22,017 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:13:22,027 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:13:22,027 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:13:22,027 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:13:22,027 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:13:22,027 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:13:22,030 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:13:22,030 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:13:22,033 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2022-10-17 10:13:22,040 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:13:22,054 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-10-17 10:13:22,054 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2022-10-17 10:13:22,054 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:13:22,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:22,057 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:13:22,059 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:13:22,059 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:13:22,059 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:13:22,059 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2022-10-17 10:13:22,077 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2022-10-17 10:13:22,098 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:22,099 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:13:22,110 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:22,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:22,134 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:13:22,146 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:22,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:22,196 INFO L263 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 7 conjunts are in the unsatisfiable core [2022-10-17 10:13:22,197 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:22,260 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:13:22,261 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 4 loop predicates [2022-10-17 10:13:22,261 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 58 states and 71 transitions. cyclomatic complexity: 17 Second operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:22,294 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 58 states and 71 transitions. cyclomatic complexity: 17. Second operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 120 states and 152 transitions. Complement of second has 6 states. [2022-10-17 10:13:22,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:13:22,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.6666666666666665) internal successors, (16), 6 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:22,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 11 transitions. [2022-10-17 10:13:22,296 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 36 letters. Loop has 9 letters. [2022-10-17 10:13:22,296 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:22,296 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 45 letters. Loop has 9 letters. [2022-10-17 10:13:22,297 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:22,297 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 11 transitions. Stem has 36 letters. Loop has 18 letters. [2022-10-17 10:13:22,297 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:13:22,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 152 transitions. [2022-10-17 10:13:22,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:22,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 82 states and 105 transitions. [2022-10-17 10:13:22,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:13:22,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-10-17 10:13:22,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 105 transitions. [2022-10-17 10:13:22,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:22,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 105 transitions. [2022-10-17 10:13:22,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 105 transitions. [2022-10-17 10:13:22,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 66. [2022-10-17 10:13:22,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.2727272727272727) internal successors, (84), 65 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:22,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 84 transitions. [2022-10-17 10:13:22,323 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 84 transitions. [2022-10-17 10:13:22,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:22,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-10-17 10:13:22,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2022-10-17 10:13:22,326 INFO L87 Difference]: Start difference. First operand 66 states and 84 transitions. Second operand has 25 states, 25 states have (on average 3.04) internal successors, (76), 25 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:22,450 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2022-10-17 10:13:22,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:22,591 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2022-10-17 10:13:22,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154 states and 172 transitions. [2022-10-17 10:13:22,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:22,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154 states to 118 states and 136 transitions. [2022-10-17 10:13:22,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-10-17 10:13:22,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-10-17 10:13:22,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 136 transitions. [2022-10-17 10:13:22,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:22,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 136 transitions. [2022-10-17 10:13:22,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 136 transitions. [2022-10-17 10:13:22,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 114. [2022-10-17 10:13:22,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114 states, 114 states have (on average 1.1578947368421053) internal successors, (132), 113 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:22,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 132 transitions. [2022-10-17 10:13:22,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114 states and 132 transitions. [2022-10-17 10:13:22,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-10-17 10:13:22,616 INFO L428 stractBuchiCegarLoop]: Abstraction has 114 states and 132 transitions. [2022-10-17 10:13:22,616 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:13:22,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114 states and 132 transitions. [2022-10-17 10:13:22,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:22,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:22,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:22,621 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 21, 2, 1, 1] [2022-10-17 10:13:22,621 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:22,621 INFO L748 eck$LassoCheckResult]: Stem: 2330#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 2331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2334#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2335#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2329#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2327#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2328#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2436#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2435#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2433#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2431#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2430#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2427#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2426#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2425#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2424#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2421#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2418#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2415#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2414#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2413#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2412#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2409#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2406#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2403#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2385#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2383#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2382#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2380#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2381#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2398#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2397#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2395#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2393#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2392#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2362#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2346#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2344#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2326#L12 [2022-10-17 10:13:22,621 INFO L750 eck$LassoCheckResult]: Loop: 2326#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2325#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2326#L12 [2022-10-17 10:13:22,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:22,622 INFO L85 PathProgramCache]: Analyzing trace with hash 1262893886, now seen corresponding path program 7 times [2022-10-17 10:13:22,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:22,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190717139] [2022-10-17 10:13:22,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:22,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:22,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:23,139 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2022-10-17 10:13:23,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:23,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190717139] [2022-10-17 10:13:23,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190717139] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:23,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1965628471] [2022-10-17 10:13:23,139 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-10-17 10:13:23,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:23,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:23,144 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:23,164 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2022-10-17 10:13:23,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:23,194 INFO L263 TraceCheckSpWp]: Trace formula consists of 151 conjuncts, 18 conjunts are in the unsatisfiable core [2022-10-17 10:13:23,198 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:23,612 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2022-10-17 10:13:23,612 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:23,935 INFO L134 CoverageAnalysis]: Checked inductivity of 782 backedges. 352 proven. 360 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2022-10-17 10:13:23,935 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1965628471] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:23,935 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:23,935 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2022-10-17 10:13:23,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320375380] [2022-10-17 10:13:23,936 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:23,936 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:23,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:23,937 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 3 times [2022-10-17 10:13:23,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:23,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578578558] [2022-10-17 10:13:23,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:23,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:23,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:23,943 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:23,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:23,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:23,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:23,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-10-17 10:13:23,966 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2022-10-17 10:13:23,966 INFO L87 Difference]: Start difference. First operand 114 states and 132 transitions. cyclomatic complexity: 24 Second operand has 38 states, 38 states have (on average 3.0526315789473686) internal successors, (116), 38 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:24,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:24,210 INFO L93 Difference]: Finished difference Result 231 states and 249 transitions. [2022-10-17 10:13:24,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231 states and 249 transitions. [2022-10-17 10:13:24,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:24,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231 states to 181 states and 199 transitions. [2022-10-17 10:13:24,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-10-17 10:13:24,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-10-17 10:13:24,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181 states and 199 transitions. [2022-10-17 10:13:24,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:24,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 181 states and 199 transitions. [2022-10-17 10:13:24,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states and 199 transitions. [2022-10-17 10:13:24,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 177. [2022-10-17 10:13:24,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177 states, 177 states have (on average 1.1016949152542372) internal successors, (195), 176 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:24,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 195 transitions. [2022-10-17 10:13:24,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 177 states and 195 transitions. [2022-10-17 10:13:24,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-10-17 10:13:24,225 INFO L428 stractBuchiCegarLoop]: Abstraction has 177 states and 195 transitions. [2022-10-17 10:13:24,226 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:13:24,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177 states and 195 transitions. [2022-10-17 10:13:24,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:24,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:24,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:24,231 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 34, 2, 1, 1] [2022-10-17 10:13:24,231 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:24,232 INFO L748 eck$LassoCheckResult]: Stem: 3150#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 3151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3153#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3154#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3321#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3149#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3148#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3320#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3319#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3318#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3317#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3316#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3315#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3314#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3313#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3312#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3311#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3310#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3309#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3307#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3306#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3305#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3304#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3301#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3299#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3298#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3296#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3295#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3294#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3293#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3292#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3291#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3290#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3289#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3288#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3287#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3286#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3284#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3283#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3282#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3281#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3280#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3279#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3278#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3277#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3276#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3274#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3273#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3272#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3271#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3230#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3231#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3229#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3228#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3227#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3226#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3225#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3270#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3267#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3266#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3265#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3264#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3261#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3258#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3257#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3256#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3255#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3254#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3253#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3252#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3249#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3246#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3245#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3244#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3243#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3242#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3241#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3240#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3237#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3234#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3182#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3169#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3164#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3146#L12 [2022-10-17 10:13:24,232 INFO L750 eck$LassoCheckResult]: Loop: 3146#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3145#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3146#L12 [2022-10-17 10:13:24,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:24,233 INFO L85 PathProgramCache]: Analyzing trace with hash -1287581916, now seen corresponding path program 8 times [2022-10-17 10:13:24,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:24,234 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598570484] [2022-10-17 10:13:24,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:24,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:24,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:24,266 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:24,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:24,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:24,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:24,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1654, now seen corresponding path program 4 times [2022-10-17 10:13:24,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:24,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685680500] [2022-10-17 10:13:24,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:24,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:24,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:24,302 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:24,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:24,305 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:24,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:24,305 INFO L85 PathProgramCache]: Analyzing trace with hash -415639335, now seen corresponding path program 1 times [2022-10-17 10:13:24,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:24,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975002324] [2022-10-17 10:13:24,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:24,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:24,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:24,433 INFO L134 CoverageAnalysis]: Checked inductivity of 1999 backedges. 179 proven. 0 refuted. 0 times theorem prover too weak. 1820 trivial. 0 not checked. [2022-10-17 10:13:24,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:24,434 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975002324] [2022-10-17 10:13:24,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975002324] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:13:24,434 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:13:24,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 10:13:24,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398090139] [2022-10-17 10:13:24,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:13:24,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:24,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:13:24,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:13:24,449 INFO L87 Difference]: Start difference. First operand 177 states and 195 transitions. cyclomatic complexity: 24 Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:24,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:24,470 INFO L93 Difference]: Finished difference Result 184 states and 199 transitions. [2022-10-17 10:13:24,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 199 transitions. [2022-10-17 10:13:24,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:24,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 135 states and 146 transitions. [2022-10-17 10:13:24,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:13:24,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:13:24,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 135 states and 146 transitions. [2022-10-17 10:13:24,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:24,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 135 states and 146 transitions. [2022-10-17 10:13:24,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states and 146 transitions. [2022-10-17 10:13:24,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 127. [2022-10-17 10:13:24,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.078740157480315) internal successors, (137), 126 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:24,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 137 transitions. [2022-10-17 10:13:24,491 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 137 transitions. [2022-10-17 10:13:24,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:13:24,492 INFO L428 stractBuchiCegarLoop]: Abstraction has 127 states and 137 transitions. [2022-10-17 10:13:24,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:13:24,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 137 transitions. [2022-10-17 10:13:24,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:24,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:24,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:24,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 37, 34, 3, 1, 1, 1] [2022-10-17 10:13:24,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:24,502 INFO L748 eck$LassoCheckResult]: Stem: 3520#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 3521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3515#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3516#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3522#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3518#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3523#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3641#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3640#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3639#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3638#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3637#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3636#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3635#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3634#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3633#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3632#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3631#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3630#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3629#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3628#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3627#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3626#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3625#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3624#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3623#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3622#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3621#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3620#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3619#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3618#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3617#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3616#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3615#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3614#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3613#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3612#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3611#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3610#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3609#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3608#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3607#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3606#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3605#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3604#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3603#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3602#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3601#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3600#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3599#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3598#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3597#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3596#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3595#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3594#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3593#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3592#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3591#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3590#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3588#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3589#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3587#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3586#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3585#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3584#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3583#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3582#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3581#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3580#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3579#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3578#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3576#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3575#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3574#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3573#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3572#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3571#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3569#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3568#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3567#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3566#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3565#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3564#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3563#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3561#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3560#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3557#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3556#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3555#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3554#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3553#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3552#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3551#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3550#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3549#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3548#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3547#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3546#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3545#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3544#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3534#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3532#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3528#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3526#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3525#L12-1 [2022-10-17 10:13:24,507 INFO L750 eck$LassoCheckResult]: Loop: 3525#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3524#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3525#L12-1 [2022-10-17 10:13:24,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:24,507 INFO L85 PathProgramCache]: Analyzing trace with hash 2325394, now seen corresponding path program 2 times [2022-10-17 10:13:24,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:24,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876251943] [2022-10-17 10:13:24,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:24,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:24,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:25,130 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2022-10-17 10:13:25,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:25,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876251943] [2022-10-17 10:13:25,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876251943] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:25,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [87394316] [2022-10-17 10:13:25,131 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:13:25,131 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:25,131 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:25,132 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:25,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-10-17 10:13:25,203 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:13:25,204 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:25,206 INFO L263 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 20 conjunts are in the unsatisfiable core [2022-10-17 10:13:25,209 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:25,718 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2022-10-17 10:13:25,718 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:26,166 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 74 proven. 1428 refuted. 0 times theorem prover too weak. 570 trivial. 0 not checked. [2022-10-17 10:13:26,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [87394316] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:26,167 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:26,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2022-10-17 10:13:26,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695399592] [2022-10-17 10:13:26,167 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:26,168 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:26,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:26,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 5 times [2022-10-17 10:13:26,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:26,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101628377] [2022-10-17 10:13:26,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:26,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:26,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:26,171 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:26,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:26,172 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:26,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:26,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-10-17 10:13:26,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2022-10-17 10:13:26,189 INFO L87 Difference]: Start difference. First operand 127 states and 137 transitions. cyclomatic complexity: 15 Second operand has 40 states, 40 states have (on average 3.075) internal successors, (123), 40 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:27,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:27,334 INFO L93 Difference]: Finished difference Result 395 states and 407 transitions. [2022-10-17 10:13:27,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 395 states and 407 transitions. [2022-10-17 10:13:27,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:27,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 395 states to 249 states and 261 transitions. [2022-10-17 10:13:27,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2022-10-17 10:13:27,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2022-10-17 10:13:27,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 261 transitions. [2022-10-17 10:13:27,343 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:27,343 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 261 transitions. [2022-10-17 10:13:27,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 261 transitions. [2022-10-17 10:13:27,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 241. [2022-10-17 10:13:27,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 241 states, 241 states have (on average 1.049792531120332) internal successors, (253), 240 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:27,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 253 transitions. [2022-10-17 10:13:27,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 241 states and 253 transitions. [2022-10-17 10:13:27,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2022-10-17 10:13:27,358 INFO L428 stractBuchiCegarLoop]: Abstraction has 241 states and 253 transitions. [2022-10-17 10:13:27,358 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:13:27,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 241 states and 253 transitions. [2022-10-17 10:13:27,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:27,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:27,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:27,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 75, 70, 5, 1, 1, 1] [2022-10-17 10:13:27,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:27,378 INFO L748 eck$LassoCheckResult]: Stem: 4845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 4846#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 4847#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4848#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4844#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4842#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4843#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4849#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5080#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5077#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5074#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5073#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5072#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5071#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5070#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5069#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5068#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5065#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5063#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5062#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5061#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5060#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5059#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5058#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5057#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5056#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5053#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5050#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5049#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5048#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5047#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5046#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5045#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5044#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5043#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5041#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5039#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5038#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5037#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5036#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5035#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5034#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5033#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5032#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5031#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5030#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5029#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5027#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5028#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5026#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5025#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5024#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5023#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5022#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5021#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5020#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5017#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5014#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5013#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5012#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5011#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5010#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5009#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5008#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5007#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5005#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5003#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5002#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5001#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5000#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4999#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4998#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4997#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4996#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4994#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4993#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4991#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4990#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4989#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4988#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4987#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4986#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4985#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4984#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4982#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4981#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4979#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4978#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4977#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4976#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4975#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4974#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4973#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4972#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4970#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4971#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4969#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4968#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4967#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4966#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4965#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4964#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4963#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4961#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4960#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4957#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4956#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4955#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4954#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4953#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4952#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4951#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4950#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4949#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4948#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4945#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4943#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4942#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4941#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4940#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4939#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4938#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4937#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4936#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4935#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4934#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4933#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4932#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4931#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4930#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4929#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4928#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4927#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4926#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4925#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4924#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4923#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4922#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4921#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4920#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4919#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4918#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4916#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4917#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4915#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4914#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4913#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4912#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4911#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4910#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4909#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4908#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4907#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4906#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4905#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4904#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4903#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4902#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4901#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4900#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4898#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4897#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4896#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4895#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4894#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4893#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4892#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4891#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4890#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4889#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4888#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4887#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4886#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4885#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4884#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4883#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4882#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4881#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4880#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4879#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4878#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4877#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4876#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4875#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4873#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4872#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4871#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4870#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4869#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4867#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4863#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4859#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 4860#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4857#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4852#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 4855#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4850#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4840#L12-1 [2022-10-17 10:13:27,378 INFO L750 eck$LassoCheckResult]: Loop: 4840#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 4841#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 4840#L12-1 [2022-10-17 10:13:27,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:27,379 INFO L85 PathProgramCache]: Analyzing trace with hash 1383057750, now seen corresponding path program 3 times [2022-10-17 10:13:27,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:27,380 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539798176] [2022-10-17 10:13:27,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:27,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:27,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:27,895 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 0 proven. 6525 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2022-10-17 10:13:27,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:27,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539798176] [2022-10-17 10:13:27,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539798176] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:27,896 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1936301454] [2022-10-17 10:13:27,896 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:13:27,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:27,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:27,901 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:27,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-10-17 10:13:27,955 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-10-17 10:13:27,955 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:27,956 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 7 conjunts are in the unsatisfiable core [2022-10-17 10:13:27,959 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:28,016 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2022-10-17 10:13:28,016 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:28,074 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 730 proven. 5 refuted. 0 times theorem prover too weak. 7740 trivial. 0 not checked. [2022-10-17 10:13:28,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1936301454] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:28,075 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:28,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 5, 5] total 11 [2022-10-17 10:13:28,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1627404799] [2022-10-17 10:13:28,076 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:28,077 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:28,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:28,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 6 times [2022-10-17 10:13:28,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:28,078 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1507815515] [2022-10-17 10:13:28,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:28,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:28,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:28,080 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:28,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:28,081 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:28,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:28,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-10-17 10:13:28,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=93, Unknown=0, NotChecked=0, Total=132 [2022-10-17 10:13:28,096 INFO L87 Difference]: Start difference. First operand 241 states and 253 transitions. cyclomatic complexity: 19 Second operand has 12 states, 11 states have (on average 3.5454545454545454) internal successors, (39), 12 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:28,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:28,395 INFO L93 Difference]: Finished difference Result 278 states and 297 transitions. [2022-10-17 10:13:28,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 278 states and 297 transitions. [2022-10-17 10:13:28,397 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:28,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 278 states to 273 states and 292 transitions. [2022-10-17 10:13:28,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2022-10-17 10:13:28,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2022-10-17 10:13:28,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 292 transitions. [2022-10-17 10:13:28,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:28,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 273 states and 292 transitions. [2022-10-17 10:13:28,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 292 transitions. [2022-10-17 10:13:28,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 257. [2022-10-17 10:13:28,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 257 states, 257 states have (on average 1.0583657587548638) internal successors, (272), 256 states have internal predecessors, (272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:28,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 272 transitions. [2022-10-17 10:13:28,407 INFO L240 hiAutomatonCegarLoop]: Abstraction has 257 states and 272 transitions. [2022-10-17 10:13:28,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:13:28,408 INFO L428 stractBuchiCegarLoop]: Abstraction has 257 states and 272 transitions. [2022-10-17 10:13:28,408 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:13:28,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 257 states and 272 transitions. [2022-10-17 10:13:28,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:28,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:28,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:28,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [78, 77, 71, 6, 1, 1, 1] [2022-10-17 10:13:28,414 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:28,414 INFO L748 eck$LassoCheckResult]: Stem: 6786#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 6787#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 6780#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6781#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6788#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7036#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6789#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6785#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6783#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6784#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7035#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7034#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7033#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7032#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7031#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7030#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7029#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7028#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7027#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7026#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7025#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7024#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7023#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7022#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7021#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7020#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7019#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7018#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7017#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7016#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7015#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7014#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7013#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7012#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7011#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7010#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7009#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7008#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7007#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7006#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7005#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7004#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7003#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7002#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7001#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7000#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6999#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6998#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6997#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6996#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6995#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6994#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6993#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6992#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6991#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6990#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6989#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6988#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6987#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6986#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6984#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6985#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6983#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6982#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6981#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6980#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6979#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6978#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6977#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6975#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6974#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6973#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6972#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6971#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6970#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6969#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6968#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6967#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6966#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6965#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6964#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6963#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6962#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6961#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6960#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6959#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6958#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6957#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6956#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6954#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6953#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6952#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6951#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6950#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6949#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6948#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6947#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6946#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6945#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6944#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6943#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6942#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6941#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6940#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6939#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6938#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6937#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6936#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6935#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6934#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6933#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6932#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6931#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6930#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6929#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6927#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6928#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6926#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6925#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6924#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6923#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6922#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6921#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6920#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6919#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6918#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6917#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6916#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6915#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6914#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6913#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6912#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6911#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6910#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6909#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6908#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6907#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6906#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6905#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6904#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6903#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6902#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6901#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6900#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6899#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6898#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6897#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6896#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6895#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6894#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6893#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6892#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6891#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6890#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6889#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6888#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6887#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6886#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6885#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6884#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6882#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6881#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6879#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6878#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6877#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6876#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6875#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6873#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6872#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6870#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6869#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6867#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6866#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6865#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6863#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6861#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6860#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6859#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6858#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6857#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6856#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6855#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6854#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6853#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6852#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6851#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6849#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6848#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6847#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6845#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6844#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6843#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6842#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6841#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6839#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6838#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6837#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6836#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6835#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6834#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6833#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6832#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6831#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6830#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6829#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6828#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6827#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6826#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6825#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6824#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6822#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6823#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6821#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6820#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6814#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6815#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6817#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6801#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 6802#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6798#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6794#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 6795#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6792#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6791#L12-1 [2022-10-17 10:13:28,415 INFO L750 eck$LassoCheckResult]: Loop: 6791#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 6790#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 6791#L12-1 [2022-10-17 10:13:28,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:28,415 INFO L85 PathProgramCache]: Analyzing trace with hash -2031563884, now seen corresponding path program 4 times [2022-10-17 10:13:28,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:28,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291441762] [2022-10-17 10:13:28,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:28,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:28,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:28,859 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 154 proven. 6828 refuted. 0 times theorem prover too weak. 1950 trivial. 0 not checked. [2022-10-17 10:13:28,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:28,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291441762] [2022-10-17 10:13:28,862 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291441762] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:28,863 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1336745516] [2022-10-17 10:13:28,863 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:13:28,863 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:28,863 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:28,865 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:28,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2022-10-17 10:13:28,967 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:13:28,968 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:28,970 INFO L263 TraceCheckSpWp]: Trace formula consists of 489 conjuncts, 28 conjunts are in the unsatisfiable core [2022-10-17 10:13:28,975 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:29,705 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2022-10-17 10:13:29,705 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:30,442 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 914 proven. 6638 refuted. 0 times theorem prover too weak. 1380 trivial. 0 not checked. [2022-10-17 10:13:30,442 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1336745516] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:30,442 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:30,443 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 28, 28] total 50 [2022-10-17 10:13:30,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988691086] [2022-10-17 10:13:30,443 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:30,444 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:30,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:30,445 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 7 times [2022-10-17 10:13:30,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:30,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220942049] [2022-10-17 10:13:30,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:30,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:30,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:30,451 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:30,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:30,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:30,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:30,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-10-17 10:13:30,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=683, Invalid=1767, Unknown=0, NotChecked=0, Total=2450 [2022-10-17 10:13:30,471 INFO L87 Difference]: Start difference. First operand 257 states and 272 transitions. cyclomatic complexity: 23 Second operand has 50 states, 50 states have (on average 3.18) internal successors, (159), 50 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:33,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:33,661 INFO L93 Difference]: Finished difference Result 1240 states and 1416 transitions. [2022-10-17 10:13:33,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1240 states and 1416 transitions. [2022-10-17 10:13:33,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:33,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1240 states to 987 states and 1104 transitions. [2022-10-17 10:13:33,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2022-10-17 10:13:33,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2022-10-17 10:13:33,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 987 states and 1104 transitions. [2022-10-17 10:13:33,682 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:33,683 INFO L218 hiAutomatonCegarLoop]: Abstraction has 987 states and 1104 transitions. [2022-10-17 10:13:33,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 987 states and 1104 transitions. [2022-10-17 10:13:33,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 987 to 691. [2022-10-17 10:13:33,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 691 states, 691 states have (on average 1.1128798842257597) internal successors, (769), 690 states have internal predecessors, (769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:33,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 691 states to 691 states and 769 transitions. [2022-10-17 10:13:33,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 691 states and 769 transitions. [2022-10-17 10:13:33,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 149 states. [2022-10-17 10:13:33,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 691 states and 769 transitions. [2022-10-17 10:13:33,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:13:33,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 691 states and 769 transitions. [2022-10-17 10:13:33,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:33,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:33,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:33,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 83, 11, 1, 1, 1] [2022-10-17 10:13:33,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:33,770 INFO L748 eck$LassoCheckResult]: Stem: 10156#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 10157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 10152#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10153#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10159#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10571#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10570#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10569#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10568#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10566#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10565#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10564#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10563#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10562#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10559#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10558#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10556#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10553#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10552#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10551#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10550#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10549#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10548#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10547#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10544#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10541#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10540#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10539#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10538#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10535#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10533#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10532#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10530#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10529#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10528#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10527#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10526#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10523#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10521#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10520#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10517#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10514#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10515#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10511#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10510#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10506#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10505#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10494#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10493#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10492#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10490#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10489#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10488#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10487#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10486#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10484#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10483#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10482#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10481#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10480#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10477#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10476#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10474#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10472#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10455#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10454#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10453#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10452#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10451#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10450#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10449#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10447#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10446#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10445#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10444#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10443#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10442#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10441#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10440#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10438#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10437#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10436#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10435#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10434#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10433#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10431#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10430#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10429#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10428#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10426#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10425#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10424#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10423#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10422#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10421#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10420#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10419#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10418#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10417#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10416#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10415#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10414#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10413#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10412#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10411#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10410#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10409#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10408#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10407#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10406#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10405#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10404#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10403#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10402#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10400#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10398#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10397#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10395#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10394#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10391#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10390#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10389#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10388#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10387#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10386#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10385#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10382#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10381#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10370#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10368#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10360#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10358#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10354#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10348#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10346#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10322#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10323#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10340#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10338#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10316#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10314#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10315#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10311#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10303#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10302#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10301#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10300#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10299#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10266#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10263#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10257#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10254#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10252#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10250#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10248#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10247#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10246#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10245#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10227#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10226#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10225#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10222#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10221#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10213#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10212#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10207#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10205#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10206#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10208#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10199#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10197#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10193#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10196#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10194#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10187#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10180#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10175#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10176#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10168#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 10169#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10166#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10163#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 10165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10160#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10161#L12-1 [2022-10-17 10:13:33,771 INFO L750 eck$LassoCheckResult]: Loop: 10161#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10164#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 10161#L12-1 [2022-10-17 10:13:33,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:33,771 INFO L85 PathProgramCache]: Analyzing trace with hash 2005033964, now seen corresponding path program 5 times [2022-10-17 10:13:33,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:33,772 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340519495] [2022-10-17 10:13:33,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:33,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:33,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:35,101 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 5787 proven. 5686 refuted. 0 times theorem prover too weak. 1828 trivial. 0 not checked. [2022-10-17 10:13:35,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:35,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340519495] [2022-10-17 10:13:35,101 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340519495] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:35,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1741444214] [2022-10-17 10:13:35,101 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:13:35,102 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:35,102 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:35,108 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:35,112 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-10-17 10:13:35,321 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 73 check-sat command(s) [2022-10-17 10:13:35,321 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:35,325 INFO L263 TraceCheckSpWp]: Trace formula consists of 455 conjuncts, 25 conjunts are in the unsatisfiable core [2022-10-17 10:13:35,331 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:35,748 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7724 proven. 317 refuted. 0 times theorem prover too weak. 5260 trivial. 0 not checked. [2022-10-17 10:13:35,748 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:36,142 INFO L134 CoverageAnalysis]: Checked inductivity of 13301 backedges. 7724 proven. 317 refuted. 0 times theorem prover too weak. 5260 trivial. 0 not checked. [2022-10-17 10:13:36,142 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1741444214] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:36,142 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:36,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 25, 25] total 44 [2022-10-17 10:13:36,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615554408] [2022-10-17 10:13:36,143 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:36,144 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:36,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:36,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 8 times [2022-10-17 10:13:36,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:36,145 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192823791] [2022-10-17 10:13:36,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:36,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:36,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:36,148 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:36,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:36,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:36,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:36,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-10-17 10:13:36,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=511, Invalid=1381, Unknown=0, NotChecked=0, Total=1892 [2022-10-17 10:13:36,171 INFO L87 Difference]: Start difference. First operand 691 states and 769 transitions. cyclomatic complexity: 85 Second operand has 44 states, 44 states have (on average 3.25) internal successors, (143), 44 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:38,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:13:38,018 INFO L93 Difference]: Finished difference Result 1294 states and 1395 transitions. [2022-10-17 10:13:38,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1294 states and 1395 transitions. [2022-10-17 10:13:38,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:38,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1294 states to 1184 states and 1285 transitions. [2022-10-17 10:13:38,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2022-10-17 10:13:38,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2022-10-17 10:13:38,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1285 transitions. [2022-10-17 10:13:38,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:13:38,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1285 transitions. [2022-10-17 10:13:38,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1285 transitions. [2022-10-17 10:13:38,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 526. [2022-10-17 10:13:38,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 526 states, 526 states have (on average 1.0874524714828897) internal successors, (572), 525 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:13:38,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 572 transitions. [2022-10-17 10:13:38,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 526 states and 572 transitions. [2022-10-17 10:13:38,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-10-17 10:13:38,071 INFO L428 stractBuchiCegarLoop]: Abstraction has 526 states and 572 transitions. [2022-10-17 10:13:38,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:13:38,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 526 states and 572 transitions. [2022-10-17 10:13:38,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2022-10-17 10:13:38,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:13:38,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:13:38,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [131, 130, 115, 15, 1, 1, 1] [2022-10-17 10:13:38,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:13:38,085 INFO L748 eck$LassoCheckResult]: Stem: 14070#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true; 14071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 14066#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14073#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14549#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14548#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14546#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14543#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14541#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14540#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14537#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14536#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14535#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14534#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14533#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14532#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14531#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14529#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14528#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14525#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14524#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14523#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14522#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14521#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14520#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14519#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14518#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14517#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14516#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14515#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14514#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14513#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14512#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14511#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14510#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14507#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14506#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14505#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14504#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14501#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14500#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14499#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14498#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14495#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14492#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14490#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14489#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14488#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14487#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14486#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14484#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14483#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14482#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14481#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14480#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14477#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14476#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14475#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14474#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14472#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14471#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14470#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14469#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14468#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14465#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14464#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14463#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14462#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14459#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14458#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14456#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14454#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14453#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14452#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14451#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14450#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14447#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14445#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14444#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14441#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14438#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14436#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14437#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14435#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14434#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14433#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14432#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14429#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14428#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14426#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14423#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14422#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14421#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14420#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14419#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14418#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14417#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14416#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14415#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14414#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14411#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14409#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14408#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14405#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14402#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14401#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14400#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14399#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14398#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14397#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14396#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14395#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14393#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14392#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14390#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14387#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14386#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14385#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14384#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14381#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14380#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14382#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14589#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14588#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14587#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14586#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14585#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14584#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14583#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14582#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14581#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14580#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14579#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14578#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14576#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14573#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14572#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14571#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14570#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14568#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14567#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14566#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14564#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14563#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14562#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14561#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14347#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14348#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14343#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14342#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14341#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14339#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14560#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14335#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14334#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14333#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14332#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14330#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14329#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14328#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14327#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14321#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14379#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14378#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14375#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14374#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14373#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14372#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14369#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14366#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14363#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14362#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14361#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14360#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14359#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14358#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14357#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14356#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14355#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14354#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14353#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14352#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14351#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14349#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14350#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14074#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14075#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14266#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14265#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14264#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14263#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14238#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14237#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14235#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14234#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14233#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14232#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14229#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14230#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14246#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14224#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14225#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14221#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14220#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14219#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14218#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14216#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14213#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14210#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14201#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14197#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14198#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14194#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14193#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14192#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14190#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14189#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14186#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14185#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14184#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14183#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14182#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14181#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14177#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14175#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14173#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14174#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14170#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14169#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14168#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14165#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14162#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14161#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14160#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14159#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14158#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14157#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14155#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14154#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14152#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14153#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14148#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14147#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14146#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14145#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14144#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14141#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14138#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14137#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14136#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14135#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14118#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14134#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14132#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14130#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14129#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14126#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14125#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14124#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14123#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14122#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14121#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14120#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14106#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14119#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14117#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14115#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14114#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14112#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14111#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14110#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14109#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14108#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14097#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14107#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14105#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14103#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14102#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14101#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14100#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14099#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14086#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14096#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14091#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14092#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14084#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14085#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14082#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14080#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14081#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14078#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14077#L12-1 [2022-10-17 10:13:38,086 INFO L750 eck$LassoCheckResult]: Loop: 14077#L12-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14076#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14077#L12-1 [2022-10-17 10:13:38,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:38,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1703910940, now seen corresponding path program 6 times [2022-10-17 10:13:38,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:38,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [154443082] [2022-10-17 10:13:38,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:38,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:38,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:13:39,510 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 12928 proven. 8663 refuted. 0 times theorem prover too weak. 3824 trivial. 0 not checked. [2022-10-17 10:13:39,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:13:39,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [154443082] [2022-10-17 10:13:39,511 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [154443082] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:13:39,511 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1380496147] [2022-10-17 10:13:39,511 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-10-17 10:13:39,512 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:13:39,512 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:13:39,514 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:13:39,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73d3482d-858b-41d2-9fd3-334498d8c2b1/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-10-17 10:13:39,787 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 81 check-sat command(s) [2022-10-17 10:13:39,787 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:13:39,791 INFO L263 TraceCheckSpWp]: Trace formula consists of 521 conjuncts, 15 conjunts are in the unsatisfiable core [2022-10-17 10:13:39,798 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:13:40,239 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2022-10-17 10:13:40,240 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:13:40,601 INFO L134 CoverageAnalysis]: Checked inductivity of 25415 backedges. 8831 proven. 411 refuted. 0 times theorem prover too weak. 16173 trivial. 0 not checked. [2022-10-17 10:13:40,601 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1380496147] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:13:40,601 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:13:40,602 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14, 14] total 37 [2022-10-17 10:13:40,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903329139] [2022-10-17 10:13:40,602 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:13:40,604 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:13:40,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:13:40,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1324, now seen corresponding path program 9 times [2022-10-17 10:13:40,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:13:40,605 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045412523] [2022-10-17 10:13:40,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:13:40,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:13:40,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:40,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:13:40,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:13:40,610 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:13:40,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:13:40,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-10-17 10:13:40,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=1140, Unknown=0, NotChecked=0, Total=1332 [2022-10-17 10:13:40,630 INFO L87 Difference]: Start difference. First operand 526 states and 572 transitions. cyclomatic complexity: 53 Second operand has 37 states, 37 states have (on average 3.324324324324324) internal successors, (123), 37 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)