./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/bist_cell.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 11:07:32,321 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 11:07:32,323 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 11:07:32,365 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 11:07:32,365 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 11:07:32,367 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 11:07:32,368 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 11:07:32,371 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 11:07:32,373 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 11:07:32,374 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 11:07:32,375 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 11:07:32,377 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 11:07:32,377 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 11:07:32,381 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 11:07:32,383 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 11:07:32,385 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 11:07:32,386 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 11:07:32,387 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 11:07:32,389 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 11:07:32,392 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 11:07:32,394 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 11:07:32,396 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 11:07:32,397 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 11:07:32,398 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 11:07:32,404 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 11:07:32,404 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 11:07:32,405 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 11:07:32,406 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 11:07:32,406 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 11:07:32,407 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 11:07:32,408 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 11:07:32,409 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 11:07:32,410 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 11:07:32,411 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 11:07:32,412 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 11:07:32,412 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 11:07:32,413 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 11:07:32,414 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 11:07:32,414 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 11:07:32,417 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 11:07:32,418 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 11:07:32,420 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 11:07:32,468 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 11:07:32,469 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 11:07:32,469 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 11:07:32,469 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 11:07:32,470 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 11:07:32,471 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 11:07:32,471 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 11:07:32,471 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 11:07:32,471 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 11:07:32,472 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 11:07:32,472 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 11:07:32,472 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 11:07:32,472 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 11:07:32,473 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 11:07:32,473 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 11:07:32,473 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 11:07:32,473 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 11:07:32,474 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 11:07:32,474 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 11:07:32,474 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 11:07:32,474 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 11:07:32,478 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 11:07:32,478 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 11:07:32,479 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 11:07:32,479 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 11:07:32,479 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 11:07:32,479 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 11:07:32,480 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 11:07:32,480 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 11:07:32,481 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 11:07:32,481 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 11:07:32,482 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 11:07:32,482 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2022-10-17 11:07:32,745 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 11:07:32,794 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 11:07:32,796 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 11:07:32,797 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 11:07:32,800 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 11:07:32,801 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/bist_cell.cil.c [2022-10-17 11:07:32,860 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/data/f18ff360b/7fe0719128cd4dafbf774d385fcf958e/FLAG2fff107ab [2022-10-17 11:07:33,292 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 11:07:33,295 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/sv-benchmarks/c/systemc/bist_cell.cil.c [2022-10-17 11:07:33,307 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/data/f18ff360b/7fe0719128cd4dafbf774d385fcf958e/FLAG2fff107ab [2022-10-17 11:07:33,656 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/data/f18ff360b/7fe0719128cd4dafbf774d385fcf958e [2022-10-17 11:07:33,659 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 11:07:33,661 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 11:07:33,662 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 11:07:33,662 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 11:07:33,682 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 11:07:33,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:07:33" (1/1) ... [2022-10-17 11:07:33,684 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@559d762b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:33, skipping insertion in model container [2022-10-17 11:07:33,684 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 11:07:33" (1/1) ... [2022-10-17 11:07:33,691 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 11:07:33,720 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 11:07:33,891 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2022-10-17 11:07:33,945 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:07:33,957 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 11:07:33,968 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/sv-benchmarks/c/systemc/bist_cell.cil.c[639,652] [2022-10-17 11:07:33,993 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 11:07:34,008 INFO L208 MainTranslator]: Completed translation [2022-10-17 11:07:34,009 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34 WrapperNode [2022-10-17 11:07:34,009 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 11:07:34,010 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 11:07:34,011 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 11:07:34,011 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 11:07:34,021 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,030 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,064 INFO L138 Inliner]: procedures = 30, calls = 30, calls flagged for inlining = 25, calls inlined = 31, statements flattened = 344 [2022-10-17 11:07:34,064 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 11:07:34,065 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 11:07:34,065 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 11:07:34,065 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 11:07:34,073 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,074 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,077 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,077 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,086 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,109 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,112 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,114 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,118 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 11:07:34,143 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 11:07:34,143 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 11:07:34,143 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 11:07:34,144 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (1/1) ... [2022-10-17 11:07:34,159 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:34,171 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:34,182 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:34,184 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 11:07:34,216 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 11:07:34,217 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 11:07:34,217 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 11:07:34,217 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 11:07:34,296 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 11:07:34,297 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 11:07:34,771 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 11:07:34,779 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 11:07:34,780 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-10-17 11:07:34,782 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:07:34 BoogieIcfgContainer [2022-10-17 11:07:34,783 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 11:07:34,784 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 11:07:34,798 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 11:07:34,803 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 11:07:34,803 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:07:34,804 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 11:07:33" (1/3) ... [2022-10-17 11:07:34,805 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@353ef309 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:07:34, skipping insertion in model container [2022-10-17 11:07:34,805 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:07:34,805 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 11:07:34" (2/3) ... [2022-10-17 11:07:34,806 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@353ef309 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 11:07:34, skipping insertion in model container [2022-10-17 11:07:34,806 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 11:07:34,806 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:07:34" (3/3) ... [2022-10-17 11:07:34,807 INFO L332 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2022-10-17 11:07:34,867 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 11:07:34,867 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 11:07:34,867 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 11:07:34,867 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 11:07:34,867 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 11:07:34,868 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 11:07:34,868 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 11:07:34,868 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 11:07:34,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:34,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:34,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:34,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:34,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:34,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:34,911 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 11:07:34,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:34,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:34,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:34,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:34,932 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:34,932 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:34,942 INFO L748 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 42#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 17#L490true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76#L212true assume !(1 == ~b0_req_up~0); 124#L212-2true assume !(1 == ~b1_req_up~0); 84#L219-1true assume !(1 == ~d0_req_up~0); 43#L226-1true assume !(1 == ~d1_req_up~0); 66#L233-1true assume !(1 == ~z_req_up~0); 107#L240-1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 117#L255-2true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67#L321true assume !(0 == ~b0_ev~0); 83#L321-2true assume !(0 == ~b1_ev~0); 24#L326-1true assume !(0 == ~d0_ev~0); 27#L331-1true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 8#L336-1true assume !(0 == ~z_ev~0); 122#L341-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 118#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 106#L129true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 57#L130true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 91#L390true assume !(0 != activate_threads_~tmp~1#1); 111#L390-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56#L354true assume !(1 == ~b0_ev~0); 39#L354-2true assume !(1 == ~b1_ev~0); 89#L359-1true assume !(1 == ~d0_ev~0); 41#L364-1true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 47#L369-1true assume !(1 == ~z_ev~0); 95#L374-1true assume { :end_inline_reset_delta_events } true; 34#L432-2true [2022-10-17 11:07:34,950 INFO L750 eck$LassoCheckResult]: Loop: 34#L432-2true assume !false; 70#L433true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 7#L295true assume !true; 48#L311true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85#L212-3true assume !(1 == ~b0_req_up~0); 108#L212-5true assume !(1 == ~b1_req_up~0); 88#L219-3true assume !(1 == ~d0_req_up~0); 4#L226-3true assume !(1 == ~d1_req_up~0); 37#L233-3true assume !(1 == ~z_req_up~0); 16#L240-3true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81#L321-3true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 65#L321-5true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 92#L326-3true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 51#L331-3true assume !(0 == ~d1_ev~0); 11#L336-3true assume 0 == ~z_ev~0;~z_ev~0 := 1; 18#L341-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 114#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 44#L129-1true is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 121#L130-1true activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9#L390-3true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 23#L390-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32#L354-3true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 100#L354-5true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 98#L359-3true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 82#L364-3true assume !(1 == ~d1_ev~0); 80#L369-3true assume 1 == ~z_ev~0;~z_ev~0 := 2; 49#L374-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 72#L268-1true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 119#L275-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 40#L276-1true stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 13#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116#L414true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#L415true start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 73#L449true assume !(0 != start_simulation_~tmp~3#1); 34#L432-2true [2022-10-17 11:07:34,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:34,962 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2022-10-17 11:07:34,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:34,994 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432247154] [2022-10-17 11:07:34,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:34,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:35,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:35,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:35,305 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432247154] [2022-10-17 11:07:35,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432247154] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:35,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:35,307 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:35,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777076460] [2022-10-17 11:07:35,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:35,314 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:35,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:35,319 INFO L85 PathProgramCache]: Analyzing trace with hash 972845291, now seen corresponding path program 1 times [2022-10-17 11:07:35,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:35,321 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560676671] [2022-10-17 11:07:35,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:35,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:35,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:35,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:35,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560676671] [2022-10-17 11:07:35,376 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560676671] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:35,376 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:35,376 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:07:35,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960304876] [2022-10-17 11:07:35,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:35,378 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:35,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:35,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:35,421 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:35,423 INFO L87 Difference]: Start difference. First operand has 125 states, 124 states have (on average 1.5887096774193548) internal successors, (197), 124 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:35,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:35,476 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2022-10-17 11:07:35,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2022-10-17 11:07:35,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:35,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2022-10-17 11:07:35,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:35,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:35,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2022-10-17 11:07:35,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:35,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-10-17 11:07:35,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2022-10-17 11:07:35,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:35,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:35,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2022-10-17 11:07:35,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-10-17 11:07:35,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:35,529 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2022-10-17 11:07:35,530 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 11:07:35,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2022-10-17 11:07:35,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:35,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:35,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:35,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:35,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:35,536 INFO L748 eck$LassoCheckResult]: Stem: 372#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 282#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 283#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 345#L137 assume !(~b0_val~0 != ~b0_val_t~0); 346#L137-2 ~b0_req_up~0 := 0; 340#L145 assume { :end_inline_update_b0 } true; 341#L212-2 assume !(1 == ~b1_req_up~0); 363#L219-1 assume !(1 == ~d0_req_up~0); 264#L226-1 assume !(1 == ~d1_req_up~0); 322#L233-1 assume !(1 == ~z_req_up~0); 350#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 278#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 279#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351#L321 assume !(0 == ~b0_ev~0); 352#L321-2 assume !(0 == ~b1_ev~0); 295#L326-1 assume !(0 == ~d0_ev~0); 296#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 267#L336-1 assume !(0 == ~z_ev~0); 268#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 374#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 288#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 335#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 336#L390 assume !(0 != activate_threads_~tmp~1#1); 365#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 334#L354 assume !(1 == ~b0_ev~0); 315#L354-2 assume !(1 == ~b1_ev~0); 316#L359-1 assume !(1 == ~d0_ev~0); 318#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 319#L369-1 assume !(1 == ~z_ev~0); 324#L374-1 assume { :end_inline_reset_delta_events } true; 307#L432-2 [2022-10-17 11:07:35,536 INFO L750 eck$LassoCheckResult]: Loop: 307#L432-2 assume !false; 308#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 265#L295 assume !false; 266#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 292#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 293#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 258#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 259#L290 assume !(0 != eval_~tmp___0~0#1); 325#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326#L212-3 assume !(1 == ~b0_req_up~0); 354#L212-5 assume !(1 == ~b1_req_up~0); 310#L219-3 assume !(1 == ~d0_req_up~0); 260#L226-3 assume !(1 == ~d1_req_up~0); 261#L233-3 assume !(1 == ~z_req_up~0); 280#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 281#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 347#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 348#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 330#L331-3 assume !(0 == ~d1_ev~0); 274#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 275#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 284#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 300#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 323#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 269#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 270#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 304#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 368#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 362#L364-3 assume !(1 == ~d1_ev~0); 361#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 327#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 328#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 355#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 317#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 276#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 277#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 369#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 356#L449 assume !(0 != start_simulation_~tmp~3#1); 307#L432-2 [2022-10-17 11:07:35,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:35,537 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2022-10-17 11:07:35,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:35,537 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467425521] [2022-10-17 11:07:35,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:35,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:35,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:35,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:35,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467425521] [2022-10-17 11:07:35,639 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467425521] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:35,639 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:35,639 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:35,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338773243] [2022-10-17 11:07:35,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:35,640 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:35,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:35,641 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 1 times [2022-10-17 11:07:35,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:35,642 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314033351] [2022-10-17 11:07:35,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:35,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:35,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:35,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:35,794 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314033351] [2022-10-17 11:07:35,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314033351] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:35,794 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:35,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:35,795 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975636909] [2022-10-17 11:07:35,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:35,795 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:35,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:35,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:35,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:35,797 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:35,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:35,821 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2022-10-17 11:07:35,821 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2022-10-17 11:07:35,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:35,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2022-10-17 11:07:35,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:35,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:35,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2022-10-17 11:07:35,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:35,829 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-10-17 11:07:35,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2022-10-17 11:07:35,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:35,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:35,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2022-10-17 11:07:35,840 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-10-17 11:07:35,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:35,841 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2022-10-17 11:07:35,841 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 11:07:35,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2022-10-17 11:07:35,844 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:35,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:35,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:35,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:35,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:35,847 INFO L748 eck$LassoCheckResult]: Stem: 615#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 525#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 526#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 588#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 589#L137-2 ~b0_req_up~0 := 0; 583#L145 assume { :end_inline_update_b0 } true; 584#L212-2 assume !(1 == ~b1_req_up~0); 606#L219-1 assume !(1 == ~d0_req_up~0); 507#L226-1 assume !(1 == ~d1_req_up~0); 565#L233-1 assume !(1 == ~z_req_up~0); 593#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 521#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 522#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 594#L321 assume !(0 == ~b0_ev~0); 595#L321-2 assume !(0 == ~b1_ev~0); 538#L326-1 assume !(0 == ~d0_ev~0); 539#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 510#L336-1 assume !(0 == ~z_ev~0); 511#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 617#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 531#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 578#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 579#L390 assume !(0 != activate_threads_~tmp~1#1); 608#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 577#L354 assume !(1 == ~b0_ev~0); 558#L354-2 assume !(1 == ~b1_ev~0); 559#L359-1 assume !(1 == ~d0_ev~0); 561#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 562#L369-1 assume !(1 == ~z_ev~0); 567#L374-1 assume { :end_inline_reset_delta_events } true; 550#L432-2 [2022-10-17 11:07:35,847 INFO L750 eck$LassoCheckResult]: Loop: 550#L432-2 assume !false; 551#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 508#L295 assume !false; 509#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 535#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 536#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 501#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 502#L290 assume !(0 != eval_~tmp___0~0#1); 568#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 569#L212-3 assume !(1 == ~b0_req_up~0); 597#L212-5 assume !(1 == ~b1_req_up~0); 553#L219-3 assume !(1 == ~d0_req_up~0); 503#L226-3 assume !(1 == ~d1_req_up~0); 504#L233-3 assume !(1 == ~z_req_up~0); 523#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 524#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 590#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 591#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 573#L331-3 assume !(0 == ~d1_ev~0); 517#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 518#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 527#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 543#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 566#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 512#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 513#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 547#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 605#L364-3 assume !(1 == ~d1_ev~0); 604#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 570#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 571#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 598#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 560#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 519#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 612#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 599#L449 assume !(0 != start_simulation_~tmp~3#1); 550#L432-2 [2022-10-17 11:07:35,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:35,848 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2022-10-17 11:07:35,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:35,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530773] [2022-10-17 11:07:35,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:35,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:35,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:35,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:35,923 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530773] [2022-10-17 11:07:35,924 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530773] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:35,924 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:35,924 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:35,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140939868] [2022-10-17 11:07:35,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:35,925 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:35,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:35,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 2 times [2022-10-17 11:07:35,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:35,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865736120] [2022-10-17 11:07:35,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:35,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:35,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865736120] [2022-10-17 11:07:36,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865736120] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,018 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,019 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:36,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557981009] [2022-10-17 11:07:36,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,019 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:36,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:36,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:36,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:36,020 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:36,055 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2022-10-17 11:07:36,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2022-10-17 11:07:36,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2022-10-17 11:07:36,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:36,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:36,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2022-10-17 11:07:36,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:36,062 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-10-17 11:07:36,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2022-10-17 11:07:36,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:36,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2022-10-17 11:07:36,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-10-17 11:07:36,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:36,077 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2022-10-17 11:07:36,079 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 11:07:36,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2022-10-17 11:07:36,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:36,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:36,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,087 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,087 INFO L748 eck$LassoCheckResult]: Stem: 858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 806#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 768#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 769#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 831#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 832#L137-2 ~b0_req_up~0 := 0; 826#L145 assume { :end_inline_update_b0 } true; 827#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 787#L152 assume !(~b1_val~0 != ~b1_val_t~0); 788#L152-2 ~b1_req_up~0 := 0; 850#L160 assume { :end_inline_update_b1 } true; 849#L219-1 assume !(1 == ~d0_req_up~0); 750#L226-1 assume !(1 == ~d1_req_up~0); 808#L233-1 assume !(1 == ~z_req_up~0); 836#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 764#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 765#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 837#L321 assume !(0 == ~b0_ev~0); 838#L321-2 assume !(0 == ~b1_ev~0); 781#L326-1 assume !(0 == ~d0_ev~0); 782#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 753#L336-1 assume !(0 == ~z_ev~0); 754#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 860#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 774#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 821#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 822#L390 assume !(0 != activate_threads_~tmp~1#1); 851#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 820#L354 assume !(1 == ~b0_ev~0); 801#L354-2 assume !(1 == ~b1_ev~0); 802#L359-1 assume !(1 == ~d0_ev~0); 804#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 805#L369-1 assume !(1 == ~z_ev~0); 810#L374-1 assume { :end_inline_reset_delta_events } true; 793#L432-2 [2022-10-17 11:07:36,087 INFO L750 eck$LassoCheckResult]: Loop: 793#L432-2 assume !false; 794#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 751#L295 assume !false; 752#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 778#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 779#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 744#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 745#L290 assume !(0 != eval_~tmp___0~0#1); 811#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 812#L212-3 assume !(1 == ~b0_req_up~0); 840#L212-5 assume !(1 == ~b1_req_up~0); 796#L219-3 assume !(1 == ~d0_req_up~0); 746#L226-3 assume !(1 == ~d1_req_up~0); 747#L233-3 assume !(1 == ~z_req_up~0); 766#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 767#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 833#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 834#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 816#L331-3 assume !(0 == ~d1_ev~0); 760#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 761#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 770#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 786#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 809#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 755#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 756#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 780#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 790#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 854#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 848#L364-3 assume !(1 == ~d1_ev~0); 847#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 813#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 814#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 841#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 803#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 762#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 763#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 855#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 842#L449 assume !(0 != start_simulation_~tmp~3#1); 793#L432-2 [2022-10-17 11:07:36,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2022-10-17 11:07:36,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516592649] [2022-10-17 11:07:36,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,248 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516592649] [2022-10-17 11:07:36,248 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516592649] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,249 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,249 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 11:07:36,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697379197] [2022-10-17 11:07:36,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,252 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:36,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,252 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 3 times [2022-10-17 11:07:36,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,253 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156542392] [2022-10-17 11:07:36,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,328 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156542392] [2022-10-17 11:07:36,329 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156542392] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,329 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,330 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:36,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518847551] [2022-10-17 11:07:36,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,331 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:36,333 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:36,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:07:36,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:07:36,335 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:36,389 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2022-10-17 11:07:36,391 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2022-10-17 11:07:36,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2022-10-17 11:07:36,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:36,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:36,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2022-10-17 11:07:36,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:36,404 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-10-17 11:07:36,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2022-10-17 11:07:36,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:36,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2022-10-17 11:07:36,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-10-17 11:07:36,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-17 11:07:36,419 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2022-10-17 11:07:36,419 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 11:07:36,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2022-10-17 11:07:36,420 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:36,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:36,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,425 INFO L748 eck$LassoCheckResult]: Stem: 1104#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1052#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1014#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1015#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1077#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1078#L137-2 ~b0_req_up~0 := 0; 1072#L145 assume { :end_inline_update_b0 } true; 1073#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1033#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1034#L152-2 ~b1_req_up~0 := 0; 1096#L160 assume { :end_inline_update_b1 } true; 1095#L219-1 assume !(1 == ~d0_req_up~0); 996#L226-1 assume !(1 == ~d1_req_up~0); 1054#L233-1 assume !(1 == ~z_req_up~0); 1082#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1010#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1011#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1083#L321 assume !(0 == ~b0_ev~0); 1084#L321-2 assume !(0 == ~b1_ev~0); 1027#L326-1 assume !(0 == ~d0_ev~0); 1028#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 999#L336-1 assume !(0 == ~z_ev~0); 1000#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1106#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1020#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1067#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1068#L390 assume !(0 != activate_threads_~tmp~1#1); 1097#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1066#L354 assume !(1 == ~b0_ev~0); 1047#L354-2 assume !(1 == ~b1_ev~0); 1048#L359-1 assume !(1 == ~d0_ev~0); 1050#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1051#L369-1 assume !(1 == ~z_ev~0); 1056#L374-1 assume { :end_inline_reset_delta_events } true; 1039#L432-2 [2022-10-17 11:07:36,426 INFO L750 eck$LassoCheckResult]: Loop: 1039#L432-2 assume !false; 1040#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 997#L295 assume !false; 998#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1024#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1025#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 990#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 991#L290 assume !(0 != eval_~tmp___0~0#1); 1057#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1058#L212-3 assume !(1 == ~b0_req_up~0); 1086#L212-5 assume !(1 == ~b1_req_up~0); 1042#L219-3 assume !(1 == ~d0_req_up~0); 992#L226-3 assume !(1 == ~d1_req_up~0); 993#L233-3 assume !(1 == ~z_req_up~0); 1012#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1013#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1079#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1080#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1062#L331-3 assume !(0 == ~d1_ev~0); 1006#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1007#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1016#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1032#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1055#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1001#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1002#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1026#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1036#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1100#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1094#L364-3 assume !(1 == ~d1_ev~0); 1093#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1059#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1060#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1087#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1049#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1008#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1009#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1101#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1088#L449 assume !(0 != start_simulation_~tmp~3#1); 1039#L432-2 [2022-10-17 11:07:36,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,429 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2022-10-17 11:07:36,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,429 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637742022] [2022-10-17 11:07:36,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,470 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637742022] [2022-10-17 11:07:36,470 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637742022] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,470 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,470 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:36,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280133945] [2022-10-17 11:07:36,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,471 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:36,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,472 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 4 times [2022-10-17 11:07:36,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,473 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282204805] [2022-10-17 11:07:36,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1282204805] [2022-10-17 11:07:36,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1282204805] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:36,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757979080] [2022-10-17 11:07:36,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,536 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:36,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:36,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:36,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:36,537 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:36,551 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2022-10-17 11:07:36,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2022-10-17 11:07:36,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2022-10-17 11:07:36,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:36,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:36,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2022-10-17 11:07:36,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:36,557 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-10-17 11:07:36,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2022-10-17 11:07:36,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:36,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2022-10-17 11:07:36,577 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-10-17 11:07:36,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:36,579 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2022-10-17 11:07:36,580 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 11:07:36,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2022-10-17 11:07:36,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:36,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:36,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,584 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,585 INFO L748 eck$LassoCheckResult]: Stem: 1347#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1257#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1258#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1320#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1321#L137-2 ~b0_req_up~0 := 0; 1315#L145 assume { :end_inline_update_b0 } true; 1316#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1276#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1277#L152-2 ~b1_req_up~0 := 0; 1339#L160 assume { :end_inline_update_b1 } true; 1338#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1260#L167 assume !(~d0_val~0 != ~d0_val_t~0); 1261#L167-2 ~d0_req_up~0 := 0; 1238#L175 assume { :end_inline_update_d0 } true; 1239#L226-1 assume !(1 == ~d1_req_up~0); 1297#L233-1 assume !(1 == ~z_req_up~0); 1325#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1253#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1254#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1326#L321 assume !(0 == ~b0_ev~0); 1327#L321-2 assume !(0 == ~b1_ev~0); 1270#L326-1 assume !(0 == ~d0_ev~0); 1271#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1242#L336-1 assume !(0 == ~z_ev~0); 1243#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1349#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1263#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1310#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1311#L390 assume !(0 != activate_threads_~tmp~1#1); 1340#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L354 assume !(1 == ~b0_ev~0); 1290#L354-2 assume !(1 == ~b1_ev~0); 1291#L359-1 assume !(1 == ~d0_ev~0); 1293#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1294#L369-1 assume !(1 == ~z_ev~0); 1299#L374-1 assume { :end_inline_reset_delta_events } true; 1282#L432-2 [2022-10-17 11:07:36,585 INFO L750 eck$LassoCheckResult]: Loop: 1282#L432-2 assume !false; 1283#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1240#L295 assume !false; 1241#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1267#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1268#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1233#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1234#L290 assume !(0 != eval_~tmp___0~0#1); 1300#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1301#L212-3 assume !(1 == ~b0_req_up~0); 1329#L212-5 assume !(1 == ~b1_req_up~0); 1285#L219-3 assume !(1 == ~d0_req_up~0); 1235#L226-3 assume !(1 == ~d1_req_up~0); 1236#L233-3 assume !(1 == ~z_req_up~0); 1255#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1256#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1322#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1323#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1305#L331-3 assume !(0 == ~d1_ev~0); 1249#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1250#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1259#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1275#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1298#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1244#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1245#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1269#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1279#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1343#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1337#L364-3 assume !(1 == ~d1_ev~0); 1336#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1302#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1303#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1330#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1292#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1251#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1252#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1344#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1331#L449 assume !(0 != start_simulation_~tmp~3#1); 1282#L432-2 [2022-10-17 11:07:36,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,586 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2022-10-17 11:07:36,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,587 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060783833] [2022-10-17 11:07:36,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,690 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060783833] [2022-10-17 11:07:36,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060783833] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,691 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,691 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 11:07:36,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531191342] [2022-10-17 11:07:36,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,691 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:36,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 5 times [2022-10-17 11:07:36,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,692 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670738966] [2022-10-17 11:07:36,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,750 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670738966] [2022-10-17 11:07:36,756 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670738966] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,756 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,756 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:36,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688516390] [2022-10-17 11:07:36,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,757 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:36,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:36,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:07:36,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:07:36,759 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:36,790 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2022-10-17 11:07:36,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2022-10-17 11:07:36,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2022-10-17 11:07:36,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:36,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:36,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2022-10-17 11:07:36,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:36,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-10-17 11:07:36,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2022-10-17 11:07:36,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:36,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2022-10-17 11:07:36,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-10-17 11:07:36,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-17 11:07:36,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2022-10-17 11:07:36,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 11:07:36,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2022-10-17 11:07:36,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:36,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:36,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,815 INFO L748 eck$LassoCheckResult]: Stem: 1593#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1541#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1503#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1504#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1566#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1567#L137-2 ~b0_req_up~0 := 0; 1561#L145 assume { :end_inline_update_b0 } true; 1562#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1522#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1523#L152-2 ~b1_req_up~0 := 0; 1585#L160 assume { :end_inline_update_b1 } true; 1584#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1506#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1507#L167-2 ~d0_req_up~0 := 0; 1484#L175 assume { :end_inline_update_d0 } true; 1485#L226-1 assume !(1 == ~d1_req_up~0); 1543#L233-1 assume !(1 == ~z_req_up~0); 1571#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1499#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1500#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1572#L321 assume !(0 == ~b0_ev~0); 1573#L321-2 assume !(0 == ~b1_ev~0); 1516#L326-1 assume !(0 == ~d0_ev~0); 1517#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1488#L336-1 assume !(0 == ~z_ev~0); 1489#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1595#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1509#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1556#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1557#L390 assume !(0 != activate_threads_~tmp~1#1); 1586#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1555#L354 assume !(1 == ~b0_ev~0); 1536#L354-2 assume !(1 == ~b1_ev~0); 1537#L359-1 assume !(1 == ~d0_ev~0); 1539#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1540#L369-1 assume !(1 == ~z_ev~0); 1545#L374-1 assume { :end_inline_reset_delta_events } true; 1528#L432-2 [2022-10-17 11:07:36,815 INFO L750 eck$LassoCheckResult]: Loop: 1528#L432-2 assume !false; 1529#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1486#L295 assume !false; 1487#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1513#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1514#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1479#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1480#L290 assume !(0 != eval_~tmp___0~0#1); 1546#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1547#L212-3 assume !(1 == ~b0_req_up~0); 1575#L212-5 assume !(1 == ~b1_req_up~0); 1531#L219-3 assume !(1 == ~d0_req_up~0); 1481#L226-3 assume !(1 == ~d1_req_up~0); 1482#L233-3 assume !(1 == ~z_req_up~0); 1501#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1568#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1569#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1551#L331-3 assume !(0 == ~d1_ev~0); 1495#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1496#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1505#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1521#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1544#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1490#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1491#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1515#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1525#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1589#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1583#L364-3 assume !(1 == ~d1_ev~0); 1582#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1548#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1549#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1576#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1538#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1497#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1498#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1590#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1577#L449 assume !(0 != start_simulation_~tmp~3#1); 1528#L432-2 [2022-10-17 11:07:36,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,816 INFO L85 PathProgramCache]: Analyzing trace with hash 2039338604, now seen corresponding path program 1 times [2022-10-17 11:07:36,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537123853] [2022-10-17 11:07:36,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,877 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,877 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537123853] [2022-10-17 11:07:36,878 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537123853] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,878 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,878 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:36,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491029881] [2022-10-17 11:07:36,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,879 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:36,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 6 times [2022-10-17 11:07:36,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917772368] [2022-10-17 11:07:36,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:36,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:36,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:36,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917772368] [2022-10-17 11:07:36,937 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917772368] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:36,937 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:36,937 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:36,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612119243] [2022-10-17 11:07:36,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:36,938 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:36,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:36,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:36,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:36,939 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:36,949 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2022-10-17 11:07:36,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2022-10-17 11:07:36,950 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2022-10-17 11:07:36,952 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2022-10-17 11:07:36,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2022-10-17 11:07:36,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2022-10-17 11:07:36,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:36,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-10-17 11:07:36,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2022-10-17 11:07:36,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2022-10-17 11:07:36,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:36,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2022-10-17 11:07:36,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-10-17 11:07:36,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:36,960 INFO L428 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2022-10-17 11:07:36,960 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 11:07:36,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2022-10-17 11:07:36,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2022-10-17 11:07:36,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:36,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:36,962 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:36,964 INFO L748 eck$LassoCheckResult]: Stem: 1836#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1746#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1747#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1809#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1810#L137-2 ~b0_req_up~0 := 0; 1803#L145 assume { :end_inline_update_b0 } true; 1804#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1765#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1766#L152-2 ~b1_req_up~0 := 0; 1828#L160 assume { :end_inline_update_b1 } true; 1827#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1749#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1750#L167-2 ~d0_req_up~0 := 0; 1727#L175 assume { :end_inline_update_d0 } true; 1728#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1785#L182 assume !(~d1_val~0 != ~d1_val_t~0); 1754#L182-2 ~d1_req_up~0 := 0; 1755#L190 assume { :end_inline_update_d1 } true; 1808#L233-1 assume !(1 == ~z_req_up~0); 1814#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1742#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1743#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L321 assume !(0 == ~b0_ev~0); 1816#L321-2 assume !(0 == ~b1_ev~0); 1759#L326-1 assume !(0 == ~d0_ev~0); 1760#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1731#L336-1 assume !(0 == ~z_ev~0); 1732#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1838#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1752#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1798#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1799#L390 assume !(0 != activate_threads_~tmp~1#1); 1829#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1797#L354 assume !(1 == ~b0_ev~0); 1779#L354-2 assume !(1 == ~b1_ev~0); 1780#L359-1 assume !(1 == ~d0_ev~0); 1782#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1783#L369-1 assume !(1 == ~z_ev~0); 1787#L374-1 assume { :end_inline_reset_delta_events } true; 1771#L432-2 [2022-10-17 11:07:36,964 INFO L750 eck$LassoCheckResult]: Loop: 1771#L432-2 assume !false; 1772#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1729#L295 assume !false; 1730#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1756#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1757#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1722#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1723#L290 assume !(0 != eval_~tmp___0~0#1); 1788#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1789#L212-3 assume !(1 == ~b0_req_up~0); 1818#L212-5 assume !(1 == ~b1_req_up~0); 1774#L219-3 assume !(1 == ~d0_req_up~0); 1724#L226-3 assume !(1 == ~d1_req_up~0); 1725#L233-3 assume !(1 == ~z_req_up~0); 1744#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1745#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1811#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1812#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1793#L331-3 assume !(0 == ~d1_ev~0); 1738#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1739#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1748#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1764#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1786#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1733#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1734#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1758#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1768#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1832#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1826#L364-3 assume !(1 == ~d1_ev~0); 1825#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1790#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1791#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1819#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1781#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1740#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1741#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1833#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1820#L449 assume !(0 != start_simulation_~tmp~3#1); 1771#L432-2 [2022-10-17 11:07:36,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:36,965 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 1 times [2022-10-17 11:07:36,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:36,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261761143] [2022-10-17 11:07:36,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:36,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:36,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:37,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:37,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:37,055 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261761143] [2022-10-17 11:07:37,056 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261761143] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:37,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:37,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 11:07:37,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140919369] [2022-10-17 11:07:37,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:37,063 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:37,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:37,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1200633539, now seen corresponding path program 7 times [2022-10-17 11:07:37,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:37,065 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300063602] [2022-10-17 11:07:37,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:37,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:37,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:37,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:37,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:37,114 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300063602] [2022-10-17 11:07:37,116 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300063602] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:37,116 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:37,117 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:37,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1825193067] [2022-10-17 11:07:37,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:37,119 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:37,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:37,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:07:37,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:07:37,120 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:37,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:37,181 INFO L93 Difference]: Finished difference Result 151 states and 225 transitions. [2022-10-17 11:07:37,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 225 transitions. [2022-10-17 11:07:37,183 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2022-10-17 11:07:37,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 151 states and 225 transitions. [2022-10-17 11:07:37,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2022-10-17 11:07:37,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2022-10-17 11:07:37,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 225 transitions. [2022-10-17 11:07:37,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 11:07:37,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151 states and 225 transitions. [2022-10-17 11:07:37,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 225 transitions. [2022-10-17 11:07:37,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 120. [2022-10-17 11:07:37,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:37,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2022-10-17 11:07:37,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2022-10-17 11:07:37,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 11:07:37,194 INFO L428 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2022-10-17 11:07:37,194 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 11:07:37,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2022-10-17 11:07:37,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2022-10-17 11:07:37,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:37,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:37,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:37,197 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:37,197 INFO L748 eck$LassoCheckResult]: Stem: 2123#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2071#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2032#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2033#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2096#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2097#L137-2 ~b0_req_up~0 := 0; 2090#L145 assume { :end_inline_update_b0 } true; 2091#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2052#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2053#L152-2 ~b1_req_up~0 := 0; 2115#L160 assume { :end_inline_update_b1 } true; 2114#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 2035#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 2036#L167-2 ~d0_req_up~0 := 0; 2013#L175 assume { :end_inline_update_d0 } true; 2014#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2072#L182 assume !(~d1_val~0 != ~d1_val_t~0); 2040#L182-2 ~d1_req_up~0 := 0; 2041#L190 assume { :end_inline_update_d1 } true; 2095#L233-1 assume !(1 == ~z_req_up~0); 2101#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2028#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 2029#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2102#L321 assume !(0 == ~b0_ev~0); 2103#L321-2 assume !(0 == ~b1_ev~0); 2046#L326-1 assume !(0 == ~d0_ev~0); 2047#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 2017#L336-1 assume !(0 == ~z_ev~0); 2018#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2125#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2038#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2085#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2086#L390 assume !(0 != activate_threads_~tmp~1#1); 2116#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2084#L354 assume !(1 == ~b0_ev~0); 2066#L354-2 assume !(1 == ~b1_ev~0); 2067#L359-1 assume !(1 == ~d0_ev~0); 2069#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2070#L369-1 assume !(1 == ~z_ev~0); 2074#L374-1 assume { :end_inline_reset_delta_events } true; 2058#L432-2 [2022-10-17 11:07:37,198 INFO L750 eck$LassoCheckResult]: Loop: 2058#L432-2 assume !false; 2059#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 2015#L295 assume !false; 2016#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2042#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2044#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2127#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2126#L290 assume !(0 != eval_~tmp___0~0#1); 2075#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2076#L212-3 assume !(1 == ~b0_req_up~0); 2105#L212-5 assume !(1 == ~b1_req_up~0); 2061#L219-3 assume !(1 == ~d0_req_up~0); 2010#L226-3 assume !(1 == ~d1_req_up~0); 2011#L233-3 assume !(1 == ~z_req_up~0); 2030#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2031#L321-3 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2098#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2099#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2080#L331-3 assume !(0 == ~d1_ev~0); 2024#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2025#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2034#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2051#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2073#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2019#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 2020#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2045#L354-3 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2055#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2119#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2113#L364-3 assume !(1 == ~d1_ev~0); 2112#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2077#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2078#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2106#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2068#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 2026#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2027#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2120#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2107#L449 assume !(0 != start_simulation_~tmp~3#1); 2058#L432-2 [2022-10-17 11:07:37,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:37,198 INFO L85 PathProgramCache]: Analyzing trace with hash -525437980, now seen corresponding path program 2 times [2022-10-17 11:07:37,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:37,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985667205] [2022-10-17 11:07:37,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:37,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:37,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:37,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:37,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:37,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985667205] [2022-10-17 11:07:37,294 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985667205] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:37,295 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:37,295 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 11:07:37,295 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024611367] [2022-10-17 11:07:37,295 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:37,296 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:37,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:37,296 INFO L85 PathProgramCache]: Analyzing trace with hash 356628037, now seen corresponding path program 1 times [2022-10-17 11:07:37,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:37,297 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961372916] [2022-10-17 11:07:37,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:37,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:37,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:37,317 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:37,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:37,353 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:37,819 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 11:07:37,820 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 11:07:37,820 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 11:07:37,820 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 11:07:37,820 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 11:07:37,820 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:37,821 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 11:07:37,821 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 11:07:37,821 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2022-10-17 11:07:37,821 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 11:07:37,822 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 11:07:37,841 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,866 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,870 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,875 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,879 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,887 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,890 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,897 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,899 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,902 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,905 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,908 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,911 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,915 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,918 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,923 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,925 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,927 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,929 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,933 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,936 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,942 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:37,944 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,224 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 11:07:38,224 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 11:07:38,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:38,232 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:38,245 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:38,245 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:38,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 11:07:38,274 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 11:07:38,274 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Honda state: {ULTIMATE.start_start_simulation_~kernel_st~0#1=3} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 11:07:38,310 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:38,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,311 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:38,312 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:38,363 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 11:07:38,363 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:38,363 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:38,392 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 11:07:38,393 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~d1_ev~0=-7} Honda state: {~d1_ev~0=-7} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 11:07:38,437 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:38,437 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:38,451 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:38,466 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:38,466 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:38,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 11:07:38,527 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:38,527 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,527 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:38,528 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:38,538 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 11:07:38,539 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 11:07:38,539 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:38,565 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 11:07:38,602 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:38,603 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 11:07:38,603 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 11:07:38,604 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 11:07:38,604 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 11:07:38,604 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 11:07:38,604 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,604 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 11:07:38,604 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 11:07:38,604 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2022-10-17 11:07:38,604 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 11:07:38,604 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 11:07:38,607 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,623 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,629 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,647 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,650 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,653 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,657 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,660 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,663 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,666 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,680 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,683 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,688 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,691 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,695 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,698 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,700 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,706 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,708 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,711 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,719 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,721 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,728 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:38,971 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 11:07:38,975 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 11:07:38,977 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:38,977 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:38,978 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:38,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 11:07:38,983 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 11:07:38,992 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 11:07:38,993 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 11:07:38,993 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 11:07:38,993 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2022-10-17 11:07:38,993 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 11:07:38,995 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2022-10-17 11:07:38,995 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 11:07:39,005 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 11:07:39,041 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2022-10-17 11:07:39,041 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:39,041 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:39,042 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:39,043 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 11:07:39,044 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 11:07:39,051 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 11:07:39,051 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 11:07:39,051 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 11:07:39,051 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 11:07:39,051 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 11:07:39,052 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 11:07:39,052 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 11:07:39,083 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 11:07:39,096 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-10-17 11:07:39,096 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-10-17 11:07:39,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:39,098 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:39,104 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:39,110 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 11:07:39,110 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 11:07:39,110 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 11:07:39,111 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~b0_ev~0) = -1*~b0_ev~0 + 1 Supporting invariants [] [2022-10-17 11:07:39,139 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 11:07:39,152 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:39,154 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 11:07:39,178 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:39,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:39,224 INFO L263 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 11:07:39,228 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:07:39,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:39,335 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 11:07:39,340 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:07:39,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:39,501 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 11:07:39,503 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,609 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 422 transitions. Complement of second has 5 states. [2022-10-17 11:07:39,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 11:07:39,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2022-10-17 11:07:39,614 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2022-10-17 11:07:39,616 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:39,617 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2022-10-17 11:07:39,620 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:39,620 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2022-10-17 11:07:39,622 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:39,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 422 transitions. [2022-10-17 11:07:39,626 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-10-17 11:07:39,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 422 transitions. [2022-10-17 11:07:39,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-10-17 11:07:39,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2022-10-17 11:07:39,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 422 transitions. [2022-10-17 11:07:39,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:39,630 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 422 transitions. [2022-10-17 11:07:39,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 422 transitions. [2022-10-17 11:07:39,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2022-10-17 11:07:39,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2022-10-17 11:07:39,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2022-10-17 11:07:39,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:39,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:07:39,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:07:39,639 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:39,669 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2022-10-17 11:07:39,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2022-10-17 11:07:39,672 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-10-17 11:07:39,674 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2022-10-17 11:07:39,675 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2022-10-17 11:07:39,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2022-10-17 11:07:39,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2022-10-17 11:07:39,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:39,678 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-10-17 11:07:39,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2022-10-17 11:07:39,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2022-10-17 11:07:39,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2022-10-17 11:07:39,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-10-17 11:07:39,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-10-17 11:07:39,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2022-10-17 11:07:39,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 11:07:39,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2022-10-17 11:07:39,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2022-10-17 11:07:39,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:39,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:39,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:39,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:39,742 INFO L748 eck$LassoCheckResult]: Stem: 3398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3308#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3246#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3247#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3349#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3350#L137-2 ~b0_req_up~0 := 0; 3339#L145 assume { :end_inline_update_b0 } true; 3340#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3275#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3276#L152-2 ~b1_req_up~0 := 0; 3380#L160 assume { :end_inline_update_b1 } true; 3378#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3250#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3251#L167-2 ~d0_req_up~0 := 0; 3214#L175 assume { :end_inline_update_d0 } true; 3215#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3311#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3261#L182-2 ~d1_req_up~0 := 0; 3262#L190 assume { :end_inline_update_d1 } true; 3348#L233-1 assume !(1 == ~z_req_up~0); 3356#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3244#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3245#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3357#L321 assume !(0 == ~b0_ev~0); 3358#L321-2 assume !(0 == ~b1_ev~0); 3269#L326-1 assume !(0 == ~d0_ev~0); 3270#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3224#L336-1 assume !(0 == ~z_ev~0); 3225#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3401#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3253#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3332#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3333#L390 assume !(0 != activate_threads_~tmp~1#1); 3382#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3331#L354 assume !(1 == ~b0_ev~0); 3304#L354-2 assume !(1 == ~b1_ev~0); 3305#L359-1 assume !(1 == ~d0_ev~0); 3306#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3307#L369-1 assume !(1 == ~z_ev~0); 3316#L374-1 assume { :end_inline_reset_delta_events } true; 3385#L432-2 assume !false; 3405#L433 [2022-10-17 11:07:39,743 INFO L750 eck$LassoCheckResult]: Loop: 3405#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3434#L295 assume !false; 3379#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3255#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3257#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3474#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3473#L290 assume !(0 != eval_~tmp___0~0#1); 3312#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3313#L212-3 assume !(1 == ~b0_req_up~0); 3360#L212-5 assume !(1 == ~b1_req_up~0); 3417#L219-3 assume !(1 == ~d0_req_up~0); 3208#L226-3 assume !(1 == ~d1_req_up~0); 3209#L233-3 assume !(1 == ~z_req_up~0); 3240#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3241#L321-3 assume !(0 == ~b0_ev~0); 3351#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3352#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3323#L331-3 assume !(0 == ~d1_ev~0); 3228#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 3229#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3248#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3272#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3309#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3220#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3221#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3263#L354-3 assume !(1 == ~b0_ev~0); 3277#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3428#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3470#L364-3 assume !(1 == ~d1_ev~0); 3467#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3464#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3463#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3460#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3459#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3458#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3455#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3453#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3452#L449 assume !(0 != start_simulation_~tmp~3#1); 3451#L432-2 assume !false; 3405#L433 [2022-10-17 11:07:39,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:39,743 INFO L85 PathProgramCache]: Analyzing trace with hash 750743388, now seen corresponding path program 1 times [2022-10-17 11:07:39,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:39,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473939274] [2022-10-17 11:07:39,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:39,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:39,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:39,779 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:39,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:39,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:39,811 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473939274] [2022-10-17 11:07:39,811 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473939274] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:39,811 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:39,811 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:39,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912210742] [2022-10-17 11:07:39,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:39,812 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:39,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:39,812 INFO L85 PathProgramCache]: Analyzing trace with hash 618560829, now seen corresponding path program 1 times [2022-10-17 11:07:39,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:39,812 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665676403] [2022-10-17 11:07:39,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:39,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:39,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:39,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:39,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:39,848 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665676403] [2022-10-17 11:07:39,848 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665676403] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:39,848 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:39,848 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:39,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [652045466] [2022-10-17 11:07:39,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:39,849 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:39,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:39,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:39,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:39,849 INFO L87 Difference]: Start difference. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 3 states, 3 states have (on average 13.0) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:39,890 INFO L93 Difference]: Finished difference Result 313 states and 475 transitions. [2022-10-17 11:07:39,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 313 states and 475 transitions. [2022-10-17 11:07:39,894 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2022-10-17 11:07:39,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 313 states to 303 states and 459 transitions. [2022-10-17 11:07:39,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 217 [2022-10-17 11:07:39,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 217 [2022-10-17 11:07:39,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2022-10-17 11:07:39,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:39,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-10-17 11:07:39,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2022-10-17 11:07:39,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2022-10-17 11:07:39,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.5148514851485149) internal successors, (459), 302 states have internal predecessors, (459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:39,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2022-10-17 11:07:39,915 INFO L240 hiAutomatonCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-10-17 11:07:39,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:39,916 INFO L428 stractBuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2022-10-17 11:07:39,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 11:07:39,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2022-10-17 11:07:39,918 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 159 [2022-10-17 11:07:39,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:39,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:39,919 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:39,919 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:39,920 INFO L748 eck$LassoCheckResult]: Stem: 3994#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3838#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3839#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3942#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3943#L137-2 ~b0_req_up~0 := 0; 3932#L145 assume { :end_inline_update_b0 } true; 3933#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3867#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3868#L152-2 ~b1_req_up~0 := 0; 3975#L160 assume { :end_inline_update_b1 } true; 3973#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3842#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3843#L167-2 ~d0_req_up~0 := 0; 3805#L175 assume { :end_inline_update_d0 } true; 3806#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3903#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3853#L182-2 ~d1_req_up~0 := 0; 3854#L190 assume { :end_inline_update_d1 } true; 3941#L233-1 assume !(1 == ~z_req_up~0); 3949#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3836#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3837#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3950#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3951#L321-2 assume !(0 == ~b1_ev~0); 3861#L326-1 assume !(0 == ~d0_ev~0); 3862#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3815#L336-1 assume !(0 == ~z_ev~0); 3816#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3998#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3990#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3929#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3930#L390 assume !(0 != activate_threads_~tmp~1#1); 3976#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3924#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3895#L354-2 assume !(1 == ~b1_ev~0); 3896#L359-1 assume !(1 == ~d0_ev~0); 3897#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3898#L369-1 assume !(1 == ~z_ev~0); 3908#L374-1 assume { :end_inline_reset_delta_events } true; 3980#L432-2 assume !false; 3878#L433 [2022-10-17 11:07:39,920 INFO L750 eck$LassoCheckResult]: Loop: 3878#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3807#L295 assume !false; 3808#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3847#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3849#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 4060#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4059#L290 assume !(0 != eval_~tmp___0~0#1); 3904#L311 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3905#L212-3 assume !(1 == ~b0_req_up~0); 3954#L212-5 assume !(1 == ~b1_req_up~0); 3882#L219-3 assume !(1 == ~d0_req_up~0); 4046#L226-3 assume !(1 == ~d1_req_up~0); 4044#L233-3 assume !(1 == ~z_req_up~0); 4042#L240-3 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4041#L321-3 assume !(0 == ~b0_ev~0); 4040#L321-5 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 4039#L326-3 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 4038#L331-3 assume !(0 == ~d1_ev~0); 4037#L336-3 assume 0 == ~z_ev~0;~z_ev~0 := 1; 4036#L341-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 4017#L107-1 assume !(1 == ~b0_ev~0); 3988#L111-1 assume 1 == ~b1_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3864#L129-1 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3900#L130-1 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3811#L390-3 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3812#L390-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3855#L354-3 assume !(1 == ~b0_ev~0); 3871#L354-5 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3983#L359-3 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3971#L364-3 assume !(1 == ~d1_ev~0); 3967#L369-3 assume 1 == ~z_ev~0;~z_ev~0 := 2; 3909#L374-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3910#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3957#L275-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3893#L276-1 stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3828#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3829#L414 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3986#L415 start_simulation_#t~ret8#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3959#L449 assume !(0 != start_simulation_~tmp~3#1); 3877#L432-2 assume !false; 3878#L433 [2022-10-17 11:07:39,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:39,921 INFO L85 PathProgramCache]: Analyzing trace with hash 969880732, now seen corresponding path program 1 times [2022-10-17 11:07:39,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:39,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083305090] [2022-10-17 11:07:39,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:39,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:39,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:39,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:39,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:39,949 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083305090] [2022-10-17 11:07:39,949 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083305090] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:39,949 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:39,950 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:39,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795812445] [2022-10-17 11:07:39,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:39,950 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:39,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:39,951 INFO L85 PathProgramCache]: Analyzing trace with hash 571541896, now seen corresponding path program 1 times [2022-10-17 11:07:39,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:39,951 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748691918] [2022-10-17 11:07:39,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:39,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:39,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:39,968 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:39,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:39,978 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:40,331 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 11:07:40,331 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 11:07:40,331 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 11:07:40,332 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 11:07:40,332 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 11:07:40,332 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,332 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 11:07:40,332 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 11:07:40,332 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2022-10-17 11:07:40,332 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 11:07:40,332 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 11:07:40,335 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,339 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,342 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,346 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,348 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,351 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,356 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,361 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,363 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,365 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,371 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,372 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,375 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,377 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,379 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,382 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,386 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,389 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,396 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,402 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,404 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,410 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,414 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,662 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 11:07:40,662 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 11:07:40,662 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:40,667 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:40,699 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:40,699 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:40,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 11:07:40,718 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 11:07:40,718 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 11:07:40,755 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:40,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:40,756 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:40,762 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:40,762 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:40,772 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-10-17 11:07:40,783 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 11:07:40,783 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret7#1=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 11:07:40,819 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:40,820 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:40,821 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:40,828 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 11:07:40,828 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:40,838 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-10-17 11:07:40,858 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:40,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:40,860 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:40,861 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-10-17 11:07:40,862 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 11:07:40,862 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 11:07:40,899 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 11:07:40,935 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:40,935 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 11:07:40,935 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 11:07:40,935 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 11:07:40,936 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 11:07:40,936 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 11:07:40,936 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:40,936 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 11:07:40,936 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 11:07:40,936 INFO L133 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration11_Loop [2022-10-17 11:07:40,936 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 11:07:40,936 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 11:07:40,938 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,943 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,946 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,948 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,950 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,955 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,960 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,964 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,966 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,969 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,976 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,978 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,983 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,985 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,988 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,991 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:40,995 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,001 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,004 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,009 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,011 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,016 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,023 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 11:07:41,283 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 11:07:41,283 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 11:07:41,284 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:41,284 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:41,299 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:41,343 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2022-10-17 11:07:41,344 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 11:07:41,356 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 11:07:41,356 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 11:07:41,356 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 11:07:41,356 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 11:07:41,356 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 11:07:41,358 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 11:07:41,358 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 11:07:41,371 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 11:07:41,374 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-10-17 11:07:41,375 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-10-17 11:07:41,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 11:07:41,375 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 11:07:41,376 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 11:07:41,381 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 11:07:41,381 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 11:07:41,382 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 11:07:41,382 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2022-10-17 11:07:41,407 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2022-10-17 11:07:41,415 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:41,416 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 11:07:41,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:41,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:41,459 INFO L263 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 11:07:41,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:07:41,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:41,516 INFO L263 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 11:07:41,518 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 11:07:41,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:41,611 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2022-10-17 11:07:41,612 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,645 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 303 states and 459 transitions. cyclomatic complexity: 159. Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 810 states and 1251 transitions. Complement of second has 5 states. [2022-10-17 11:07:41,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 11:07:41,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2022-10-17 11:07:41,647 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 40 letters. [2022-10-17 11:07:41,647 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:41,648 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 81 letters. Loop has 40 letters. [2022-10-17 11:07:41,648 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:41,648 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 80 letters. [2022-10-17 11:07:41,649 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 11:07:41,649 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 810 states and 1251 transitions. [2022-10-17 11:07:41,658 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 318 [2022-10-17 11:07:41,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 810 states to 810 states and 1251 transitions. [2022-10-17 11:07:41,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 378 [2022-10-17 11:07:41,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 384 [2022-10-17 11:07:41,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 810 states and 1251 transitions. [2022-10-17 11:07:41,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:41,667 INFO L218 hiAutomatonCegarLoop]: Abstraction has 810 states and 1251 transitions. [2022-10-17 11:07:41,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states and 1251 transitions. [2022-10-17 11:07:41,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 804. [2022-10-17 11:07:41,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 804 states, 804 states have (on average 1.5422885572139304) internal successors, (1240), 803 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 804 states to 804 states and 1240 transitions. [2022-10-17 11:07:41,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 804 states and 1240 transitions. [2022-10-17 11:07:41,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:41,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:41,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:41,689 INFO L87 Difference]: Start difference. First operand 804 states and 1240 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:41,715 INFO L93 Difference]: Finished difference Result 963 states and 1454 transitions. [2022-10-17 11:07:41,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 1454 transitions. [2022-10-17 11:07:41,724 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-10-17 11:07:41,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 1454 transitions. [2022-10-17 11:07:41,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2022-10-17 11:07:41,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2022-10-17 11:07:41,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 1454 transitions. [2022-10-17 11:07:41,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:41,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-10-17 11:07:41,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 1454 transitions. [2022-10-17 11:07:41,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2022-10-17 11:07:41,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 1.509865005192108) internal successors, (1454), 962 states have internal predecessors, (1454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1454 transitions. [2022-10-17 11:07:41,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-10-17 11:07:41,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:41,795 INFO L428 stractBuchiCegarLoop]: Abstraction has 963 states and 1454 transitions. [2022-10-17 11:07:41,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 11:07:41,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1454 transitions. [2022-10-17 11:07:41,802 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-10-17 11:07:41,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:41,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:41,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:41,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:41,803 INFO L748 eck$LassoCheckResult]: Stem: 7152#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 7045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 6980#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6981#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 7088#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 7089#L137-2 ~b0_req_up~0 := 0; 7078#L145 assume { :end_inline_update_b0 } true; 7079#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 7012#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 7013#L152-2 ~b1_req_up~0 := 0; 7126#L160 assume { :end_inline_update_b1 } true; 7123#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6985#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6986#L167-2 ~d0_req_up~0 := 0; 6948#L175 assume { :end_inline_update_d0 } true; 6949#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 7049#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6996#L182-2 ~d1_req_up~0 := 0; 6997#L190 assume { :end_inline_update_d1 } true; 7087#L233-1 assume !(1 == ~z_req_up~0); 7095#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6978#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6979#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7096#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 7097#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 7164#L326-1 assume !(0 == ~d0_ev~0); 7007#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 6958#L336-1 assume !(0 == ~z_ev~0); 6959#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 7157#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 7146#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 7075#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 7076#L390 assume !(0 != activate_threads_~tmp~1#1); 7127#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7069#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 7041#L354-2 assume !(1 == ~b1_ev~0); 7042#L359-1 assume !(1 == ~d0_ev~0); 7043#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 7044#L369-1 assume !(1 == ~z_ev~0); 7054#L374-1 assume { :end_inline_reset_delta_events } true; 7131#L432-2 assume !false; 7312#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 6950#L295 [2022-10-17 11:07:41,803 INFO L750 eck$LassoCheckResult]: Loop: 6950#L295 assume !false; 6951#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 6990#L268 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 6992#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 7185#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7171#L290 assume 0 != eval_~tmp___0~0#1; 7150#L290-1 assume !(0 == ~comp_m1_st~0); 6950#L295 [2022-10-17 11:07:41,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:41,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1995676522, now seen corresponding path program 1 times [2022-10-17 11:07:41,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:41,811 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894230708] [2022-10-17 11:07:41,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:41,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:41,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:41,820 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2022-10-17 11:07:41,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:41,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:41,841 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894230708] [2022-10-17 11:07:41,841 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894230708] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:41,841 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:41,842 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:41,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576152060] [2022-10-17 11:07:41,842 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:41,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:41,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:41,843 INFO L85 PathProgramCache]: Analyzing trace with hash 831114558, now seen corresponding path program 1 times [2022-10-17 11:07:41,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:41,843 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161770157] [2022-10-17 11:07:41,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:41,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:41,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:41,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:41,886 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:41,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161770157] [2022-10-17 11:07:41,886 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161770157] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:41,886 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:41,886 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 11:07:41,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788829395] [2022-10-17 11:07:41,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:41,887 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:41,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:41,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 11:07:41,888 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 11:07:41,888 INFO L87 Difference]: Start difference. First operand 963 states and 1454 transitions. cyclomatic complexity: 500 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:41,948 INFO L93 Difference]: Finished difference Result 1053 states and 1544 transitions. [2022-10-17 11:07:41,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1053 states and 1544 transitions. [2022-10-17 11:07:41,958 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 428 [2022-10-17 11:07:41,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1053 states to 1053 states and 1544 transitions. [2022-10-17 11:07:41,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2022-10-17 11:07:41,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2022-10-17 11:07:41,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1053 states and 1544 transitions. [2022-10-17 11:07:41,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:41,971 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1053 states and 1544 transitions. [2022-10-17 11:07:41,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1053 states and 1544 transitions. [2022-10-17 11:07:41,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1053 to 963. [2022-10-17 11:07:41,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 963 states, 963 states have (on average 1.5005192107995846) internal successors, (1445), 962 states have internal predecessors, (1445), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:41,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1445 transitions. [2022-10-17 11:07:41,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 963 states and 1445 transitions. [2022-10-17 11:07:41,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 11:07:41,997 INFO L428 stractBuchiCegarLoop]: Abstraction has 963 states and 1445 transitions. [2022-10-17 11:07:41,997 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 11:07:41,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1445 transitions. [2022-10-17 11:07:42,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 388 [2022-10-17 11:07:42,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,004 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,005 INFO L748 eck$LassoCheckResult]: Stem: 9183#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 9075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 9012#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9013#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 9118#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 9119#L137-2 ~b0_req_up~0 := 0; 9109#L145 assume { :end_inline_update_b0 } true; 9110#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 9042#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 9043#L152-2 ~b1_req_up~0 := 0; 9157#L160 assume { :end_inline_update_b1 } true; 9155#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 9016#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 9017#L167-2 ~d0_req_up~0 := 0; 8980#L175 assume { :end_inline_update_d0 } true; 8981#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 9078#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 9027#L182-2 ~d1_req_up~0 := 0; 9028#L190 assume { :end_inline_update_d1 } true; 9117#L233-1 assume !(1 == ~z_req_up~0); 9125#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9010#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 9011#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9126#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 9127#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 9199#L326-1 assume !(0 == ~d0_ev~0); 9037#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 8990#L336-1 assume !(0 == ~z_ev~0); 8991#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 9189#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9178#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 9106#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9107#L390 assume !(0 != activate_threads_~tmp~1#1); 9158#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9101#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 9071#L354-2 assume !(1 == ~b1_ev~0); 9072#L359-1 assume !(1 == ~d0_ev~0); 9073#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 9074#L369-1 assume !(1 == ~z_ev~0); 9083#L374-1 assume { :end_inline_reset_delta_events } true; 9162#L432-2 assume !false; 9604#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 9518#L295 [2022-10-17 11:07:42,005 INFO L750 eck$LassoCheckResult]: Loop: 9518#L295 assume !false; 9423#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 9417#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 9173#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 8976#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8977#L290 assume 0 != eval_~tmp___0~0#1; 9192#L290-1 assume !(0 == ~comp_m1_st~0); 9518#L295 [2022-10-17 11:07:42,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,006 INFO L85 PathProgramCache]: Analyzing trace with hash 1995676522, now seen corresponding path program 2 times [2022-10-17 11:07:42,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,006 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456160705] [2022-10-17 11:07:42,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,032 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456160705] [2022-10-17 11:07:42,032 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456160705] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,032 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,032 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:42,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183644158] [2022-10-17 11:07:42,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,033 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:42,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,033 INFO L85 PathProgramCache]: Analyzing trace with hash 829267516, now seen corresponding path program 1 times [2022-10-17 11:07:42,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,034 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211639938] [2022-10-17 11:07:42,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,042 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211639938] [2022-10-17 11:07:42,042 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [211639938] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,043 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,043 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 11:07:42,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742771498] [2022-10-17 11:07:42,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,043 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 11:07:42,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:42,044 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:42,044 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:42,044 INFO L87 Difference]: Start difference. First operand 963 states and 1445 transitions. cyclomatic complexity: 491 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:42,072 INFO L93 Difference]: Finished difference Result 1188 states and 1749 transitions. [2022-10-17 11:07:42,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1188 states and 1749 transitions. [2022-10-17 11:07:42,083 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-10-17 11:07:42,094 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1188 states to 1188 states and 1749 transitions. [2022-10-17 11:07:42,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 563 [2022-10-17 11:07:42,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 563 [2022-10-17 11:07:42,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1188 states and 1749 transitions. [2022-10-17 11:07:42,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:42,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-10-17 11:07:42,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1188 states and 1749 transitions. [2022-10-17 11:07:42,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1188 to 1188. [2022-10-17 11:07:42,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1188 states, 1188 states have (on average 1.4722222222222223) internal successors, (1749), 1187 states have internal predecessors, (1749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1188 states to 1188 states and 1749 transitions. [2022-10-17 11:07:42,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-10-17 11:07:42,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:42,125 INFO L428 stractBuchiCegarLoop]: Abstraction has 1188 states and 1749 transitions. [2022-10-17 11:07:42,125 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 11:07:42,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1188 states and 1749 transitions. [2022-10-17 11:07:42,134 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-10-17 11:07:42,134 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,135 INFO L748 eck$LassoCheckResult]: Stem: 11363#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 11236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 11173#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11174#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 11282#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 11283#L137-2 ~b0_req_up~0 := 0; 11272#L145 assume { :end_inline_update_b0 } true; 11273#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 11202#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 11203#L152-2 ~b1_req_up~0 := 0; 11329#L160 assume { :end_inline_update_b1 } true; 11320#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 11179#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 11180#L167-2 ~d0_req_up~0 := 0; 11138#L175 assume { :end_inline_update_d0 } true; 11139#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 11240#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 11188#L182-2 ~d1_req_up~0 := 0; 11189#L190 assume { :end_inline_update_d1 } true; 11281#L233-1 assume !(1 == ~z_req_up~0); 11289#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11170#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 11171#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11290#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 11291#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 11196#L326-1 assume !(0 == ~d0_ev~0); 11197#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 11150#L336-1 assume !(0 == ~z_ev~0); 11151#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 11371#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 11372#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 11385#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 11331#L390 assume !(0 != activate_threads_~tmp~1#1); 11332#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11362#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 11232#L354-2 assume !(1 == ~b1_ev~0); 11233#L359-1 assume !(1 == ~d0_ev~0); 11915#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 11913#L369-1 assume !(1 == ~z_ev~0); 11339#L374-1 assume { :end_inline_reset_delta_events } true; 11340#L432-2 assume !false; 11891#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 11226#L295 [2022-10-17 11:07:42,135 INFO L750 eck$LassoCheckResult]: Loop: 11226#L295 assume !false; 11400#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 11184#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 11185#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 11134#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11135#L290 assume 0 != eval_~tmp___0~0#1; 11360#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11225#L299 assume !(0 != eval_~tmp~0#1); 11226#L295 [2022-10-17 11:07:42,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1572974696, now seen corresponding path program 1 times [2022-10-17 11:07:42,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550787629] [2022-10-17 11:07:42,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,185 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550787629] [2022-10-17 11:07:42,185 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550787629] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,186 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-10-17 11:07:42,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899797218] [2022-10-17 11:07:42,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,186 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:42,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,187 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 1 times [2022-10-17 11:07:42,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,187 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185473145] [2022-10-17 11:07:42,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,191 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:42,230 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 11:07:42,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 11:07:42,230 INFO L87 Difference]: Start difference. First operand 1188 states and 1749 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:42,268 INFO L93 Difference]: Finished difference Result 1165 states and 1712 transitions. [2022-10-17 11:07:42,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1165 states and 1712 transitions. [2022-10-17 11:07:42,283 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-10-17 11:07:42,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1165 states to 1165 states and 1712 transitions. [2022-10-17 11:07:42,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 540 [2022-10-17 11:07:42,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 540 [2022-10-17 11:07:42,296 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1165 states and 1712 transitions. [2022-10-17 11:07:42,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:42,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-10-17 11:07:42,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1165 states and 1712 transitions. [2022-10-17 11:07:42,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1165 to 1165. [2022-10-17 11:07:42,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1165 states, 1165 states have (on average 1.4695278969957082) internal successors, (1712), 1164 states have internal predecessors, (1712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1165 states to 1165 states and 1712 transitions. [2022-10-17 11:07:42,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-10-17 11:07:42,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 11:07:42,323 INFO L428 stractBuchiCegarLoop]: Abstraction has 1165 states and 1712 transitions. [2022-10-17 11:07:42,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 11:07:42,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1165 states and 1712 transitions. [2022-10-17 11:07:42,331 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 468 [2022-10-17 11:07:42,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,332 INFO L748 eck$LassoCheckResult]: Stem: 13715#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 13599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 13534#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13535#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 13644#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 13645#L137-2 ~b0_req_up~0 := 0; 13634#L145 assume { :end_inline_update_b0 } true; 13635#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 13565#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 13566#L152-2 ~b1_req_up~0 := 0; 13684#L160 assume { :end_inline_update_b1 } true; 13681#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 13538#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 13539#L167-2 ~d0_req_up~0 := 0; 13500#L175 assume { :end_inline_update_d0 } true; 13501#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 13600#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 13543#L182-2 ~d1_req_up~0 := 0; 13544#L190 assume { :end_inline_update_d1 } true; 13643#L233-1 assume !(1 == ~z_req_up~0); 13651#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13528#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 13529#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13652#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 13653#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 13553#L326-1 assume !(0 == ~d0_ev~0); 13554#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 13506#L336-1 assume !(0 == ~z_ev~0); 13507#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 13720#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 13708#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 13709#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 13685#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 13686#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13714#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 13593#L354-2 assume !(1 == ~b1_ev~0); 13594#L359-1 assume !(1 == ~d0_ev~0); 13597#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 13598#L369-1 assume !(1 == ~z_ev~0); 13690#L374-1 assume { :end_inline_reset_delta_events } true; 13691#L432-2 assume !false; 14279#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 14092#L295 [2022-10-17 11:07:42,332 INFO L750 eck$LassoCheckResult]: Loop: 14092#L295 assume !false; 14211#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 14099#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 13942#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 14096#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14095#L290 assume 0 != eval_~tmp___0~0#1; 14093#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14091#L299 assume !(0 != eval_~tmp~0#1); 14092#L295 [2022-10-17 11:07:42,333 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,333 INFO L85 PathProgramCache]: Analyzing trace with hash -1906263764, now seen corresponding path program 1 times [2022-10-17 11:07:42,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,333 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015832124] [2022-10-17 11:07:42,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,370 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015832124] [2022-10-17 11:07:42,370 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015832124] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,370 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,370 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:42,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894655755] [2022-10-17 11:07:42,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,371 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:42,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,372 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 2 times [2022-10-17 11:07:42,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765394288] [2022-10-17 11:07:42,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,375 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:42,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:42,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:42,422 INFO L87 Difference]: Start difference. First operand 1165 states and 1712 transitions. cyclomatic complexity: 556 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:42,462 INFO L93 Difference]: Finished difference Result 1252 states and 1830 transitions. [2022-10-17 11:07:42,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1252 states and 1830 transitions. [2022-10-17 11:07:42,473 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 525 [2022-10-17 11:07:42,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1252 states to 1252 states and 1830 transitions. [2022-10-17 11:07:42,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 597 [2022-10-17 11:07:42,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 597 [2022-10-17 11:07:42,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1252 states and 1830 transitions. [2022-10-17 11:07:42,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:42,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-10-17 11:07:42,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1252 states and 1830 transitions. [2022-10-17 11:07:42,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1252 to 1252. [2022-10-17 11:07:42,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1252 states, 1252 states have (on average 1.461661341853035) internal successors, (1830), 1251 states have internal predecessors, (1830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1252 states to 1252 states and 1830 transitions. [2022-10-17 11:07:42,515 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-10-17 11:07:42,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:42,516 INFO L428 stractBuchiCegarLoop]: Abstraction has 1252 states and 1830 transitions. [2022-10-17 11:07:42,516 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2022-10-17 11:07:42,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1252 states and 1830 transitions. [2022-10-17 11:07:42,524 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 525 [2022-10-17 11:07:42,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,525 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,525 INFO L748 eck$LassoCheckResult]: Stem: 16146#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 16021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 15957#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15958#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 16068#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 16069#L137-2 ~b0_req_up~0 := 0; 16059#L145 assume { :end_inline_update_b0 } true; 16060#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 15987#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 15988#L152-2 ~b1_req_up~0 := 0; 16111#L160 assume { :end_inline_update_b1 } true; 16107#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 15961#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 15962#L167-2 ~d0_req_up~0 := 0; 15923#L175 assume { :end_inline_update_d0 } true; 15924#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 16022#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 15966#L182-2 ~d1_req_up~0 := 0; 15967#L190 assume { :end_inline_update_d1 } true; 16067#L233-1 assume !(1 == ~z_req_up~0); 16075#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15951#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 15952#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16076#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 16077#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 15975#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 15976#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 15929#L336-1 assume !(0 == ~z_ev~0); 15930#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 16152#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 16139#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 16140#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 16117#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 16118#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16145#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 16014#L354-2 assume !(1 == ~b1_ev~0); 16015#L359-1 assume !(1 == ~d0_ev~0); 16019#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 16020#L369-1 assume !(1 == ~z_ev~0); 16121#L374-1 assume { :end_inline_reset_delta_events } true; 16122#L432-2 assume !false; 17144#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 16570#L295 [2022-10-17 11:07:42,525 INFO L750 eck$LassoCheckResult]: Loop: 16570#L295 assume !false; 16585#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 16584#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 16171#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 16580#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16576#L290 assume 0 != eval_~tmp___0~0#1; 16572#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 16569#L299 assume !(0 != eval_~tmp~0#1); 16570#L295 [2022-10-17 11:07:42,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,526 INFO L85 PathProgramCache]: Analyzing trace with hash -317915862, now seen corresponding path program 1 times [2022-10-17 11:07:42,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,526 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338190164] [2022-10-17 11:07:42,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,553 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338190164] [2022-10-17 11:07:42,553 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338190164] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,553 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,554 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:42,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688032847] [2022-10-17 11:07:42,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,554 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:42,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,555 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 3 times [2022-10-17 11:07:42,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615443306] [2022-10-17 11:07:42,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,558 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:42,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:42,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:42,602 INFO L87 Difference]: Start difference. First operand 1252 states and 1830 transitions. cyclomatic complexity: 587 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:42,630 INFO L93 Difference]: Finished difference Result 1473 states and 2140 transitions. [2022-10-17 11:07:42,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1473 states and 2140 transitions. [2022-10-17 11:07:42,642 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 612 [2022-10-17 11:07:42,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1473 states to 1473 states and 2140 transitions. [2022-10-17 11:07:42,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 682 [2022-10-17 11:07:42,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 682 [2022-10-17 11:07:42,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1473 states and 2140 transitions. [2022-10-17 11:07:42,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:42,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-10-17 11:07:42,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1473 states and 2140 transitions. [2022-10-17 11:07:42,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1473 to 1473. [2022-10-17 11:07:42,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1473 states, 1473 states have (on average 1.4528173794976238) internal successors, (2140), 1472 states have internal predecessors, (2140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1473 states to 1473 states and 2140 transitions. [2022-10-17 11:07:42,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-10-17 11:07:42,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:42,694 INFO L428 stractBuchiCegarLoop]: Abstraction has 1473 states and 2140 transitions. [2022-10-17 11:07:42,694 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2022-10-17 11:07:42,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1473 states and 2140 transitions. [2022-10-17 11:07:42,703 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 612 [2022-10-17 11:07:42,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,704 INFO L748 eck$LassoCheckResult]: Stem: 18896#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 18753#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 18689#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18690#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 18802#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 18803#L137-2 ~b0_req_up~0 := 0; 18792#L145 assume { :end_inline_update_b0 } true; 18793#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 18718#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 18719#L152-2 ~b1_req_up~0 := 0; 18854#L160 assume { :end_inline_update_b1 } true; 18848#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 18693#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 18694#L167-2 ~d0_req_up~0 := 0; 18654#L175 assume { :end_inline_update_d0 } true; 18655#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 18754#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 18697#L182-2 ~d1_req_up~0 := 0; 18698#L190 assume { :end_inline_update_d1 } true; 18801#L233-1 assume !(1 == ~z_req_up~0); 18809#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18687#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 18688#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18810#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 18811#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 18710#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 18711#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 18660#L336-1 assume !(0 == ~z_ev~0); 18661#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 18901#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 18886#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 18887#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 18857#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 18858#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18895#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 18746#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 18747#L359-1 assume !(1 == ~d0_ev~0); 18751#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 18752#L369-1 assume !(1 == ~z_ev~0); 18867#L374-1 assume { :end_inline_reset_delta_events } true; 18868#L432-2 assume !false; 19056#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 18821#L295 [2022-10-17 11:07:42,704 INFO L750 eck$LassoCheckResult]: Loop: 18821#L295 assume !false; 19857#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 19855#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 19699#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 18644#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18645#L290 assume 0 != eval_~tmp___0~0#1; 18891#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 18892#L299 assume !(0 != eval_~tmp~0#1); 18821#L295 [2022-10-17 11:07:42,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,705 INFO L85 PathProgramCache]: Analyzing trace with hash -2092923224, now seen corresponding path program 1 times [2022-10-17 11:07:42,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818349476] [2022-10-17 11:07:42,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 11:07:42,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 11:07:42,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 11:07:42,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818349476] [2022-10-17 11:07:42,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818349476] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 11:07:42,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 11:07:42,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 11:07:42,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048367081] [2022-10-17 11:07:42,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 11:07:42,730 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 11:07:42,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,731 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 4 times [2022-10-17 11:07:42,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,731 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202858038] [2022-10-17 11:07:42,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,734 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,774 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 11:07:42,774 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 11:07:42,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 11:07:42,774 INFO L87 Difference]: Start difference. First operand 1473 states and 2140 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 11:07:42,802 INFO L93 Difference]: Finished difference Result 1878 states and 2694 transitions. [2022-10-17 11:07:42,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1878 states and 2694 transitions. [2022-10-17 11:07:42,815 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 696 [2022-10-17 11:07:42,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1878 states to 1747 states and 2497 transitions. [2022-10-17 11:07:42,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-10-17 11:07:42,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-10-17 11:07:42,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1747 states and 2497 transitions. [2022-10-17 11:07:42,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 11:07:42,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-10-17 11:07:42,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1747 states and 2497 transitions. [2022-10-17 11:07:42,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1747 to 1747. [2022-10-17 11:07:42,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1747 states, 1747 states have (on average 1.4293073840870063) internal successors, (2497), 1746 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 11:07:42,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1747 states to 1747 states and 2497 transitions. [2022-10-17 11:07:42,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-10-17 11:07:42,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 11:07:42,880 INFO L428 stractBuchiCegarLoop]: Abstraction has 1747 states and 2497 transitions. [2022-10-17 11:07:42,880 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2022-10-17 11:07:42,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1747 states and 2497 transitions. [2022-10-17 11:07:42,889 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 696 [2022-10-17 11:07:42,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 11:07:42,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 11:07:42,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 11:07:42,891 INFO L748 eck$LassoCheckResult]: Stem: 22250#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 22111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 22045#L490 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22046#L212 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 22161#L137 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 22162#L137-2 ~b0_req_up~0 := 0; 22150#L145 assume { :end_inline_update_b0 } true; 22151#L212-2 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 22075#L152 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 22076#L152-2 ~b1_req_up~0 := 0; 22206#L160 assume { :end_inline_update_b1 } true; 22200#L219-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 22050#L167 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 22051#L167-2 ~d0_req_up~0 := 0; 22011#L175 assume { :end_inline_update_d0 } true; 22012#L226-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 22116#L182 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 22058#L182-2 ~d1_req_up~0 := 0; 22059#L190 assume { :end_inline_update_d1 } true; 22160#L233-1 assume !(1 == ~z_req_up~0); 22168#L240-1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22043#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 22044#L255-2 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22169#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 22170#L321-2 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 22067#L326-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 22068#L331-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 22023#L336-1 assume !(0 == ~z_ev~0); 22024#L341-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 22254#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 22241#L129 is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 22242#L130 activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 22209#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 22210#L390-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22249#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 22107#L354-2 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 22108#L359-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 22109#L364-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 22110#L369-1 assume !(1 == ~z_ev~0); 22218#L374-1 assume { :end_inline_reset_delta_events } true; 22219#L432-2 assume !false; 22881#L433 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 22181#L295 [2022-10-17 11:07:42,891 INFO L750 eck$LassoCheckResult]: Loop: 22181#L295 assume !false; 22202#L286 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 22054#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 22055#L275 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 22232#L276 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22256#L290 assume 0 != eval_~tmp___0~0#1; 22257#L290-1 assume 0 == ~comp_m1_st~0;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 22398#L299 assume !(0 != eval_~tmp~0#1); 22181#L295 [2022-10-17 11:07:42,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,892 INFO L85 PathProgramCache]: Analyzing trace with hash 2144785770, now seen corresponding path program 1 times [2022-10-17 11:07:42,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,892 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108682841] [2022-10-17 11:07:42,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,917 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,918 INFO L85 PathProgramCache]: Analyzing trace with hash -62512628, now seen corresponding path program 5 times [2022-10-17 11:07:42,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,918 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667925785] [2022-10-17 11:07:42,918 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,922 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,926 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:42,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 11:07:42,927 INFO L85 PathProgramCache]: Analyzing trace with hash 109674101, now seen corresponding path program 1 times [2022-10-17 11:07:42,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 11:07:42,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403448436] [2022-10-17 11:07:42,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 11:07:42,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 11:07:42,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,938 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:42,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:42,953 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 11:07:44,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:44,189 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 11:07:44,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 11:07:44,347 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 11:07:44 BoogieIcfgContainer [2022-10-17 11:07:44,347 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 11:07:44,348 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 11:07:44,348 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 11:07:44,348 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 11:07:44,348 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 11:07:34" (3/4) ... [2022-10-17 11:07:44,354 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 11:07:44,442 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 11:07:44,443 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 11:07:44,444 INFO L158 Benchmark]: Toolchain (without parser) took 10782.42ms. Allocated memory was 107.0MB in the beginning and 188.7MB in the end (delta: 81.8MB). Free memory was 70.1MB in the beginning and 53.5MB in the end (delta: 16.6MB). Peak memory consumption was 97.5MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,444 INFO L158 Benchmark]: CDTParser took 0.13ms. Allocated memory is still 107.0MB. Free memory is still 86.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 11:07:44,445 INFO L158 Benchmark]: CACSL2BoogieTranslator took 347.30ms. Allocated memory is still 107.0MB. Free memory was 69.7MB in the beginning and 78.4MB in the end (delta: -8.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,445 INFO L158 Benchmark]: Boogie Procedure Inliner took 53.87ms. Allocated memory is still 107.0MB. Free memory was 78.4MB in the beginning and 76.0MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,445 INFO L158 Benchmark]: Boogie Preprocessor took 53.24ms. Allocated memory is still 107.0MB. Free memory was 76.0MB in the beginning and 74.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,446 INFO L158 Benchmark]: RCFGBuilder took 639.89ms. Allocated memory is still 107.0MB. Free memory was 73.9MB in the beginning and 53.2MB in the end (delta: 20.6MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,446 INFO L158 Benchmark]: BuchiAutomizer took 9563.49ms. Allocated memory was 107.0MB in the beginning and 188.7MB in the end (delta: 81.8MB). Free memory was 53.2MB in the beginning and 58.7MB in the end (delta: -5.5MB). Peak memory consumption was 77.0MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,447 INFO L158 Benchmark]: Witness Printer took 95.05ms. Allocated memory is still 188.7MB. Free memory was 58.7MB in the beginning and 53.5MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-10-17 11:07:44,449 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13ms. Allocated memory is still 107.0MB. Free memory is still 86.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 347.30ms. Allocated memory is still 107.0MB. Free memory was 69.7MB in the beginning and 78.4MB in the end (delta: -8.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 53.87ms. Allocated memory is still 107.0MB. Free memory was 78.4MB in the beginning and 76.0MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 53.24ms. Allocated memory is still 107.0MB. Free memory was 76.0MB in the beginning and 74.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 639.89ms. Allocated memory is still 107.0MB. Free memory was 73.9MB in the beginning and 53.2MB in the end (delta: 20.6MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 9563.49ms. Allocated memory was 107.0MB in the beginning and 188.7MB in the end (delta: 81.8MB). Free memory was 53.2MB in the beginning and 58.7MB in the end (delta: -5.5MB). Peak memory consumption was 77.0MB. Max. memory is 16.1GB. * Witness Printer took 95.05ms. Allocated memory is still 188.7MB. Free memory was 58.7MB in the beginning and 53.5MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (17 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * b0_ev + 1 and consists of 3 locations. One deterministic module has affine ranking function -1 * d0_ev + 1 and consists of 3 locations. 17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1747 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 9.3s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 7.0s. Construction of modules took 0.2s. Büchi inclusion checks took 1.8s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 11. Automata minimization 0.4s AutomataMinimizationTime, 19 MinimizatonAttempts, 130 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1086 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1084 mSDsluCounter, 7414 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4054 mSDsCounter, 49 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 260 IncrementalHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 49 mSolverCounterUnsat, 3360 mSDtfsCounter, 260 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN4 SILU0 SILI11 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital95 mio100 ax100 hnf100 lsp11 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 29ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.4s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, __retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, tmp=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, kernel_st=0, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, __retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, tmp=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, kernel_st=0, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 11:07:44,600 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82a8cbd6-f8c2-4fa3-abc6-e3576c7021ac/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)