./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:27:14,191 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:27:14,195 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:27:14,246 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:27:14,247 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:27:14,256 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:27:14,260 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:27:14,267 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:27:14,271 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:27:14,284 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:27:14,285 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:27:14,287 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:27:14,289 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:27:14,291 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:27:14,294 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:27:14,297 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:27:14,299 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:27:14,301 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:27:14,303 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:27:14,308 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:27:14,314 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:27:14,316 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:27:14,321 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:27:14,322 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:27:14,331 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:27:14,331 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:27:14,332 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:27:14,335 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:27:14,336 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:27:14,337 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:27:14,338 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:27:14,339 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:27:14,342 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:27:14,343 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:27:14,345 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:27:14,345 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:27:14,346 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:27:14,346 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:27:14,347 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:27:14,348 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:27:14,349 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:27:14,350 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:27:14,393 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:27:14,394 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:27:14,394 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:27:14,394 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:27:14,396 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:27:14,396 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:27:14,396 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:27:14,396 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:27:14,397 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:27:14,397 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:27:14,397 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:27:14,398 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:27:14,398 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:27:14,398 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:27:14,398 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:27:14,399 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:27:14,399 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:27:14,399 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:27:14,399 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:27:14,400 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:27:14,400 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:27:14,400 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:27:14,401 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:27:14,401 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:27:14,401 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:27:14,401 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:27:14,402 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:27:14,402 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:27:14,402 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:27:14,403 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:27:14,403 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:27:14,404 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:27:14,404 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2022-10-17 10:27:14,722 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:27:14,768 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:27:14,772 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:27:14,773 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:27:14,774 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:27:14,776 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-10-17 10:27:14,864 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/data/d708ce55e/4b8b06ecaaab418da03b56808861038f/FLAGedb38b0eb [2022-10-17 10:27:15,446 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:27:15,447 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2022-10-17 10:27:15,456 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/data/d708ce55e/4b8b06ecaaab418da03b56808861038f/FLAGedb38b0eb [2022-10-17 10:27:15,752 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/data/d708ce55e/4b8b06ecaaab418da03b56808861038f [2022-10-17 10:27:15,755 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:27:15,757 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:27:15,759 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:27:15,759 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:27:15,764 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:27:15,765 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:27:15" (1/1) ... [2022-10-17 10:27:15,766 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5d2342a7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:15, skipping insertion in model container [2022-10-17 10:27:15,767 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:27:15" (1/1) ... [2022-10-17 10:27:15,776 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:27:15,794 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:27:16,037 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-10-17 10:27:16,055 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:27:16,065 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:27:16,081 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/sv-benchmarks/c/array-examples/sanfoundry_24-1.i[848,861] [2022-10-17 10:27:16,089 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:27:16,106 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:27:16,107 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16 WrapperNode [2022-10-17 10:27:16,107 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:27:16,109 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:27:16,109 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:27:16,109 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:27:16,119 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,127 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,153 INFO L138 Inliner]: procedures = 18, calls = 18, calls flagged for inlining = 6, calls inlined = 6, statements flattened = 73 [2022-10-17 10:27:16,154 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:27:16,155 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:27:16,155 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:27:16,155 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:27:16,167 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,167 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,170 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,170 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,178 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,183 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,185 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,187 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,190 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:27:16,191 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:27:16,191 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:27:16,191 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:27:16,193 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (1/1) ... [2022-10-17 10:27:16,206 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:16,221 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:16,252 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:16,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:27:16,324 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:27:16,325 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:27:16,325 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-10-17 10:27:16,325 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-10-17 10:27:16,326 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:27:16,326 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:27:16,326 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-10-17 10:27:16,327 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-10-17 10:27:16,421 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:27:16,423 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:27:16,686 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:27:16,694 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:27:16,712 INFO L300 CfgBuilder]: Removed 3 assume(true) statements. [2022-10-17 10:27:16,714 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:27:16 BoogieIcfgContainer [2022-10-17 10:27:16,715 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:27:16,716 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:27:16,716 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:27:16,721 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:27:16,722 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:16,722 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:27:15" (1/3) ... [2022-10-17 10:27:16,723 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3602c15c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:27:16, skipping insertion in model container [2022-10-17 10:27:16,724 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:16,724 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:16" (2/3) ... [2022-10-17 10:27:16,724 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3602c15c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:27:16, skipping insertion in model container [2022-10-17 10:27:16,724 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:16,725 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:27:16" (3/3) ... [2022-10-17 10:27:16,726 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2022-10-17 10:27:16,807 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:27:16,820 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:27:16,820 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:27:16,820 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:27:16,821 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:27:16,821 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:27:16,821 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:27:16,821 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:27:16,826 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,849 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-10-17 10:27:16,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:27:16,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:27:16,872 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:27:16,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,876 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2022-10-17 10:27:16,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2022-10-17 10:27:16,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2022-10-17 10:27:16,886 INFO L748 eck$LassoCheckResult]: Stem: 4#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19#L27-3true [2022-10-17 10:27:16,886 INFO L750 eck$LassoCheckResult]: Loop: 19#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 10#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19#L27-3true [2022-10-17 10:27:16,906 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,907 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2022-10-17 10:27:16,918 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330044380] [2022-10-17 10:27:16,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:17,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2022-10-17 10:27:17,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:17,126 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143083234] [2022-10-17 10:27:17,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:17,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,149 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,179 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,181 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:17,181 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2022-10-17 10:27:17,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:17,182 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981344469] [2022-10-17 10:27:17,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:17,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,275 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,808 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:27:17,809 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:27:17,810 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:27:17,810 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:27:17,810 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:27:17,810 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:17,811 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:27:17,812 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:27:17,812 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2022-10-17 10:27:17,813 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:27:17,813 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:27:17,844 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,169 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,172 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,176 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,179 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,183 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,187 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,191 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,194 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,197 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,200 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,203 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:27:18,474 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:27:18,479 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:27:18,481 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,482 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,485 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,497 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,509 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,509 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,509 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,510 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,519 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:18,519 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:18,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 10:27:18,540 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:18,583 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2022-10-17 10:27:18,584 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,584 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,586 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,594 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 10:27:18,596 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,606 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,607 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,607 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,607 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,612 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:18,612 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:18,632 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:18,671 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:18,671 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,671 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,676 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,683 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:27:18,694 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,694 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:27:18,694 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,694 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,695 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,696 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:27:18,696 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:27:18,712 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:18,754 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2022-10-17 10:27:18,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,757 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,761 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:27:18,762 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,771 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,771 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,771 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,771 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,783 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:18,783 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:18,796 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:18,839 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2022-10-17 10:27:18,840 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,841 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,861 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,872 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,872 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,872 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,873 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,879 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:18,879 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:18,886 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:27:18,904 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:18,947 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:18,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:18,948 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:18,950 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:18,955 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:27:18,956 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:18,968 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:18,968 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:18,969 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:18,969 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:18,983 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:18,983 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:19,012 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:19,059 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:19,059 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:19,059 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:19,061 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:19,068 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:19,079 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:19,080 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:19,080 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:19,080 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:19,085 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:19,086 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:19,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:27:19,104 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:19,145 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:19,145 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:19,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:19,148 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:19,157 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:19,168 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:19,168 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:19,168 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:19,168 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:19,174 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:19,174 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:19,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2022-10-17 10:27:19,192 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:19,238 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:19,239 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:19,239 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:19,241 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:19,247 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:19,254 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2022-10-17 10:27:19,257 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:19,257 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:19,257 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:19,257 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:19,261 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:19,263 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:19,292 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:27:19,335 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:19,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:19,335 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:19,336 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:19,342 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:27:19,353 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:27:19,353 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:27:19,353 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:27:19,353 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:27:19,370 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2022-10-17 10:27:19,370 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2022-10-17 10:27:19,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2022-10-17 10:27:19,392 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:27:19,454 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2022-10-17 10:27:19,454 INFO L444 ModelExtractionUtils]: 3 out of 16 variables were initially zero. Simplification set additionally 9 variables to zero. [2022-10-17 10:27:19,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:19,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:19,460 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:19,497 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:27:19,497 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2022-10-17 10:27:19,519 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2022-10-17 10:27:19,519 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:27:19,520 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2022-10-17 10:27:19,559 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:19,584 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2022-10-17 10:27:19,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:19,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:19,640 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:27:19,642 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:19,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:19,659 INFO L263 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:27:19,660 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:19,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:19,769 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2022-10-17 10:27:19,772 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:19,839 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.434782608695652) internal successors, (33), 23 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 47 states and 67 transitions. Complement of second has 8 states. [2022-10-17 10:27:19,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2022-10-17 10:27:19,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:19,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 33 transitions. [2022-10-17 10:27:19,854 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 2 letters. [2022-10-17 10:27:19,855 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:27:19,855 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 4 letters. Loop has 2 letters. [2022-10-17 10:27:19,855 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:27:19,855 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 33 transitions. Stem has 2 letters. Loop has 4 letters. [2022-10-17 10:27:19,856 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:27:19,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 67 transitions. [2022-10-17 10:27:19,868 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:27:19,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 21 states and 29 transitions. [2022-10-17 10:27:19,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2022-10-17 10:27:19,877 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-10-17 10:27:19,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 29 transitions. [2022-10-17 10:27:19,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:19,878 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-10-17 10:27:19,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 29 transitions. [2022-10-17 10:27:19,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-10-17 10:27:19,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.380952380952381) internal successors, (29), 20 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:19,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 29 transitions. [2022-10-17 10:27:19,915 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-10-17 10:27:19,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 29 transitions. [2022-10-17 10:27:19,915 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:27:19,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 29 transitions. [2022-10-17 10:27:19,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2022-10-17 10:27:19,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:19,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:19,920 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2022-10-17 10:27:19,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:19,921 INFO L748 eck$LassoCheckResult]: Stem: 132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 139#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 143#L27-4 main_~i~0#1 := 0; 144#L32-3 [2022-10-17 10:27:19,921 INFO L750 eck$LassoCheckResult]: Loop: 144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 149#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 138#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 144#L32-3 [2022-10-17 10:27:19,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:19,921 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2022-10-17 10:27:19,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:19,922 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1677300596] [2022-10-17 10:27:19,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:19,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:19,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:19,934 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:19,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:19,946 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:19,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:19,946 INFO L85 PathProgramCache]: Analyzing trace with hash 54137, now seen corresponding path program 1 times [2022-10-17 10:27:19,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:19,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230103379] [2022-10-17 10:27:19,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:19,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:19,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:19,959 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:19,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:19,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:19,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:19,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1807957807, now seen corresponding path program 1 times [2022-10-17 10:27:19,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:19,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160582646] [2022-10-17 10:27:19,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:19,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:20,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:20,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:20,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:20,173 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160582646] [2022-10-17 10:27:20,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160582646] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:20,174 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:20,174 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:27:20,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945098230] [2022-10-17 10:27:20,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:20,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:20,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:27:20,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:27:20,244 INFO L87 Difference]: Start difference. First operand 21 states and 29 transitions. cyclomatic complexity: 11 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:20,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:20,355 INFO L93 Difference]: Finished difference Result 40 states and 47 transitions. [2022-10-17 10:27:20,355 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 47 transitions. [2022-10-17 10:27:20,357 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:20,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 32 states and 38 transitions. [2022-10-17 10:27:20,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2022-10-17 10:27:20,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2022-10-17 10:27:20,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2022-10-17 10:27:20,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:20,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2022-10-17 10:27:20,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2022-10-17 10:27:20,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2022-10-17 10:27:20,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:20,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2022-10-17 10:27:20,363 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-10-17 10:27:20,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:27:20,384 INFO L428 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-10-17 10:27:20,384 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:27:20,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2022-10-17 10:27:20,385 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:20,385 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:20,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:20,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:20,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:20,386 INFO L748 eck$LassoCheckResult]: Stem: 203#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 213#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 214#L27-4 main_~i~0#1 := 0; 215#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 219#L34 [2022-10-17 10:27:20,387 INFO L750 eck$LassoCheckResult]: Loop: 219#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 208#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 219#L34 [2022-10-17 10:27:20,387 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:20,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2022-10-17 10:27:20,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:20,388 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482546327] [2022-10-17 10:27:20,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:20,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:20,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:20,409 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:20,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:20,440 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:20,440 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:20,441 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 2 times [2022-10-17 10:27:20,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:20,441 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1752830403] [2022-10-17 10:27:20,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:20,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:20,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:20,449 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:20,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:20,463 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:20,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:20,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1436015051, now seen corresponding path program 1 times [2022-10-17 10:27:20,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:20,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600240285] [2022-10-17 10:27:20,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:20,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:20,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:20,611 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2022-10-17 10:27:20,700 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:20,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:20,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600240285] [2022-10-17 10:27:20,701 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600240285] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:20,701 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [53251667] [2022-10-17 10:27:20,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:20,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:20,702 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:20,703 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:20,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-10-17 10:27:20,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:20,766 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:27:20,767 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:20,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:20,841 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:20,896 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:20,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [53251667] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:20,897 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:20,897 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2022-10-17 10:27:20,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869131711] [2022-10-17 10:27:20,898 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:20,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:20,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-10-17 10:27:20,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2022-10-17 10:27:20,962 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:21,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:21,172 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2022-10-17 10:27:21,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2022-10-17 10:27:21,181 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:21,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2022-10-17 10:27:21,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2022-10-17 10:27:21,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2022-10-17 10:27:21,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2022-10-17 10:27:21,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:21,187 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2022-10-17 10:27:21,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2022-10-17 10:27:21,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2022-10-17 10:27:21,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:21,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-10-17 10:27:21,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-10-17 10:27:21,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-10-17 10:27:21,196 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-10-17 10:27:21,197 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:27:21,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2022-10-17 10:27:21,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:21,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:21,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:21,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:21,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:21,205 INFO L748 eck$LassoCheckResult]: Stem: 360#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 366#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 380#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 381#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 369#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 370#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 371#L27-4 main_~i~0#1 := 0; 372#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 377#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 365#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 374#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 379#L34 [2022-10-17 10:27:21,205 INFO L750 eck$LassoCheckResult]: Loop: 379#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 384#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 383#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 379#L34 [2022-10-17 10:27:21,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:21,206 INFO L85 PathProgramCache]: Analyzing trace with hash 780817485, now seen corresponding path program 2 times [2022-10-17 10:27:21,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:21,206 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286940547] [2022-10-17 10:27:21,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:21,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:21,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:21,253 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:21,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:21,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:21,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:21,295 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 3 times [2022-10-17 10:27:21,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:21,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1787232207] [2022-10-17 10:27:21,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:21,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:21,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:21,314 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:21,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:21,326 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:21,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:21,327 INFO L85 PathProgramCache]: Analyzing trace with hash -209139735, now seen corresponding path program 3 times [2022-10-17 10:27:21,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:21,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456044804] [2022-10-17 10:27:21,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:21,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:21,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:21,553 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:21,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:21,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456044804] [2022-10-17 10:27:21,554 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456044804] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:21,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [256119257] [2022-10-17 10:27:21,554 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:27:21,554 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:21,555 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:21,556 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:21,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-10-17 10:27:21,627 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-10-17 10:27:21,627 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:21,628 INFO L263 TraceCheckSpWp]: Trace formula consists of 87 conjuncts, 8 conjunts are in the unsatisfiable core [2022-10-17 10:27:21,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:21,773 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:21,774 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:21,868 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:21,868 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [256119257] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:21,869 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:21,869 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2022-10-17 10:27:21,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1886347191] [2022-10-17 10:27:21,869 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:21,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:21,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-10-17 10:27:21,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2022-10-17 10:27:21,932 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:22,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:22,153 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2022-10-17 10:27:22,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2022-10-17 10:27:22,155 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:22,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2022-10-17 10:27:22,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2022-10-17 10:27:22,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2022-10-17 10:27:22,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2022-10-17 10:27:22,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:22,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2022-10-17 10:27:22,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2022-10-17 10:27:22,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2022-10-17 10:27:22,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:22,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2022-10-17 10:27:22,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-10-17 10:27:22,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-10-17 10:27:22,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2022-10-17 10:27:22,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:27:22,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2022-10-17 10:27:22,166 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:22,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:22,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:22,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2022-10-17 10:27:22,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:22,167 INFO L748 eck$LassoCheckResult]: Stem: 586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 592#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 603#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 604#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 595#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 596#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 607#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 606#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 597#L27-4 main_~i~0#1 := 0; 598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 602#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 591#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 599#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 617#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 615#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 [2022-10-17 10:27:22,168 INFO L750 eck$LassoCheckResult]: Loop: 609#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 610#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 608#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 609#L34 [2022-10-17 10:27:22,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:22,168 INFO L85 PathProgramCache]: Analyzing trace with hash -286749017, now seen corresponding path program 4 times [2022-10-17 10:27:22,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:22,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1140769779] [2022-10-17 10:27:22,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:22,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:22,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:22,208 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:22,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:22,235 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:22,236 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:22,236 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 4 times [2022-10-17 10:27:22,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:22,236 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1262316952] [2022-10-17 10:27:22,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:22,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:22,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:22,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:22,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:22,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:22,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:22,254 INFO L85 PathProgramCache]: Analyzing trace with hash 150026063, now seen corresponding path program 5 times [2022-10-17 10:27:22,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:22,255 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445381399] [2022-10-17 10:27:22,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:22,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:22,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:22,498 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:22,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:22,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445381399] [2022-10-17 10:27:22,498 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445381399] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:22,498 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1782819476] [2022-10-17 10:27:22,499 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:27:22,499 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:22,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:22,501 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:22,528 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-10-17 10:27:22,589 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2022-10-17 10:27:22,590 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:22,591 INFO L263 TraceCheckSpWp]: Trace formula consists of 108 conjuncts, 10 conjunts are in the unsatisfiable core [2022-10-17 10:27:22,593 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:22,757 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:22,757 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:22,884 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:22,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1782819476] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:22,885 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:22,885 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2022-10-17 10:27:22,888 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648062714] [2022-10-17 10:27:22,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:22,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:22,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-10-17 10:27:22,956 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2022-10-17 10:27:22,956 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:23,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:23,260 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2022-10-17 10:27:23,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2022-10-17 10:27:23,263 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:23,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2022-10-17 10:27:23,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2022-10-17 10:27:23,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2022-10-17 10:27:23,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2022-10-17 10:27:23,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:23,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2022-10-17 10:27:23,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2022-10-17 10:27:23,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2022-10-17 10:27:23,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:23,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2022-10-17 10:27:23,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-10-17 10:27:23,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:27:23,272 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2022-10-17 10:27:23,273 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:27:23,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2022-10-17 10:27:23,274 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:23,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:23,274 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:23,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2022-10-17 10:27:23,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:23,275 INFO L748 eck$LassoCheckResult]: Stem: 881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 887#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 901#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 890#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 891#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 910#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 909#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 905#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 904#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 892#L27-4 main_~i~0#1 := 0; 893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 921#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 919#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 918#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 895#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2022-10-17 10:27:23,276 INFO L750 eck$LassoCheckResult]: Loop: 907#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 908#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 906#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 907#L34 [2022-10-17 10:27:23,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:23,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1958082385, now seen corresponding path program 6 times [2022-10-17 10:27:23,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:23,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090168827] [2022-10-17 10:27:23,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:23,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:23,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:23,301 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:23,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:23,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:23,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:23,324 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 5 times [2022-10-17 10:27:23,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:23,324 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474595297] [2022-10-17 10:27:23,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:23,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:23,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:23,329 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:23,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:23,336 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:23,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:23,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1013442971, now seen corresponding path program 7 times [2022-10-17 10:27:23,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:23,338 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602652829] [2022-10-17 10:27:23,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:23,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:23,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:23,583 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:23,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:23,587 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602652829] [2022-10-17 10:27:23,588 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [602652829] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:23,589 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [858583064] [2022-10-17 10:27:23,589 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-10-17 10:27:23,589 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:23,589 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:23,595 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:23,616 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-10-17 10:27:23,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:23,674 INFO L263 TraceCheckSpWp]: Trace formula consists of 129 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-17 10:27:23,677 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:23,871 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:23,871 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:24,024 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:24,024 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [858583064] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:24,024 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:24,025 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2022-10-17 10:27:24,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864517344] [2022-10-17 10:27:24,025 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:24,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:24,084 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-10-17 10:27:24,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2022-10-17 10:27:24,085 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:24,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:24,395 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2022-10-17 10:27:24,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2022-10-17 10:27:24,397 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:24,398 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2022-10-17 10:27:24,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2022-10-17 10:27:24,399 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2022-10-17 10:27:24,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2022-10-17 10:27:24,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:24,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2022-10-17 10:27:24,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2022-10-17 10:27:24,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2022-10-17 10:27:24,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:24,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2022-10-17 10:27:24,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-10-17 10:27:24,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-10-17 10:27:24,416 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2022-10-17 10:27:24,417 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:27:24,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2022-10-17 10:27:24,418 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:24,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:24,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:24,420 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2022-10-17 10:27:24,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:24,421 INFO L748 eck$LassoCheckResult]: Stem: 1245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1251#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1265#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1266#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1254#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1255#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1276#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1275#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1274#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1273#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1269#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1268#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1256#L27-4 main_~i~0#1 := 0; 1257#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1286#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1284#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1285#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1293#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1262#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1250#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1259#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1264#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1281#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1280#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1271#L34 [2022-10-17 10:27:24,421 INFO L750 eck$LassoCheckResult]: Loop: 1271#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1272#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1270#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1271#L34 [2022-10-17 10:27:24,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:24,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1204484189, now seen corresponding path program 8 times [2022-10-17 10:27:24,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:24,422 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804254256] [2022-10-17 10:27:24,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:24,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:24,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:24,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:24,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:24,529 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:24,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:24,530 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 6 times [2022-10-17 10:27:24,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:24,530 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29599560] [2022-10-17 10:27:24,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:24,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:24,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:24,535 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:24,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:24,541 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:24,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:24,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1663323347, now seen corresponding path program 9 times [2022-10-17 10:27:24,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:24,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254350121] [2022-10-17 10:27:24,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:24,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:24,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:24,881 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:24,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:24,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254350121] [2022-10-17 10:27:24,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254350121] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:24,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1821414943] [2022-10-17 10:27:24,882 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:27:24,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:24,882 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:24,885 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:24,890 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-10-17 10:27:25,009 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-10-17 10:27:25,010 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:25,012 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 14 conjunts are in the unsatisfiable core [2022-10-17 10:27:25,014 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:25,233 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:25,233 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:25,407 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:25,408 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1821414943] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:25,408 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:25,408 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2022-10-17 10:27:25,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938056392] [2022-10-17 10:27:25,409 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:25,468 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:25,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2022-10-17 10:27:25,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2022-10-17 10:27:25,471 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:25,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:25,791 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2022-10-17 10:27:25,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2022-10-17 10:27:25,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:25,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2022-10-17 10:27:25,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2022-10-17 10:27:25,795 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2022-10-17 10:27:25,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2022-10-17 10:27:25,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:25,796 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2022-10-17 10:27:25,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2022-10-17 10:27:25,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2022-10-17 10:27:25,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:25,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2022-10-17 10:27:25,810 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-10-17 10:27:25,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-10-17 10:27:25,813 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2022-10-17 10:27:25,813 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:27:25,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2022-10-17 10:27:25,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:25,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:25,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:25,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2022-10-17 10:27:25,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:25,815 INFO L748 eck$LassoCheckResult]: Stem: 1678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1711#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1709#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1708#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1707#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1706#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1701#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1689#L27-4 main_~i~0#1 := 0; 1690#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1732#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1721#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1719#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1724#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1730#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1729#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1683#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1704#L34 [2022-10-17 10:27:25,816 INFO L750 eck$LassoCheckResult]: Loop: 1704#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1704#L34 [2022-10-17 10:27:25,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:25,816 INFO L85 PathProgramCache]: Analyzing trace with hash -1715309995, now seen corresponding path program 10 times [2022-10-17 10:27:25,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:25,821 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210154298] [2022-10-17 10:27:25,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:25,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:25,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:25,896 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:25,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:25,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:25,973 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:25,973 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 7 times [2022-10-17 10:27:25,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:25,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910143506] [2022-10-17 10:27:25,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:25,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:25,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:25,979 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:25,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:25,984 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:25,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:25,985 INFO L85 PathProgramCache]: Analyzing trace with hash 720866529, now seen corresponding path program 11 times [2022-10-17 10:27:25,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:25,985 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520951728] [2022-10-17 10:27:25,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:25,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:26,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:26,421 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:26,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:26,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520951728] [2022-10-17 10:27:26,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520951728] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:26,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [226164443] [2022-10-17 10:27:26,422 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:27:26,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:26,422 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:26,428 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:26,451 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-10-17 10:27:26,587 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2022-10-17 10:27:26,587 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:26,589 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 16 conjunts are in the unsatisfiable core [2022-10-17 10:27:26,591 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:26,861 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:26,861 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:27,059 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:27,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [226164443] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:27,060 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:27,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2022-10-17 10:27:27,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815737541] [2022-10-17 10:27:27,060 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:27,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:27,112 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-10-17 10:27:27,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2022-10-17 10:27:27,113 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:27,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:27,510 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2022-10-17 10:27:27,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2022-10-17 10:27:27,512 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:27,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2022-10-17 10:27:27,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2022-10-17 10:27:27,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2022-10-17 10:27:27,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2022-10-17 10:27:27,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:27,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2022-10-17 10:27:27,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2022-10-17 10:27:27,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2022-10-17 10:27:27,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:27,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2022-10-17 10:27:27,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-10-17 10:27:27,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-10-17 10:27:27,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2022-10-17 10:27:27,533 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:27:27,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2022-10-17 10:27:27,534 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:27,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:27,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:27,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2022-10-17 10:27:27,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:27,536 INFO L748 eck$LassoCheckResult]: Stem: 2180#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2181#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2186#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2201#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2202#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2189#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2190#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2216#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2215#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2214#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2213#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2211#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2210#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2205#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2204#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2191#L27-4 main_~i~0#1 := 0; 2192#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2224#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2225#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2226#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2230#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2229#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2242#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2239#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2237#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2236#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2234#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2233#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2232#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2198#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2185#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2195#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2200#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2221#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2220#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2207#L34 [2022-10-17 10:27:27,550 INFO L750 eck$LassoCheckResult]: Loop: 2207#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2208#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2206#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2207#L34 [2022-10-17 10:27:27,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:27,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1748928671, now seen corresponding path program 12 times [2022-10-17 10:27:27,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:27,551 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900180240] [2022-10-17 10:27:27,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:27,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:27,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:27,606 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:27,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:27,683 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:27,685 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:27,686 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 8 times [2022-10-17 10:27:27,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:27,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183839497] [2022-10-17 10:27:27,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:27,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:27,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:27,695 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:27,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:27,703 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:27,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:27,704 INFO L85 PathProgramCache]: Analyzing trace with hash 85809751, now seen corresponding path program 13 times [2022-10-17 10:27:27,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:27,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395875569] [2022-10-17 10:27:27,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:27,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:27,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:28,204 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:28,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:28,204 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395875569] [2022-10-17 10:27:28,204 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395875569] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:28,205 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [870787578] [2022-10-17 10:27:28,205 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-10-17 10:27:28,205 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:28,205 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:28,216 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:28,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-10-17 10:27:28,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:28,297 INFO L263 TraceCheckSpWp]: Trace formula consists of 192 conjuncts, 18 conjunts are in the unsatisfiable core [2022-10-17 10:27:28,299 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:28,630 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:28,630 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:28,889 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:28,889 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [870787578] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:28,889 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:28,889 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2022-10-17 10:27:28,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414621206] [2022-10-17 10:27:28,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:28,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:28,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2022-10-17 10:27:28,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2022-10-17 10:27:28,947 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:29,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:29,413 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2022-10-17 10:27:29,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2022-10-17 10:27:29,416 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:29,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2022-10-17 10:27:29,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2022-10-17 10:27:29,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2022-10-17 10:27:29,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2022-10-17 10:27:29,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:29,419 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2022-10-17 10:27:29,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2022-10-17 10:27:29,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2022-10-17 10:27:29,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:29,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2022-10-17 10:27:29,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-10-17 10:27:29,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-10-17 10:27:29,427 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2022-10-17 10:27:29,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:27:29,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2022-10-17 10:27:29,428 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:29,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:29,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:29,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2022-10-17 10:27:29,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:29,431 INFO L748 eck$LassoCheckResult]: Stem: 2751#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2752#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2787#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2774#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2762#L27-4 main_~i~0#1 := 0; 2763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2807#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2805#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2756#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2793#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2792#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2777#L34 [2022-10-17 10:27:29,431 INFO L750 eck$LassoCheckResult]: Loop: 2777#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2776#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2777#L34 [2022-10-17 10:27:29,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:29,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1204550311, now seen corresponding path program 14 times [2022-10-17 10:27:29,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:29,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434305986] [2022-10-17 10:27:29,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:29,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:29,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:29,499 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:29,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:29,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:29,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:29,552 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 9 times [2022-10-17 10:27:29,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:29,553 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33087745] [2022-10-17 10:27:29,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:29,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:29,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:29,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:29,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:29,562 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:29,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:29,563 INFO L85 PathProgramCache]: Analyzing trace with hash -306517155, now seen corresponding path program 15 times [2022-10-17 10:27:29,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:29,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992284251] [2022-10-17 10:27:29,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:29,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:29,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:30,091 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:30,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:30,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992284251] [2022-10-17 10:27:30,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992284251] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:30,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1112344602] [2022-10-17 10:27:30,092 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:27:30,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:30,092 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:30,094 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:30,096 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-10-17 10:27:30,293 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2022-10-17 10:27:30,293 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:30,295 INFO L263 TraceCheckSpWp]: Trace formula consists of 213 conjuncts, 20 conjunts are in the unsatisfiable core [2022-10-17 10:27:30,298 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:30,649 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:30,650 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:30,940 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:30,940 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1112344602] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:30,940 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:30,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2022-10-17 10:27:30,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848639520] [2022-10-17 10:27:30,941 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:30,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:30,984 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-10-17 10:27:30,985 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2022-10-17 10:27:30,985 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:31,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:31,496 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2022-10-17 10:27:31,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2022-10-17 10:27:31,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:31,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2022-10-17 10:27:31,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2022-10-17 10:27:31,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2022-10-17 10:27:31,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2022-10-17 10:27:31,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:31,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2022-10-17 10:27:31,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2022-10-17 10:27:31,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2022-10-17 10:27:31,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:31,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2022-10-17 10:27:31,520 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-10-17 10:27:31,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-10-17 10:27:31,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2022-10-17 10:27:31,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:27:31,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2022-10-17 10:27:31,523 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:31,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:31,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:31,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2022-10-17 10:27:31,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:31,531 INFO L748 eck$LassoCheckResult]: Stem: 3391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3397#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3412#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3413#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3400#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3401#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3431#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3430#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3429#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3428#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3427#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3426#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3425#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3424#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3423#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3422#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3421#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3420#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3416#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3415#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3402#L27-4 main_~i~0#1 := 0; 3403#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3439#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3440#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3441#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3445#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3444#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3469#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3466#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3464#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3463#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3460#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3458#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3457#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3454#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3452#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3451#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3449#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3448#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3447#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3409#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3396#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3406#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3411#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3436#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3435#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3418#L34 [2022-10-17 10:27:31,531 INFO L750 eck$LassoCheckResult]: Loop: 3418#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3419#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3417#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3418#L34 [2022-10-17 10:27:31,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:31,531 INFO L85 PathProgramCache]: Analyzing trace with hash -2004823653, now seen corresponding path program 16 times [2022-10-17 10:27:31,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:31,531 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071952548] [2022-10-17 10:27:31,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:31,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:31,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:31,630 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:31,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:31,697 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:31,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:31,698 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 10 times [2022-10-17 10:27:31,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:31,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720054901] [2022-10-17 10:27:31,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:31,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:31,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:31,703 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:31,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:31,722 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:31,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:31,727 INFO L85 PathProgramCache]: Analyzing trace with hash 113811419, now seen corresponding path program 17 times [2022-10-17 10:27:31,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:31,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771797293] [2022-10-17 10:27:31,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:31,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:31,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:32,318 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:32,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:32,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771797293] [2022-10-17 10:27:32,318 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771797293] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:32,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1443427778] [2022-10-17 10:27:32,318 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:27:32,318 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:32,319 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:32,320 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:32,353 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-10-17 10:27:32,580 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2022-10-17 10:27:32,580 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:32,582 INFO L263 TraceCheckSpWp]: Trace formula consists of 234 conjuncts, 22 conjunts are in the unsatisfiable core [2022-10-17 10:27:32,585 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:32,959 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:32,959 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:33,269 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:33,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1443427778] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:33,269 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:33,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2022-10-17 10:27:33,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1605113880] [2022-10-17 10:27:33,270 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:33,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:33,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2022-10-17 10:27:33,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2022-10-17 10:27:33,311 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:33,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:33,864 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2022-10-17 10:27:33,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2022-10-17 10:27:33,867 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:33,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2022-10-17 10:27:33,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2022-10-17 10:27:33,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2022-10-17 10:27:33,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2022-10-17 10:27:33,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:33,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2022-10-17 10:27:33,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2022-10-17 10:27:33,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2022-10-17 10:27:33,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:33,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2022-10-17 10:27:33,876 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-10-17 10:27:33,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:27:33,878 INFO L428 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2022-10-17 10:27:33,878 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:27:33,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2022-10-17 10:27:33,879 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:33,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:33,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:33,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2022-10-17 10:27:33,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:33,881 INFO L748 eck$LassoCheckResult]: Stem: 4100#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4106#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4120#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4121#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4109#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4110#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4141#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4140#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4139#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4138#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4137#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4136#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4135#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4134#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4133#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4132#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4131#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4130#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4129#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4128#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4124#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4123#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4111#L27-4 main_~i~0#1 := 0; 4112#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4186#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4149#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4154#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4184#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4181#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4179#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4178#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4175#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4173#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4172#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4169#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4167#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4166#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4161#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4160#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4159#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4158#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4157#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4117#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4119#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4146#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4145#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4126#L34 [2022-10-17 10:27:33,881 INFO L750 eck$LassoCheckResult]: Loop: 4126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4126#L34 [2022-10-17 10:27:33,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:33,882 INFO L85 PathProgramCache]: Analyzing trace with hash 1133441117, now seen corresponding path program 18 times [2022-10-17 10:27:33,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:33,882 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285461415] [2022-10-17 10:27:33,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:33,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:33,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:33,948 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:33,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:34,007 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:34,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:34,008 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 11 times [2022-10-17 10:27:34,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:34,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104725691] [2022-10-17 10:27:34,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:34,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:34,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:34,013 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:34,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:34,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:34,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:34,018 INFO L85 PathProgramCache]: Analyzing trace with hash -688524839, now seen corresponding path program 19 times [2022-10-17 10:27:34,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:34,018 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623421099] [2022-10-17 10:27:34,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:34,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:34,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:34,724 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:34,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:34,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1623421099] [2022-10-17 10:27:34,725 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1623421099] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:34,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [426670597] [2022-10-17 10:27:34,725 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-10-17 10:27:34,725 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:34,726 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:34,736 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:34,760 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-10-17 10:27:34,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:34,862 INFO L263 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-17 10:27:34,865 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:35,397 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:35,397 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:35,773 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:35,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [426670597] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:35,774 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:35,774 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2022-10-17 10:27:35,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920982055] [2022-10-17 10:27:35,774 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:35,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:35,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-10-17 10:27:35,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2022-10-17 10:27:35,834 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:36,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:36,486 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2022-10-17 10:27:36,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2022-10-17 10:27:36,490 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:36,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2022-10-17 10:27:36,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2022-10-17 10:27:36,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2022-10-17 10:27:36,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2022-10-17 10:27:36,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:36,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2022-10-17 10:27:36,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2022-10-17 10:27:36,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2022-10-17 10:27:36,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:36,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2022-10-17 10:27:36,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-10-17 10:27:36,500 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-10-17 10:27:36,501 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2022-10-17 10:27:36,501 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:27:36,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2022-10-17 10:27:36,502 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:36,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:36,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:36,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2022-10-17 10:27:36,504 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:36,504 INFO L748 eck$LassoCheckResult]: Stem: 4878#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4879#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4884#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4899#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4887#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4922#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4921#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4920#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4919#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4918#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4917#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4916#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4915#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4914#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4913#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4912#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4911#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4910#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4909#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4908#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4907#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4903#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4902#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4889#L27-4 main_~i~0#1 := 0; 4890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4931#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4935#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4972#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4969#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4967#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4966#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4963#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4961#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4960#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4957#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4955#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4954#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4951#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4949#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4948#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4945#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4943#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4942#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4896#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4883#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4893#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4898#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4905#L34 [2022-10-17 10:27:36,504 INFO L750 eck$LassoCheckResult]: Loop: 4905#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4906#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4904#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4905#L34 [2022-10-17 10:27:36,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:36,505 INFO L85 PathProgramCache]: Analyzing trace with hash 125280919, now seen corresponding path program 20 times [2022-10-17 10:27:36,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:36,506 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983408047] [2022-10-17 10:27:36,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:36,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:36,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:36,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:36,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:36,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:36,653 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:36,653 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 12 times [2022-10-17 10:27:36,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:36,653 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2005469471] [2022-10-17 10:27:36,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:36,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:36,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:36,658 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:36,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:36,662 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:36,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:36,663 INFO L85 PathProgramCache]: Analyzing trace with hash -82682529, now seen corresponding path program 21 times [2022-10-17 10:27:36,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:36,664 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703222623] [2022-10-17 10:27:36,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:36,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:36,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:37,337 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:37,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:37,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703222623] [2022-10-17 10:27:37,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703222623] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:37,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [139925326] [2022-10-17 10:27:37,338 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:27:37,338 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:37,339 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:37,343 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:37,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-10-17 10:27:37,734 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2022-10-17 10:27:37,734 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:37,738 INFO L263 TraceCheckSpWp]: Trace formula consists of 276 conjuncts, 26 conjunts are in the unsatisfiable core [2022-10-17 10:27:37,740 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:38,278 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:38,278 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:38,597 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:38,598 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [139925326] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:38,598 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:38,598 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2022-10-17 10:27:38,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [240787026] [2022-10-17 10:27:38,598 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:38,647 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:38,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2022-10-17 10:27:38,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2022-10-17 10:27:38,648 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:39,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:39,304 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2022-10-17 10:27:39,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2022-10-17 10:27:39,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:39,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2022-10-17 10:27:39,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2022-10-17 10:27:39,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2022-10-17 10:27:39,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2022-10-17 10:27:39,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:39,311 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2022-10-17 10:27:39,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2022-10-17 10:27:39,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2022-10-17 10:27:39,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:39,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2022-10-17 10:27:39,320 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-10-17 10:27:39,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2022-10-17 10:27:39,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2022-10-17 10:27:39,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:27:39,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2022-10-17 10:27:39,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:39,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:39,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:39,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2022-10-17 10:27:39,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:39,325 INFO L748 eck$LassoCheckResult]: Stem: 5725#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5726#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5770#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5769#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5768#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5765#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5764#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5763#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5748#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5736#L27-4 main_~i~0#1 := 0; 5737#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5780#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5779#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5783#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5827#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5824#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5822#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5821#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5816#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5815#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5810#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5809#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5806#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5804#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5803#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5800#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5798#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5797#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5794#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5792#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5791#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5789#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5787#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5786#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5730#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5744#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5775#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5774#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5751#L34 [2022-10-17 10:27:39,330 INFO L750 eck$LassoCheckResult]: Loop: 5751#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5750#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5751#L34 [2022-10-17 10:27:39,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:39,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1940425887, now seen corresponding path program 22 times [2022-10-17 10:27:39,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:39,332 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674731794] [2022-10-17 10:27:39,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:39,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:39,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:39,414 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:39,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:39,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:39,533 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:39,533 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 13 times [2022-10-17 10:27:39,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:39,533 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [759843736] [2022-10-17 10:27:39,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:39,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:39,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:39,538 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:39,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:39,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:39,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:39,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1262722987, now seen corresponding path program 23 times [2022-10-17 10:27:39,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:39,544 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692183157] [2022-10-17 10:27:39,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:39,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:39,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:40,435 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:40,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:40,435 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692183157] [2022-10-17 10:27:40,435 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692183157] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:27:40,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [526787285] [2022-10-17 10:27:40,436 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:27:40,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:27:40,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:40,441 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:27:40,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2a3d77c1-1c10-41f0-825e-7957fd9421e6/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-10-17 10:27:41,105 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2022-10-17 10:27:41,105 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:27:41,110 INFO L263 TraceCheckSpWp]: Trace formula consists of 297 conjuncts, 28 conjunts are in the unsatisfiable core [2022-10-17 10:27:41,113 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:27:41,781 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:41,781 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:27:42,193 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:42,193 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [526787285] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:27:42,194 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:27:42,194 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2022-10-17 10:27:42,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181724672] [2022-10-17 10:27:42,194 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:27:42,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:42,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2022-10-17 10:27:42,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2022-10-17 10:27:42,250 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:42,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:42,952 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2022-10-17 10:27:42,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2022-10-17 10:27:42,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:42,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2022-10-17 10:27:42,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2022-10-17 10:27:42,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2022-10-17 10:27:42,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2022-10-17 10:27:42,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:42,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2022-10-17 10:27:42,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2022-10-17 10:27:42,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2022-10-17 10:27:42,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:42,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2022-10-17 10:27:42,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-10-17 10:27:42,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2022-10-17 10:27:42,967 INFO L428 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2022-10-17 10:27:42,967 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2022-10-17 10:27:42,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2022-10-17 10:27:42,969 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2022-10-17 10:27:42,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:42,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:42,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2022-10-17 10:27:42,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-10-17 10:27:42,971 INFO L748 eck$LassoCheckResult]: Stem: 6641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6647#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6662#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6663#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6650#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6675#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6671#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6666#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6665#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6652#L27-4 main_~i~0#1 := 0; 6653#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6697#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6699#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6703#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6702#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6748#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6742#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6736#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6730#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6724#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6712#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6706#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6705#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6659#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6646#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6661#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6694#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6693#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6668#L34 [2022-10-17 10:27:42,971 INFO L750 eck$LassoCheckResult]: Loop: 6668#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6667#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6668#L34 [2022-10-17 10:27:42,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:42,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1264665709, now seen corresponding path program 24 times [2022-10-17 10:27:42,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:42,972 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575677811] [2022-10-17 10:27:42,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:42,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:43,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:43,075 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:43,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:43,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:43,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:43,147 INFO L85 PathProgramCache]: Analyzing trace with hash 69557, now seen corresponding path program 14 times [2022-10-17 10:27:43,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:43,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789947473] [2022-10-17 10:27:43,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:43,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:43,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:43,151 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:43,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:43,156 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:43,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:43,157 INFO L85 PathProgramCache]: Analyzing trace with hash -202976541, now seen corresponding path program 25 times [2022-10-17 10:27:43,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:43,157 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441983757] [2022-10-17 10:27:43,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:43,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:43,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat