./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:10:43,380 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:10:43,383 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:10:43,436 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:10:43,437 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:10:43,444 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:10:43,447 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:10:43,451 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:10:43,454 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:10:43,462 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:10:43,463 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:10:43,466 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:10:43,467 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:10:43,470 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:10:43,472 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:10:43,474 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:10:43,476 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:10:43,477 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:10:43,479 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:10:43,489 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:10:43,491 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:10:43,493 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:10:43,497 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:10:43,498 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:10:43,504 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:10:43,504 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:10:43,505 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:10:43,507 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:10:43,508 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:10:43,509 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:10:43,510 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:10:43,512 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:10:43,514 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:10:43,516 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:10:43,517 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:10:43,517 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:10:43,518 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:10:43,518 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:10:43,519 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:10:43,520 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:10:43,521 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:10:43,522 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:10:43,573 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:10:43,573 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:10:43,574 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:10:43,574 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:10:43,576 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:10:43,576 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:10:43,576 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:10:43,577 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:10:43,577 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:10:43,577 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:10:43,579 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:10:43,579 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:10:43,579 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:10:43,580 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:10:43,580 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:10:43,580 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:10:43,580 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:10:43,581 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:10:43,581 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:10:43,581 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:10:43,581 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:10:43,582 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:10:43,582 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:10:43,582 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:10:43,583 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:10:43,583 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:10:43,583 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:10:43,584 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:10:43,584 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:10:43,584 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:10:43,584 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:10:43,586 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:10:43,586 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2022-10-17 10:10:43,937 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:10:43,972 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:10:43,975 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:10:43,976 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:10:43,977 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:10:43,979 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-10-17 10:10:44,056 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/data/719531989/151ee82ad4d74259b8bc48c67d6f56b2/FLAGa548b1b0f [2022-10-17 10:10:44,654 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:10:44,656 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2022-10-17 10:10:44,665 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/data/719531989/151ee82ad4d74259b8bc48c67d6f56b2/FLAGa548b1b0f [2022-10-17 10:10:44,977 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/data/719531989/151ee82ad4d74259b8bc48c67d6f56b2 [2022-10-17 10:10:44,980 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:10:44,982 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:10:44,985 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:10:44,985 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:10:44,990 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:10:44,991 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:10:44" (1/1) ... [2022-10-17 10:10:44,992 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@42a1249c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:44, skipping insertion in model container [2022-10-17 10:10:44,992 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:10:44" (1/1) ... [2022-10-17 10:10:45,002 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:10:45,020 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:10:45,264 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-10-17 10:10:45,291 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:10:45,302 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:10:45,316 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/sv-benchmarks/c/loop-invgen/string_concat-noarr.i[893,906] [2022-10-17 10:10:45,319 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:10:45,336 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:10:45,337 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45 WrapperNode [2022-10-17 10:10:45,337 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:10:45,339 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:10:45,339 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:10:45,339 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:10:45,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,357 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,379 INFO L138 Inliner]: procedures = 16, calls = 7, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 51 [2022-10-17 10:10:45,380 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:10:45,381 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:10:45,381 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:10:45,381 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:10:45,392 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,392 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,394 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,394 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,398 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,403 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,404 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,405 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,407 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:10:45,408 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:10:45,408 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:10:45,408 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:10:45,409 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (1/1) ... [2022-10-17 10:10:45,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:45,440 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:45,455 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:45,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:10:45,513 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:10:45,513 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:10:45,513 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:10:45,514 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:10:45,590 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:10:45,593 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:10:45,822 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:10:45,829 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:10:45,833 INFO L300 CfgBuilder]: Removed 2 assume(true) statements. [2022-10-17 10:10:45,835 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:10:45 BoogieIcfgContainer [2022-10-17 10:10:45,835 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:10:45,837 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:10:45,837 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:10:45,844 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:10:45,845 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:10:45,845 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:10:44" (1/3) ... [2022-10-17 10:10:45,847 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4bf0a60a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:10:45, skipping insertion in model container [2022-10-17 10:10:45,847 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:10:45,847 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:10:45" (2/3) ... [2022-10-17 10:10:45,848 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4bf0a60a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:10:45, skipping insertion in model container [2022-10-17 10:10:45,848 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:10:45,848 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:10:45" (3/3) ... [2022-10-17 10:10:45,851 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2022-10-17 10:10:45,994 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:10:45,995 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:10:45,995 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:10:45,995 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:10:45,995 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:10:45,995 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:10:45,996 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:10:45,996 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:10:46,001 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:46,050 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-10-17 10:10:46,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:46,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:46,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-10-17 10:10:46,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:46,056 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:10:46,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:46,059 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3 [2022-10-17 10:10:46,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:46,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:46,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2022-10-17 10:10:46,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:46,085 INFO L748 eck$LassoCheckResult]: Stem: 3#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 4#L29-1true [2022-10-17 10:10:46,086 INFO L750 eck$LassoCheckResult]: Loop: 4#L29-1true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4#L29-1true [2022-10-17 10:10:46,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:46,093 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2022-10-17 10:10:46,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:46,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468649468] [2022-10-17 10:10:46,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:46,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:46,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,240 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:46,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,291 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:46,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:46,295 INFO L85 PathProgramCache]: Analyzing trace with hash 44, now seen corresponding path program 1 times [2022-10-17 10:10:46,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:46,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961639924] [2022-10-17 10:10:46,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:46,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:46,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,321 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:46,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:46,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:46,348 INFO L85 PathProgramCache]: Analyzing trace with hash 925580, now seen corresponding path program 1 times [2022-10-17 10:10:46,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:46,349 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210520060] [2022-10-17 10:10:46,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:46,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:46,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,361 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:46,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:46,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:46,496 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:10:46,497 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:10:46,497 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:10:46,497 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:10:46,497 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2022-10-17 10:10:46,498 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,498 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:10:46,498 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:10:46,498 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-10-17 10:10:46,499 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:10:46,499 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:10:46,518 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:46,530 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:46,536 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:46,603 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:10:46,604 INFO L404 LassoAnalysis]: Checking for nontermination... [2022-10-17 10:10:46,607 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,607 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:46,611 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:46,614 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:10:46,615 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:10:46,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2022-10-17 10:10:46,652 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:10:46,652 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~post2#1=0} Honda state: {ULTIMATE.start_main_#t~post2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:10:46,687 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:46,688 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,688 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:46,691 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:46,700 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:10:46,700 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:10:46,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2022-10-17 10:10:46,723 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2022-10-17 10:10:46,723 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_main_#t~nondet1#1=-1} Honda state: {ULTIMATE.start_main_#t~nondet1#1=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2022-10-17 10:10:46,769 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:46,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:46,771 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:46,778 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2022-10-17 10:10:46,778 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:10:46,792 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2022-10-17 10:10:46,851 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:46,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:46,855 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:46,862 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2022-10-17 10:10:46,862 INFO L160 nArgumentSynthesizer]: Using integer mode. [2022-10-17 10:10:46,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2022-10-17 10:10:46,918 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2022-10-17 10:10:46,924 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:46,924 INFO L210 LassoAnalysis]: Preferences: [2022-10-17 10:10:46,924 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2022-10-17 10:10:46,924 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2022-10-17 10:10:46,925 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2022-10-17 10:10:46,925 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2022-10-17 10:10:46,925 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:46,925 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2022-10-17 10:10:46,925 INFO L132 ssoRankerPreferences]: Path of dumped script: [2022-10-17 10:10:46,925 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2022-10-17 10:10:46,925 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2022-10-17 10:10:46,925 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2022-10-17 10:10:46,927 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:46,931 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:46,942 INFO L117 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2022-10-17 10:10:47,007 INFO L294 LassoAnalysis]: Preprocessing complete. [2022-10-17 10:10:47,013 INFO L490 LassoAnalysis]: Using template 'affine'. [2022-10-17 10:10:47,032 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:47,032 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:47,044 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:47,056 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:10:47,067 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:10:47,067 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:10:47,068 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:10:47,068 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:10:47,068 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:10:47,071 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:10:47,072 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:10:47,078 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2022-10-17 10:10:47,079 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2022-10-17 10:10:47,106 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:47,107 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:47,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:47,109 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:47,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2022-10-17 10:10:47,111 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2022-10-17 10:10:47,122 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2022-10-17 10:10:47,122 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2022-10-17 10:10:47,122 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2022-10-17 10:10:47,122 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2022-10-17 10:10:47,122 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2022-10-17 10:10:47,124 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2022-10-17 10:10:47,124 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2022-10-17 10:10:47,129 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2022-10-17 10:10:47,134 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2022-10-17 10:10:47,135 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2022-10-17 10:10:47,136 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:10:47,136 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:47,138 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:10:47,139 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2022-10-17 10:10:47,143 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2022-10-17 10:10:47,143 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2022-10-17 10:10:47,144 INFO L513 LassoAnalysis]: Proved termination. [2022-10-17 10:10:47,144 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2022-10-17 10:10:47,176 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:47,180 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2022-10-17 10:10:47,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:47,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:47,232 INFO L263 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 2 conjunts are in the unsatisfiable core [2022-10-17 10:10:47,234 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:47,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:47,251 WARN L261 TraceCheckSpWp]: Trace formula consists of 6 conjuncts, 4 conjunts are in the unsatisfiable core [2022-10-17 10:10:47,252 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:47,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:47,306 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2022-10-17 10:10:47,308 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:47,403 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2022-10-17 10:10:47,418 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 14 states, 13 states have (on average 1.5384615384615385) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 37 states and 56 transitions. Complement of second has 5 states. [2022-10-17 10:10:47,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2022-10-17 10:10:47,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 2.0) internal successors, (4), 2 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:47,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 37 transitions. [2022-10-17 10:10:47,428 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 1 letters. [2022-10-17 10:10:47,429 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:10:47,430 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 4 letters. Loop has 1 letters. [2022-10-17 10:10:47,430 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:10:47,430 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 37 transitions. Stem has 3 letters. Loop has 2 letters. [2022-10-17 10:10:47,430 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2022-10-17 10:10:47,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 56 transitions. [2022-10-17 10:10:47,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:47,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 13 states and 19 transitions. [2022-10-17 10:10:47,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:47,449 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2022-10-17 10:10:47,449 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 19 transitions. [2022-10-17 10:10:47,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:47,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-10-17 10:10:47,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 19 transitions. [2022-10-17 10:10:47,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2022-10-17 10:10:47,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.5) internal successors, (18), 11 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:47,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 18 transitions. [2022-10-17 10:10:47,488 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-10-17 10:10:47,488 INFO L428 stractBuchiCegarLoop]: Abstraction has 12 states and 18 transitions. [2022-10-17 10:10:47,488 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:10:47,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 18 transitions. [2022-10-17 10:10:47,490 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:47,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:47,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:47,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2022-10-17 10:10:47,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:47,491 INFO L748 eck$LassoCheckResult]: Stem: 89#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 90#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 96#L26 main_~i~0#1 := 0; 91#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 93#L29-2 assume main_~i~0#1 >= 100; 95#L39 [2022-10-17 10:10:47,491 INFO L750 eck$LassoCheckResult]: Loop: 95#L39 assume true; 95#L39 [2022-10-17 10:10:47,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:47,492 INFO L85 PathProgramCache]: Analyzing trace with hash 28692937, now seen corresponding path program 1 times [2022-10-17 10:10:47,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:47,492 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428274015] [2022-10-17 10:10:47,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:47,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:47,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:47,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:47,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:47,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428274015] [2022-10-17 10:10:47,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428274015] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:10:47,556 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:10:47,556 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:10:47,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883143102] [2022-10-17 10:10:47,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:10:47,559 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:47,559 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:47,560 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 1 times [2022-10-17 10:10:47,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:47,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381783238] [2022-10-17 10:10:47,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:47,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:47,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:47,563 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:47,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:47,566 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:47,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:47,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:10:47,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:10:47,589 INFO L87 Difference]: Start difference. First operand 12 states and 18 transitions. cyclomatic complexity: 9 Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:47,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:47,620 INFO L93 Difference]: Finished difference Result 18 states and 24 transitions. [2022-10-17 10:10:47,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 24 transitions. [2022-10-17 10:10:47,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2022-10-17 10:10:47,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 18 states and 24 transitions. [2022-10-17 10:10:47,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2022-10-17 10:10:47,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2022-10-17 10:10:47,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 24 transitions. [2022-10-17 10:10:47,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:47,624 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 24 transitions. [2022-10-17 10:10:47,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 24 transitions. [2022-10-17 10:10:47,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 13. [2022-10-17 10:10:47,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 12 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:47,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 19 transitions. [2022-10-17 10:10:47,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-10-17 10:10:47,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:10:47,632 INFO L428 stractBuchiCegarLoop]: Abstraction has 13 states and 19 transitions. [2022-10-17 10:10:47,632 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:10:47,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 19 transitions. [2022-10-17 10:10:47,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:47,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:47,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:47,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2022-10-17 10:10:47,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:47,637 INFO L748 eck$LassoCheckResult]: Stem: 125#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 133#L26 main_~i~0#1 := 0; 127#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 130#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 131#L29-2 assume main_~i~0#1 >= 100; 132#L39 [2022-10-17 10:10:47,637 INFO L750 eck$LassoCheckResult]: Loop: 132#L39 assume true; 132#L39 [2022-10-17 10:10:47,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:47,638 INFO L85 PathProgramCache]: Analyzing trace with hash 889482740, now seen corresponding path program 1 times [2022-10-17 10:10:47,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:47,638 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144239204] [2022-10-17 10:10:47,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:47,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:47,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:47,752 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:47,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:47,752 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2144239204] [2022-10-17 10:10:47,753 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2144239204] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:47,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1733058547] [2022-10-17 10:10:47,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:47,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:47,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:47,760 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:47,782 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-10-17 10:10:47,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:47,807 INFO L263 TraceCheckSpWp]: Trace formula consists of 30 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:10:47,809 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:47,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:47,864 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:47,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:47,918 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1733058547] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:47,918 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:47,918 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-10-17 10:10:47,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364345558] [2022-10-17 10:10:47,919 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:47,919 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:47,919 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:47,920 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 2 times [2022-10-17 10:10:47,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:47,920 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159134836] [2022-10-17 10:10:47,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:47,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:47,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:47,923 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:47,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:47,926 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:47,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:47,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:10:47,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:10:47,937 INFO L87 Difference]: Start difference. First operand 13 states and 19 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 2.0) internal successors, (12), 7 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:48,028 INFO L93 Difference]: Finished difference Result 40 states and 55 transitions. [2022-10-17 10:10:48,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 55 transitions. [2022-10-17 10:10:48,038 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2022-10-17 10:10:48,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 40 states and 55 transitions. [2022-10-17 10:10:48,040 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2022-10-17 10:10:48,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2022-10-17 10:10:48,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 55 transitions. [2022-10-17 10:10:48,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:48,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40 states and 55 transitions. [2022-10-17 10:10:48,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 55 transitions. [2022-10-17 10:10:48,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 16. [2022-10-17 10:10:48,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 15 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 28 transitions. [2022-10-17 10:10:48,048 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-10-17 10:10:48,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:10:48,052 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 28 transitions. [2022-10-17 10:10:48,052 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:10:48,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 28 transitions. [2022-10-17 10:10:48,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:48,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:48,055 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:10:48,055 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:48,055 INFO L748 eck$LassoCheckResult]: Stem: 218#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 219#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 226#L26 main_~i~0#1 := 0; 220#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 222#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 214#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 215#L35-2 assume main_~j~0#1 >= 100; 225#L39 [2022-10-17 10:10:48,055 INFO L750 eck$LassoCheckResult]: Loop: 225#L39 assume true; 225#L39 [2022-10-17 10:10:48,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,057 INFO L85 PathProgramCache]: Analyzing trace with hash 1804112500, now seen corresponding path program 1 times [2022-10-17 10:10:48,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869252922] [2022-10-17 10:10:48,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:48,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:48,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869252922] [2022-10-17 10:10:48,130 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869252922] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:10:48,130 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:10:48,130 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:10:48,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1216448641] [2022-10-17 10:10:48,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:10:48,131 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:48,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,132 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 3 times [2022-10-17 10:10:48,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,132 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621432095] [2022-10-17 10:10:48,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,135 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:48,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:48,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:48,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:10:48,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:10:48,141 INFO L87 Difference]: Start difference. First operand 16 states and 28 transitions. cyclomatic complexity: 15 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:48,148 INFO L93 Difference]: Finished difference Result 17 states and 28 transitions. [2022-10-17 10:10:48,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 28 transitions. [2022-10-17 10:10:48,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 14 states and 21 transitions. [2022-10-17 10:10:48,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:48,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:10:48,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 21 transitions. [2022-10-17 10:10:48,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:48,151 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-10-17 10:10:48,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 21 transitions. [2022-10-17 10:10:48,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-10-17 10:10:48,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5) internal successors, (21), 13 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 21 transitions. [2022-10-17 10:10:48,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-10-17 10:10:48,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:10:48,156 INFO L428 stractBuchiCegarLoop]: Abstraction has 14 states and 21 transitions. [2022-10-17 10:10:48,156 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:10:48,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 21 transitions. [2022-10-17 10:10:48,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:48,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:48,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:10:48,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:48,158 INFO L748 eck$LassoCheckResult]: Stem: 255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 263#L26 main_~i~0#1 := 0; 257#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 258#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 253#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 254#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 261#L35-2 assume main_~j~0#1 >= 100; 262#L39 [2022-10-17 10:10:48,159 INFO L750 eck$LassoCheckResult]: Loop: 262#L39 assume true; 262#L39 [2022-10-17 10:10:48,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,159 INFO L85 PathProgramCache]: Analyzing trace with hash 92914363, now seen corresponding path program 1 times [2022-10-17 10:10:48,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,160 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323153829] [2022-10-17 10:10:48,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:48,208 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:48,209 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323153829] [2022-10-17 10:10:48,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323153829] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:48,210 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [378663655] [2022-10-17 10:10:48,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:48,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:48,211 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:48,218 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-10-17 10:10:48,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:48,264 INFO L263 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 3 conjunts are in the unsatisfiable core [2022-10-17 10:10:48,266 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:48,288 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,289 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:48,314 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [378663655] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:48,315 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:48,315 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2022-10-17 10:10:48,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561549090] [2022-10-17 10:10:48,316 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:48,317 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:48,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,318 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 4 times [2022-10-17 10:10:48,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,319 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580554014] [2022-10-17 10:10:48,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,323 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:48,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,328 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:48,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:48,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-10-17 10:10:48,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2022-10-17 10:10:48,334 INFO L87 Difference]: Start difference. First operand 14 states and 21 transitions. cyclomatic complexity: 10 Second operand has 7 states, 6 states have (on average 2.3333333333333335) internal successors, (14), 7 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:48,357 INFO L93 Difference]: Finished difference Result 20 states and 27 transitions. [2022-10-17 10:10:48,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 27 transitions. [2022-10-17 10:10:48,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 17 states and 24 transitions. [2022-10-17 10:10:48,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:48,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:10:48,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 24 transitions. [2022-10-17 10:10:48,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:48,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-10-17 10:10:48,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 24 transitions. [2022-10-17 10:10:48,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-10-17 10:10:48,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.411764705882353) internal successors, (24), 16 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 24 transitions. [2022-10-17 10:10:48,368 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-10-17 10:10:48,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:10:48,372 INFO L428 stractBuchiCegarLoop]: Abstraction has 17 states and 24 transitions. [2022-10-17 10:10:48,372 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:10:48,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 24 transitions. [2022-10-17 10:10:48,374 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:48,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:48,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1] [2022-10-17 10:10:48,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:48,376 INFO L748 eck$LassoCheckResult]: Stem: 341#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 349#L26 main_~i~0#1 := 0; 343#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 345#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 346#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 354#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 352#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 350#L29-2 assume main_~i~0#1 >= 100; 348#L39 [2022-10-17 10:10:48,376 INFO L750 eck$LassoCheckResult]: Loop: 348#L39 assume true; 348#L39 [2022-10-17 10:10:48,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,377 INFO L85 PathProgramCache]: Analyzing trace with hash -1366227831, now seen corresponding path program 2 times [2022-10-17 10:10:48,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,378 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109580722] [2022-10-17 10:10:48,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:48,517 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:48,527 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109580722] [2022-10-17 10:10:48,528 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109580722] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:48,528 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1594257303] [2022-10-17 10:10:48,529 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:10:48,529 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:48,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:48,563 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:48,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-10-17 10:10:48,613 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:10:48,613 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:48,614 INFO L263 TraceCheckSpWp]: Trace formula consists of 42 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:10:48,616 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:48,645 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,646 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:48,740 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:48,740 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1594257303] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:48,741 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:48,741 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-10-17 10:10:48,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795058062] [2022-10-17 10:10:48,743 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:48,743 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:48,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,744 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 5 times [2022-10-17 10:10:48,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981984011] [2022-10-17 10:10:48,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:48,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:48,764 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:48,767 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:48,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:10:48,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:10:48,771 INFO L87 Difference]: Start difference. First operand 17 states and 24 transitions. cyclomatic complexity: 10 Second operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:48,953 INFO L93 Difference]: Finished difference Result 90 states and 109 transitions. [2022-10-17 10:10:48,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 109 transitions. [2022-10-17 10:10:48,966 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2022-10-17 10:10:48,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 84 states and 103 transitions. [2022-10-17 10:10:48,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2022-10-17 10:10:48,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2022-10-17 10:10:48,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 103 transitions. [2022-10-17 10:10:48,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:48,970 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84 states and 103 transitions. [2022-10-17 10:10:48,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 103 transitions. [2022-10-17 10:10:48,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 23. [2022-10-17 10:10:48,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.565217391304348) internal successors, (36), 22 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:48,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 36 transitions. [2022-10-17 10:10:48,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-10-17 10:10:48,976 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:10:48,977 INFO L428 stractBuchiCegarLoop]: Abstraction has 23 states and 36 transitions. [2022-10-17 10:10:48,977 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:10:48,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 36 transitions. [2022-10-17 10:10:48,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:48,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:48,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:48,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:10:48,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:48,984 INFO L748 eck$LassoCheckResult]: Stem: 512#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 520#L26 main_~i~0#1 := 0; 514#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 515#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 510#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 511#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 532#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 531#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 530#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 518#L35-2 assume main_~j~0#1 >= 100; 519#L39 [2022-10-17 10:10:48,984 INFO L750 eck$LassoCheckResult]: Loop: 519#L39 assume true; 519#L39 [2022-10-17 10:10:48,984 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:48,984 INFO L85 PathProgramCache]: Analyzing trace with hash 2054548532, now seen corresponding path program 2 times [2022-10-17 10:10:48,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:48,984 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125255228] [2022-10-17 10:10:48,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:48,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:48,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:49,090 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:49,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:49,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125255228] [2022-10-17 10:10:49,091 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125255228] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:49,091 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [359573631] [2022-10-17 10:10:49,091 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-10-17 10:10:49,092 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:49,092 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:49,100 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:49,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-10-17 10:10:49,151 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-10-17 10:10:49,151 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:49,152 INFO L263 TraceCheckSpWp]: Trace formula consists of 54 conjuncts, 6 conjunts are in the unsatisfiable core [2022-10-17 10:10:49,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:49,189 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:49,189 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:49,287 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:49,287 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [359573631] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:49,287 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:49,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2022-10-17 10:10:49,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951767446] [2022-10-17 10:10:49,288 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:49,288 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:49,289 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:49,289 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 6 times [2022-10-17 10:10:49,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:49,289 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842224254] [2022-10-17 10:10:49,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:49,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:49,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:49,292 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:49,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:49,295 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:49,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:49,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-10-17 10:10:49,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2022-10-17 10:10:49,299 INFO L87 Difference]: Start difference. First operand 23 states and 36 transitions. cyclomatic complexity: 16 Second operand has 13 states, 12 states have (on average 1.6666666666666667) internal successors, (20), 13 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:49,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:49,334 INFO L93 Difference]: Finished difference Result 35 states and 48 transitions. [2022-10-17 10:10:49,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 48 transitions. [2022-10-17 10:10:49,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:49,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 29 states and 42 transitions. [2022-10-17 10:10:49,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:49,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:10:49,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 42 transitions. [2022-10-17 10:10:49,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:49,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-10-17 10:10:49,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 42 transitions. [2022-10-17 10:10:49,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2022-10-17 10:10:49,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.4482758620689655) internal successors, (42), 28 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:49,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2022-10-17 10:10:49,349 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-10-17 10:10:49,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-10-17 10:10:49,353 INFO L428 stractBuchiCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-10-17 10:10:49,353 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:10:49,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 42 transitions. [2022-10-17 10:10:49,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:49,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:49,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:49,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1] [2022-10-17 10:10:49,357 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:49,357 INFO L748 eck$LassoCheckResult]: Stem: 646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 647#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 654#L26 main_~i~0#1 := 0; 648#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 650#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 651#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 669#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 667#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 665#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 663#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 661#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 660#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 659#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 657#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 655#L29-2 assume main_~i~0#1 >= 100; 653#L39 [2022-10-17 10:10:49,357 INFO L750 eck$LassoCheckResult]: Loop: 653#L39 assume true; 653#L39 [2022-10-17 10:10:49,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:49,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1329396905, now seen corresponding path program 3 times [2022-10-17 10:10:49,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:49,362 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082502401] [2022-10-17 10:10:49,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:49,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:49,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:49,664 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:49,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:49,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082502401] [2022-10-17 10:10:49,665 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082502401] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:49,665 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [574209822] [2022-10-17 10:10:49,665 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:10:49,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:49,666 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:49,668 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:49,690 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-10-17 10:10:49,718 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-10-17 10:10:49,719 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:49,720 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-17 10:10:49,722 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:49,778 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:49,778 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:50,048 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:50,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [574209822] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:50,048 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:50,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-10-17 10:10:50,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848377858] [2022-10-17 10:10:50,049 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:50,051 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:50,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:50,051 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 7 times [2022-10-17 10:10:50,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:50,052 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856604720] [2022-10-17 10:10:50,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:50,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:50,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:50,054 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:50,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:50,056 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:50,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:50,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-10-17 10:10:50,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-10-17 10:10:50,060 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. cyclomatic complexity: 16 Second operand has 25 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:50,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:50,359 INFO L93 Difference]: Finished difference Result 285 states and 322 transitions. [2022-10-17 10:10:50,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 285 states and 322 transitions. [2022-10-17 10:10:50,364 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2022-10-17 10:10:50,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 285 states to 273 states and 310 transitions. [2022-10-17 10:10:50,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2022-10-17 10:10:50,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2022-10-17 10:10:50,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 310 transitions. [2022-10-17 10:10:50,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:50,375 INFO L218 hiAutomatonCegarLoop]: Abstraction has 273 states and 310 transitions. [2022-10-17 10:10:50,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 310 transitions. [2022-10-17 10:10:50,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 41. [2022-10-17 10:10:50,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.6097560975609757) internal successors, (66), 40 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:50,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 66 transitions. [2022-10-17 10:10:50,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-10-17 10:10:50,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:10:50,403 INFO L428 stractBuchiCegarLoop]: Abstraction has 41 states and 66 transitions. [2022-10-17 10:10:50,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:10:50,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 66 transitions. [2022-10-17 10:10:50,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:50,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:50,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:50,407 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:10:50,407 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:50,408 INFO L748 eck$LassoCheckResult]: Stem: 1072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1080#L26 main_~i~0#1 := 0; 1074#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1075#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1070#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1071#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1110#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1109#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1108#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1107#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1106#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1105#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1104#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1103#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1102#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1078#L35-2 assume main_~j~0#1 >= 100; 1079#L39 [2022-10-17 10:10:50,408 INFO L750 eck$LassoCheckResult]: Loop: 1079#L39 assume true; 1079#L39 [2022-10-17 10:10:50,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:50,409 INFO L85 PathProgramCache]: Analyzing trace with hash -719352108, now seen corresponding path program 3 times [2022-10-17 10:10:50,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:50,409 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198392129] [2022-10-17 10:10:50,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:50,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:50,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:50,634 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:50,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:50,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198392129] [2022-10-17 10:10:50,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198392129] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:50,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1247828332] [2022-10-17 10:10:50,636 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-10-17 10:10:50,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:50,636 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:50,639 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:50,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-10-17 10:10:50,684 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-10-17 10:10:50,685 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:50,686 INFO L263 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 12 conjunts are in the unsatisfiable core [2022-10-17 10:10:50,688 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:50,725 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:50,726 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:50,975 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:50,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1247828332] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:50,975 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:50,976 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2022-10-17 10:10:50,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1829639260] [2022-10-17 10:10:50,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:50,977 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:50,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:50,977 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 8 times [2022-10-17 10:10:50,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:50,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781039832] [2022-10-17 10:10:50,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:50,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:50,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:50,980 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:50,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:50,982 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:50,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:50,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2022-10-17 10:10:50,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2022-10-17 10:10:50,986 INFO L87 Difference]: Start difference. First operand 41 states and 66 transitions. cyclomatic complexity: 28 Second operand has 25 states, 24 states have (on average 1.3333333333333333) internal successors, (32), 25 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:51,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:51,025 INFO L93 Difference]: Finished difference Result 65 states and 90 transitions. [2022-10-17 10:10:51,025 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 90 transitions. [2022-10-17 10:10:51,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:51,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 53 states and 78 transitions. [2022-10-17 10:10:51,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:51,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:10:51,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 78 transitions. [2022-10-17 10:10:51,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:51,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-10-17 10:10:51,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 78 transitions. [2022-10-17 10:10:51,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2022-10-17 10:10:51,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.471698113207547) internal successors, (78), 52 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:51,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 78 transitions. [2022-10-17 10:10:51,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-10-17 10:10:51,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-10-17 10:10:51,032 INFO L428 stractBuchiCegarLoop]: Abstraction has 53 states and 78 transitions. [2022-10-17 10:10:51,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:10:51,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 78 transitions. [2022-10-17 10:10:51,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:51,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:51,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:51,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1] [2022-10-17 10:10:51,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:51,035 INFO L748 eck$LassoCheckResult]: Stem: 1302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1310#L26 main_~i~0#1 := 0; 1304#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1306#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1307#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1352#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1351#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1349#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1347#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1345#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1343#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1341#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1339#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1337#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1335#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1333#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1331#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1329#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1327#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1325#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1323#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1321#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1319#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1315#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1313#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1311#L29-2 assume main_~i~0#1 >= 100; 1309#L39 [2022-10-17 10:10:51,035 INFO L750 eck$LassoCheckResult]: Loop: 1309#L39 assume true; 1309#L39 [2022-10-17 10:10:51,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:51,036 INFO L85 PathProgramCache]: Analyzing trace with hash -525392663, now seen corresponding path program 4 times [2022-10-17 10:10:51,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:51,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667175247] [2022-10-17 10:10:51,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:51,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:51,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:51,482 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:51,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:51,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667175247] [2022-10-17 10:10:51,483 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667175247] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:51,483 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [572564954] [2022-10-17 10:10:51,483 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:10:51,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:51,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:51,491 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:51,510 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-10-17 10:10:51,540 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:10:51,540 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:51,541 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-17 10:10:51,544 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:51,597 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:51,597 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:52,359 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:52,360 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [572564954] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:52,360 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:52,360 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-10-17 10:10:52,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426927027] [2022-10-17 10:10:52,360 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:52,361 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:52,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:52,361 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 9 times [2022-10-17 10:10:52,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:52,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281749708] [2022-10-17 10:10:52,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:52,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:52,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:52,364 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:52,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:52,366 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:52,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:52,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-10-17 10:10:52,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-10-17 10:10:52,371 INFO L87 Difference]: Start difference. First operand 53 states and 78 transitions. cyclomatic complexity: 28 Second operand has 49 states, 48 states have (on average 1.125) internal successors, (54), 49 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:53,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:53,002 INFO L93 Difference]: Finished difference Result 999 states and 1072 transitions. [2022-10-17 10:10:53,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 999 states and 1072 transitions. [2022-10-17 10:10:53,012 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2022-10-17 10:10:53,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 999 states to 975 states and 1048 transitions. [2022-10-17 10:10:53,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2022-10-17 10:10:53,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2022-10-17 10:10:53,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 975 states and 1048 transitions. [2022-10-17 10:10:53,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:53,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 975 states and 1048 transitions. [2022-10-17 10:10:53,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 975 states and 1048 transitions. [2022-10-17 10:10:53,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 975 to 77. [2022-10-17 10:10:53,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.6363636363636365) internal successors, (126), 76 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:53,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 126 transitions. [2022-10-17 10:10:53,044 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-10-17 10:10:53,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-10-17 10:10:53,045 INFO L428 stractBuchiCegarLoop]: Abstraction has 77 states and 126 transitions. [2022-10-17 10:10:53,045 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:10:53,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 126 transitions. [2022-10-17 10:10:53,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:53,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:53,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:53,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:10:53,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:53,050 INFO L748 eck$LassoCheckResult]: Stem: 2562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2570#L26 main_~i~0#1 := 0; 2564#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2565#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 2560#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2561#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2636#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2635#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2634#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2633#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2632#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2631#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2630#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2629#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2628#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2627#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2626#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2625#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2624#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2623#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2622#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2621#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2620#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2619#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2618#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2617#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 2616#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 2568#L35-2 assume main_~j~0#1 >= 100; 2569#L39 [2022-10-17 10:10:53,050 INFO L750 eck$LassoCheckResult]: Loop: 2569#L39 assume true; 2569#L39 [2022-10-17 10:10:53,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:53,053 INFO L85 PathProgramCache]: Analyzing trace with hash 798452756, now seen corresponding path program 4 times [2022-10-17 10:10:53,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:53,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951989181] [2022-10-17 10:10:53,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:53,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:53,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:53,576 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:53,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:53,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951989181] [2022-10-17 10:10:53,576 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951989181] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:53,576 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [394613026] [2022-10-17 10:10:53,577 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-10-17 10:10:53,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:53,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:53,583 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:53,599 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-10-17 10:10:53,651 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-10-17 10:10:53,651 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:53,652 INFO L263 TraceCheckSpWp]: Trace formula consists of 162 conjuncts, 24 conjunts are in the unsatisfiable core [2022-10-17 10:10:53,655 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:53,753 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:53,753 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:54,618 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:54,619 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [394613026] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:54,619 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:54,619 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2022-10-17 10:10:54,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [911841718] [2022-10-17 10:10:54,619 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:54,620 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:54,620 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:54,620 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 10 times [2022-10-17 10:10:54,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:54,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277976208] [2022-10-17 10:10:54,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:54,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:54,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:54,626 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:54,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:54,628 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:54,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:54,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-10-17 10:10:54,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2022-10-17 10:10:54,635 INFO L87 Difference]: Start difference. First operand 77 states and 126 transitions. cyclomatic complexity: 52 Second operand has 49 states, 48 states have (on average 1.1666666666666667) internal successors, (56), 49 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:54,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:10:54,735 INFO L93 Difference]: Finished difference Result 125 states and 174 transitions. [2022-10-17 10:10:54,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125 states and 174 transitions. [2022-10-17 10:10:54,737 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:54,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125 states to 101 states and 150 transitions. [2022-10-17 10:10:54,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:10:54,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:10:54,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 150 transitions. [2022-10-17 10:10:54,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:10:54,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-10-17 10:10:54,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 150 transitions. [2022-10-17 10:10:54,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2022-10-17 10:10:54,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.4851485148514851) internal successors, (150), 100 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:10:54,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 150 transitions. [2022-10-17 10:10:54,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-10-17 10:10:54,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2022-10-17 10:10:54,757 INFO L428 stractBuchiCegarLoop]: Abstraction has 101 states and 150 transitions. [2022-10-17 10:10:54,757 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2022-10-17 10:10:54,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 150 transitions. [2022-10-17 10:10:54,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:10:54,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:10:54,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:10:54,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1] [2022-10-17 10:10:54,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:10:54,762 INFO L748 eck$LassoCheckResult]: Stem: 2984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2992#L26 main_~i~0#1 := 0; 2986#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2988#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2989#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3082#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3081#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3079#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3077#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3075#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3073#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3071#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3069#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3067#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3065#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3063#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3061#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3059#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3057#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3055#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3053#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3051#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3049#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3047#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3045#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3043#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3041#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3039#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3037#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3035#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3033#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3031#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3029#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3027#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3025#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3023#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3021#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3019#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3017#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3015#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3013#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3011#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3009#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3007#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3005#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3003#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3001#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2997#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2995#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2993#L29-2 assume main_~i~0#1 >= 100; 2991#L39 [2022-10-17 10:10:54,766 INFO L750 eck$LassoCheckResult]: Loop: 2991#L39 assume true; 2991#L39 [2022-10-17 10:10:54,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:54,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1685345641, now seen corresponding path program 5 times [2022-10-17 10:10:54,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:54,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318639787] [2022-10-17 10:10:54,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:54,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:54,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:10:56,581 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:56,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:10:56,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318639787] [2022-10-17 10:10:56,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318639787] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:10:56,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [62387075] [2022-10-17 10:10:56,582 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:10:56,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:10:56,582 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:10:56,584 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:10:56,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-10-17 10:10:56,662 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-10-17 10:10:56,663 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:10:56,665 INFO L263 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 48 conjunts are in the unsatisfiable core [2022-10-17 10:10:56,669 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:10:56,812 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:56,812 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:10:59,427 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:10:59,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [62387075] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:10:59,428 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:10:59,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-10-17 10:10:59,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303214632] [2022-10-17 10:10:59,429 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:10:59,430 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:10:59,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:10:59,430 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 11 times [2022-10-17 10:10:59,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:10:59,431 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162496733] [2022-10-17 10:10:59,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:10:59,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:10:59,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:59,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:10:59,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:10:59,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:10:59,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:10:59,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-10-17 10:10:59,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-10-17 10:10:59,451 INFO L87 Difference]: Start difference. First operand 101 states and 150 transitions. cyclomatic complexity: 52 Second operand has 97 states, 96 states have (on average 1.0625) internal successors, (102), 97 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:11:01,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:11:01,626 INFO L93 Difference]: Finished difference Result 3723 states and 3868 transitions. [2022-10-17 10:11:01,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3723 states and 3868 transitions. [2022-10-17 10:11:01,667 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2022-10-17 10:11:01,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3723 states to 3675 states and 3820 transitions. [2022-10-17 10:11:01,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103 [2022-10-17 10:11:01,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103 [2022-10-17 10:11:01,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3675 states and 3820 transitions. [2022-10-17 10:11:01,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:11:01,703 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3675 states and 3820 transitions. [2022-10-17 10:11:01,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3675 states and 3820 transitions. [2022-10-17 10:11:01,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3675 to 149. [2022-10-17 10:11:01,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 149 states have (on average 1.651006711409396) internal successors, (246), 148 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:11:01,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 246 transitions. [2022-10-17 10:11:01,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-10-17 10:11:01,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-10-17 10:11:01,728 INFO L428 stractBuchiCegarLoop]: Abstraction has 149 states and 246 transitions. [2022-10-17 10:11:01,728 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2022-10-17 10:11:01,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 149 states and 246 transitions. [2022-10-17 10:11:01,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:11:01,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:11:01,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:11:01,731 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [46, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:11:01,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:11:01,732 INFO L748 eck$LassoCheckResult]: Stem: 7208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 7209#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 7216#L26 main_~i~0#1 := 0; 7210#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 7211#L29-2 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 7206#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7207#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7354#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7353#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7352#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7351#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7350#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7349#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7348#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7347#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7346#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7345#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7344#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7343#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7342#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7341#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7340#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7339#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7338#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7337#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7336#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7335#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7334#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7333#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7332#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7331#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7330#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7329#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7328#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7327#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7326#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7325#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7324#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7323#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7322#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7321#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7320#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7319#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7318#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7317#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7316#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7315#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7314#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7313#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7312#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7311#L35-1 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 7310#L35-1 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 7214#L35-2 assume main_~j~0#1 >= 100; 7215#L39 [2022-10-17 10:11:01,732 INFO L750 eck$LassoCheckResult]: Loop: 7215#L39 assume true; 7215#L39 [2022-10-17 10:11:01,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:11:01,733 INFO L85 PathProgramCache]: Analyzing trace with hash 821134996, now seen corresponding path program 5 times [2022-10-17 10:11:01,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:11:01,733 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447619579] [2022-10-17 10:11:01,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:11:01,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:11:01,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:11:03,198 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:11:03,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:11:03,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447619579] [2022-10-17 10:11:03,199 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447619579] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:11:03,199 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2118319512] [2022-10-17 10:11:03,199 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-10-17 10:11:03,199 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:11:03,199 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:11:03,204 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:11:03,221 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-10-17 10:11:03,305 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-10-17 10:11:03,306 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:11:03,308 INFO L263 TraceCheckSpWp]: Trace formula consists of 306 conjuncts, 48 conjunts are in the unsatisfiable core [2022-10-17 10:11:03,312 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:11:03,435 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:11:03,435 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-10-17 10:11:05,998 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:11:05,999 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2118319512] provided 0 perfect and 2 imperfect interpolant sequences [2022-10-17 10:11:05,999 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-10-17 10:11:05,999 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2022-10-17 10:11:05,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855975712] [2022-10-17 10:11:05,999 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-10-17 10:11:06,000 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:11:06,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:11:06,000 INFO L85 PathProgramCache]: Analyzing trace with hash 84, now seen corresponding path program 12 times [2022-10-17 10:11:06,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:11:06,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251892352] [2022-10-17 10:11:06,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:11:06,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:11:06,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:11:06,003 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:11:06,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:11:06,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:11:06,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:11:06,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2022-10-17 10:11:06,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2022-10-17 10:11:06,016 INFO L87 Difference]: Start difference. First operand 149 states and 246 transitions. cyclomatic complexity: 100 Second operand has 97 states, 96 states have (on average 1.0833333333333333) internal successors, (104), 97 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:11:06,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:11:06,229 INFO L93 Difference]: Finished difference Result 245 states and 342 transitions. [2022-10-17 10:11:06,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 342 transitions. [2022-10-17 10:11:06,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:11:06,233 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 197 states and 294 transitions. [2022-10-17 10:11:06,233 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2022-10-17 10:11:06,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2022-10-17 10:11:06,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 294 transitions. [2022-10-17 10:11:06,234 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2022-10-17 10:11:06,234 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-10-17 10:11:06,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 294 transitions. [2022-10-17 10:11:06,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2022-10-17 10:11:06,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197 states, 197 states have (on average 1.4923857868020305) internal successors, (294), 196 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:11:06,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 294 transitions. [2022-10-17 10:11:06,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-10-17 10:11:06,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2022-10-17 10:11:06,240 INFO L428 stractBuchiCegarLoop]: Abstraction has 197 states and 294 transitions. [2022-10-17 10:11:06,241 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2022-10-17 10:11:06,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197 states and 294 transitions. [2022-10-17 10:11:06,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2022-10-17 10:11:06,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:11:06,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:11:06,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [94, 1, 1, 1, 1, 1] [2022-10-17 10:11:06,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2022-10-17 10:11:06,245 INFO L748 eck$LassoCheckResult]: Stem: 8014#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 8015#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 8022#L26 main_~i~0#1 := 0; 8016#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8018#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8019#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8208#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8207#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8205#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8203#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8201#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8199#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8197#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8195#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8193#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8191#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8189#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8187#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8185#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8183#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8181#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8179#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8177#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8175#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8173#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8171#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8169#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8167#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8165#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8163#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8161#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8159#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8157#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8155#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8153#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8151#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8149#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8147#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8145#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8143#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8141#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8139#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8137#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8135#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8133#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8131#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8129#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8127#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8125#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8123#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8121#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8119#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8117#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8115#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8113#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8111#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8109#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8107#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8105#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8103#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8101#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8099#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8097#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8095#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8093#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8091#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8089#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8087#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8085#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8083#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8081#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8079#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8077#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8075#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8073#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8071#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8069#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8067#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8065#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8063#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8061#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8059#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8057#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8055#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8053#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8051#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8049#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8047#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8045#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8043#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8041#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8039#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8037#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8035#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8033#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8031#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8027#L29-1 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8025#L29-1 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 8023#L29-2 assume main_~i~0#1 >= 100; 8021#L39 [2022-10-17 10:11:06,245 INFO L750 eck$LassoCheckResult]: Loop: 8021#L39 assume true; 8021#L39 [2022-10-17 10:11:06,246 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:11:06,246 INFO L85 PathProgramCache]: Analyzing trace with hash -415091095, now seen corresponding path program 6 times [2022-10-17 10:11:06,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:11:06,246 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825595126] [2022-10-17 10:11:06,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:11:06,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:11:06,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:11:10,772 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:11:10,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:11:10,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825595126] [2022-10-17 10:11:10,772 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825595126] provided 0 perfect and 1 imperfect interpolant sequences [2022-10-17 10:11:10,772 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261722054] [2022-10-17 10:11:10,773 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-10-17 10:11:10,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-10-17 10:11:10,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:11:10,774 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-10-17 10:11:10,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b4226970-c714-41c0-82d3-648fac7e1246/bin/uautomizer-J5u9QxTXDZ/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-10-17 10:11:10,958 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 48 check-sat command(s) [2022-10-17 10:11:10,959 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-10-17 10:11:10,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 402 conjuncts, 96 conjunts are in the unsatisfiable core [2022-10-17 10:11:10,968 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-10-17 10:11:11,202 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:11:11,203 INFO L328 TraceCheckSpWp]: Computing backward predicates...