./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.01.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.01.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:27:10,376 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:27:10,378 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:27:10,428 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:27:10,429 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:27:10,434 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:27:10,437 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:27:10,444 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:27:10,447 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:27:10,453 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:27:10,455 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:27:10,458 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:27:10,458 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:27:10,461 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:27:10,464 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:27:10,466 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:27:10,468 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:27:10,470 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:27:10,473 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:27:10,482 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:27:10,484 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:27:10,486 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:27:10,491 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:27:10,492 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:27:10,505 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:27:10,505 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:27:10,506 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:27:10,509 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:27:10,509 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:27:10,512 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:27:10,513 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:27:10,515 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:27:10,517 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:27:10,519 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:27:10,520 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:27:10,520 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:27:10,521 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:27:10,522 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:27:10,522 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:27:10,523 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:27:10,524 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:27:10,525 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:27:10,585 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:27:10,587 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:27:10,588 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:27:10,588 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:27:10,590 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:27:10,590 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:27:10,591 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:27:10,591 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:27:10,591 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:27:10,591 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:27:10,593 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:27:10,593 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:27:10,593 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:27:10,594 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:27:10,594 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:27:10,594 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:27:10,595 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:27:10,595 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:27:10,595 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:27:10,595 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:27:10,596 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:27:10,596 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:27:10,620 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:27:10,620 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:27:10,620 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:27:10,621 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:27:10,621 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:27:10,621 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:27:10,621 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:27:10,622 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:27:10,622 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:27:10,624 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:27:10,624 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 [2022-10-17 10:27:10,934 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:27:10,962 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:27:10,965 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:27:10,967 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:27:10,971 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:27:10,973 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2022-10-17 10:27:11,055 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/data/4a65dfb09/6393d37daa734fd0a1d7ffb9bca596f2/FLAG7c274b246 [2022-10-17 10:27:11,654 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:27:11,655 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2022-10-17 10:27:11,671 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/data/4a65dfb09/6393d37daa734fd0a1d7ffb9bca596f2/FLAG7c274b246 [2022-10-17 10:27:11,948 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/data/4a65dfb09/6393d37daa734fd0a1d7ffb9bca596f2 [2022-10-17 10:27:11,951 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:27:11,953 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:27:11,955 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:27:11,956 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:27:11,960 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:27:11,961 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:27:11" (1/1) ... [2022-10-17 10:27:11,963 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e83795d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:11, skipping insertion in model container [2022-10-17 10:27:11,963 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:27:11" (1/1) ... [2022-10-17 10:27:11,972 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:27:12,040 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:27:12,271 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2022-10-17 10:27:12,339 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:27:12,368 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:27:12,388 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2022-10-17 10:27:12,414 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:27:12,434 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:27:12,435 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12 WrapperNode [2022-10-17 10:27:12,435 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:27:12,437 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:27:12,437 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:27:12,437 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:27:12,447 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,466 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,524 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 38, statements flattened = 405 [2022-10-17 10:27:12,525 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:27:12,526 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:27:12,526 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:27:12,526 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:27:12,537 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,537 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,542 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,543 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,564 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,574 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,577 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,579 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,585 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:27:12,586 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:27:12,586 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:27:12,586 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:27:12,600 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (1/1) ... [2022-10-17 10:27:12,607 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:27:12,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:27:12,667 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:27:12,683 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:27:12,736 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:27:12,736 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:27:12,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:27:12,737 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:27:12,876 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:27:12,879 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:27:13,573 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:27:13,601 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:27:13,602 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-10-17 10:27:13,604 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:27:13 BoogieIcfgContainer [2022-10-17 10:27:13,605 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:27:13,606 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:27:13,606 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:27:13,626 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:27:13,627 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:13,627 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:27:11" (1/3) ... [2022-10-17 10:27:13,628 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61eab6d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:27:13, skipping insertion in model container [2022-10-17 10:27:13,628 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:13,629 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:27:12" (2/3) ... [2022-10-17 10:27:13,629 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@61eab6d6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:27:13, skipping insertion in model container [2022-10-17 10:27:13,629 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:27:13,629 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:27:13" (3/3) ... [2022-10-17 10:27:13,631 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.01.cil-1.c [2022-10-17 10:27:13,729 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:27:13,729 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:27:13,729 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:27:13,729 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:27:13,729 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:27:13,729 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:27:13,730 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:27:13,730 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:27:13,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:13,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2022-10-17 10:27:13,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:13,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:13,784 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:13,784 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:13,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:27:13,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:13,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2022-10-17 10:27:13,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:13,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:13,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:13,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:13,816 INFO L748 eck$LassoCheckResult]: Stem: 139#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 97#L391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59#L163true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76#L170true assume !(1 == ~m_i~0);~m_st~0 := 2; 56#L170-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 140#L175-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78#L259true assume !(0 == ~M_E~0); 135#L259-2true assume !(0 == ~T1_E~0); 95#L264-1true assume !(0 == ~E_M~0); 113#L269-1true assume !(0 == ~E_1~0); 88#L274-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L124true assume 1 == ~m_pc~0; 99#L125true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 126#L135true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19#L136true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 153#L319true assume !(0 != activate_threads_~tmp~1#1); 20#L319-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118#L143true assume 1 == ~t1_pc~0; 7#L144true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 103#L154true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55#L155true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27#L327true assume !(0 != activate_threads_~tmp___0~0#1); 42#L327-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73#L287true assume !(1 == ~M_E~0); 105#L287-2true assume !(1 == ~T1_E~0); 38#L292-1true assume !(1 == ~E_M~0); 41#L297-1true assume !(1 == ~E_1~0); 28#L302-1true assume { :end_inline_reset_delta_events } true; 53#L428-2true [2022-10-17 10:27:13,821 INFO L750 eck$LassoCheckResult]: Loop: 53#L428-2true assume !false; 92#L429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79#L234true assume false; 5#L249true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25#L163-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144#L259-3true assume 0 == ~M_E~0;~M_E~0 := 1; 137#L259-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 112#L264-3true assume 0 == ~E_M~0;~E_M~0 := 1; 17#L269-3true assume 0 == ~E_1~0;~E_1~0 := 1; 66#L274-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13#L124-9true assume !(1 == ~m_pc~0); 101#L124-11true is_master_triggered_~__retres1~0#1 := 0; 71#L135-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24#L136-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 89#L319-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50#L319-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64#L143-9true assume !(1 == ~t1_pc~0); 26#L143-11true is_transmit1_triggered_~__retres1~1#1 := 0; 65#L154-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16#L155-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 115#L327-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152#L327-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 141#L287-3true assume !(1 == ~M_E~0); 74#L287-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 82#L292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 86#L297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 6#L302-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 129#L188-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 30#L200-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 110#L201-1true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 37#L447true assume !(0 == start_simulation_~tmp~3#1); 107#L447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8#L188-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 98#L200-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 133#L201-2true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 100#L402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143#L409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117#L410true start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 67#L460true assume !(0 != start_simulation_~tmp___0~1#1); 53#L428-2true [2022-10-17 10:27:13,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:13,832 INFO L85 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2022-10-17 10:27:13,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:13,848 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119696753] [2022-10-17 10:27:13,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:13,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:13,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,184 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119696753] [2022-10-17 10:27:14,185 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119696753] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,186 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,187 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:14,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359310132] [2022-10-17 10:27:14,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,203 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:27:14,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:14,207 INFO L85 PathProgramCache]: Analyzing trace with hash -791617431, now seen corresponding path program 1 times [2022-10-17 10:27:14,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:14,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598750496] [2022-10-17 10:27:14,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:14,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:14,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,273 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598750496] [2022-10-17 10:27:14,273 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598750496] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,274 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:27:14,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678533990] [2022-10-17 10:27:14,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,276 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:14,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:14,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:14,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:14,321 INFO L87 Difference]: Start difference. First operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:14,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:14,357 INFO L93 Difference]: Finished difference Result 151 states and 219 transitions. [2022-10-17 10:27:14,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 219 transitions. [2022-10-17 10:27:14,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2022-10-17 10:27:14,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 146 states and 214 transitions. [2022-10-17 10:27:14,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2022-10-17 10:27:14,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2022-10-17 10:27:14,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 214 transitions. [2022-10-17 10:27:14,378 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:14,378 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-10-17 10:27:14,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 214 transitions. [2022-10-17 10:27:14,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2022-10-17 10:27:14,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:14,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 214 transitions. [2022-10-17 10:27:14,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-10-17 10:27:14,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:14,434 INFO L428 stractBuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-10-17 10:27:14,435 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:27:14,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 214 transitions. [2022-10-17 10:27:14,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2022-10-17 10:27:14,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:14,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:14,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:14,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:14,442 INFO L748 eck$LassoCheckResult]: Stem: 456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 396#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 408#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 409#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 404#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 424#L259 assume !(0 == ~M_E~0); 425#L259-2 assume !(0 == ~T1_E~0); 441#L264-1 assume !(0 == ~E_M~0); 442#L269-1 assume !(0 == ~E_1~0); 435#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436#L124 assume 1 == ~m_pc~0; 437#L125 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 416#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 345#L319 assume !(0 != activate_threads_~tmp~1#1); 346#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L143 assume 1 == ~t1_pc~0; 326#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 403#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 360#L327 assume !(0 != activate_threads_~tmp___0~0#1); 361#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 384#L287 assume !(1 == ~M_E~0); 423#L287-2 assume !(1 == ~T1_E~0); 379#L292-1 assume !(1 == ~E_M~0); 380#L297-1 assume !(1 == ~E_1~0); 362#L302-1 assume { :end_inline_reset_delta_events } true; 363#L428-2 [2022-10-17 10:27:14,443 INFO L750 eck$LassoCheckResult]: Loop: 363#L428-2 assume !false; 401#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L234 assume !false; 426#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 348#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 349#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 418#L215 assume !(0 != eval_~tmp~0#1); 319#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 320#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 355#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 455#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 447#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 342#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332#L124-9 assume 1 == ~m_pc~0; 333#L125-3 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 368#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 354#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398#L143-9 assume !(1 == ~t1_pc~0); 356#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 357#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 338#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 449#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457#L287-3 assume !(1 == ~M_E~0); 421#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 422#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 432#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 318#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 358#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 359#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 376#L447 assume !(0 == start_simulation_~tmp~3#1); 377#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 321#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 322#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 443#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 444#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 445#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 450#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 414#L460 assume !(0 != start_simulation_~tmp___0~1#1); 363#L428-2 [2022-10-17 10:27:14,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:14,444 INFO L85 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2022-10-17 10:27:14,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:14,445 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552637351] [2022-10-17 10:27:14,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:14,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:14,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552637351] [2022-10-17 10:27:14,538 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552637351] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,539 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,539 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:27:14,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290514405] [2022-10-17 10:27:14,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,540 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:27:14,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:14,541 INFO L85 PathProgramCache]: Analyzing trace with hash -1897027051, now seen corresponding path program 1 times [2022-10-17 10:27:14,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:14,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718266461] [2022-10-17 10:27:14,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:14,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:14,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718266461] [2022-10-17 10:27:14,621 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718266461] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,621 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,621 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:14,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388873548] [2022-10-17 10:27:14,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,623 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:14,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:14,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:14,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:14,624 INFO L87 Difference]: Start difference. First operand 146 states and 214 transitions. cyclomatic complexity: 69 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:14,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:14,691 INFO L93 Difference]: Finished difference Result 253 states and 362 transitions. [2022-10-17 10:27:14,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253 states and 362 transitions. [2022-10-17 10:27:14,696 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 222 [2022-10-17 10:27:14,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253 states to 253 states and 362 transitions. [2022-10-17 10:27:14,707 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253 [2022-10-17 10:27:14,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253 [2022-10-17 10:27:14,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253 states and 362 transitions. [2022-10-17 10:27:14,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:14,715 INFO L218 hiAutomatonCegarLoop]: Abstraction has 253 states and 362 transitions. [2022-10-17 10:27:14,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states and 362 transitions. [2022-10-17 10:27:14,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 240. [2022-10-17 10:27:14,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:14,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 345 transitions. [2022-10-17 10:27:14,751 INFO L240 hiAutomatonCegarLoop]: Abstraction has 240 states and 345 transitions. [2022-10-17 10:27:14,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:14,753 INFO L428 stractBuchiCegarLoop]: Abstraction has 240 states and 345 transitions. [2022-10-17 10:27:14,753 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:27:14,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 240 states and 345 transitions. [2022-10-17 10:27:14,757 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 209 [2022-10-17 10:27:14,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:14,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:14,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:14,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:14,767 INFO L748 eck$LassoCheckResult]: Stem: 876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 804#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 818#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 819#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 814#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 815#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 836#L259 assume !(0 == ~M_E~0); 837#L259-2 assume !(0 == ~T1_E~0); 855#L264-1 assume !(0 == ~E_M~0); 856#L269-1 assume !(0 == ~E_1~0); 849#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 850#L124 assume !(1 == ~m_pc~0); 826#L124-2 is_master_triggered_~__retres1~0#1 := 0; 827#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 749#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 750#L319 assume !(0 != activate_threads_~tmp~1#1); 751#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 752#L143 assume 1 == ~t1_pc~0; 732#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 733#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 767#L327 assume !(0 != activate_threads_~tmp___0~0#1); 768#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 791#L287 assume !(1 == ~M_E~0); 835#L287-2 assume !(1 == ~T1_E~0); 786#L292-1 assume !(1 == ~E_M~0); 787#L297-1 assume !(1 == ~E_1~0); 769#L302-1 assume { :end_inline_reset_delta_events } true; 770#L428-2 [2022-10-17 10:27:14,767 INFO L750 eck$LassoCheckResult]: Loop: 770#L428-2 assume !false; 915#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 843#L234 assume !false; 844#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 753#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 754#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 828#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 829#L215 assume !(0 != eval_~tmp~0#1); 725#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 726#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 760#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 875#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 862#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 746#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 747#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 738#L124-9 assume !(1 == ~m_pc~0); 739#L124-11 is_master_triggered_~__retres1~0#1 := 0; 957#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 956#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 955#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 954#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L143-9 assume !(1 == ~t1_pc~0); 951#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 950#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 744#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 745#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 865#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877#L287-3 assume !(1 == ~M_E~0); 833#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 834#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 845#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 723#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 724#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 765#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 766#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 783#L447 assume !(0 == start_simulation_~tmp~3#1); 784#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 928#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 925#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 924#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 923#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 922#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 918#L460 assume !(0 != start_simulation_~tmp___0~1#1); 770#L428-2 [2022-10-17 10:27:14,769 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:14,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2022-10-17 10:27:14,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:14,770 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465718583] [2022-10-17 10:27:14,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:14,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:14,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465718583] [2022-10-17 10:27:14,895 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465718583] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,895 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,895 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:14,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157744030] [2022-10-17 10:27:14,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,896 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:27:14,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:14,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 1 times [2022-10-17 10:27:14,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:14,898 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035771185] [2022-10-17 10:27:14,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:14,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:14,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:14,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:14,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:14,986 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2035771185] [2022-10-17 10:27:14,986 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2035771185] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:14,986 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:14,987 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:14,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780317405] [2022-10-17 10:27:14,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:14,988 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:14,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:14,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:27:14,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:27:14,989 INFO L87 Difference]: Start difference. First operand 240 states and 345 transitions. cyclomatic complexity: 107 Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:15,111 INFO L93 Difference]: Finished difference Result 512 states and 719 transitions. [2022-10-17 10:27:15,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 719 transitions. [2022-10-17 10:27:15,118 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 461 [2022-10-17 10:27:15,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 719 transitions. [2022-10-17 10:27:15,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2022-10-17 10:27:15,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2022-10-17 10:27:15,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 719 transitions. [2022-10-17 10:27:15,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:15,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 512 states and 719 transitions. [2022-10-17 10:27:15,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 719 transitions. [2022-10-17 10:27:15,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 407. [2022-10-17 10:27:15,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 580 transitions. [2022-10-17 10:27:15,195 INFO L240 hiAutomatonCegarLoop]: Abstraction has 407 states and 580 transitions. [2022-10-17 10:27:15,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:27:15,199 INFO L428 stractBuchiCegarLoop]: Abstraction has 407 states and 580 transitions. [2022-10-17 10:27:15,199 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:27:15,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 580 transitions. [2022-10-17 10:27:15,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-10-17 10:27:15,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:15,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:15,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,206 INFO L748 eck$LassoCheckResult]: Stem: 1641#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1567#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1580#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 1575#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1576#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L259 assume !(0 == ~M_E~0); 1597#L259-2 assume !(0 == ~T1_E~0); 1618#L264-1 assume !(0 == ~E_M~0); 1619#L269-1 assume !(0 == ~E_1~0); 1612#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1613#L124 assume !(1 == ~m_pc~0); 1586#L124-2 is_master_triggered_~__retres1~0#1 := 0; 1587#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1511#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1512#L319 assume !(0 != activate_threads_~tmp~1#1); 1513#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1514#L143 assume !(1 == ~t1_pc~0); 1497#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1498#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1574#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1529#L327 assume !(0 != activate_threads_~tmp___0~0#1); 1530#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L287 assume !(1 == ~M_E~0); 1595#L287-2 assume !(1 == ~T1_E~0); 1546#L292-1 assume !(1 == ~E_M~0); 1547#L297-1 assume !(1 == ~E_1~0); 1531#L302-1 assume { :end_inline_reset_delta_events } true; 1532#L428-2 [2022-10-17 10:27:15,207 INFO L750 eck$LassoCheckResult]: Loop: 1532#L428-2 assume !false; 1572#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1592#L234 assume !false; 1598#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1515#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1516#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1589#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1590#L215 assume !(0 != eval_~tmp~0#1); 1643#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1886#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1885#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1884#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1883#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1882#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1881#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1868#L124-9 assume !(1 == ~m_pc~0); 1623#L124-11 is_master_triggered_~__retres1~0#1 := 0; 1588#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1520#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1521#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1568#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569#L143-9 assume !(1 == ~t1_pc~0); 1523#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1524#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1506#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1507#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1626#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642#L287-3 assume !(1 == ~M_E~0); 1593#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1594#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1604#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1487#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1488#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1527#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1528#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1543#L447 assume !(0 == start_simulation_~tmp~3#1); 1544#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1489#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1490#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1620#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1621#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1622#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1628#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1585#L460 assume !(0 != start_simulation_~tmp___0~1#1); 1532#L428-2 [2022-10-17 10:27:15,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,208 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2022-10-17 10:27:15,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,209 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662812700] [2022-10-17 10:27:15,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:15,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:15,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:15,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:15,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 2 times [2022-10-17 10:27:15,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,305 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [849290272] [2022-10-17 10:27:15,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:15,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:15,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:15,396 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [849290272] [2022-10-17 10:27:15,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [849290272] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:15,401 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:15,402 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:15,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669610130] [2022-10-17 10:27:15,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:15,408 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:15,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:15,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:15,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:15,411 INFO L87 Difference]: Start difference. First operand 407 states and 580 transitions. cyclomatic complexity: 175 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:15,449 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2022-10-17 10:27:15,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 496 states and 698 transitions. [2022-10-17 10:27:15,455 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2022-10-17 10:27:15,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 496 states to 496 states and 698 transitions. [2022-10-17 10:27:15,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 496 [2022-10-17 10:27:15,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 496 [2022-10-17 10:27:15,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 496 states and 698 transitions. [2022-10-17 10:27:15,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:15,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-10-17 10:27:15,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states and 698 transitions. [2022-10-17 10:27:15,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 496. [2022-10-17 10:27:15,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 698 transitions. [2022-10-17 10:27:15,491 INFO L240 hiAutomatonCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-10-17 10:27:15,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:15,493 INFO L428 stractBuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-10-17 10:27:15,493 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:27:15,493 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 698 transitions. [2022-10-17 10:27:15,498 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2022-10-17 10:27:15,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:15,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:15,500 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,500 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,500 INFO L748 eck$LassoCheckResult]: Stem: 2562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2474#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2475#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2488#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2489#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 2484#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2485#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2507#L259 assume 0 == ~M_E~0;~M_E~0 := 1; 2508#L259-2 assume !(0 == ~T1_E~0); 2646#L264-1 assume !(0 == ~E_M~0); 2644#L269-1 assume !(0 == ~E_1~0); 2642#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2641#L124 assume !(1 == ~m_pc~0); 2640#L124-2 is_master_triggered_~__retres1~0#1 := 0; 2639#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2635#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2634#L319 assume !(0 != activate_threads_~tmp~1#1); 2632#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2631#L143 assume !(1 == ~t1_pc~0); 2628#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2626#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2624#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2614#L327 assume !(0 != activate_threads_~tmp___0~0#1); 2459#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2460#L287 assume 1 == ~M_E~0;~M_E~0 := 2; 2506#L287-2 assume !(1 == ~T1_E~0); 2454#L292-1 assume !(1 == ~E_M~0); 2455#L297-1 assume !(1 == ~E_1~0); 2439#L302-1 assume { :end_inline_reset_delta_events } true; 2440#L428-2 [2022-10-17 10:27:15,501 INFO L750 eck$LassoCheckResult]: Loop: 2440#L428-2 assume !false; 2845#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2549#L234 assume !false; 2844#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2842#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2841#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2680#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2678#L215 assume !(0 != eval_~tmp~0#1); 2679#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2839#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2836#L259-3 assume !(0 == ~M_E~0); 2834#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2832#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2830#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2828#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2826#L124-9 assume !(1 == ~m_pc~0); 2825#L124-11 is_master_triggered_~__retres1~0#1 := 0; 2824#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2823#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2525#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2526#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2822#L143-9 assume !(1 == ~t1_pc~0); 2790#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2818#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2815#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2807#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2808#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L287-3 assume !(1 == ~M_E~0); 2564#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2516#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2517#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2394#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2395#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2810#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2809#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2451#L447 assume !(0 == start_simulation_~tmp~3#1); 2452#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2853#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2851#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2850#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2849#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2848#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2847#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2846#L460 assume !(0 != start_simulation_~tmp___0~1#1); 2440#L428-2 [2022-10-17 10:27:15,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,502 INFO L85 PathProgramCache]: Analyzing trace with hash 175996037, now seen corresponding path program 1 times [2022-10-17 10:27:15,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,502 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144229420] [2022-10-17 10:27:15,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:15,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:15,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:15,539 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144229420] [2022-10-17 10:27:15,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144229420] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:15,540 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:15,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:27:15,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653306118] [2022-10-17 10:27:15,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:15,541 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:27:15,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,542 INFO L85 PathProgramCache]: Analyzing trace with hash -817717740, now seen corresponding path program 1 times [2022-10-17 10:27:15,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464721585] [2022-10-17 10:27:15,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:15,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:15,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:15,644 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464721585] [2022-10-17 10:27:15,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464721585] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:15,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:15,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:27:15,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790942868] [2022-10-17 10:27:15,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:15,646 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:15,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:15,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:15,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:15,647 INFO L87 Difference]: Start difference. First operand 496 states and 698 transitions. cyclomatic complexity: 204 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:15,667 INFO L93 Difference]: Finished difference Result 407 states and 566 transitions. [2022-10-17 10:27:15,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407 states and 566 transitions. [2022-10-17 10:27:15,672 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-10-17 10:27:15,677 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407 states to 407 states and 566 transitions. [2022-10-17 10:27:15,677 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407 [2022-10-17 10:27:15,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2022-10-17 10:27:15,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 566 transitions. [2022-10-17 10:27:15,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:15,681 INFO L218 hiAutomatonCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-10-17 10:27:15,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 566 transitions. [2022-10-17 10:27:15,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 407. [2022-10-17 10:27:15,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 566 transitions. [2022-10-17 10:27:15,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-10-17 10:27:15,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:15,698 INFO L428 stractBuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-10-17 10:27:15,699 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:27:15,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 566 transitions. [2022-10-17 10:27:15,702 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-10-17 10:27:15,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:15,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:15,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:15,706 INFO L748 eck$LassoCheckResult]: Stem: 3479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 3386#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3387#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3402#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3403#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 3398#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3399#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3424#L259 assume !(0 == ~M_E~0); 3425#L259-2 assume !(0 == ~T1_E~0); 3449#L264-1 assume !(0 == ~E_M~0); 3450#L269-1 assume !(0 == ~E_1~0); 3440#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3441#L124 assume !(1 == ~m_pc~0); 3411#L124-2 is_master_triggered_~__retres1~0#1 := 0; 3412#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3332#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3333#L319 assume !(0 != activate_threads_~tmp~1#1); 3334#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3335#L143 assume !(1 == ~t1_pc~0); 3319#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3320#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3397#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3350#L327 assume !(0 != activate_threads_~tmp___0~0#1); 3351#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3374#L287 assume !(1 == ~M_E~0); 3420#L287-2 assume !(1 == ~T1_E~0); 3369#L292-1 assume !(1 == ~E_M~0); 3370#L297-1 assume !(1 == ~E_1~0); 3352#L302-1 assume { :end_inline_reset_delta_events } true; 3353#L428-2 [2022-10-17 10:27:15,707 INFO L750 eck$LassoCheckResult]: Loop: 3353#L428-2 assume !false; 3445#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3417#L234 assume !false; 3646#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3644#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3643#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3642#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3483#L215 assume !(0 != eval_~tmp~0#1); 3306#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3307#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3343#L259-3 assume !(0 == ~M_E~0); 3478#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3458#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3330#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3331#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3321#L124-9 assume !(1 == ~m_pc~0); 3322#L124-11 is_master_triggered_~__retres1~0#1 := 0; 3415#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3341#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3342#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3442#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3408#L143-9 assume !(1 == ~t1_pc~0); 3344#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 3345#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3325#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3326#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3459#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3480#L287-3 assume !(1 == ~M_E~0); 3418#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3419#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3433#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3308#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3309#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3346#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3347#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3366#L447 assume !(0 == start_simulation_~tmp~3#1); 3367#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3310#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3311#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3651#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 3453#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3454#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3461#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 3410#L460 assume !(0 != start_simulation_~tmp___0~1#1); 3353#L428-2 [2022-10-17 10:27:15,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,708 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2022-10-17 10:27:15,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,708 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840600648] [2022-10-17 10:27:15,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:15,722 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:15,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:15,746 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:15,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:15,747 INFO L85 PathProgramCache]: Analyzing trace with hash -817717740, now seen corresponding path program 2 times [2022-10-17 10:27:15,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:15,748 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664468716] [2022-10-17 10:27:15,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:15,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:15,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:15,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:15,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:15,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664468716] [2022-10-17 10:27:15,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664468716] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:15,816 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:15,819 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:27:15,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005855597] [2022-10-17 10:27:15,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:15,820 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:15,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:15,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:27:15,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:27:15,828 INFO L87 Difference]: Start difference. First operand 407 states and 566 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:15,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:15,963 INFO L93 Difference]: Finished difference Result 693 states and 942 transitions. [2022-10-17 10:27:15,966 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 942 transitions. [2022-10-17 10:27:15,975 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 660 [2022-10-17 10:27:15,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 942 transitions. [2022-10-17 10:27:15,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2022-10-17 10:27:15,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2022-10-17 10:27:15,984 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 942 transitions. [2022-10-17 10:27:15,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:15,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 942 transitions. [2022-10-17 10:27:15,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 942 transitions. [2022-10-17 10:27:15,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 419. [2022-10-17 10:27:15,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 578 transitions. [2022-10-17 10:27:16,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 419 states and 578 transitions. [2022-10-17 10:27:16,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:27:16,005 INFO L428 stractBuchiCegarLoop]: Abstraction has 419 states and 578 transitions. [2022-10-17 10:27:16,005 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:27:16,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 578 transitions. [2022-10-17 10:27:16,009 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2022-10-17 10:27:16,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,012 INFO L748 eck$LassoCheckResult]: Stem: 4583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 4500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4501#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4516#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4517#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 4512#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4513#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4536#L259 assume !(0 == ~M_E~0); 4537#L259-2 assume !(0 == ~T1_E~0); 4558#L264-1 assume !(0 == ~E_M~0); 4559#L269-1 assume !(0 == ~E_1~0); 4553#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4554#L124 assume !(1 == ~m_pc~0); 4525#L124-2 is_master_triggered_~__retres1~0#1 := 0; 4526#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4448#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4449#L319 assume !(0 != activate_threads_~tmp~1#1); 4450#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4451#L143 assume !(1 == ~t1_pc~0); 4434#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4435#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4511#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4466#L327 assume !(0 != activate_threads_~tmp___0~0#1); 4467#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4488#L287 assume !(1 == ~M_E~0); 4535#L287-2 assume !(1 == ~T1_E~0); 4483#L292-1 assume !(1 == ~E_M~0); 4484#L297-1 assume !(1 == ~E_1~0); 4468#L302-1 assume { :end_inline_reset_delta_events } true; 4469#L428-2 [2022-10-17 10:27:16,012 INFO L750 eck$LassoCheckResult]: Loop: 4469#L428-2 assume !false; 4691#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4676#L234 assume !false; 4674#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4671#L188 assume !(0 == ~m_st~0); 4667#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4663#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4654#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4653#L215 assume !(0 != eval_~tmp~0#1); 4652#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4651#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4650#L259-3 assume !(0 == ~M_E~0); 4649#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4648#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4444#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4445#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4436#L124-9 assume !(1 == ~m_pc~0); 4437#L124-11 is_master_triggered_~__retres1~0#1 := 0; 4527#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4457#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4458#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4504#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4505#L143-9 assume !(1 == ~t1_pc~0); 4730#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4770#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4769#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4768#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4767#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4766#L287-3 assume !(1 == ~M_E~0); 4765#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4764#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4763#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4762#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4761#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4758#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4756#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 4753#L447 assume !(0 == start_simulation_~tmp~3#1); 4750#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4749#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4731#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4706#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 4704#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4702#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4700#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4698#L460 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L428-2 [2022-10-17 10:27:16,013 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,013 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2022-10-17 10:27:16,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,013 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094654049] [2022-10-17 10:27:16,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:16,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,048 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:16,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,050 INFO L85 PathProgramCache]: Analyzing trace with hash 56440981, now seen corresponding path program 1 times [2022-10-17 10:27:16,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658283415] [2022-10-17 10:27:16,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:16,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:16,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:16,231 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658283415] [2022-10-17 10:27:16,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658283415] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:16,231 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:16,231 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:27:16,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902005593] [2022-10-17 10:27:16,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:16,233 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:16,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:16,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:27:16,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:27:16,234 INFO L87 Difference]: Start difference. First operand 419 states and 578 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:16,366 INFO L93 Difference]: Finished difference Result 792 states and 1077 transitions. [2022-10-17 10:27:16,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1077 transitions. [2022-10-17 10:27:16,374 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 761 [2022-10-17 10:27:16,387 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1077 transitions. [2022-10-17 10:27:16,387 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2022-10-17 10:27:16,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2022-10-17 10:27:16,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1077 transitions. [2022-10-17 10:27:16,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:16,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 792 states and 1077 transitions. [2022-10-17 10:27:16,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1077 transitions. [2022-10-17 10:27:16,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 440. [2022-10-17 10:27:16,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 593 transitions. [2022-10-17 10:27:16,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 440 states and 593 transitions. [2022-10-17 10:27:16,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:27:16,409 INFO L428 stractBuchiCegarLoop]: Abstraction has 440 states and 593 transitions. [2022-10-17 10:27:16,409 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:27:16,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 440 states and 593 transitions. [2022-10-17 10:27:16,413 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 409 [2022-10-17 10:27:16,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,417 INFO L748 eck$LassoCheckResult]: Stem: 5815#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 5725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5726#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5743#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5744#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 5738#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5739#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5764#L259 assume !(0 == ~M_E~0); 5765#L259-2 assume !(0 == ~T1_E~0); 5786#L264-1 assume !(0 == ~E_M~0); 5787#L269-1 assume !(0 == ~E_1~0); 5780#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5781#L124 assume !(1 == ~m_pc~0); 5752#L124-2 is_master_triggered_~__retres1~0#1 := 0; 5753#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5672#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5673#L319 assume !(0 != activate_threads_~tmp~1#1); 5674#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5675#L143 assume !(1 == ~t1_pc~0); 5658#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5659#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5737#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5686#L327 assume !(0 != activate_threads_~tmp___0~0#1); 5687#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5712#L287 assume !(1 == ~M_E~0); 5760#L287-2 assume !(1 == ~T1_E~0); 5707#L292-1 assume !(1 == ~E_M~0); 5708#L297-1 assume !(1 == ~E_1~0); 5688#L302-1 assume { :end_inline_reset_delta_events } true; 5689#L428-2 [2022-10-17 10:27:16,418 INFO L750 eck$LassoCheckResult]: Loop: 5689#L428-2 assume !false; 5866#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5867#L234 assume !false; 5862#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5863#L188 assume !(0 == ~m_st~0); 5856#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 5858#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5852#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5853#L215 assume !(0 != eval_~tmp~0#1); 5847#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5848#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5843#L259-3 assume !(0 == ~M_E~0); 5844#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5839#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5840#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5748#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5749#L124-9 assume !(1 == ~m_pc~0); 5989#L124-11 is_master_triggered_~__retres1~0#1 := 0; 5986#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5983#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5980#L319-9 assume !(0 != activate_threads_~tmp~1#1); 5977#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5974#L143-9 assume !(1 == ~t1_pc~0); 5971#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 5969#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5967#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5965#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5963#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5947#L287-3 assume !(1 == ~M_E~0); 5948#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5939#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5940#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5931#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5932#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5922#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5923#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 5915#L447 assume !(0 == start_simulation_~tmp~3#1); 5914#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5910#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5909#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5904#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 5905#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5900#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5901#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 5897#L460 assume !(0 != start_simulation_~tmp___0~1#1); 5689#L428-2 [2022-10-17 10:27:16,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,418 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 4 times [2022-10-17 10:27:16,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,419 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788481432] [2022-10-17 10:27:16,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:16,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,462 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:16,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,463 INFO L85 PathProgramCache]: Analyzing trace with hash 196989591, now seen corresponding path program 1 times [2022-10-17 10:27:16,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801461751] [2022-10-17 10:27:16,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:16,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:16,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:16,536 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801461751] [2022-10-17 10:27:16,536 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801461751] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:16,537 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:16,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:16,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1766906100] [2022-10-17 10:27:16,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:16,538 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:27:16,538 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:16,538 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:16,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:16,539 INFO L87 Difference]: Start difference. First operand 440 states and 593 transitions. cyclomatic complexity: 155 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:16,580 INFO L93 Difference]: Finished difference Result 641 states and 847 transitions. [2022-10-17 10:27:16,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 641 states and 847 transitions. [2022-10-17 10:27:16,587 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 606 [2022-10-17 10:27:16,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 641 states to 641 states and 847 transitions. [2022-10-17 10:27:16,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 641 [2022-10-17 10:27:16,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 641 [2022-10-17 10:27:16,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 641 states and 847 transitions. [2022-10-17 10:27:16,596 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:16,596 INFO L218 hiAutomatonCegarLoop]: Abstraction has 641 states and 847 transitions. [2022-10-17 10:27:16,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states and 847 transitions. [2022-10-17 10:27:16,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 624. [2022-10-17 10:27:16,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 826 transitions. [2022-10-17 10:27:16,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 624 states and 826 transitions. [2022-10-17 10:27:16,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:16,616 INFO L428 stractBuchiCegarLoop]: Abstraction has 624 states and 826 transitions. [2022-10-17 10:27:16,617 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:27:16,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 624 states and 826 transitions. [2022-10-17 10:27:16,622 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 589 [2022-10-17 10:27:16,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,623 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,623 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,624 INFO L748 eck$LassoCheckResult]: Stem: 6898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6812#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6826#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6827#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 6821#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6822#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6845#L259 assume !(0 == ~M_E~0); 6846#L259-2 assume !(0 == ~T1_E~0); 6866#L264-1 assume !(0 == ~E_M~0); 6867#L269-1 assume !(0 == ~E_1~0); 6862#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6863#L124 assume !(1 == ~m_pc~0); 6833#L124-2 is_master_triggered_~__retres1~0#1 := 0; 6834#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6756#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6757#L319 assume !(0 != activate_threads_~tmp~1#1); 6758#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6759#L143 assume !(1 == ~t1_pc~0); 6743#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6744#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6820#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6773#L327 assume !(0 != activate_threads_~tmp___0~0#1); 6774#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6796#L287 assume !(1 == ~M_E~0); 6842#L287-2 assume !(1 == ~T1_E~0); 6791#L292-1 assume !(1 == ~E_M~0); 6792#L297-1 assume !(1 == ~E_1~0); 6775#L302-1 assume { :end_inline_reset_delta_events } true; 6776#L428-2 assume !false; 7339#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7114#L234 [2022-10-17 10:27:16,624 INFO L750 eck$LassoCheckResult]: Loop: 7114#L234 assume !false; 7336#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7334#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7325#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7324#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7322#L215 assume 0 != eval_~tmp~0#1; 7321#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 6843#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 6844#L220 assume !(0 == ~t1_st~0); 7114#L234 [2022-10-17 10:27:16,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,625 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 1 times [2022-10-17 10:27:16,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,625 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968155306] [2022-10-17 10:27:16,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,650 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:16,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,665 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:16,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,666 INFO L85 PathProgramCache]: Analyzing trace with hash 2078330545, now seen corresponding path program 1 times [2022-10-17 10:27:16,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201903755] [2022-10-17 10:27:16,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,671 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:16,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:16,676 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,676 INFO L85 PathProgramCache]: Analyzing trace with hash 1188516331, now seen corresponding path program 1 times [2022-10-17 10:27:16,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,677 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732723250] [2022-10-17 10:27:16,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:16,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:16,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:16,711 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732723250] [2022-10-17 10:27:16,711 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [732723250] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:16,712 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:16,712 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:27:16,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804241293] [2022-10-17 10:27:16,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:16,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:16,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:16,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:16,785 INFO L87 Difference]: Start difference. First operand 624 states and 826 transitions. cyclomatic complexity: 206 Second operand has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:16,831 INFO L93 Difference]: Finished difference Result 1035 states and 1346 transitions. [2022-10-17 10:27:16,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1035 states and 1346 transitions. [2022-10-17 10:27:16,841 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 973 [2022-10-17 10:27:16,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1035 states to 1035 states and 1346 transitions. [2022-10-17 10:27:16,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1035 [2022-10-17 10:27:16,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1035 [2022-10-17 10:27:16,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1035 states and 1346 transitions. [2022-10-17 10:27:16,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:16,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1035 states and 1346 transitions. [2022-10-17 10:27:16,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1035 states and 1346 transitions. [2022-10-17 10:27:16,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1035 to 1019. [2022-10-17 10:27:16,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:16,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1019 states to 1019 states and 1330 transitions. [2022-10-17 10:27:16,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1019 states and 1330 transitions. [2022-10-17 10:27:16,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:16,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 1019 states and 1330 transitions. [2022-10-17 10:27:16,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2022-10-17 10:27:16,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1019 states and 1330 transitions. [2022-10-17 10:27:16,893 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 957 [2022-10-17 10:27:16,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:16,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:16,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:16,895 INFO L748 eck$LassoCheckResult]: Stem: 8580#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 8476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8477#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8494#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8495#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 8489#L170-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8490#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9140#L259 assume !(0 == ~M_E~0); 9139#L259-2 assume !(0 == ~T1_E~0); 9138#L264-1 assume !(0 == ~E_M~0); 9137#L269-1 assume !(0 == ~E_1~0); 9136#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9135#L124 assume !(1 == ~m_pc~0); 9134#L124-2 is_master_triggered_~__retres1~0#1 := 0; 9133#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9132#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9131#L319 assume !(0 != activate_threads_~tmp~1#1); 9130#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9129#L143 assume !(1 == ~t1_pc~0); 9128#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9127#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9126#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9125#L327 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8439#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8463#L287 assume !(1 == ~M_E~0); 8514#L287-2 assume !(1 == ~T1_E~0); 8458#L292-1 assume !(1 == ~E_M~0); 8459#L297-1 assume !(1 == ~E_1~0); 8440#L302-1 assume { :end_inline_reset_delta_events } true; 8441#L428-2 assume !false; 9121#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9119#L234 [2022-10-17 10:27:16,895 INFO L750 eck$LassoCheckResult]: Loop: 9119#L234 assume !false; 9117#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9105#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9102#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9103#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9096#L215 assume 0 != eval_~tmp~0#1; 9097#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 9088#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 8512#L220 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 8513#L237 assume !(0 != eval_~tmp_ndt_2~0#1); 9119#L234 [2022-10-17 10:27:16,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1643521085, now seen corresponding path program 1 times [2022-10-17 10:27:16,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,896 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343599357] [2022-10-17 10:27:16,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:27:16,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:27:16,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:27:16,918 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343599357] [2022-10-17 10:27:16,919 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343599357] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:27:16,919 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:27:16,919 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:27:16,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397900748] [2022-10-17 10:27:16,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:27:16,920 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:27:16,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:16,921 INFO L85 PathProgramCache]: Analyzing trace with hash 3735164, now seen corresponding path program 1 times [2022-10-17 10:27:16,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:16,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896874260] [2022-10-17 10:27:16,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:16,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:16,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,925 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:16,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:16,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:27:17,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:27:17,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:27:17,015 INFO L87 Difference]: Start difference. First operand 1019 states and 1330 transitions. cyclomatic complexity: 316 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:17,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:27:17,027 INFO L93 Difference]: Finished difference Result 984 states and 1283 transitions. [2022-10-17 10:27:17,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 984 states and 1283 transitions. [2022-10-17 10:27:17,037 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 948 [2022-10-17 10:27:17,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 984 states to 984 states and 1283 transitions. [2022-10-17 10:27:17,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 984 [2022-10-17 10:27:17,049 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 984 [2022-10-17 10:27:17,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 984 states and 1283 transitions. [2022-10-17 10:27:17,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:27:17,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-10-17 10:27:17,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 984 states and 1283 transitions. [2022-10-17 10:27:17,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 984 to 984. [2022-10-17 10:27:17,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:27:17,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 984 states to 984 states and 1283 transitions. [2022-10-17 10:27:17,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-10-17 10:27:17,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:27:17,077 INFO L428 stractBuchiCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-10-17 10:27:17,077 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2022-10-17 10:27:17,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 984 states and 1283 transitions. [2022-10-17 10:27:17,085 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 948 [2022-10-17 10:27:17,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:27:17,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:27:17,086 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:17,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:27:17,086 INFO L748 eck$LassoCheckResult]: Stem: 10578#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 10484#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10485#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10501#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10502#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 10496#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10497#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10521#L259 assume !(0 == ~M_E~0); 10522#L259-2 assume !(0 == ~T1_E~0); 10546#L264-1 assume !(0 == ~E_M~0); 10547#L269-1 assume !(0 == ~E_1~0); 10539#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10540#L124 assume !(1 == ~m_pc~0); 10509#L124-2 is_master_triggered_~__retres1~0#1 := 0; 10510#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10432#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10433#L319 assume !(0 != activate_threads_~tmp~1#1); 10434#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10435#L143 assume !(1 == ~t1_pc~0); 10419#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10420#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10495#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10447#L327 assume !(0 != activate_threads_~tmp___0~0#1); 10448#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10471#L287 assume !(1 == ~M_E~0); 10515#L287-2 assume !(1 == ~T1_E~0); 10466#L292-1 assume !(1 == ~E_M~0); 10467#L297-1 assume !(1 == ~E_1~0); 10449#L302-1 assume { :end_inline_reset_delta_events } true; 10450#L428-2 assume !false; 10832#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10814#L234 [2022-10-17 10:27:17,086 INFO L750 eck$LassoCheckResult]: Loop: 10814#L234 assume !false; 10829#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10827#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10825#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10823#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10821#L215 assume 0 != eval_~tmp~0#1; 10819#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 10817#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 10815#L220 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 10813#L237 assume !(0 != eval_~tmp_ndt_2~0#1); 10814#L234 [2022-10-17 10:27:17,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:17,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 2 times [2022-10-17 10:27:17,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:17,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493475528] [2022-10-17 10:27:17,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:17,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:17,106 INFO L85 PathProgramCache]: Analyzing trace with hash 3735164, now seen corresponding path program 2 times [2022-10-17 10:27:17,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:17,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771797731] [2022-10-17 10:27:17,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:17,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,111 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,115 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:27:17,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1810701694, now seen corresponding path program 1 times [2022-10-17 10:27:17,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:27:17,116 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118782732] [2022-10-17 10:27:17,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:27:17,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:27:17,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,125 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,136 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:27:17,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:17,983 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:27:17,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:27:18,145 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 10:27:18 BoogieIcfgContainer [2022-10-17 10:27:18,154 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 10:27:18,154 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 10:27:18,155 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 10:27:18,155 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 10:27:18,156 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:27:13" (3/4) ... [2022-10-17 10:27:18,159 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 10:27:18,255 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 10:27:18,255 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 10:27:18,256 INFO L158 Benchmark]: Toolchain (without parser) took 6302.81ms. Allocated memory was 83.9MB in the beginning and 144.7MB in the end (delta: 60.8MB). Free memory was 43.7MB in the beginning and 82.5MB in the end (delta: -38.8MB). Peak memory consumption was 21.8MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,257 INFO L158 Benchmark]: CDTParser took 0.30ms. Allocated memory is still 83.9MB. Free memory was 60.4MB in the beginning and 60.3MB in the end (delta: 44.7kB). There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 10:27:18,258 INFO L158 Benchmark]: CACSL2BoogieTranslator took 480.43ms. Allocated memory was 83.9MB in the beginning and 117.4MB in the end (delta: 33.6MB). Free memory was 43.5MB in the beginning and 86.7MB in the end (delta: -43.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,258 INFO L158 Benchmark]: Boogie Procedure Inliner took 88.36ms. Allocated memory is still 117.4MB. Free memory was 86.7MB in the beginning and 84.1MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,259 INFO L158 Benchmark]: Boogie Preprocessor took 59.16ms. Allocated memory is still 117.4MB. Free memory was 84.1MB in the beginning and 82.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,259 INFO L158 Benchmark]: RCFGBuilder took 1019.11ms. Allocated memory is still 117.4MB. Free memory was 82.0MB in the beginning and 60.4MB in the end (delta: 21.6MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,260 INFO L158 Benchmark]: BuchiAutomizer took 4547.86ms. Allocated memory was 117.4MB in the beginning and 144.7MB in the end (delta: 27.3MB). Free memory was 60.1MB in the beginning and 85.6MB in the end (delta: -25.5MB). Peak memory consumption was 3.0MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,260 INFO L158 Benchmark]: Witness Printer took 101.04ms. Allocated memory is still 144.7MB. Free memory was 85.6MB in the beginning and 82.5MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:27:18,264 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.30ms. Allocated memory is still 83.9MB. Free memory was 60.4MB in the beginning and 60.3MB in the end (delta: 44.7kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 480.43ms. Allocated memory was 83.9MB in the beginning and 117.4MB in the end (delta: 33.6MB). Free memory was 43.5MB in the beginning and 86.7MB in the end (delta: -43.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 88.36ms. Allocated memory is still 117.4MB. Free memory was 86.7MB in the beginning and 84.1MB in the end (delta: 2.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 59.16ms. Allocated memory is still 117.4MB. Free memory was 84.1MB in the beginning and 82.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1019.11ms. Allocated memory is still 117.4MB. Free memory was 82.0MB in the beginning and 60.4MB in the end (delta: 21.6MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 4547.86ms. Allocated memory was 117.4MB in the beginning and 144.7MB in the end (delta: 27.3MB). Free memory was 60.1MB in the beginning and 85.6MB in the end (delta: -25.5MB). Peak memory consumption was 3.0MB. Max. memory is 16.1GB. * Witness Printer took 101.04ms. Allocated memory is still 144.7MB. Free memory was 85.6MB in the beginning and 82.5MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 984 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.3s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 2.8s. Construction of modules took 0.3s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 10 MinimizatonAttempts, 777 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2356 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2356 mSDsluCounter, 4359 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2303 mSDsCounter, 80 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 223 IncrementalHoareTripleChecker+Invalid, 303 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 80 mSolverCounterUnsat, 2056 mSDtfsCounter, 223 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 210]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int m_st ; [L27] int t1_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L37] int token ; [L39] int local ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, token=0] [L473] int __retres1 ; [L477] CALL init_model() [L388] m_i = 1 [L389] t1_i = 1 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L477] RET init_model() [L478] CALL start_simulation() [L414] int kernel_st ; [L415] int tmp ; [L416] int tmp___0 ; [L420] kernel_st = 0 [L421] FCALL update_channels() [L422] CALL init_threads() [L170] COND TRUE m_i == 1 [L171] m_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L175] COND TRUE t1_i == 1 [L176] t1_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L422] RET init_threads() [L423] CALL fire_delta_events() [L259] COND FALSE !(M_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L264] COND FALSE !(T1_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L269] COND FALSE !(E_M == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L274] COND FALSE !(E_1 == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L423] RET fire_delta_events() [L424] CALL activate_threads() [L312] int tmp ; [L313] int tmp___0 ; [L317] CALL, EXPR is_master_triggered() [L121] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L124] COND FALSE !(m_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L134] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L136] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L317] RET, EXPR is_master_triggered() [L317] tmp = is_master_triggered() [L319] COND FALSE !(\read(tmp)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, token=0] [L325] CALL, EXPR is_transmit1_triggered() [L140] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L143] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L153] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L155] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L325] RET, EXPR is_transmit1_triggered() [L325] tmp___0 = is_transmit1_triggered() [L327] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0, token=0] [L424] RET activate_threads() [L425] CALL reset_delta_events() [L287] COND FALSE !(M_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L292] COND FALSE !(T1_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L297] COND FALSE !(E_M == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L302] COND FALSE !(E_1 == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L425] RET reset_delta_events() [L428] COND TRUE 1 VAL [E_1=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L431] kernel_st = 1 [L432] CALL eval() [L206] int tmp ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] Loop: [L210] COND TRUE 1 [L213] CALL, EXPR exists_runnable_thread() [L185] int __retres1 ; [L188] COND TRUE m_st == 0 [L189] __retres1 = 1 [L201] return (__retres1); [L213] RET, EXPR exists_runnable_thread() [L213] tmp = exists_runnable_thread() [L215] COND TRUE \read(tmp) [L220] COND TRUE m_st == 0 [L221] int tmp_ndt_1; [L222] tmp_ndt_1 = __VERIFIER_nondet_int() [L223] COND FALSE !(\read(tmp_ndt_1)) [L234] COND TRUE t1_st == 0 [L235] int tmp_ndt_2; [L236] tmp_ndt_2 = __VERIFIER_nondet_int() [L237] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 210]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int m_st ; [L27] int t1_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L37] int token ; [L39] int local ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, token=0] [L473] int __retres1 ; [L477] CALL init_model() [L388] m_i = 1 [L389] t1_i = 1 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L477] RET init_model() [L478] CALL start_simulation() [L414] int kernel_st ; [L415] int tmp ; [L416] int tmp___0 ; [L420] kernel_st = 0 [L421] FCALL update_channels() [L422] CALL init_threads() [L170] COND TRUE m_i == 1 [L171] m_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L175] COND TRUE t1_i == 1 [L176] t1_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L422] RET init_threads() [L423] CALL fire_delta_events() [L259] COND FALSE !(M_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L264] COND FALSE !(T1_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L269] COND FALSE !(E_M == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L274] COND FALSE !(E_1 == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L423] RET fire_delta_events() [L424] CALL activate_threads() [L312] int tmp ; [L313] int tmp___0 ; [L317] CALL, EXPR is_master_triggered() [L121] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L124] COND FALSE !(m_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L134] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L136] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L317] RET, EXPR is_master_triggered() [L317] tmp = is_master_triggered() [L319] COND FALSE !(\read(tmp)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, token=0] [L325] CALL, EXPR is_transmit1_triggered() [L140] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L143] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L153] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L155] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L325] RET, EXPR is_transmit1_triggered() [L325] tmp___0 = is_transmit1_triggered() [L327] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0, token=0] [L424] RET activate_threads() [L425] CALL reset_delta_events() [L287] COND FALSE !(M_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L292] COND FALSE !(T1_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L297] COND FALSE !(E_M == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L302] COND FALSE !(E_1 == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L425] RET reset_delta_events() [L428] COND TRUE 1 VAL [E_1=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L431] kernel_st = 1 [L432] CALL eval() [L206] int tmp ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] Loop: [L210] COND TRUE 1 [L213] CALL, EXPR exists_runnable_thread() [L185] int __retres1 ; [L188] COND TRUE m_st == 0 [L189] __retres1 = 1 [L201] return (__retres1); [L213] RET, EXPR exists_runnable_thread() [L213] tmp = exists_runnable_thread() [L215] COND TRUE \read(tmp) [L220] COND TRUE m_st == 0 [L221] int tmp_ndt_1; [L222] tmp_ndt_1 = __VERIFIER_nondet_int() [L223] COND FALSE !(\read(tmp_ndt_1)) [L234] COND TRUE t1_st == 0 [L235] int tmp_ndt_2; [L236] tmp_ndt_2 = __VERIFIER_nondet_int() [L237] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 10:27:18,359 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_34edfe7a-0c6a-483e-87b9-13a2caa9f72b/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)