./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.01.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version dbf71c69 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.01.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 327bb4ad7f981d20a6e5212aac300a9249d1857b0280531d57d587d5a0195c5f --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-dbf71c6-m [2022-10-17 10:17:11,245 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-10-17 10:17:11,248 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-10-17 10:17:11,303 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-10-17 10:17:11,304 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-10-17 10:17:11,309 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-10-17 10:17:11,312 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-10-17 10:17:11,316 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-10-17 10:17:11,319 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-10-17 10:17:11,325 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-10-17 10:17:11,326 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-10-17 10:17:11,329 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-10-17 10:17:11,329 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-10-17 10:17:11,332 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-10-17 10:17:11,335 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-10-17 10:17:11,337 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-10-17 10:17:11,339 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-10-17 10:17:11,341 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-10-17 10:17:11,343 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-10-17 10:17:11,352 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-10-17 10:17:11,354 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-10-17 10:17:11,356 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-10-17 10:17:11,360 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-10-17 10:17:11,361 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-10-17 10:17:11,372 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-10-17 10:17:11,373 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-10-17 10:17:11,373 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-10-17 10:17:11,375 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-10-17 10:17:11,376 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-10-17 10:17:11,378 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-10-17 10:17:11,378 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-10-17 10:17:11,381 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-10-17 10:17:11,383 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-10-17 10:17:11,385 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-10-17 10:17:11,386 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-10-17 10:17:11,387 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-10-17 10:17:11,387 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-10-17 10:17:11,388 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-10-17 10:17:11,388 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-10-17 10:17:11,389 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-10-17 10:17:11,390 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-10-17 10:17:11,392 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-10-17 10:17:11,439 INFO L113 SettingsManager]: Loading preferences was successful [2022-10-17 10:17:11,439 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-10-17 10:17:11,440 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-10-17 10:17:11,440 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-10-17 10:17:11,442 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-10-17 10:17:11,442 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-10-17 10:17:11,442 INFO L138 SettingsManager]: * Use SBE=true [2022-10-17 10:17:11,442 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-10-17 10:17:11,443 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-10-17 10:17:11,443 INFO L138 SettingsManager]: * Use old map elimination=false [2022-10-17 10:17:11,444 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-10-17 10:17:11,444 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-10-17 10:17:11,445 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-10-17 10:17:11,445 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-10-17 10:17:11,445 INFO L138 SettingsManager]: * sizeof long=4 [2022-10-17 10:17:11,445 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-10-17 10:17:11,446 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-10-17 10:17:11,446 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-10-17 10:17:11,446 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-10-17 10:17:11,446 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-10-17 10:17:11,446 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-10-17 10:17:11,447 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-10-17 10:17:11,447 INFO L138 SettingsManager]: * sizeof long double=12 [2022-10-17 10:17:11,449 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-10-17 10:17:11,449 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-10-17 10:17:11,449 INFO L138 SettingsManager]: * Use constant arrays=true [2022-10-17 10:17:11,449 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-10-17 10:17:11,450 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-10-17 10:17:11,450 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-10-17 10:17:11,450 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-10-17 10:17:11,451 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-10-17 10:17:11,452 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-10-17 10:17:11,452 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 327bb4ad7f981d20a6e5212aac300a9249d1857b0280531d57d587d5a0195c5f [2022-10-17 10:17:11,797 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-10-17 10:17:11,835 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-10-17 10:17:11,837 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-10-17 10:17:11,838 INFO L271 PluginConnector]: Initializing CDTParser... [2022-10-17 10:17:11,839 INFO L275 PluginConnector]: CDTParser initialized [2022-10-17 10:17:11,841 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/../../sv-benchmarks/c/systemc/token_ring.01.cil-2.c [2022-10-17 10:17:11,902 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/data/942d31b05/43b87110b38c465b8e00fbd93089f547/FLAGc405b1952 [2022-10-17 10:17:12,381 INFO L306 CDTParser]: Found 1 translation units. [2022-10-17 10:17:12,382 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/sv-benchmarks/c/systemc/token_ring.01.cil-2.c [2022-10-17 10:17:12,392 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/data/942d31b05/43b87110b38c465b8e00fbd93089f547/FLAGc405b1952 [2022-10-17 10:17:12,713 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/data/942d31b05/43b87110b38c465b8e00fbd93089f547 [2022-10-17 10:17:12,717 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-10-17 10:17:12,720 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-10-17 10:17:12,726 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-10-17 10:17:12,726 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-10-17 10:17:12,738 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-10-17 10:17:12,739 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:17:12" (1/1) ... [2022-10-17 10:17:12,741 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6fb94b85 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:12, skipping insertion in model container [2022-10-17 10:17:12,741 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.10 10:17:12" (1/1) ... [2022-10-17 10:17:12,750 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-10-17 10:17:12,797 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-10-17 10:17:13,007 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/sv-benchmarks/c/systemc/token_ring.01.cil-2.c[671,684] [2022-10-17 10:17:13,076 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:17:13,085 INFO L203 MainTranslator]: Completed pre-run [2022-10-17 10:17:13,097 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/sv-benchmarks/c/systemc/token_ring.01.cil-2.c[671,684] [2022-10-17 10:17:13,119 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-10-17 10:17:13,136 INFO L208 MainTranslator]: Completed translation [2022-10-17 10:17:13,136 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13 WrapperNode [2022-10-17 10:17:13,137 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-10-17 10:17:13,138 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-10-17 10:17:13,138 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-10-17 10:17:13,138 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-10-17 10:17:13,147 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,156 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,189 INFO L138 Inliner]: procedures = 30, calls = 35, calls flagged for inlining = 30, calls inlined = 39, statements flattened = 417 [2022-10-17 10:17:13,189 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-10-17 10:17:13,190 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-10-17 10:17:13,190 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-10-17 10:17:13,190 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-10-17 10:17:13,199 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,199 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,202 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,203 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,210 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,219 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,222 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,225 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,230 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-10-17 10:17:13,231 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-10-17 10:17:13,231 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-10-17 10:17:13,231 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-10-17 10:17:13,232 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (1/1) ... [2022-10-17 10:17:13,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-10-17 10:17:13,258 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/z3 [2022-10-17 10:17:13,270 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-10-17 10:17:13,281 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-10-17 10:17:13,319 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-10-17 10:17:13,319 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-10-17 10:17:13,320 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-10-17 10:17:13,320 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-10-17 10:17:13,399 INFO L235 CfgBuilder]: Building ICFG [2022-10-17 10:17:13,402 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-10-17 10:17:14,048 INFO L276 CfgBuilder]: Performing block encoding [2022-10-17 10:17:14,057 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-10-17 10:17:14,062 INFO L300 CfgBuilder]: Removed 4 assume(true) statements. [2022-10-17 10:17:14,065 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:17:14 BoogieIcfgContainer [2022-10-17 10:17:14,066 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-10-17 10:17:14,093 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-10-17 10:17:14,093 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-10-17 10:17:14,098 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-10-17 10:17:14,099 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:17:14,099 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.10 10:17:12" (1/3) ... [2022-10-17 10:17:14,101 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3faceb79 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:17:14, skipping insertion in model container [2022-10-17 10:17:14,101 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:17:14,101 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.10 10:17:13" (2/3) ... [2022-10-17 10:17:14,101 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3faceb79 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.10 10:17:14, skipping insertion in model container [2022-10-17 10:17:14,102 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-10-17 10:17:14,102 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:17:14" (3/3) ... [2022-10-17 10:17:14,103 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.01.cil-2.c [2022-10-17 10:17:14,203 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2022-10-17 10:17:14,203 INFO L304 stractBuchiCegarLoop]: Hoare is false [2022-10-17 10:17:14,203 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-10-17 10:17:14,203 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-10-17 10:17:14,203 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-10-17 10:17:14,204 INFO L308 stractBuchiCegarLoop]: Difference is false [2022-10-17 10:17:14,204 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-10-17 10:17:14,204 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2022-10-17 10:17:14,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 159 states, 158 states have (on average 1.5316455696202531) internal successors, (242), 158 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:14,266 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 124 [2022-10-17 10:17:14,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:14,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:14,279 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,280 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2022-10-17 10:17:14,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 159 states, 158 states have (on average 1.5316455696202531) internal successors, (242), 158 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:14,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 124 [2022-10-17 10:17:14,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:14,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:14,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,301 INFO L748 eck$LassoCheckResult]: Stem: 140#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 51#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 57#L403true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3#L175true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122#L182true assume !(1 == ~m_i~0);~m_st~0 := 2; 26#L182-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 119#L187-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41#L271true assume !(0 == ~M_E~0); 92#L271-2true assume !(0 == ~T1_E~0); 50#L276-1true assume !(0 == ~E_M~0); 107#L281-1true assume !(0 == ~E_1~0); 32#L286-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14#L136true assume 1 == ~m_pc~0; 71#L137true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 136#L147true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38#L148true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9#L331true assume !(0 != activate_threads_~tmp~1#1); 141#L331-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54#L155true assume 1 == ~t1_pc~0; 152#L156true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 106#L166true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24#L167true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 153#L339true assume !(0 != activate_threads_~tmp___0~0#1); 120#L339-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47#L299true assume !(1 == ~M_E~0); 98#L299-2true assume !(1 == ~T1_E~0); 114#L304-1true assume !(1 == ~E_M~0); 18#L309-1true assume !(1 == ~E_1~0); 62#L314-1true assume { :end_inline_reset_delta_events } true; 115#L440-2true [2022-10-17 10:17:14,302 INFO L750 eck$LassoCheckResult]: Loop: 115#L440-2true assume !false; 27#L441true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73#L246true assume false; 160#L261true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 142#L175-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85#L271-3true assume 0 == ~M_E~0;~M_E~0 := 1; 109#L271-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 22#L276-3true assume 0 == ~E_M~0;~E_M~0 := 1; 30#L281-3true assume 0 == ~E_1~0;~E_1~0 := 1; 132#L286-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67#L136-9true assume !(1 == ~m_pc~0); 7#L136-11true is_master_triggered_~__retres1~0#1 := 0; 95#L147-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126#L148-3true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 66#L331-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123#L331-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52#L155-9true assume 1 == ~t1_pc~0; 143#L156-3true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29#L166-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65#L167-3true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74#L339-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79#L339-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108#L299-3true assume 1 == ~M_E~0;~M_E~0 := 2; 35#L299-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 125#L304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 90#L309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 36#L314-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 23#L200-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 118#L212-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 139#L213-1true start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6#L459true assume !(0 == start_simulation_~tmp~3#1); 28#L459-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 96#L200-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 155#L212-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10#L213-2true stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 144#L414true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37#L421true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16#L422true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 43#L472true assume !(0 != start_simulation_~tmp___0~1#1); 115#L440-2true [2022-10-17 10:17:14,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:14,312 INFO L85 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2022-10-17 10:17:14,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:14,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290381501] [2022-10-17 10:17:14,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:14,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:14,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:14,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:14,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:14,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290381501] [2022-10-17 10:17:14,519 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290381501] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:14,519 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:14,520 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:17:14,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901203096] [2022-10-17 10:17:14,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:14,527 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:17:14,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:14,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1767991770, now seen corresponding path program 1 times [2022-10-17 10:17:14,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:14,528 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321542872] [2022-10-17 10:17:14,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:14,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:14,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:14,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:14,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:14,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321542872] [2022-10-17 10:17:14,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321542872] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:14,565 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:14,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:17:14,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724461243] [2022-10-17 10:17:14,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:14,567 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:14,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:14,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:17:14,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:17:14,607 INFO L87 Difference]: Start difference. First operand has 159 states, 158 states have (on average 1.5316455696202531) internal successors, (242), 158 states have internal predecessors, (242), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:14,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:14,646 INFO L93 Difference]: Finished difference Result 157 states and 229 transitions. [2022-10-17 10:17:14,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157 states and 229 transitions. [2022-10-17 10:17:14,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 120 [2022-10-17 10:17:14,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157 states to 151 states and 223 transitions. [2022-10-17 10:17:14,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2022-10-17 10:17:14,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2022-10-17 10:17:14,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 151 states and 223 transitions. [2022-10-17 10:17:14,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:14,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 151 states and 223 transitions. [2022-10-17 10:17:14,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states and 223 transitions. [2022-10-17 10:17:14,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2022-10-17 10:17:14,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 151 states, 151 states have (on average 1.4768211920529801) internal successors, (223), 150 states have internal predecessors, (223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:14,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 223 transitions. [2022-10-17 10:17:14,710 INFO L240 hiAutomatonCegarLoop]: Abstraction has 151 states and 223 transitions. [2022-10-17 10:17:14,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:17:14,716 INFO L428 stractBuchiCegarLoop]: Abstraction has 151 states and 223 transitions. [2022-10-17 10:17:14,716 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2022-10-17 10:17:14,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 151 states and 223 transitions. [2022-10-17 10:17:14,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 120 [2022-10-17 10:17:14,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:14,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:14,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:14,723 INFO L748 eck$LassoCheckResult]: Stem: 473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 417#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 325#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 326#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 377#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 378#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 397#L271 assume !(0 == ~M_E~0); 398#L271-2 assume !(0 == ~T1_E~0); 414#L276-1 assume !(0 == ~E_M~0); 415#L281-1 assume !(0 == ~E_1~0); 384#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 349#L136 assume 1 == ~m_pc~0; 350#L137 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 396#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 340#L331 assume !(0 != activate_threads_~tmp~1#1); 341#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 421#L155 assume 1 == ~t1_pc~0; 422#L156 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 465#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 375#L339 assume !(0 != activate_threads_~tmp___0~0#1); 470#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 410#L299 assume !(1 == ~M_E~0); 411#L299-2 assume !(1 == ~T1_E~0); 462#L304-1 assume !(1 == ~E_M~0); 360#L309-1 assume !(1 == ~E_1~0); 361#L314-1 assume { :end_inline_reset_delta_events } true; 401#L440-2 [2022-10-17 10:17:14,723 INFO L750 eck$LassoCheckResult]: Loop: 401#L440-2 assume !false; 379#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 328#L246 assume !false; 445#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 446#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 454#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 455#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 466#L227 assume !(0 != eval_~tmp~0#1); 467#L261 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 474#L175-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 452#L271-3 assume 0 == ~M_E~0;~M_E~0 := 1; 453#L271-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 370#L276-3 assume 0 == ~E_M~0;~E_M~0 := 1; 371#L281-3 assume 0 == ~E_1~0;~E_1~0 := 1; 383#L286-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 438#L136-9 assume !(1 == ~m_pc~0); 336#L136-11 is_master_triggered_~__retres1~0#1 := 0; 337#L147-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 460#L148-3 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 434#L331-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 435#L331-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 418#L155-9 assume 1 == ~t1_pc~0; 419#L156-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 380#L166-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 381#L167-3 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 433#L339-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 444#L339-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 448#L299-3 assume 1 == ~M_E~0;~M_E~0 := 2; 389#L299-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 390#L304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 456#L309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 391#L314-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 367#L200-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 368#L212-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 468#L213-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 333#L459 assume !(0 == start_simulation_~tmp~3#1); 334#L459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 376#L200-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 458#L212-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 342#L213-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 343#L414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 392#L421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 352#L422 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 353#L472 assume !(0 != start_simulation_~tmp___0~1#1); 401#L440-2 [2022-10-17 10:17:14,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:14,724 INFO L85 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2022-10-17 10:17:14,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:14,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774693976] [2022-10-17 10:17:14,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:14,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:14,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:14,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:14,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:14,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [774693976] [2022-10-17 10:17:14,824 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [774693976] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:14,825 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:14,825 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:17:14,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808551656] [2022-10-17 10:17:14,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:14,826 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:17:14,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:14,827 INFO L85 PathProgramCache]: Analyzing trace with hash 449891219, now seen corresponding path program 1 times [2022-10-17 10:17:14,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:14,827 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139990838] [2022-10-17 10:17:14,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:14,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:14,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:15,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:15,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:15,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139990838] [2022-10-17 10:17:15,048 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139990838] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:15,048 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:15,048 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:17:15,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828853734] [2022-10-17 10:17:15,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:15,049 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:15,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:15,050 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:17:15,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:17:15,050 INFO L87 Difference]: Start difference. First operand 151 states and 223 transitions. cyclomatic complexity: 73 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:15,118 INFO L93 Difference]: Finished difference Result 258 states and 371 transitions. [2022-10-17 10:17:15,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 258 states and 371 transitions. [2022-10-17 10:17:15,121 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 227 [2022-10-17 10:17:15,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 258 states to 258 states and 371 transitions. [2022-10-17 10:17:15,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 258 [2022-10-17 10:17:15,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 258 [2022-10-17 10:17:15,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 258 states and 371 transitions. [2022-10-17 10:17:15,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:15,128 INFO L218 hiAutomatonCegarLoop]: Abstraction has 258 states and 371 transitions. [2022-10-17 10:17:15,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258 states and 371 transitions. [2022-10-17 10:17:15,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258 to 245. [2022-10-17 10:17:15,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.4448979591836735) internal successors, (354), 244 states have internal predecessors, (354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 354 transitions. [2022-10-17 10:17:15,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 354 transitions. [2022-10-17 10:17:15,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:17:15,146 INFO L428 stractBuchiCegarLoop]: Abstraction has 245 states and 354 transitions. [2022-10-17 10:17:15,146 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2022-10-17 10:17:15,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 354 transitions. [2022-10-17 10:17:15,148 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 214 [2022-10-17 10:17:15,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:15,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:15,151 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,151 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,151 INFO L748 eck$LassoCheckResult]: Stem: 906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 833#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 834#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 743#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 744#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 795#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 796#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 814#L271 assume !(0 == ~M_E~0); 815#L271-2 assume !(0 == ~T1_E~0); 831#L276-1 assume !(0 == ~E_M~0); 832#L281-1 assume !(0 == ~E_1~0); 801#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 767#L136 assume !(1 == ~m_pc~0); 768#L136-2 is_master_triggered_~__retres1~0#1 := 0; 813#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 810#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 758#L331 assume !(0 != activate_threads_~tmp~1#1); 759#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 839#L155 assume 1 == ~t1_pc~0; 840#L156 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 893#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 790#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 791#L339 assume !(0 != activate_threads_~tmp___0~0#1); 900#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828#L299 assume !(1 == ~M_E~0); 829#L299-2 assume !(1 == ~T1_E~0); 886#L304-1 assume !(1 == ~E_M~0); 773#L309-1 assume !(1 == ~E_1~0); 774#L314-1 assume { :end_inline_reset_delta_events } true; 818#L440-2 [2022-10-17 10:17:15,152 INFO L750 eck$LassoCheckResult]: Loop: 818#L440-2 assume !false; 792#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 746#L246 assume !false; 864#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 866#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 875#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 876#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 908#L227 assume !(0 != eval_~tmp~0#1); 911#L261 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 907#L175-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 873#L271-3 assume 0 == ~M_E~0;~M_E~0 := 1; 874#L271-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 783#L276-3 assume 0 == ~E_M~0;~E_M~0 := 1; 784#L281-3 assume 0 == ~E_1~0;~E_1~0 := 1; 799#L286-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 854#L136-9 assume !(1 == ~m_pc~0); 754#L136-11 is_master_triggered_~__retres1~0#1 := 0; 755#L147-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 882#L148-3 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 852#L331-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 853#L331-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 835#L155-9 assume 1 == ~t1_pc~0; 836#L156-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 877#L166-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 946#L167-3 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 944#L339-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 941#L339-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 894#L299-3 assume 1 == ~M_E~0;~M_E~0 := 2; 806#L299-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 807#L304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 879#L309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 880#L314-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 934#L200-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 932#L212-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 931#L213-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 930#L459 assume !(0 == start_simulation_~tmp~3#1); 793#L459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 794#L200-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 883#L212-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 760#L213-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 761#L414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 809#L421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 769#L422 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 770#L472 assume !(0 != start_simulation_~tmp___0~1#1); 818#L440-2 [2022-10-17 10:17:15,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2022-10-17 10:17:15,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,153 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914883051] [2022-10-17 10:17:15,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:15,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:15,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:15,266 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914883051] [2022-10-17 10:17:15,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914883051] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:15,266 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:15,267 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:17:15,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463499587] [2022-10-17 10:17:15,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:15,268 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:17:15,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,270 INFO L85 PathProgramCache]: Analyzing trace with hash 449891219, now seen corresponding path program 2 times [2022-10-17 10:17:15,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,271 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013531539] [2022-10-17 10:17:15,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:15,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:15,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:15,378 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013531539] [2022-10-17 10:17:15,378 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013531539] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:15,378 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:15,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:17:15,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704141472] [2022-10-17 10:17:15,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:15,379 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:15,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:15,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-10-17 10:17:15,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-10-17 10:17:15,381 INFO L87 Difference]: Start difference. First operand 245 states and 354 transitions. cyclomatic complexity: 111 Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:15,488 INFO L93 Difference]: Finished difference Result 522 states and 737 transitions. [2022-10-17 10:17:15,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 737 transitions. [2022-10-17 10:17:15,495 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 471 [2022-10-17 10:17:15,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 737 transitions. [2022-10-17 10:17:15,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2022-10-17 10:17:15,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2022-10-17 10:17:15,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 737 transitions. [2022-10-17 10:17:15,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:15,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 522 states and 737 transitions. [2022-10-17 10:17:15,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 737 transitions. [2022-10-17 10:17:15,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 417. [2022-10-17 10:17:15,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 417 states, 417 states have (on average 1.434052757793765) internal successors, (598), 416 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417 states to 417 states and 598 transitions. [2022-10-17 10:17:15,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 417 states and 598 transitions. [2022-10-17 10:17:15,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-10-17 10:17:15,558 INFO L428 stractBuchiCegarLoop]: Abstraction has 417 states and 598 transitions. [2022-10-17 10:17:15,558 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2022-10-17 10:17:15,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 417 states and 598 transitions. [2022-10-17 10:17:15,562 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 386 [2022-10-17 10:17:15,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:15,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:15,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,567 INFO L748 eck$LassoCheckResult]: Stem: 1682#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1611#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1522#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1523#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 1571#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1572#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1591#L271 assume !(0 == ~M_E~0); 1592#L271-2 assume !(0 == ~T1_E~0); 1608#L276-1 assume !(0 == ~E_M~0); 1609#L281-1 assume !(0 == ~E_1~0); 1578#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1545#L136 assume !(1 == ~m_pc~0); 1546#L136-2 is_master_triggered_~__retres1~0#1 := 0; 1590#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1587#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1537#L331 assume !(0 != activate_threads_~tmp~1#1); 1538#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1614#L155 assume !(1 == ~t1_pc~0); 1615#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1667#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1567#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1568#L339 assume !(0 != activate_threads_~tmp___0~0#1); 1675#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1602#L299 assume !(1 == ~M_E~0); 1603#L299-2 assume !(1 == ~T1_E~0); 1660#L304-1 assume !(1 == ~E_M~0); 1551#L309-1 assume !(1 == ~E_1~0); 1552#L314-1 assume { :end_inline_reset_delta_events } true; 1595#L440-2 [2022-10-17 10:17:15,568 INFO L750 eck$LassoCheckResult]: Loop: 1595#L440-2 assume !false; 1569#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1525#L246 assume !false; 1638#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1640#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1651#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1652#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1668#L227 assume !(0 != eval_~tmp~0#1); 1669#L261 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1683#L175-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1649#L271-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1650#L271-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1560#L276-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1561#L281-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1929#L286-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1628#L136-9 assume !(1 == ~m_pc~0); 1533#L136-11 is_master_triggered_~__retres1~0#1 := 0; 1534#L147-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1656#L148-3 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1626#L331-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1627#L331-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1612#L155-9 assume !(1 == ~t1_pc~0); 1613#L155-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1573#L166-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1574#L167-3 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1625#L339-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1639#L339-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642#L299-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1583#L299-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1584#L304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1654#L309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1585#L314-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1562#L200-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1563#L212-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1670#L213-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1530#L459 assume !(0 == start_simulation_~tmp~3#1); 1531#L459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1570#L200-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1657#L212-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1539#L213-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1540#L414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1586#L421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1547#L422 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1548#L472 assume !(0 != start_simulation_~tmp___0~1#1); 1595#L440-2 [2022-10-17 10:17:15,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,569 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2022-10-17 10:17:15,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,569 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541520211] [2022-10-17 10:17:15,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:15,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:15,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:15,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:15,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1229872148, now seen corresponding path program 1 times [2022-10-17 10:17:15,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209543661] [2022-10-17 10:17:15,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:15,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:15,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:15,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209543661] [2022-10-17 10:17:15,727 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209543661] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:15,729 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:15,730 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:17:15,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858345001] [2022-10-17 10:17:15,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:15,731 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:15,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:15,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:17:15,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:17:15,733 INFO L87 Difference]: Start difference. First operand 417 states and 598 transitions. cyclomatic complexity: 183 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:15,844 INFO L93 Difference]: Finished difference Result 713 states and 996 transitions. [2022-10-17 10:17:15,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 713 states and 996 transitions. [2022-10-17 10:17:15,854 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 680 [2022-10-17 10:17:15,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 713 states to 713 states and 996 transitions. [2022-10-17 10:17:15,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 713 [2022-10-17 10:17:15,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 713 [2022-10-17 10:17:15,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 713 states and 996 transitions. [2022-10-17 10:17:15,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:15,865 INFO L218 hiAutomatonCegarLoop]: Abstraction has 713 states and 996 transitions. [2022-10-17 10:17:15,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 713 states and 996 transitions. [2022-10-17 10:17:15,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 713 to 429. [2022-10-17 10:17:15,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 429 states, 429 states have (on average 1.421911421911422) internal successors, (610), 428 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:15,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 610 transitions. [2022-10-17 10:17:15,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 429 states and 610 transitions. [2022-10-17 10:17:15,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-10-17 10:17:15,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 429 states and 610 transitions. [2022-10-17 10:17:15,890 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2022-10-17 10:17:15,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 429 states and 610 transitions. [2022-10-17 10:17:15,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 398 [2022-10-17 10:17:15,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:15,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:15,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,898 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:15,898 INFO L748 eck$LassoCheckResult]: Stem: 2847#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2760#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2668#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2669#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 2719#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2720#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2740#L271 assume !(0 == ~M_E~0); 2741#L271-2 assume !(0 == ~T1_E~0); 2757#L276-1 assume !(0 == ~E_M~0); 2758#L281-1 assume !(0 == ~E_1~0); 2726#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2691#L136 assume !(1 == ~m_pc~0); 2692#L136-2 is_master_triggered_~__retres1~0#1 := 0; 2739#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2736#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2683#L331 assume !(0 != activate_threads_~tmp~1#1); 2684#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2764#L155 assume !(1 == ~t1_pc~0); 2765#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2825#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2713#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2714#L339 assume !(0 != activate_threads_~tmp___0~0#1); 2833#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2754#L299 assume !(1 == ~M_E~0); 2755#L299-2 assume !(1 == ~T1_E~0); 2821#L304-1 assume !(1 == ~E_M~0); 2699#L309-1 assume !(1 == ~E_1~0); 2700#L314-1 assume { :end_inline_reset_delta_events } true; 2775#L440-2 [2022-10-17 10:17:15,900 INFO L750 eck$LassoCheckResult]: Loop: 2775#L440-2 assume !false; 3082#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2671#L246 assume !false; 2792#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2793#L200 assume !(0 == ~m_st~0); 2836#L204 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2840#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3039#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3038#L227 assume !(0 != eval_~tmp~0#1); 2857#L261 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2848#L175-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2805#L271-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2806#L271-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2923#L276-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2920#L281-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2918#L286-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2915#L136-9 assume !(1 == ~m_pc~0); 2901#L136-11 is_master_triggered_~__retres1~0#1 := 0; 2902#L147-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2839#L148-3 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2778#L331-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2779#L331-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2761#L155-9 assume !(1 == ~t1_pc~0); 2762#L155-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2809#L166-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2776#L167-3 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2777#L339-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2796#L339-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2797#L299-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2731#L299-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2732#L304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2813#L309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2814#L314-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2708#L200-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2709#L212-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2831#L213-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2676#L459 assume !(0 == start_simulation_~tmp~3#1); 2677#L459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3089#L200-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2855#L212-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2685#L213-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2686#L414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3086#L421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3085#L422 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3084#L472 assume !(0 != start_simulation_~tmp___0~1#1); 2775#L440-2 [2022-10-17 10:17:15,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,901 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2022-10-17 10:17:15,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863773306] [2022-10-17 10:17:15,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:15,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:15,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:15,941 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:15,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:15,946 INFO L85 PathProgramCache]: Analyzing trace with hash 2104030869, now seen corresponding path program 1 times [2022-10-17 10:17:15,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:15,947 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130112597] [2022-10-17 10:17:15,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:15,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:15,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:16,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:16,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:16,108 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130112597] [2022-10-17 10:17:16,108 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130112597] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:16,108 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:16,109 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-10-17 10:17:16,109 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583418936] [2022-10-17 10:17:16,109 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:16,110 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:16,110 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:16,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-10-17 10:17:16,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-10-17 10:17:16,111 INFO L87 Difference]: Start difference. First operand 429 states and 610 transitions. cyclomatic complexity: 183 Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:16,226 INFO L93 Difference]: Finished difference Result 822 states and 1157 transitions. [2022-10-17 10:17:16,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 822 states and 1157 transitions. [2022-10-17 10:17:16,234 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 791 [2022-10-17 10:17:16,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 822 states to 822 states and 1157 transitions. [2022-10-17 10:17:16,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 822 [2022-10-17 10:17:16,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 822 [2022-10-17 10:17:16,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 822 states and 1157 transitions. [2022-10-17 10:17:16,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:16,245 INFO L218 hiAutomatonCegarLoop]: Abstraction has 822 states and 1157 transitions. [2022-10-17 10:17:16,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 822 states and 1157 transitions. [2022-10-17 10:17:16,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 822 to 450. [2022-10-17 10:17:16,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 450 states, 450 states have (on average 1.3888888888888888) internal successors, (625), 449 states have internal predecessors, (625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 625 transitions. [2022-10-17 10:17:16,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 450 states and 625 transitions. [2022-10-17 10:17:16,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-10-17 10:17:16,259 INFO L428 stractBuchiCegarLoop]: Abstraction has 450 states and 625 transitions. [2022-10-17 10:17:16,259 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2022-10-17 10:17:16,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 450 states and 625 transitions. [2022-10-17 10:17:16,262 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 419 [2022-10-17 10:17:16,263 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:16,263 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:16,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,264 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,264 INFO L748 eck$LassoCheckResult]: Stem: 4101#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 4019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4020#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3932#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3933#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 3979#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3980#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4000#L271 assume !(0 == ~M_E~0); 4001#L271-2 assume !(0 == ~T1_E~0); 4017#L276-1 assume !(0 == ~E_M~0); 4018#L281-1 assume !(0 == ~E_1~0); 3987#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3955#L136 assume !(1 == ~m_pc~0); 3956#L136-2 is_master_triggered_~__retres1~0#1 := 0; 3999#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3996#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3947#L331 assume !(0 != activate_threads_~tmp~1#1); 3948#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4024#L155 assume !(1 == ~t1_pc~0); 4025#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4082#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3975#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3976#L339 assume !(0 != activate_threads_~tmp___0~0#1); 4088#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4011#L299 assume !(1 == ~M_E~0); 4012#L299-2 assume !(1 == ~T1_E~0); 4075#L304-1 assume !(1 == ~E_M~0); 3961#L309-1 assume !(1 == ~E_1~0); 3962#L314-1 assume { :end_inline_reset_delta_events } true; 4035#L440-2 [2022-10-17 10:17:16,264 INFO L750 eck$LassoCheckResult]: Loop: 4035#L440-2 assume !false; 4194#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4164#L246 assume !false; 4165#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4161#L200 assume !(0 == ~m_st~0); 4158#L204 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 4160#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4154#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4155#L227 assume !(0 != eval_~tmp~0#1); 4209#L261 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4148#L175-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4149#L271-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4144#L271-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4145#L276-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4140#L281-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4141#L286-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4298#L136-9 assume !(1 == ~m_pc~0); 4297#L136-11 is_master_triggered_~__retres1~0#1 := 0; 4295#L147-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4293#L148-3 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4291#L331-9 assume !(0 != activate_threads_~tmp~1#1); 4288#L331-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4283#L155-9 assume !(1 == ~t1_pc~0); 4278#L155-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4274#L166-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4270#L167-3 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4267#L339-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4262#L339-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4258#L299-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4254#L299-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4250#L304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4246#L309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4242#L314-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4237#L200-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4232#L212-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4228#L213-1 start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4223#L459 assume !(0 == start_simulation_~tmp~3#1); 4220#L459-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4217#L200-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4214#L212-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4212#L213-2 stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4205#L414 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4206#L421 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4201#L422 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4202#L472 assume !(0 != start_simulation_~tmp___0~1#1); 4035#L440-2 [2022-10-17 10:17:16,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,265 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2022-10-17 10:17:16,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,265 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240650826] [2022-10-17 10:17:16,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,299 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,300 INFO L85 PathProgramCache]: Analyzing trace with hash -2050387817, now seen corresponding path program 1 times [2022-10-17 10:17:16,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470107986] [2022-10-17 10:17:16,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:16,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:16,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:16,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470107986] [2022-10-17 10:17:16,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470107986] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:16,368 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:16,369 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:17:16,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010424112] [2022-10-17 10:17:16,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:16,369 INFO L765 eck$LassoCheckResult]: loop already infeasible [2022-10-17 10:17:16,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:16,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:17:16,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:17:16,370 INFO L87 Difference]: Start difference. First operand 450 states and 625 transitions. cyclomatic complexity: 177 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:16,406 INFO L93 Difference]: Finished difference Result 651 states and 883 transitions. [2022-10-17 10:17:16,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 651 states and 883 transitions. [2022-10-17 10:17:16,413 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 616 [2022-10-17 10:17:16,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 651 states to 651 states and 883 transitions. [2022-10-17 10:17:16,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 651 [2022-10-17 10:17:16,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 651 [2022-10-17 10:17:16,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 651 states and 883 transitions. [2022-10-17 10:17:16,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:16,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 651 states and 883 transitions. [2022-10-17 10:17:16,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 651 states and 883 transitions. [2022-10-17 10:17:16,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 651 to 634. [2022-10-17 10:17:16,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 634 states, 634 states have (on average 1.359621451104101) internal successors, (862), 633 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 634 states to 634 states and 862 transitions. [2022-10-17 10:17:16,439 INFO L240 hiAutomatonCegarLoop]: Abstraction has 634 states and 862 transitions. [2022-10-17 10:17:16,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:17:16,441 INFO L428 stractBuchiCegarLoop]: Abstraction has 634 states and 862 transitions. [2022-10-17 10:17:16,442 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2022-10-17 10:17:16,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 634 states and 862 transitions. [2022-10-17 10:17:16,446 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 599 [2022-10-17 10:17:16,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:16,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:16,447 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,447 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,448 INFO L748 eck$LassoCheckResult]: Stem: 5215#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 5126#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 5127#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5039#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5040#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 5084#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5085#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5107#L271 assume !(0 == ~M_E~0); 5108#L271-2 assume !(0 == ~T1_E~0); 5124#L276-1 assume !(0 == ~E_M~0); 5125#L281-1 assume !(0 == ~E_1~0); 5093#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5062#L136 assume !(1 == ~m_pc~0); 5063#L136-2 is_master_triggered_~__retres1~0#1 := 0; 5106#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5103#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5054#L331 assume !(0 != activate_threads_~tmp~1#1); 5055#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5130#L155 assume !(1 == ~t1_pc~0); 5131#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5191#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5080#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5081#L339 assume !(0 != activate_threads_~tmp___0~0#1); 5203#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5118#L299 assume !(1 == ~M_E~0); 5119#L299-2 assume !(1 == ~T1_E~0); 5183#L304-1 assume !(1 == ~E_M~0); 5068#L309-1 assume !(1 == ~E_1~0); 5069#L314-1 assume { :end_inline_reset_delta_events } true; 5140#L440-2 assume !false; 5458#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5355#L246 [2022-10-17 10:17:16,448 INFO L750 eck$LassoCheckResult]: Loop: 5355#L246 assume !false; 5450#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5445#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5440#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5435#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5432#L227 assume 0 != eval_~tmp~0#1; 5428#L227-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5208#L235 assume !(0 != eval_~tmp_ndt_1~0#1); 5209#L232 assume !(0 == ~t1_st~0); 5355#L246 [2022-10-17 10:17:16,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,448 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 1 times [2022-10-17 10:17:16,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158439284] [2022-10-17 10:17:16,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,477 INFO L85 PathProgramCache]: Analyzing trace with hash 2078331601, now seen corresponding path program 1 times [2022-10-17 10:17:16,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,482 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800432419] [2022-10-17 10:17:16,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,491 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1188517387, now seen corresponding path program 1 times [2022-10-17 10:17:16,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,493 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866964009] [2022-10-17 10:17:16,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:16,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:16,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:16,543 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866964009] [2022-10-17 10:17:16,543 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866964009] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:16,544 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:16,544 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-10-17 10:17:16,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669850970] [2022-10-17 10:17:16,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:16,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:16,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:17:16,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:17:16,606 INFO L87 Difference]: Start difference. First operand 634 states and 862 transitions. cyclomatic complexity: 232 Second operand has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:16,664 INFO L93 Difference]: Finished difference Result 1055 states and 1414 transitions. [2022-10-17 10:17:16,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1055 states and 1414 transitions. [2022-10-17 10:17:16,674 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 993 [2022-10-17 10:17:16,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1055 states to 1055 states and 1414 transitions. [2022-10-17 10:17:16,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1055 [2022-10-17 10:17:16,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1055 [2022-10-17 10:17:16,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1055 states and 1414 transitions. [2022-10-17 10:17:16,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:16,687 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1055 states and 1414 transitions. [2022-10-17 10:17:16,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1055 states and 1414 transitions. [2022-10-17 10:17:16,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1055 to 1039. [2022-10-17 10:17:16,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1039 states, 1039 states have (on average 1.3455245428296438) internal successors, (1398), 1038 states have internal predecessors, (1398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1039 states to 1039 states and 1398 transitions. [2022-10-17 10:17:16,711 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1039 states and 1398 transitions. [2022-10-17 10:17:16,711 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:17:16,714 INFO L428 stractBuchiCegarLoop]: Abstraction has 1039 states and 1398 transitions. [2022-10-17 10:17:16,714 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2022-10-17 10:17:16,714 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1039 states and 1398 transitions. [2022-10-17 10:17:16,721 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 977 [2022-10-17 10:17:16,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:16,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:16,725 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,725 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,725 INFO L748 eck$LassoCheckResult]: Stem: 6914#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6826#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6736#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6737#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 6784#L182-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 6785#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6805#L271 assume !(0 == ~M_E~0); 6806#L271-2 assume !(0 == ~T1_E~0); 6823#L276-1 assume !(0 == ~E_M~0); 6824#L281-1 assume !(0 == ~E_1~0); 6792#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6759#L136 assume !(1 == ~m_pc~0); 6760#L136-2 is_master_triggered_~__retres1~0#1 := 0; 6804#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6801#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6751#L331 assume !(0 != activate_threads_~tmp~1#1); 6752#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6830#L155 assume !(1 == ~t1_pc~0); 6831#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6892#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6779#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6780#L339 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6920#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7673#L299 assume !(1 == ~M_E~0); 7672#L299-2 assume !(1 == ~T1_E~0); 7671#L304-1 assume !(1 == ~E_M~0); 7670#L309-1 assume !(1 == ~E_1~0); 7669#L314-1 assume { :end_inline_reset_delta_events } true; 7668#L440-2 assume !false; 7667#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7651#L246 [2022-10-17 10:17:16,726 INFO L750 eck$LassoCheckResult]: Loop: 7651#L246 assume !false; 7666#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7663#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7661#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7659#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7657#L227 assume 0 != eval_~tmp~0#1; 7654#L227-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6905#L235 assume !(0 != eval_~tmp_ndt_1~0#1); 6906#L232 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 7650#L249 assume !(0 != eval_~tmp_ndt_2~0#1); 7651#L246 [2022-10-17 10:17:16,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,726 INFO L85 PathProgramCache]: Analyzing trace with hash -1643521085, now seen corresponding path program 1 times [2022-10-17 10:17:16,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,727 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211069804] [2022-10-17 10:17:16,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-10-17 10:17:16,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-10-17 10:17:16,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-10-17 10:17:16,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211069804] [2022-10-17 10:17:16,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211069804] provided 1 perfect and 0 imperfect interpolant sequences [2022-10-17 10:17:16,759 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-10-17 10:17:16,759 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-10-17 10:17:16,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583498943] [2022-10-17 10:17:16,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-10-17 10:17:16,762 INFO L753 eck$LassoCheckResult]: stem already infeasible [2022-10-17 10:17:16,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,762 INFO L85 PathProgramCache]: Analyzing trace with hash 3767933, now seen corresponding path program 1 times [2022-10-17 10:17:16,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,767 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335014413] [2022-10-17 10:17:16,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,771 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,781 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-10-17 10:17:16,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-10-17 10:17:16,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-10-17 10:17:16,860 INFO L87 Difference]: Start difference. First operand 1039 states and 1398 transitions. cyclomatic complexity: 364 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-10-17 10:17:16,872 INFO L93 Difference]: Finished difference Result 1004 states and 1349 transitions. [2022-10-17 10:17:16,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1004 states and 1349 transitions. [2022-10-17 10:17:16,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 968 [2022-10-17 10:17:16,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1004 states to 1004 states and 1349 transitions. [2022-10-17 10:17:16,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1004 [2022-10-17 10:17:16,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1004 [2022-10-17 10:17:16,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1004 states and 1349 transitions. [2022-10-17 10:17:16,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-10-17 10:17:16,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1004 states and 1349 transitions. [2022-10-17 10:17:16,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1004 states and 1349 transitions. [2022-10-17 10:17:16,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1004 to 1004. [2022-10-17 10:17:16,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1004 states, 1004 states have (on average 1.343625498007968) internal successors, (1349), 1003 states have internal predecessors, (1349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-10-17 10:17:16,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1004 states to 1004 states and 1349 transitions. [2022-10-17 10:17:16,925 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1004 states and 1349 transitions. [2022-10-17 10:17:16,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-10-17 10:17:16,929 INFO L428 stractBuchiCegarLoop]: Abstraction has 1004 states and 1349 transitions. [2022-10-17 10:17:16,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2022-10-17 10:17:16,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1004 states and 1349 transitions. [2022-10-17 10:17:16,936 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 968 [2022-10-17 10:17:16,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-10-17 10:17:16,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-10-17 10:17:16,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-10-17 10:17:16,937 INFO L748 eck$LassoCheckResult]: Stem: 8976#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 8873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8874#L403 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8785#L175 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8786#L182 assume 1 == ~m_i~0;~m_st~0 := 0; 8833#L182-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8834#L187-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8853#L271 assume !(0 == ~M_E~0); 8854#L271-2 assume !(0 == ~T1_E~0); 8871#L276-1 assume !(0 == ~E_M~0); 8872#L281-1 assume !(0 == ~E_1~0); 8839#L286-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8808#L136 assume !(1 == ~m_pc~0); 8809#L136-2 is_master_triggered_~__retres1~0#1 := 0; 8852#L147 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8849#L148 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8800#L331 assume !(0 != activate_threads_~tmp~1#1); 8801#L331-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8878#L155 assume !(1 == ~t1_pc~0); 8879#L155-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8942#L166 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8828#L167 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8829#L339 assume !(0 != activate_threads_~tmp___0~0#1); 8955#L339-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8864#L299 assume !(1 == ~M_E~0); 8865#L299-2 assume !(1 == ~T1_E~0); 8936#L304-1 assume !(1 == ~E_M~0); 8816#L309-1 assume !(1 == ~E_1~0); 8817#L314-1 assume { :end_inline_reset_delta_events } true; 8891#L440-2 assume !false; 9258#L441 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9257#L246 [2022-10-17 10:17:16,937 INFO L750 eck$LassoCheckResult]: Loop: 9257#L246 assume !false; 9256#L223 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9255#L200 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9254#L212 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9253#L213 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9252#L227 assume 0 != eval_~tmp~0#1; 9251#L227-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 9249#L235 assume !(0 != eval_~tmp_ndt_1~0#1); 9250#L232 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 9259#L249 assume !(0 != eval_~tmp_ndt_2~0#1); 9257#L246 [2022-10-17 10:17:16,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,938 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 2 times [2022-10-17 10:17:16,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,938 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378675949] [2022-10-17 10:17:16,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,947 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,962 INFO L85 PathProgramCache]: Analyzing trace with hash 3767933, now seen corresponding path program 2 times [2022-10-17 10:17:16,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256242544] [2022-10-17 10:17:16,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,968 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:16,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-10-17 10:17:16,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1810668925, now seen corresponding path program 1 times [2022-10-17 10:17:16,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-10-17 10:17:16,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801070321] [2022-10-17 10:17:16,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-10-17 10:17:16,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-10-17 10:17:16,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:16,986 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:16,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:17,012 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-10-17 10:17:17,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:17,688 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-10-17 10:17:17,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-10-17 10:17:17,831 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.10 10:17:17 BoogieIcfgContainer [2022-10-17 10:17:17,832 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-10-17 10:17:17,833 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-10-17 10:17:17,839 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-10-17 10:17:17,839 INFO L275 PluginConnector]: Witness Printer initialized [2022-10-17 10:17:17,839 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 17.10 10:17:14" (3/4) ... [2022-10-17 10:17:17,842 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-10-17 10:17:17,903 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/witness.graphml [2022-10-17 10:17:17,903 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-10-17 10:17:17,904 INFO L158 Benchmark]: Toolchain (without parser) took 5183.96ms. Allocated memory was 88.1MB in the beginning and 142.6MB in the end (delta: 54.5MB). Free memory was 47.3MB in the beginning and 73.4MB in the end (delta: -26.1MB). Peak memory consumption was 28.2MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,904 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 88.1MB. Free memory was 63.5MB in the beginning and 63.4MB in the end (delta: 49.2kB). There was no memory consumed. Max. memory is 16.1GB. [2022-10-17 10:17:17,905 INFO L158 Benchmark]: CACSL2BoogieTranslator took 411.33ms. Allocated memory is still 88.1MB. Free memory was 47.0MB in the beginning and 61.6MB in the end (delta: -14.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,905 INFO L158 Benchmark]: Boogie Procedure Inliner took 51.33ms. Allocated memory is still 88.1MB. Free memory was 61.4MB in the beginning and 58.9MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,911 INFO L158 Benchmark]: Boogie Preprocessor took 40.17ms. Allocated memory is still 88.1MB. Free memory was 58.9MB in the beginning and 56.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,911 INFO L158 Benchmark]: RCFGBuilder took 834.78ms. Allocated memory is still 88.1MB. Free memory was 56.8MB in the beginning and 34.5MB in the end (delta: 22.3MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,912 INFO L158 Benchmark]: BuchiAutomizer took 3740.01ms. Allocated memory was 88.1MB in the beginning and 142.6MB in the end (delta: 54.5MB). Free memory was 65.2MB in the beginning and 77.6MB in the end (delta: -12.4MB). Peak memory consumption was 40.1MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,912 INFO L158 Benchmark]: Witness Printer took 69.94ms. Allocated memory is still 142.6MB. Free memory was 77.6MB in the beginning and 73.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-10-17 10:17:17,914 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 88.1MB. Free memory was 63.5MB in the beginning and 63.4MB in the end (delta: 49.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 411.33ms. Allocated memory is still 88.1MB. Free memory was 47.0MB in the beginning and 61.6MB in the end (delta: -14.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 51.33ms. Allocated memory is still 88.1MB. Free memory was 61.4MB in the beginning and 58.9MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 40.17ms. Allocated memory is still 88.1MB. Free memory was 58.9MB in the beginning and 56.8MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 834.78ms. Allocated memory is still 88.1MB. Free memory was 56.8MB in the beginning and 34.5MB in the end (delta: 22.3MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 3740.01ms. Allocated memory was 88.1MB in the beginning and 142.6MB in the end (delta: 54.5MB). Free memory was 65.2MB in the beginning and 77.6MB in the end (delta: -12.4MB). Peak memory consumption was 40.1MB. Max. memory is 16.1GB. * Witness Printer took 69.94ms. Allocated memory is still 142.6MB. Free memory was 77.6MB in the beginning and 73.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 8 terminating modules (8 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.8 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1004 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.5s and 9 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.2s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 8. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 8 MinimizatonAttempts, 807 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2268 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2268 mSDsluCounter, 3998 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2237 mSDsCounter, 72 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 207 IncrementalHoareTripleChecker+Invalid, 279 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 72 mSolverCounterUnsat, 1761 mSDtfsCounter, 207 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN1 SILU0 SILI3 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 222]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int m_st ; [L27] int t1_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L37] int token ; [L39] int local ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, token=0] [L485] int __retres1 ; [L489] CALL init_model() [L400] m_i = 1 [L401] t1_i = 1 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L489] RET init_model() [L490] CALL start_simulation() [L426] int kernel_st ; [L427] int tmp ; [L428] int tmp___0 ; [L432] kernel_st = 0 [L433] FCALL update_channels() [L434] CALL init_threads() [L182] COND TRUE m_i == 1 [L183] m_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L187] COND TRUE t1_i == 1 [L188] t1_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L434] RET init_threads() [L435] CALL fire_delta_events() [L271] COND FALSE !(M_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L276] COND FALSE !(T1_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L281] COND FALSE !(E_M == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L286] COND FALSE !(E_1 == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L435] RET fire_delta_events() [L436] CALL activate_threads() [L324] int tmp ; [L325] int tmp___0 ; [L329] CALL, EXPR is_master_triggered() [L133] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L136] COND FALSE !(m_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L146] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L148] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L329] RET, EXPR is_master_triggered() [L329] tmp = is_master_triggered() [L331] COND FALSE !(\read(tmp)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, token=0] [L337] CALL, EXPR is_transmit1_triggered() [L152] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L155] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L165] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L167] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L337] RET, EXPR is_transmit1_triggered() [L337] tmp___0 = is_transmit1_triggered() [L339] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0, token=0] [L436] RET activate_threads() [L437] CALL reset_delta_events() [L299] COND FALSE !(M_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L304] COND FALSE !(T1_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L309] COND FALSE !(E_M == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L314] COND FALSE !(E_1 == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L437] RET reset_delta_events() [L440] COND TRUE 1 VAL [E_1=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L443] kernel_st = 1 [L444] CALL eval() [L218] int tmp ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] Loop: [L222] COND TRUE 1 [L225] CALL, EXPR exists_runnable_thread() [L197] int __retres1 ; [L200] COND TRUE m_st == 0 [L201] __retres1 = 1 [L213] return (__retres1); [L225] RET, EXPR exists_runnable_thread() [L225] tmp = exists_runnable_thread() [L227] COND TRUE \read(tmp) [L232] COND TRUE m_st == 0 [L233] int tmp_ndt_1; [L234] tmp_ndt_1 = __VERIFIER_nondet_int() [L235] COND FALSE !(\read(tmp_ndt_1)) [L246] COND TRUE t1_st == 0 [L247] int tmp_ndt_2; [L248] tmp_ndt_2 = __VERIFIER_nondet_int() [L249] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 222]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int m_st ; [L27] int t1_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L37] int token ; [L39] int local ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=0, m_pc=0, m_st=0, T1_E=2, t1_i=0, t1_pc=0, t1_st=0, token=0] [L485] int __retres1 ; [L489] CALL init_model() [L400] m_i = 1 [L401] t1_i = 1 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L489] RET init_model() [L490] CALL start_simulation() [L426] int kernel_st ; [L427] int tmp ; [L428] int tmp___0 ; [L432] kernel_st = 0 [L433] FCALL update_channels() [L434] CALL init_threads() [L182] COND TRUE m_i == 1 [L183] m_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L187] COND TRUE t1_i == 1 [L188] t1_st = 0 VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L434] RET init_threads() [L435] CALL fire_delta_events() [L271] COND FALSE !(M_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L276] COND FALSE !(T1_E == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L281] COND FALSE !(E_M == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L286] COND FALSE !(E_1 == 0) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L435] RET fire_delta_events() [L436] CALL activate_threads() [L324] int tmp ; [L325] int tmp___0 ; [L329] CALL, EXPR is_master_triggered() [L133] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L136] COND FALSE !(m_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L146] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L148] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L329] RET, EXPR is_master_triggered() [L329] tmp = is_master_triggered() [L331] COND FALSE !(\read(tmp)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, token=0] [L337] CALL, EXPR is_transmit1_triggered() [L152] int __retres1 ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L155] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L165] __retres1 = 0 VAL [__retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L167] return (__retres1); VAL [\result=0, __retres1=0, E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L337] RET, EXPR is_transmit1_triggered() [L337] tmp___0 = is_transmit1_triggered() [L339] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0, token=0] [L436] RET activate_threads() [L437] CALL reset_delta_events() [L299] COND FALSE !(M_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L304] COND FALSE !(T1_E == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L309] COND FALSE !(E_M == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L314] COND FALSE !(E_1 == 1) VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L437] RET reset_delta_events() [L440] COND TRUE 1 VAL [E_1=2, E_M=2, kernel_st=0, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] [L443] kernel_st = 1 [L444] CALL eval() [L218] int tmp ; VAL [E_1=2, E_M=2, local=0, M_E=2, m_i=1, m_pc=0, m_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, token=0] Loop: [L222] COND TRUE 1 [L225] CALL, EXPR exists_runnable_thread() [L197] int __retres1 ; [L200] COND TRUE m_st == 0 [L201] __retres1 = 1 [L213] return (__retres1); [L225] RET, EXPR exists_runnable_thread() [L225] tmp = exists_runnable_thread() [L227] COND TRUE \read(tmp) [L232] COND TRUE m_st == 0 [L233] int tmp_ndt_1; [L234] tmp_ndt_1 = __VERIFIER_nondet_int() [L235] COND FALSE !(\read(tmp_ndt_1)) [L246] COND TRUE t1_st == 0 [L247] int tmp_ndt_2; [L248] tmp_ndt_2 = __VERIFIER_nondet_int() [L249] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-10-17 10:17:18,050 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_70a4a901-70c6-4e21-9e0e-62d02435adc2/bin/uautomizer-J5u9QxTXDZ/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)